[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
/* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
#define MAX_OPC_PARAM 10
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

/* Maximum size a TCG op can expand to.  This is complicated because a
   single op may require several host instructions and regirster reloads.
   For now take a wild guess at 128 bytes, which should allow at least
   a couple of fixup instructions per argument.  */
#define TCG_MAX_OP_SIZE 128

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)

extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];
extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);

#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
unsigned long code_gen_max_block_size(void);
void cpu_gen_init(void);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb,
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb,
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(CPUState *env);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                      target_phys_addr_t paddr, int prot,
                      int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
                               target_phys_addr_t paddr, int prot,
                               int mmu_idx, int is_softmmu)
{
    if (prot & PAGE_READ)
        prot |= PAGE_EXEC;
    return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
}

#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__ia64)
#define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)	/* range of addl */
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
/* XXX: make it dynamic on x86 */
#define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) || defined(__x86_64__)
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    uint64_t flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next;
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2];
    target_ulong page_addr[2];

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    unsigned long tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2];
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
}

static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
{
    target_ulong tmp;
    tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
    return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
	    (tmp & TB_JMP_ADDR_MASK));
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link_phys(TranslationBlock *tb,
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__) || defined(__x86_64__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n,
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);

        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#if defined(__hppa__)

typedef int spinlock_t[4];

#define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }

static inline void resetlock (spinlock_t *p)
{
    (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
}

#else

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

static inline void resetlock (spinlock_t *p)
{
    *p = SPIN_LOCK_UNLOCKED;
}

#endif

#if defined(__powerpc__)
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#elif defined(__i386__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__x86_64__)
static inline int testandset (int *p)
{
    long int readval = 0;

    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#elif defined(__s390__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p)
			  : "cc", "memory" );
    return ret;
}
#elif defined(__alpha__)
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#elif defined(__sparc__)
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#elif defined(__arm__)
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));

    return ret;
}
#elif defined(__mc68000)
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret;
}
#elif defined(__hppa__)

/* Because malloc only guarantees 8-byte alignment for malloc'd data,
   and GCC only guarantees 8-byte alignment for stack locals, we can't
   be assured of 16-byte alignment for atomic lock data even if we
   specify "__attribute ((aligned(16)))" in the type declaration.  So,
   we use a struct containing an array of four ints for the atomic lock
   type and dynamically select the 16-byte aligned int from the array
   for the semaphore.  */
#define __PA_LDCW_ALIGNMENT 16
static inline void *ldcw_align (void *p) {
    unsigned long a = (unsigned long)p;
    a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
    return (void *)a;
}

static inline int testandset (spinlock_t *p)
{
    unsigned int ret;
    p = ldcw_align(p);
    __asm__ __volatile__("ldcw 0(%1),%0"
                         : "=r" (ret)
                         : "r" (p)
                         : "memory" );
    return !ret;
}

#elif defined(__ia64)

#include <ia64intrin.h>

static inline int testandset (int *p)
{
    return __sync_lock_test_and_set (p, 1);
}
#elif defined(__mips__)
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ (
	"	.set push		\n"
	"	.set noat		\n"
	"	.set mips2		\n"
	"1:	li	$1, 1		\n"
	"	ll	%0, %1		\n"
	"	sc	$1, %1		\n"
	"	beqz	$1, 1b		\n"
	"	.set pop		"
	: "=r" (ret), "+R" (*p)
	:
	: "memory");

    return ret;
}
#else
#error unimplemented CPU support
#endif

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    resetlock(lock);
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
              void *retaddr);

#define ACCESS_TYPE (NB_MMU_MODES + 1)
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int mmu_idx, index, pd;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = cpu_mmu_index(env);
    if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
#if defined(TARGET_SPARC) || defined(TARGET_MIPS)
        do_unassigned_access(addr, 0, 1, 0);
#else
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
#endif
    }
    return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
}
#endif

#ifdef USE_KQEMU
#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))

int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
void kqemu_cpu_interrupt(CPUState *env);
void kqemu_record_dump(void);

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->cr[0] & CR0_PE_MASK) &&
           !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK) &&
           (env->kqemu_enabled == 2 ||
            ((env->hflags & HF_CPL_MASK) == 3 &&
             (env->eflags & IOPL_MASK) != IOPL_MASK)));
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
d4e8164f FB	2	* internal execution defines for qemu
5fafdf24	3	*
d4e8164f FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
	24	/* is_jmp field values */
	25	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	26	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	27	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	28	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	29
	30	struct TranslationBlock;
	31
	32	/* XXX: make safe guess about sizes */
	33	#define MAX_OP_PER_INSTR 32
0115be31 PB	34	/* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
0115be31 PB	35	#define MAX_OPC_PARAM 10
b346ff46 FB	36	#define OPC_BUF_SIZE 512
	37	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	38
a208e54a PB	39	/* Maximum size a TCG op can expand to. This is complicated because a
	40	single op may require several host instructions and regirster reloads.
	41	For now take a wild guess at 128 bytes, which should allow at least
	42	a couple of fixup instructions per argument. */
	43	#define TCG_MAX_OP_SIZE 128
	44
0115be31	45	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
b346ff46	46
c27004ec FB	47	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
c27004ec FB	48	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	49	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	50	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
c3278b7b	51	extern target_ulong gen_opc_jump_pc[2];
30d6cb84	52	extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
b346ff46	53
9886cc16 FB	54	typedef void (GenOpFunc)(void);
	55	typedef void (GenOpFunc1)(long);
	56	typedef void (GenOpFunc2)(long, long);
	57	typedef void (GenOpFunc3)(long, long, long);
3b46e624	58
b346ff46 FB	59	#if defined(TARGET_I386)
b346ff46 FB	60
33417e70	61	void optimize_flags_init(void);
d4e8164f	62
b346ff46 FB	63	#endif
	64
	65	extern FILE *logfile;
	66	extern int loglevel;
	67
4c3a88a2 FB	68	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	69	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
d07bde88	70	unsigned long code_gen_max_block_size(void);
57fec1fe	71	void cpu_gen_init(void);
4c3a88a2	72	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
d07bde88	73	int *gen_code_size_ptr);
5fafdf24	74	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	75	CPUState *env, unsigned long searched_pc,
	76	void *puc);
	77	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	78	int max_code_size, int *gen_code_size_ptr);
5fafdf24	79	int cpu_restore_state_copy(struct TranslationBlock *tb,
58fe2f10 FB	80	CPUState *env, unsigned long searched_pc,
58fe2f10 FB	81	void *puc);
2e12669a	82	void cpu_resume_from_signal(CPUState env1, void puc);
6a00d601	83	void cpu_exec_init(CPUState *env);
53a5960a	84	int page_unprotect(target_ulong address, unsigned long pc, void *puc);
03875444	85	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
2e12669a	86	int is_cpu_write_access);
4390df51	87	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	88	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	89	void tlb_flush(CPUState *env, int flush_global);
5fafdf24 TS	90	int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
5fafdf24 TS	91	target_phys_addr_t paddr, int prot,
6ebbf390	92	int mmu_idx, int is_softmmu);
5fafdf24 TS	93	static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
5fafdf24 TS	94	target_phys_addr_t paddr, int prot,
6ebbf390	95	int mmu_idx, int is_softmmu)
84b7b8e7 FB	96	{
	97	if (prot & PAGE_READ)
	98	prot \|= PAGE_EXEC;
6ebbf390	99	return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
84b7b8e7	100	}
d4e8164f	101
d4e8164f FB	102	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
d4e8164f FB	103
4390df51 FB	104	#define CODE_GEN_PHYS_HASH_BITS 15
	105	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	106
d4e8164f	107	/* maximum total translate dcode allocated */
4390df51 FB	108
4390df51 FB	109	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	110	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	111	summary of the ranges:
	112
	113	i386 : signed 32 bits
	114	arm : signed 26 bits
	115	ppc : signed 24 bits
	116	sparc : signed 32 bits
	117	alpha : signed 23 bits
	118	*/
	119
	120	#if defined(__alpha__)
	121	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
b8076a74 FB	122	#elif defined(__ia64)
b8076a74 FB	123	#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
4390df51	124	#elif defined(__powerpc__)
c4c7e3e6	125	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51	126	#else
57fec1fe	127	/* XXX: make it dynamic on x86 */
c98baaac	128	#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
4390df51 FB	129	#endif
4390df51 FB	130
d4e8164f FB	131	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	132
4390df51 FB	133	/* estimated block size for TB allocation */
	134	/* XXX: use a per code average code fragment size and modulate it
	135	according to the host CPU */
	136	#if defined(CONFIG_SOFTMMU)
	137	#define CODE_GEN_AVG_BLOCK_SIZE 128
	138	#else
	139	#define CODE_GEN_AVG_BLOCK_SIZE 64
	140	#endif
	141
	142	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	143
57fec1fe	144	#if defined(__powerpc__) \|\| defined(__x86_64__)
4390df51 FB	145	#define USE_DIRECT_JUMP
4390df51 FB	146	#endif
67b915a5	147	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	148	#define USE_DIRECT_JUMP
	149	#endif
	150
	151	typedef struct TranslationBlock {
2e12669a FB	152	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	153	target_ulong cs_base; /* CS base for this block */
c068688b	154	uint64_t flags; /* flags defining in which context the code was generated */
d4e8164f FB	155	uint16_t size; /* size of target code for this block (1 <=
d4e8164f FB	156	size <= TARGET_PAGE_SIZE) */
58fe2f10	157	uint16_t cflags; /* compile flags */
bf088061 FB	158	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	159	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	160	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	161	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	162
d4e8164f	163	uint8_t tc_ptr; / pointer to the translated code */
4390df51	164	/* next matching tb for physical address. */
5fafdf24	165	struct TranslationBlock *phys_hash_next;
4390df51 FB	166	/* first and second physical page containing code. The lower bit
4390df51 FB	167	of the pointer tells the index in page_next[] */
5fafdf24 TS	168	struct TranslationBlock *page_next[2];
5fafdf24 TS	169	target_ulong page_addr[2];
4390df51	170
d4e8164f FB	171	/* the following data are used to directly call another TB from
	172	the code of this one. */
	173	uint16_t tb_next_offset[2]; /* offset of original jump target */
	174	#ifdef USE_DIRECT_JUMP
4cbb86e1	175	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	176	#else
57fec1fe	177	unsigned long tb_next[2]; /* address of jump generated code */
d4e8164f FB	178	#endif
	179	/* list of TBs jumping to this one. This is a circular list using
	180	the two least significant bits of the pointers to tell what is
	181	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	182	jmp_first */
5fafdf24	183	struct TranslationBlock *jmp_next[2];
d4e8164f FB	184	struct TranslationBlock *jmp_first;
	185	} TranslationBlock;
	186
b362e5e0 PB	187	static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
	188	{
	189	target_ulong tmp;
	190	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	191	return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
	192	}
	193
8a40a180	194	static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
d4e8164f	195	{
b362e5e0 PB	196	target_ulong tmp;
	197	tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
	198	return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) \|
	199	(tmp & TB_JMP_ADDR_MASK));
d4e8164f FB	200	}
d4e8164f FB	201
4390df51 FB	202	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	203	{
	204	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	205	}
	206
c27004ec	207	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	208	void tb_flush(CPUState *env);
5fafdf24	209	void tb_link_phys(TranslationBlock *tb,
4390df51	210	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f	211
4390df51	212	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	213
	214	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	215	extern uint8_t *code_gen_ptr;
	216
4390df51 FB	217	#if defined(USE_DIRECT_JUMP)
	218
	219	#if defined(__powerpc__)
4cbb86e1	220	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	221	{
d4e8164f FB	222	uint32_t val, *ptr;
d4e8164f FB	223
d4e8164f FB	224	/* patch the branch destination */
4cbb86e1	225	ptr = (uint32_t *)jmp_addr;
d4e8164f	226	val = *ptr;
4cbb86e1	227	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	228	*ptr = val;
	229	/* flush icache */
	230	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	231	asm volatile ("sync" : : : "memory");
	232	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	233	asm volatile ("sync" : : : "memory");
	234	asm volatile ("isync" : : : "memory");
	235	}
57fec1fe	236	#elif defined(__i386__) \|\| defined(__x86_64__)
4390df51 FB	237	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	238	{
	239	/* patch the branch destination */
	240	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	241	/* no need to flush icache explicitely */
	242	}
	243	#endif
d4e8164f	244
5fafdf24	245	static inline void tb_set_jmp_target(TranslationBlock *tb,
4cbb86e1 FB	246	int n, unsigned long addr)
	247	{
	248	unsigned long offset;
	249
	250	offset = tb->tb_jmp_offset[n];
	251	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	252	offset = tb->tb_jmp_offset[n + 2];
	253	if (offset != 0xffff)
	254	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	255	}
	256
d4e8164f FB	257	#else
	258
	259	/* set the jump target */
5fafdf24	260	static inline void tb_set_jmp_target(TranslationBlock *tb,
d4e8164f FB	261	int n, unsigned long addr)
d4e8164f FB	262	{
95f7652d	263	tb->tb_next[n] = addr;
d4e8164f FB	264	}
	265
	266	#endif
	267
5fafdf24	268	static inline void tb_add_jump(TranslationBlock *tb, int n,
d4e8164f FB	269	TranslationBlock *tb_next)
d4e8164f FB	270	{
cf25629d FB	271	/* NOTE: this test is only needed for thread safety */
	272	if (!tb->jmp_next[n]) {
	273	/* patch the native jump address */
	274	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
3b46e624	275
cf25629d FB	276	/* add in TB jmp circular list */
	277	tb->jmp_next[n] = tb_next->jmp_first;
	278	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	279	}
d4e8164f FB	280	}
d4e8164f FB	281
a513fe19 FB	282	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	283
d4e8164f FB	284	#ifndef offsetof
	285	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	286	#endif
	287
d549f7d9 FB	288	#if defined(_WIN32)
	289	#define ASM_DATA_SECTION ".section \".data\"\n"
	290	#define ASM_PREVIOUS_SECTION ".section .text\n"
	291	#elif defined(__APPLE__)
	292	#define ASM_DATA_SECTION ".data\n"
	293	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	294	#else
	295	#define ASM_DATA_SECTION ".section \".data\"\n"
	296	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	297	#endif
d549f7d9 FB	298
75913b72 FB	299	#define ASM_OP_LABEL_NAME(n, opname) \
	300	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	301
33417e70 FB	302	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	303	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	304	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	305
15a51156 AJ	306	#if defined(__hppa__)
	307
	308	typedef int spinlock_t[4];
	309
	310	#define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
	311
	312	static inline void resetlock (spinlock_t *p)
	313	{
	314	(p)[0] = (p)[1] = (p)[2] = (p)[3] = 1;
	315	}
	316
	317	#else
	318
	319	typedef int spinlock_t;
	320
	321	#define SPIN_LOCK_UNLOCKED 0
	322
	323	static inline void resetlock (spinlock_t *p)
	324	{
	325	*p = SPIN_LOCK_UNLOCKED;
	326	}
	327
	328	#endif
	329
204a1b8d	330	#if defined(__powerpc__)
d4e8164f FB	331	static inline int testandset (int *p)
	332	{
	333	int ret;
	334	__asm__ __volatile__ (
02e1ec9b FB	335	"0: lwarx %0,0,%1\n"
	336	" xor. %0,%3,%0\n"
	337	" bne 1f\n"
	338	" stwcx. %2,0,%1\n"
	339	" bne- 0b\n"
d4e8164f FB	340	"1: "
	341	: "=&r" (ret)
	342	: "r" (p), "r" (1), "r" (0)
	343	: "cr0", "memory");
	344	return ret;
	345	}
204a1b8d	346	#elif defined(__i386__)
d4e8164f FB	347	static inline int testandset (int *p)
d4e8164f FB	348	{
4955a2cd	349	long int readval = 0;
3b46e624	350
4955a2cd FB	351	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	352	: "+m" (*p), "+a" (readval)
	353	: "r" (1)
	354	: "cc");
	355	return readval;
d4e8164f	356	}
204a1b8d	357	#elif defined(__x86_64__)
bc51c5c9 FB	358	static inline int testandset (int *p)
bc51c5c9 FB	359	{
4955a2cd	360	long int readval = 0;
3b46e624	361
4955a2cd FB	362	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	363	: "+m" (*p), "+a" (readval)
	364	: "r" (1)
	365	: "cc");
	366	return readval;
bc51c5c9	367	}
204a1b8d	368	#elif defined(__s390__)
d4e8164f FB	369	static inline int testandset (int *p)
	370	{
	371	int ret;
	372
	373	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	374	" jl 0b"
	375	: "=&d" (ret)
5fafdf24	376	: "r" (1), "a" (p), "0" (*p)
d4e8164f FB	377	: "cc", "memory" );
	378	return ret;
	379	}
204a1b8d	380	#elif defined(__alpha__)
2f87c607	381	static inline int testandset (int *p)
d4e8164f FB	382	{
	383	int ret;
	384	unsigned long one;
	385
	386	__asm__ __volatile__ ("0: mov 1,%2\n"
	387	" ldl_l %0,%1\n"
	388	" stl_c %2,%1\n"
	389	" beq %2,1f\n"
	390	".subsection 2\n"
	391	"1: br 0b\n"
	392	".previous"
	393	: "=r" (ret), "=m" (*p), "=r" (one)
	394	: "m" (*p));
	395	return ret;
	396	}
204a1b8d	397	#elif defined(__sparc__)
d4e8164f FB	398	static inline int testandset (int *p)
	399	{
	400	int ret;
	401
	402	__asm__ __volatile__("ldstub [%1], %0"
	403	: "=r" (ret)
	404	: "r" (p)
	405	: "memory");
	406
	407	return (ret ? 1 : 0);
	408	}
204a1b8d	409	#elif defined(__arm__)
a95c6790 FB	410	static inline int testandset (int *spinlock)
	411	{
	412	register unsigned int ret;
	413	__asm__ __volatile__("swp %0, %1, [%2]"
	414	: "=r"(ret)
	415	: "0"(1), "r"(spinlock));
3b46e624	416
a95c6790 FB	417	return ret;
a95c6790 FB	418	}
204a1b8d	419	#elif defined(__mc68000)
38e584a0 FB	420	static inline int testandset (int *p)
	421	{
	422	char ret;
	423	__asm__ __volatile__("tas %1; sne %0"
	424	: "=r" (ret)
	425	: "m" (p)
	426	: "cc","memory");
4955a2cd	427	return ret;
38e584a0	428	}
15a51156 AJ	429	#elif defined(__hppa__)
	430
	431	/* Because malloc only guarantees 8-byte alignment for malloc'd data,
	432	and GCC only guarantees 8-byte alignment for stack locals, we can't
	433	be assured of 16-byte alignment for atomic lock data even if we
	434	specify "__attribute ((aligned(16)))" in the type declaration. So,
	435	we use a struct containing an array of four ints for the atomic lock
	436	type and dynamically select the 16-byte aligned int from the array
	437	for the semaphore. */
	438	#define __PA_LDCW_ALIGNMENT 16
	439	static inline void ldcw_align (void p) {
	440	unsigned long a = (unsigned long)p;
	441	a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
	442	return (void *)a;
	443	}
	444
	445	static inline int testandset (spinlock_t *p)
	446	{
	447	unsigned int ret;
	448	p = ldcw_align(p);
	449	__asm__ __volatile__("ldcw 0(%1),%0"
	450	: "=r" (ret)
	451	: "r" (p)
	452	: "memory" );
	453	return !ret;
	454	}
	455
204a1b8d	456	#elif defined(__ia64)
38e584a0	457
b8076a74 FB	458	#include <ia64intrin.h>
	459
	460	static inline int testandset (int *p)
	461	{
	462	return __sync_lock_test_and_set (p, 1);
	463	}
204a1b8d	464	#elif defined(__mips__)
c4b89d18 TS	465	static inline int testandset (int *p)
	466	{
	467	int ret;
	468
	469	__asm__ __volatile__ (
	470	" .set push \n"
	471	" .set noat \n"
	472	" .set mips2 \n"
	473	"1: li $1, 1 \n"
	474	" ll %0, %1 \n"
	475	" sc $1, %1 \n"
976a0d0d	476	" beqz $1, 1b \n"
c4b89d18 TS	477	" .set pop "
	478	: "=r" (ret), "+R" (*p)
	479	:
	480	: "memory");
	481
	482	return ret;
	483	}
204a1b8d TS	484	#else
204a1b8d TS	485	#error unimplemented CPU support
c4b89d18 TS	486	#endif
c4b89d18 TS	487
aebcb60e	488	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	489	static inline void spin_lock(spinlock_t *lock)
	490	{
	491	while (testandset(lock));
	492	}
	493
	494	static inline void spin_unlock(spinlock_t *lock)
	495	{
15a51156	496	resetlock(lock);
d4e8164f FB	497	}
	498
	499	static inline int spin_trylock(spinlock_t *lock)
	500	{
	501	return !testandset(lock);
	502	}
3c1cf9fa FB	503	#else
	504	static inline void spin_lock(spinlock_t *lock)
	505	{
	506	}
	507
	508	static inline void spin_unlock(spinlock_t *lock)
	509	{
	510	}
	511
	512	static inline int spin_trylock(spinlock_t *lock)
	513	{
	514	return 1;
	515	}
	516	#endif
d4e8164f FB	517
	518	extern spinlock_t tb_lock;
	519
36bdbe54	520	extern int tb_invalidated_flag;
6e59c1db	521
e95c8d51	522	#if !defined(CONFIG_USER_ONLY)
6e59c1db	523
6ebbf390	524	void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
6e59c1db FB	525	void *retaddr);
6e59c1db FB	526
6ebbf390	527	#define ACCESS_TYPE (NB_MMU_MODES + 1)
6e59c1db FB	528	#define MEMSUFFIX _code
	529	#define env cpu_single_env
	530
	531	#define DATA_SIZE 1
	532	#include "softmmu_header.h"
	533
	534	#define DATA_SIZE 2
	535	#include "softmmu_header.h"
	536
	537	#define DATA_SIZE 4
	538	#include "softmmu_header.h"
	539
c27004ec FB	540	#define DATA_SIZE 8
	541	#include "softmmu_header.h"
	542
6e59c1db FB	543	#undef ACCESS_TYPE
	544	#undef MEMSUFFIX
	545	#undef env
	546
	547	#endif
4390df51 FB	548
	549	#if defined(CONFIG_USER_ONLY)
	550	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	551	{
	552	return addr;
	553	}
	554	#else
	555	/* NOTE: this function can trigger an exception */
1ccde1cb FB	556	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	557	is the offset relative to phys_ram_base */
4390df51 FB	558	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
4390df51 FB	559	{
6ebbf390	560	int mmu_idx, index, pd;
4390df51 FB	561
4390df51 FB	562	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390 JM	563	mmu_idx = cpu_mmu_index(env);
6ebbf390 JM	564	if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
4390df51	565	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	566	ldub_code(addr);
c27004ec FB	567	}
6ebbf390	568	pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
2a4188a3	569	if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
647de6ca	570	#if defined(TARGET_SPARC) \|\| defined(TARGET_MIPS)
6c36d3fa BS	571	do_unassigned_access(addr, 0, 1, 0);
6c36d3fa BS	572	#else
36d23958	573	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
6c36d3fa	574	#endif
4390df51	575	}
6ebbf390	576	return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
4390df51 FB	577	}
4390df51 FB	578	#endif
9df217a3	579
9df217a3	580	#ifdef USE_KQEMU
f32fc648 FB	581	#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG \| CODE_DIRTY_FLAG))
f32fc648 FB	582
9df217a3 FB	583	int kqemu_init(CPUState *env);
	584	int kqemu_cpu_exec(CPUState *env);
	585	void kqemu_flush_page(CPUState *env, target_ulong addr);
	586	void kqemu_flush(CPUState *env, int global);
4b7df22f	587	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
f32fc648	588	void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
a332e112	589	void kqemu_cpu_interrupt(CPUState *env);
f32fc648	590	void kqemu_record_dump(void);
9df217a3 FB	591
	592	static inline int kqemu_is_ok(CPUState *env)
	593	{
	594	return(env->kqemu_enabled &&
5fafdf24	595	(env->cr[0] & CR0_PE_MASK) &&
f32fc648	596	!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
9df217a3	597	(env->eflags & IF_MASK) &&
f32fc648	598	!(env->eflags & VM_MASK) &&
5fafdf24	599	(env->kqemu_enabled == 2 \|\|
f32fc648 FB	600	((env->hflags & HF_CPL_MASK) == 3 &&
f32fc648 FB	601	(env->eflags & IOPL_MASK) != IOPL_MASK)));
9df217a3 FB	602	}
	603
	604	#endif