[qemu.git] / exec-all.h

/*
 * internal execution defines for qemu
 * 
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

/* allow to see translation results - the slowdown should be negligible, so we leave it */
#define DEBUG_DISAS

#ifndef glue
#define xglue(x, y) x ## y
#define glue(x, y) xglue(x, y)
#define stringify(s)	tostring(s)
#define tostring(s)	#s
#endif

#if __GNUC__ < 3
#define __builtin_expect(x, n) (x)
#endif

#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#else
#define REGPARM(n)
#endif

/* is_jmp field values */
#define DISAS_NEXT    0 /* next instruction can be analyzed */
#define DISAS_JUMP    1 /* only pc was modified dynamically */
#define DISAS_UPDATE  2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */

struct TranslationBlock;

/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)

#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)

extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
extern long gen_labels[OPC_BUF_SIZE];
extern int nb_gen_labels;
extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
extern target_ulong gen_opc_jump_pc[2];

typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
                    
#if defined(TARGET_I386)

void optimize_flags_init(void);

#endif

extern FILE *logfile;
extern int loglevel;

int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
                 int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state(struct TranslationBlock *tb, 
                      CPUState *env, unsigned long searched_pc,
                      void *puc);
int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
                      int max_code_size, int *gen_code_size_ptr);
int cpu_restore_state_copy(struct TranslationBlock *tb, 
                           CPUState *env, unsigned long searched_pc,
                           void *puc);
void cpu_resume_from_signal(CPUState *env1, void *puc);
void cpu_exec_init(void);
int page_unprotect(unsigned long address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                   int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page(CPUState *env, target_ulong vaddr, 
                 target_phys_addr_t paddr, int prot, 
                 int is_user, int is_softmmu);

#define CODE_GEN_MAX_SIZE        65536
#define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */

#define CODE_GEN_HASH_BITS     15
#define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)

#define CODE_GEN_PHYS_HASH_BITS     15
#define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)

/* maximum total translate dcode allocated */

/* NOTE: the translated code area cannot be too big because on some
   archs the range of "fast" function calls is limited. Here is a
   summary of the ranges:

   i386  : signed 32 bits
   arm   : signed 26 bits
   ppc   : signed 24 bits
   sparc : signed 32 bits
   alpha : signed 23 bits
*/

#if defined(__alpha__)
#define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
#elif defined(__ia64)
#define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)	/* range of addl */
#elif defined(__powerpc__)
#define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
#else
#define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
#endif

//#define CODE_GEN_BUFFER_SIZE     (128 * 1024)

/* estimated block size for TB allocation */
/* XXX: use a per code average code fragment size and modulate it
   according to the host CPU */
#if defined(CONFIG_SOFTMMU)
#define CODE_GEN_AVG_BLOCK_SIZE 128
#else
#define CODE_GEN_AVG_BLOCK_SIZE 64
#endif

#define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)

#if defined(__powerpc__) 
#define USE_DIRECT_JUMP
#endif
#if defined(__i386__) && !defined(_WIN32)
#define USE_DIRECT_JUMP
#endif

typedef struct TranslationBlock {
    target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
    target_ulong cs_base; /* CS base for this block */
    unsigned int flags; /* flags defining in which context the code was generated */
    uint16_t size;      /* size of target code for this block (1 <=
                           size <= TARGET_PAGE_SIZE) */
    uint16_t cflags;    /* compile flags */
#define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
#define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
#define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */

    uint8_t *tc_ptr;    /* pointer to the translated code */
    struct TranslationBlock *hash_next; /* next matching tb for virtual address */
    /* next matching tb for physical address. */
    struct TranslationBlock *phys_hash_next; 
    /* first and second physical page containing code. The lower bit
       of the pointer tells the index in page_next[] */
    struct TranslationBlock *page_next[2]; 
    target_ulong page_addr[2]; 

    /* the following data are used to directly call another TB from
       the code of this one. */
    uint16_t tb_next_offset[2]; /* offset of original jump target */
#ifdef USE_DIRECT_JUMP
    uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
    uint32_t tb_next[2]; /* address of jump generated code */
#endif
    /* list of TBs jumping to this one. This is a circular list using
       the two least significant bits of the pointers to tell what is
       the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
       jmp_first */
    struct TranslationBlock *jmp_next[2]; 
    struct TranslationBlock *jmp_first;
} TranslationBlock;

static inline unsigned int tb_hash_func(target_ulong pc)
{
    return pc & (CODE_GEN_HASH_SIZE - 1);
}

static inline unsigned int tb_phys_hash_func(unsigned long pc)
{
    return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
}

TranslationBlock *tb_alloc(target_ulong pc);
void tb_flush(CPUState *env);
void tb_link(TranslationBlock *tb);
void tb_link_phys(TranslationBlock *tb, 
                  target_ulong phys_pc, target_ulong phys_page2);

extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];

extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
extern uint8_t *code_gen_ptr;

/* find a translation block in the translation cache. If not found,
   return NULL and the pointer to the last element of the list in pptb */
static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
                                        target_ulong pc, 
                                        target_ulong cs_base,
                                        unsigned int flags)
{
    TranslationBlock **ptb, *tb;
    unsigned int h;
 
    h = tb_hash_func(pc);
    ptb = &tb_hash[h];
    for(;;) {
        tb = *ptb;
        if (!tb)
            break;
        if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
            return tb;
        ptb = &tb->hash_next;
    }
    *pptb = ptb;
    return NULL;
}


#if defined(USE_DIRECT_JUMP)

#if defined(__powerpc__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    uint32_t val, *ptr;

    /* patch the branch destination */
    ptr = (uint32_t *)jmp_addr;
    val = *ptr;
    val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
    *ptr = val;
    /* flush icache */
    asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
    asm volatile ("sync" : : : "memory");
    asm volatile ("isync" : : : "memory");
}
#elif defined(__i386__)
static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
{
    /* patch the branch destination */
    *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
    /* no need to flush icache explicitely */
}
#endif

static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    unsigned long offset;

    offset = tb->tb_jmp_offset[n];
    tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
    offset = tb->tb_jmp_offset[n + 2];
    if (offset != 0xffff)
        tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
}

#else

/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb, 
                                     int n, unsigned long addr)
{
    tb->tb_next[n] = addr;
}

#endif

static inline void tb_add_jump(TranslationBlock *tb, int n, 
                               TranslationBlock *tb_next)
{
    /* NOTE: this test is only needed for thread safety */
    if (!tb->jmp_next[n]) {
        /* patch the native jump address */
        tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
        
        /* add in TB jmp circular list */
        tb->jmp_next[n] = tb_next->jmp_first;
        tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
    }
}

TranslationBlock *tb_find_pc(unsigned long pc_ptr);

#ifndef offsetof
#define offsetof(type, field) ((size_t) &((type *)0)->field)
#endif

#if defined(_WIN32)
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".section .text\n"
#elif defined(__APPLE__)
#define ASM_DATA_SECTION ".data\n"
#define ASM_PREVIOUS_SECTION ".text\n"
#else
#define ASM_DATA_SECTION ".section \".data\"\n"
#define ASM_PREVIOUS_SECTION ".previous\n"
#endif

#define ASM_OP_LABEL_NAME(n, opname) \
    ASM_NAME(__op_label) #n "." ASM_NAME(opname)

#if defined(__powerpc__)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (ASM_DATA_SECTION\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "b " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#elif defined(__i386__) && defined(USE_DIRECT_JUMP)

/* we patch the jump instruction directly */
#define GOTO_TB(opname, tbparam, n)\
do {\
    asm volatile (".section .data\n"\
		  ASM_OP_LABEL_NAME(n, opname) ":\n"\
		  ".long 1f\n"\
		  ASM_PREVIOUS_SECTION \
                  "jmp " ASM_NAME(__op_jmp) #n "\n"\
		  "1:\n");\
} while (0)

#else

/* jump to next block operations (more portable code, does not need
   cache flushing, but slower because of indirect jump) */
#define GOTO_TB(opname, tbparam, n)\
do {\
    static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
    static void __attribute__((unused)) *__op_label ## n \
        __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
    goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
label ## n: ;\
dummy_label ## n: ;\
} while (0)

#endif

/* XXX: will be suppressed */
#define JUMP_TB(opname, tbparam, n, eip)\
do {\
    GOTO_TB(opname, tbparam, n);\
    T0 = (long)(tbparam) + (n);\
    EIP = (int32_t)eip;\
    EXIT_TB();\
} while (0)

extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];

#ifdef __powerpc__
static inline int testandset (int *p)
{
    int ret;
    __asm__ __volatile__ (
                          "0:    lwarx %0,0,%1\n"
                          "      xor. %0,%3,%0\n"
                          "      bne 1f\n"
                          "      stwcx. %2,0,%1\n"
                          "      bne- 0b\n"
                          "1:    "
                          : "=&r" (ret)
                          : "r" (p), "r" (1), "r" (0)
                          : "cr0", "memory");
    return ret;
}
#endif

#ifdef __i386__
static inline int testandset (int *p)
{
    long int readval = 0;
    
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#endif

#ifdef __x86_64__
static inline int testandset (int *p)
{
    long int readval = 0;
    
    __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
                          : "+m" (*p), "+a" (readval)
                          : "r" (1)
                          : "cc");
    return readval;
}
#endif

#ifdef __s390__
static inline int testandset (int *p)
{
    int ret;

    __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
			  "   jl    0b"
			  : "=&d" (ret)
			  : "r" (1), "a" (p), "0" (*p) 
			  : "cc", "memory" );
    return ret;
}
#endif

#ifdef __alpha__
static inline int testandset (int *p)
{
    int ret;
    unsigned long one;

    __asm__ __volatile__ ("0:	mov 1,%2\n"
			  "	ldl_l %0,%1\n"
			  "	stl_c %2,%1\n"
			  "	beq %2,1f\n"
			  ".subsection 2\n"
			  "1:	br 0b\n"
			  ".previous"
			  : "=r" (ret), "=m" (*p), "=r" (one)
			  : "m" (*p));
    return ret;
}
#endif

#ifdef __sparc__
static inline int testandset (int *p)
{
	int ret;

	__asm__ __volatile__("ldstub	[%1], %0"
			     : "=r" (ret)
			     : "r" (p)
			     : "memory");

	return (ret ? 1 : 0);
}
#endif

#ifdef __arm__
static inline int testandset (int *spinlock)
{
    register unsigned int ret;
    __asm__ __volatile__("swp %0, %1, [%2]"
                         : "=r"(ret)
                         : "0"(1), "r"(spinlock));
    
    return ret;
}
#endif

#ifdef __mc68000
static inline int testandset (int *p)
{
    char ret;
    __asm__ __volatile__("tas %1; sne %0"
                         : "=r" (ret)
                         : "m" (p)
                         : "cc","memory");
    return ret;
}
#endif

#ifdef __ia64
#include <ia64intrin.h>

static inline int testandset (int *p)
{
    return __sync_lock_test_and_set (p, 1);
}
#endif

typedef int spinlock_t;

#define SPIN_LOCK_UNLOCKED 0

#if defined(CONFIG_USER_ONLY)
static inline void spin_lock(spinlock_t *lock)
{
    while (testandset(lock));
}

static inline void spin_unlock(spinlock_t *lock)
{
    *lock = 0;
}

static inline int spin_trylock(spinlock_t *lock)
{
    return !testandset(lock);
}
#else
static inline void spin_lock(spinlock_t *lock)
{
}

static inline void spin_unlock(spinlock_t *lock)
{
}

static inline int spin_trylock(spinlock_t *lock)
{
    return 1;
}
#endif

extern spinlock_t tb_lock;

extern int tb_invalidated_flag;

#if !defined(CONFIG_USER_ONLY)

void tlb_fill(target_ulong addr, int is_write, int is_user, 
              void *retaddr);

#define ACCESS_TYPE 3
#define MEMSUFFIX _code
#define env cpu_single_env

#define DATA_SIZE 1
#include "softmmu_header.h"

#define DATA_SIZE 2
#include "softmmu_header.h"

#define DATA_SIZE 4
#include "softmmu_header.h"

#define DATA_SIZE 8
#include "softmmu_header.h"

#undef ACCESS_TYPE
#undef MEMSUFFIX
#undef env

#endif

#if defined(CONFIG_USER_ONLY)
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
   is the offset relative to phys_ram_base */
static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
{
    int is_user, index, pd;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
#if defined(TARGET_I386)
    is_user = ((env->hflags & HF_CPL_MASK) == 3);
#elif defined (TARGET_PPC)
    is_user = msr_pr;
#elif defined (TARGET_MIPS)
    is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
#elif defined (TARGET_SPARC)
    is_user = (env->psrs == 0);
#else
#error "Unimplemented !"
#endif
    if (__builtin_expect(env->tlb_read[is_user][index].address != 
                         (addr & TARGET_PAGE_MASK), 0)) {
        ldub_code(addr);
    }
    pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
    if (pd > IO_MEM_ROM) {
        cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
    }
    return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
}
#endif


#ifdef USE_KQEMU
int kqemu_init(CPUState *env);
int kqemu_cpu_exec(CPUState *env);
void kqemu_flush_page(CPUState *env, target_ulong addr);
void kqemu_flush(CPUState *env, int global);
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);

static inline int kqemu_is_ok(CPUState *env)
{
    return(env->kqemu_enabled &&
           (env->hflags & HF_CPL_MASK) == 3 &&
           (env->eflags & IOPL_MASK) != IOPL_MASK &&
           (env->cr[0] & CR0_PE_MASK) && 
           (env->eflags & IF_MASK) &&
           !(env->eflags & VM_MASK)
#if 1
           && (env->ldt.limit == 0 || env->ldt.limit == 0x27)
#endif
           );
}

#endif
Commit	Line	Data
d4e8164f FB	1	/*
	2	* internal execution defines for qemu
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
b346ff46 FB	21	/* allow to see translation results - the slowdown should be negligible, so we leave it */
	22	#define DEBUG_DISAS
	23
33417e70 FB	24	#ifndef glue
	25	#define xglue(x, y) x ## y
	26	#define glue(x, y) xglue(x, y)
	27	#define stringify(s) tostring(s)
	28	#define tostring(s) #s
	29	#endif
	30
c98baaac	31	#if __GNUC__ < 3
33417e70 FB	32	#define __builtin_expect(x, n) (x)
	33	#endif
	34
e2222c39 FB	35	#ifdef __i386__
	36	#define REGPARM(n) __attribute((regparm(n)))
	37	#else
	38	#define REGPARM(n)
	39	#endif
	40
b346ff46 FB	41	/* is_jmp field values */
	42	#define DISAS_NEXT 0 /* next instruction can be analyzed */
	43	#define DISAS_JUMP 1 /* only pc was modified dynamically */
	44	#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
	45	#define DISAS_TB_JUMP 3 /* only pc was modified statically */
	46
	47	struct TranslationBlock;
	48
	49	/* XXX: make safe guess about sizes */
	50	#define MAX_OP_PER_INSTR 32
	51	#define OPC_BUF_SIZE 512
	52	#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
	53
	54	#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
	55
	56	extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
	57	extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
c27004ec FB	58	extern long gen_labels[OPC_BUF_SIZE];
	59	extern int nb_gen_labels;
	60	extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
	61	extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
66e85a21	62	extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
b346ff46	63	extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
c3278b7b	64	extern target_ulong gen_opc_jump_pc[2];
b346ff46	65
9886cc16 FB	66	typedef void (GenOpFunc)(void);
	67	typedef void (GenOpFunc1)(long);
	68	typedef void (GenOpFunc2)(long, long);
	69	typedef void (GenOpFunc3)(long, long, long);
	70
b346ff46 FB	71	#if defined(TARGET_I386)
b346ff46 FB	72
33417e70	73	void optimize_flags_init(void);
d4e8164f	74
b346ff46 FB	75	#endif
	76
	77	extern FILE *logfile;
	78	extern int loglevel;
	79
4c3a88a2 FB	80	int gen_intermediate_code(CPUState env, struct TranslationBlock tb);
4c3a88a2 FB	81	int gen_intermediate_code_pc(CPUState env, struct TranslationBlock tb);
b346ff46	82	void dump_ops(const uint16_t opc_buf, const uint32_t opparam_buf);
4c3a88a2	83	int cpu_gen_code(CPUState env, struct TranslationBlock tb,
b346ff46	84	int max_code_size, int *gen_code_size_ptr);
66e85a21	85	int cpu_restore_state(struct TranslationBlock *tb,
58fe2f10 FB	86	CPUState *env, unsigned long searched_pc,
	87	void *puc);
	88	int cpu_gen_code_copy(CPUState env, struct TranslationBlock tb,
	89	int max_code_size, int *gen_code_size_ptr);
	90	int cpu_restore_state_copy(struct TranslationBlock *tb,
	91	CPUState *env, unsigned long searched_pc,
	92	void *puc);
2e12669a	93	void cpu_resume_from_signal(CPUState env1, void puc);
b346ff46	94	void cpu_exec_init(void);
2e12669a FB	95	int page_unprotect(unsigned long address, unsigned long pc, void *puc);
	96	void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
	97	int is_cpu_write_access);
4390df51	98	void tb_invalidate_page_range(target_ulong start, target_ulong end);
2e12669a	99	void tlb_flush_page(CPUState *env, target_ulong addr);
ee8b7021	100	void tlb_flush(CPUState *env, int flush_global);
2e12669a FB	101	int tlb_set_page(CPUState *env, target_ulong vaddr,
2e12669a FB	102	target_phys_addr_t paddr, int prot,
4390df51	103	int is_user, int is_softmmu);
d4e8164f FB	104
	105	#define CODE_GEN_MAX_SIZE 65536
	106	#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
	107
	108	#define CODE_GEN_HASH_BITS 15
	109	#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
	110
4390df51 FB	111	#define CODE_GEN_PHYS_HASH_BITS 15
	112	#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
	113
d4e8164f	114	/* maximum total translate dcode allocated */
4390df51 FB	115
4390df51 FB	116	/* NOTE: the translated code area cannot be too big because on some
c4c7e3e6	117	archs the range of "fast" function calls is limited. Here is a
4390df51 FB	118	summary of the ranges:
	119
	120	i386 : signed 32 bits
	121	arm : signed 26 bits
	122	ppc : signed 24 bits
	123	sparc : signed 32 bits
	124	alpha : signed 23 bits
	125	*/
	126
	127	#if defined(__alpha__)
	128	#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
b8076a74 FB	129	#elif defined(__ia64)
b8076a74 FB	130	#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
4390df51	131	#elif defined(__powerpc__)
c4c7e3e6	132	#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
4390df51	133	#else
c98baaac	134	#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
4390df51 FB	135	#endif
4390df51 FB	136
d4e8164f FB	137	//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
d4e8164f FB	138
4390df51 FB	139	/* estimated block size for TB allocation */
	140	/* XXX: use a per code average code fragment size and modulate it
	141	according to the host CPU */
	142	#if defined(CONFIG_SOFTMMU)
	143	#define CODE_GEN_AVG_BLOCK_SIZE 128
	144	#else
	145	#define CODE_GEN_AVG_BLOCK_SIZE 64
	146	#endif
	147
	148	#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
	149
	150	#if defined(__powerpc__)
	151	#define USE_DIRECT_JUMP
	152	#endif
67b915a5	153	#if defined(__i386__) && !defined(_WIN32)
d4e8164f FB	154	#define USE_DIRECT_JUMP
	155	#endif
	156
	157	typedef struct TranslationBlock {
2e12669a FB	158	target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
2e12669a FB	159	target_ulong cs_base; /* CS base for this block */
d4e8164f FB	160	unsigned int flags; /* flags defining in which context the code was generated */
	161	uint16_t size; /* size of target code for this block (1 <=
	162	size <= TARGET_PAGE_SIZE) */
58fe2f10	163	uint16_t cflags; /* compile flags */
bf088061 FB	164	#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
	165	#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
	166	#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
2e12669a	167	#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
58fe2f10	168
d4e8164f	169	uint8_t tc_ptr; / pointer to the translated code */
4390df51 FB	170	struct TranslationBlock hash_next; / next matching tb for virtual address */
	171	/* next matching tb for physical address. */
	172	struct TranslationBlock *phys_hash_next;
	173	/* first and second physical page containing code. The lower bit
	174	of the pointer tells the index in page_next[] */
	175	struct TranslationBlock *page_next[2];
	176	target_ulong page_addr[2];
	177
d4e8164f FB	178	/* the following data are used to directly call another TB from
	179	the code of this one. */
	180	uint16_t tb_next_offset[2]; /* offset of original jump target */
	181	#ifdef USE_DIRECT_JUMP
4cbb86e1	182	uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
d4e8164f	183	#else
95f7652d	184	uint32_t tb_next[2]; /* address of jump generated code */
d4e8164f FB	185	#endif
	186	/* list of TBs jumping to this one. This is a circular list using
	187	the two least significant bits of the pointers to tell what is
	188	the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
	189	jmp_first */
	190	struct TranslationBlock *jmp_next[2];
	191	struct TranslationBlock *jmp_first;
	192	} TranslationBlock;
	193
c27004ec	194	static inline unsigned int tb_hash_func(target_ulong pc)
d4e8164f FB	195	{
	196	return pc & (CODE_GEN_HASH_SIZE - 1);
	197	}
	198
4390df51 FB	199	static inline unsigned int tb_phys_hash_func(unsigned long pc)
	200	{
	201	return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
	202	}
	203
c27004ec	204	TranslationBlock *tb_alloc(target_ulong pc);
0124311e	205	void tb_flush(CPUState *env);
d4e8164f	206	void tb_link(TranslationBlock *tb);
4390df51 FB	207	void tb_link_phys(TranslationBlock *tb,
4390df51 FB	208	target_ulong phys_pc, target_ulong phys_page2);
d4e8164f FB	209
d4e8164f FB	210	extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
4390df51	211	extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
d4e8164f FB	212
	213	extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
	214	extern uint8_t *code_gen_ptr;
	215
	216	/* find a translation block in the translation cache. If not found,
	217	return NULL and the pointer to the last element of the list in pptb */
	218	static inline TranslationBlock tb_find(TranslationBlock **pptb,
2e12669a FB	219	target_ulong pc,
2e12669a FB	220	target_ulong cs_base,
d4e8164f FB	221	unsigned int flags)
	222	{
	223	TranslationBlock *ptb, tb;
	224	unsigned int h;
	225
	226	h = tb_hash_func(pc);
	227	ptb = &tb_hash[h];
	228	for(;;) {
	229	tb = *ptb;
	230	if (!tb)
	231	break;
	232	if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
	233	return tb;
	234	ptb = &tb->hash_next;
	235	}
	236	*pptb = ptb;
	237	return NULL;
	238	}
	239
d4e8164f	240
4390df51 FB	241	#if defined(USE_DIRECT_JUMP)
	242
	243	#if defined(__powerpc__)
4cbb86e1	244	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
d4e8164f FB	245	{
d4e8164f FB	246	uint32_t val, *ptr;
d4e8164f FB	247
d4e8164f FB	248	/* patch the branch destination */
4cbb86e1	249	ptr = (uint32_t *)jmp_addr;
d4e8164f	250	val = *ptr;
4cbb86e1	251	val = (val & ~0x03fffffc) \| ((addr - jmp_addr) & 0x03fffffc);
d4e8164f FB	252	*ptr = val;
	253	/* flush icache */
	254	asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
	255	asm volatile ("sync" : : : "memory");
	256	asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
	257	asm volatile ("sync" : : : "memory");
	258	asm volatile ("isync" : : : "memory");
	259	}
4390df51 FB	260	#elif defined(__i386__)
	261	static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
	262	{
	263	/* patch the branch destination */
	264	(uint32_t )jmp_addr = addr - (jmp_addr + 4);
	265	/* no need to flush icache explicitely */
	266	}
	267	#endif
d4e8164f	268
4cbb86e1 FB	269	static inline void tb_set_jmp_target(TranslationBlock *tb,
	270	int n, unsigned long addr)
	271	{
	272	unsigned long offset;
	273
	274	offset = tb->tb_jmp_offset[n];
	275	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	276	offset = tb->tb_jmp_offset[n + 2];
	277	if (offset != 0xffff)
	278	tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
	279	}
	280
d4e8164f FB	281	#else
	282
	283	/* set the jump target */
	284	static inline void tb_set_jmp_target(TranslationBlock *tb,
	285	int n, unsigned long addr)
	286	{
95f7652d	287	tb->tb_next[n] = addr;
d4e8164f FB	288	}
	289
	290	#endif
	291
	292	static inline void tb_add_jump(TranslationBlock *tb, int n,
	293	TranslationBlock *tb_next)
	294	{
cf25629d FB	295	/* NOTE: this test is only needed for thread safety */
	296	if (!tb->jmp_next[n]) {
	297	/* patch the native jump address */
	298	tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
	299
	300	/* add in TB jmp circular list */
	301	tb->jmp_next[n] = tb_next->jmp_first;
	302	tb_next->jmp_first = (TranslationBlock *)((long)(tb) \| (n));
	303	}
d4e8164f FB	304	}
d4e8164f FB	305
a513fe19 FB	306	TranslationBlock *tb_find_pc(unsigned long pc_ptr);
a513fe19 FB	307
d4e8164f FB	308	#ifndef offsetof
	309	#define offsetof(type, field) ((size_t) &((type *)0)->field)
	310	#endif
	311
d549f7d9 FB	312	#if defined(_WIN32)
	313	#define ASM_DATA_SECTION ".section \".data\"\n"
	314	#define ASM_PREVIOUS_SECTION ".section .text\n"
	315	#elif defined(__APPLE__)
	316	#define ASM_DATA_SECTION ".data\n"
	317	#define ASM_PREVIOUS_SECTION ".text\n"
d549f7d9 FB	318	#else
	319	#define ASM_DATA_SECTION ".section \".data\"\n"
	320	#define ASM_PREVIOUS_SECTION ".previous\n"
d549f7d9 FB	321	#endif
d549f7d9 FB	322
75913b72 FB	323	#define ASM_OP_LABEL_NAME(n, opname) \
	324	ASM_NAME(__op_label) #n "." ASM_NAME(opname)
	325
b346ff46 FB	326	#if defined(__powerpc__)
b346ff46 FB	327
4390df51	328	/* we patch the jump instruction directly */
ae063a68	329	#define GOTO_TB(opname, tbparam, n)\
b346ff46	330	do {\
d549f7d9	331	asm volatile (ASM_DATA_SECTION\
75913b72	332	ASM_OP_LABEL_NAME(n, opname) ":\n"\
9257a9e4	333	".long 1f\n"\
d549f7d9 FB	334	ASM_PREVIOUS_SECTION \
d549f7d9 FB	335	"b " ASM_NAME(__op_jmp) #n "\n"\
9257a9e4	336	"1:\n");\
4390df51 FB	337	} while (0)
	338
	339	#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
	340
	341	/* we patch the jump instruction directly */
ae063a68	342	#define GOTO_TB(opname, tbparam, n)\
c27004ec FB	343	do {\
c27004ec FB	344	asm volatile (".section .data\n"\
75913b72	345	ASM_OP_LABEL_NAME(n, opname) ":\n"\
c27004ec FB	346	".long 1f\n"\
	347	ASM_PREVIOUS_SECTION \
	348	"jmp " ASM_NAME(__op_jmp) #n "\n"\
	349	"1:\n");\
	350	} while (0)
	351
b346ff46 FB	352	#else
	353
	354	/* jump to next block operations (more portable code, does not need
	355	cache flushing, but slower because of indirect jump) */
ae063a68	356	#define GOTO_TB(opname, tbparam, n)\
b346ff46	357	do {\
2f62b397	358	static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
75913b72 FB	359	static void __attribute__((unused)) *__op_label ## n \
75913b72 FB	360	__asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\
b346ff46	361	goto (void )(((TranslationBlock *)tbparam)->tb_next[n]);\
ae063a68 FB	362	label ## n: ;\
ae063a68 FB	363	dummy_label ## n: ;\
b346ff46 FB	364	} while (0)
b346ff46 FB	365
ae063a68 FB	366	#endif
	367
	368	/* XXX: will be suppressed */
	369	#define JUMP_TB(opname, tbparam, n, eip)\
4cbb86e1	370	do {\
ae063a68 FB	371	GOTO_TB(opname, tbparam, n);\
	372	T0 = (long)(tbparam) + (n);\
	373	EIP = (int32_t)eip;\
	374	EXIT_TB();\
4cbb86e1 FB	375	} while (0)
4cbb86e1 FB	376
33417e70 FB	377	extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
33417e70 FB	378	extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
a4193c8a	379	extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
33417e70	380
d4e8164f FB	381	#ifdef __powerpc__
	382	static inline int testandset (int *p)
	383	{
	384	int ret;
	385	__asm__ __volatile__ (
02e1ec9b FB	386	"0: lwarx %0,0,%1\n"
	387	" xor. %0,%3,%0\n"
	388	" bne 1f\n"
	389	" stwcx. %2,0,%1\n"
	390	" bne- 0b\n"
d4e8164f FB	391	"1: "
	392	: "=&r" (ret)
	393	: "r" (p), "r" (1), "r" (0)
	394	: "cr0", "memory");
	395	return ret;
	396	}
	397	#endif
	398
	399	#ifdef __i386__
	400	static inline int testandset (int *p)
	401	{
4955a2cd	402	long int readval = 0;
d4e8164f	403
4955a2cd FB	404	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	405	: "+m" (*p), "+a" (readval)
	406	: "r" (1)
	407	: "cc");
	408	return readval;
d4e8164f FB	409	}
	410	#endif
	411
bc51c5c9 FB	412	#ifdef __x86_64__
	413	static inline int testandset (int *p)
	414	{
4955a2cd	415	long int readval = 0;
bc51c5c9	416
4955a2cd FB	417	__asm__ __volatile__ ("lock; cmpxchgl %2, %0"
	418	: "+m" (*p), "+a" (readval)
	419	: "r" (1)
	420	: "cc");
	421	return readval;
bc51c5c9 FB	422	}
	423	#endif
	424
d4e8164f FB	425	#ifdef __s390__
	426	static inline int testandset (int *p)
	427	{
	428	int ret;
	429
	430	__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
	431	" jl 0b"
	432	: "=&d" (ret)
	433	: "r" (1), "a" (p), "0" (*p)
	434	: "cc", "memory" );
	435	return ret;
	436	}
	437	#endif
	438
	439	#ifdef __alpha__
2f87c607	440	static inline int testandset (int *p)
d4e8164f FB	441	{
	442	int ret;
	443	unsigned long one;
	444
	445	__asm__ __volatile__ ("0: mov 1,%2\n"
	446	" ldl_l %0,%1\n"
	447	" stl_c %2,%1\n"
	448	" beq %2,1f\n"
	449	".subsection 2\n"
	450	"1: br 0b\n"
	451	".previous"
	452	: "=r" (ret), "=m" (*p), "=r" (one)
	453	: "m" (*p));
	454	return ret;
	455	}
	456	#endif
	457
	458	#ifdef __sparc__
	459	static inline int testandset (int *p)
	460	{
	461	int ret;
	462
	463	__asm__ __volatile__("ldstub [%1], %0"
	464	: "=r" (ret)
	465	: "r" (p)
	466	: "memory");
	467
	468	return (ret ? 1 : 0);
	469	}
	470	#endif
	471
a95c6790 FB	472	#ifdef __arm__
	473	static inline int testandset (int *spinlock)
	474	{
	475	register unsigned int ret;
	476	__asm__ __volatile__("swp %0, %1, [%2]"
	477	: "=r"(ret)
	478	: "0"(1), "r"(spinlock));
	479
	480	return ret;
	481	}
	482	#endif
	483
38e584a0 FB	484	#ifdef __mc68000
	485	static inline int testandset (int *p)
	486	{
	487	char ret;
	488	__asm__ __volatile__("tas %1; sne %0"
	489	: "=r" (ret)
	490	: "m" (p)
	491	: "cc","memory");
4955a2cd	492	return ret;
38e584a0 FB	493	}
	494	#endif
	495
b8076a74 FB	496	#ifdef __ia64
	497	#include <ia64intrin.h>
	498
	499	static inline int testandset (int *p)
	500	{
	501	return __sync_lock_test_and_set (p, 1);
	502	}
	503	#endif
	504
d4e8164f FB	505	typedef int spinlock_t;
	506
	507	#define SPIN_LOCK_UNLOCKED 0
	508
aebcb60e	509	#if defined(CONFIG_USER_ONLY)
d4e8164f FB	510	static inline void spin_lock(spinlock_t *lock)
	511	{
	512	while (testandset(lock));
	513	}
	514
	515	static inline void spin_unlock(spinlock_t *lock)
	516	{
	517	*lock = 0;
	518	}
	519
	520	static inline int spin_trylock(spinlock_t *lock)
	521	{
	522	return !testandset(lock);
	523	}
3c1cf9fa FB	524	#else
	525	static inline void spin_lock(spinlock_t *lock)
	526	{
	527	}
	528
	529	static inline void spin_unlock(spinlock_t *lock)
	530	{
	531	}
	532
	533	static inline int spin_trylock(spinlock_t *lock)
	534	{
	535	return 1;
	536	}
	537	#endif
d4e8164f FB	538
	539	extern spinlock_t tb_lock;
	540
36bdbe54	541	extern int tb_invalidated_flag;
6e59c1db	542
e95c8d51	543	#if !defined(CONFIG_USER_ONLY)
6e59c1db	544
c27004ec	545	void tlb_fill(target_ulong addr, int is_write, int is_user,
6e59c1db FB	546	void *retaddr);
	547
	548	#define ACCESS_TYPE 3
	549	#define MEMSUFFIX _code
	550	#define env cpu_single_env
	551
	552	#define DATA_SIZE 1
	553	#include "softmmu_header.h"
	554
	555	#define DATA_SIZE 2
	556	#include "softmmu_header.h"
	557
	558	#define DATA_SIZE 4
	559	#include "softmmu_header.h"
	560
c27004ec FB	561	#define DATA_SIZE 8
	562	#include "softmmu_header.h"
	563
6e59c1db FB	564	#undef ACCESS_TYPE
	565	#undef MEMSUFFIX
	566	#undef env
	567
	568	#endif
4390df51 FB	569
	570	#if defined(CONFIG_USER_ONLY)
	571	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
	572	{
	573	return addr;
	574	}
	575	#else
	576	/* NOTE: this function can trigger an exception */
1ccde1cb FB	577	/* NOTE2: the returned address is not exactly the physical address: it
1ccde1cb FB	578	is the offset relative to phys_ram_base */
4390df51 FB	579	static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
4390df51 FB	580	{
c27004ec	581	int is_user, index, pd;
4390df51 FB	582
4390df51 FB	583	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
3f5dcc34	584	#if defined(TARGET_I386)
4390df51	585	is_user = ((env->hflags & HF_CPL_MASK) == 3);
3f5dcc34 FB	586	#elif defined (TARGET_PPC)
3f5dcc34 FB	587	is_user = msr_pr;
6af0bf9c FB	588	#elif defined (TARGET_MIPS)
6af0bf9c FB	589	is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
e95c8d51 FB	590	#elif defined (TARGET_SPARC)
e95c8d51 FB	591	is_user = (env->psrs == 0);
3f5dcc34 FB	592	#else
	593	#error "Unimplemented !"
	594	#endif
4390df51 FB	595	if (__builtin_expect(env->tlb_read[is_user][index].address !=
4390df51 FB	596	(addr & TARGET_PAGE_MASK), 0)) {
c27004ec FB	597	ldub_code(addr);
	598	}
	599	pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;
	600	if (pd > IO_MEM_ROM) {
	601	cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
4390df51 FB	602	}
	603	return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
	604	}
	605	#endif
9df217a3 FB	606
	607
	608	#ifdef USE_KQEMU
9df217a3 FB	609	int kqemu_init(CPUState *env);
	610	int kqemu_cpu_exec(CPUState *env);
	611	void kqemu_flush_page(CPUState *env, target_ulong addr);
	612	void kqemu_flush(CPUState *env, int global);
4b7df22f	613	void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
9df217a3 FB	614
	615	static inline int kqemu_is_ok(CPUState *env)
	616	{
	617	return(env->kqemu_enabled &&
	618	(env->hflags & HF_CPL_MASK) == 3 &&
	619	(env->eflags & IOPL_MASK) != IOPL_MASK &&
	620	(env->cr[0] & CR0_PE_MASK) &&
	621	(env->eflags & IF_MASK) &&
4b7df22f FB	622	!(env->eflags & VM_MASK)
	623	#if 1
	624	&& (env->ldt.limit == 0 \|\| env->ldt.limit == 0x27)
	625	#endif
	626	);
9df217a3 FB	627	}
	628
	629	#endif