[qemu.git] / target-sparc / cpu.h

#ifndef CPU_SPARC_H
#define CPU_SPARC_H

#include "config.h"

#if !defined(TARGET_SPARC64)
#define TARGET_LONG_BITS 32
#define TARGET_FPREGS 32
#define TARGET_PAGE_BITS 12 /* 4k */
#else
#define TARGET_LONG_BITS 64
#define TARGET_FPREGS 64
#define TARGET_PAGE_BITS 13 /* 8k */
#endif

#define TARGET_PHYS_ADDR_BITS 64

#define CPUState struct CPUSPARCState

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#if !defined(TARGET_SPARC64)
#define ELF_MACHINE     EM_SPARC
#else
#define ELF_MACHINE     EM_SPARCV9
#endif

/*#define EXCP_INTERRUPT 0x100*/

/* trap definitions */
#ifndef TARGET_SPARC64
#define TT_TFAULT   0x01
#define TT_ILL_INSN 0x02
#define TT_PRIV_INSN 0x03
#define TT_NFPU_INSN 0x04
#define TT_WIN_OVF  0x05
#define TT_WIN_UNF  0x06
#define TT_UNALIGNED 0x07
#define TT_FP_EXCP  0x08
#define TT_DFAULT   0x09
#define TT_TOVF     0x0a
#define TT_EXTINT   0x10
#define TT_CODE_ACCESS 0x21
#define TT_UNIMP_FLUSH 0x25
#define TT_DATA_ACCESS 0x29
#define TT_DIV_ZERO 0x2a
#define TT_NCP_INSN 0x24
#define TT_TRAP     0x80
#else
#define TT_TFAULT   0x08
#define TT_CODE_ACCESS 0x0a
#define TT_ILL_INSN 0x10
#define TT_UNIMP_FLUSH TT_ILL_INSN
#define TT_PRIV_INSN 0x11
#define TT_NFPU_INSN 0x20
#define TT_FP_EXCP  0x21
#define TT_TOVF     0x23
#define TT_CLRWIN   0x24
#define TT_DIV_ZERO 0x28
#define TT_DFAULT   0x30
#define TT_DATA_ACCESS 0x32
#define TT_UNALIGNED 0x34
#define TT_PRIV_ACT 0x37
#define TT_EXTINT   0x40
#define TT_IVEC     0x60
#define TT_TMISS    0x64
#define TT_DMISS    0x68
#define TT_DPROT    0x6c
#define TT_SPILL    0x80
#define TT_FILL     0xc0
#define TT_WOTHER   0x10
#define TT_TRAP     0x100
#endif

#define PSR_NEG_SHIFT 23
#define PSR_NEG   (1 << PSR_NEG_SHIFT)
#define PSR_ZERO_SHIFT 22
#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
#define PSR_OVF_SHIFT 21
#define PSR_OVF   (1 << PSR_OVF_SHIFT)
#define PSR_CARRY_SHIFT 20
#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
#define PSR_EF    (1<<12)
#define PSR_PIL   0xf00
#define PSR_S     (1<<7)
#define PSR_PS    (1<<6)
#define PSR_ET    (1<<5)
#define PSR_CWP   0x1f

/* Trap base register */
#define TBR_BASE_MASK 0xfffff000

#if defined(TARGET_SPARC64)
#define PS_IG    (1<<11)
#define PS_MG    (1<<10)
#define PS_RMO   (1<<7)
#define PS_RED   (1<<5)
#define PS_PEF   (1<<4)
#define PS_AM    (1<<3)
#define PS_PRIV  (1<<2)
#define PS_IE    (1<<1)
#define PS_AG    (1<<0)

#define FPRS_FEF (1<<2)

#define HS_PRIV  (1<<2)
#endif

/* Fcc */
#define FSR_RD1        (1ULL << 31)
#define FSR_RD0        (1ULL << 30)
#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
#define FSR_RD_NEAREST 0
#define FSR_RD_ZERO    FSR_RD0
#define FSR_RD_POS     FSR_RD1
#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)

#define FSR_NVM   (1ULL << 27)
#define FSR_OFM   (1ULL << 26)
#define FSR_UFM   (1ULL << 25)
#define FSR_DZM   (1ULL << 24)
#define FSR_NXM   (1ULL << 23)
#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)

#define FSR_NVA   (1ULL << 9)
#define FSR_OFA   (1ULL << 8)
#define FSR_UFA   (1ULL << 7)
#define FSR_DZA   (1ULL << 6)
#define FSR_NXA   (1ULL << 5)
#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)

#define FSR_NVC   (1ULL << 4)
#define FSR_OFC   (1ULL << 3)
#define FSR_UFC   (1ULL << 2)
#define FSR_DZC   (1ULL << 1)
#define FSR_NXC   (1ULL << 0)
#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)

#define FSR_FTT2   (1ULL << 16)
#define FSR_FTT1   (1ULL << 15)
#define FSR_FTT0   (1ULL << 14)
//gcc warns about constant overflow for ~FSR_FTT_MASK
//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#ifdef TARGET_SPARC64
#define FSR_FTT_NMASK      0xfffffffffffe3fffULL
#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
#define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
#define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
#else
#define FSR_FTT_NMASK      0xfffe3fffULL
#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
#define FSR_LDFSR_OLDMASK  0x000fc000ULL
#endif
#define FSR_LDFSR_MASK     0xcfc00fffULL
#define FSR_FTT_IEEE_EXCP (1ULL << 14)
#define FSR_FTT_UNIMPFPOP (3ULL << 14)
#define FSR_FTT_SEQ_ERROR (4ULL << 14)
#define FSR_FTT_INVAL_FPR (6ULL << 14)

#define FSR_FCC1_SHIFT 11
#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
#define FSR_FCC0_SHIFT 10
#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)

/* MMU */
#define MMU_E     (1<<0)
#define MMU_NF    (1<<1)

#define PTE_ENTRYTYPE_MASK 3
#define PTE_ACCESS_MASK    0x1c
#define PTE_ACCESS_SHIFT   2
#define PTE_PPN_SHIFT      7
#define PTE_ADDR_MASK      0xffffff00

#define PG_ACCESSED_BIT 5
#define PG_MODIFIED_BIT 6
#define PG_CACHE_BIT    7

#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)

/* 3 <= NWINDOWS <= 32. */
#define MIN_NWINDOWS 3
#define MAX_NWINDOWS 32

#if !defined(TARGET_SPARC64)
#define NB_MMU_MODES 2
#else
#define NB_MMU_MODES 3
typedef struct trap_state {
    uint64_t tpc;
    uint64_t tnpc;
    uint64_t tstate;
    uint32_t tt;
} trap_state;
#endif

typedef struct sparc_def_t {
    const char *name;
    target_ulong iu_version;
    uint32_t fpu_version;
    uint32_t mmu_version;
    uint32_t mmu_bm;
    uint32_t mmu_ctpr_mask;
    uint32_t mmu_cxr_mask;
    uint32_t mmu_sfsr_mask;
    uint32_t mmu_trcr_mask;
    uint32_t mxcc_version;
    uint32_t features;
    uint32_t nwindows;
    uint32_t maxtl;
} sparc_def_t;

#define CPU_FEATURE_FLOAT    (1 << 0)
#define CPU_FEATURE_FLOAT128 (1 << 1)
#define CPU_FEATURE_SWAP     (1 << 2)
#define CPU_FEATURE_MUL      (1 << 3)
#define CPU_FEATURE_DIV      (1 << 4)
#define CPU_FEATURE_FLUSH    (1 << 5)
#define CPU_FEATURE_FSQRT    (1 << 6)
#define CPU_FEATURE_FMUL     (1 << 7)
#define CPU_FEATURE_VIS1     (1 << 8)
#define CPU_FEATURE_VIS2     (1 << 9)
#define CPU_FEATURE_FSMULD   (1 << 10)
#define CPU_FEATURE_HYPV     (1 << 11)
#define CPU_FEATURE_CMT      (1 << 12)
#define CPU_FEATURE_GL       (1 << 13)
#ifndef TARGET_SPARC64
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
#else
#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
enum {
    mmu_us_12, // Ultrasparc < III (64 entry TLB)
    mmu_us_3,  // Ultrasparc III (512 entry TLB)
    mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
    mmu_sun4v, // T1, T2
};
#endif

typedef struct CPUSPARCState {
    target_ulong gregs[8]; /* general registers */
    target_ulong *regwptr; /* pointer to current register window */
    target_ulong pc;       /* program counter */
    target_ulong npc;      /* next program counter */
    target_ulong y;        /* multiply/divide register */

    /* emulator internal flags handling */
    target_ulong cc_src, cc_src2;
    target_ulong cc_dst;

    target_ulong t0, t1; /* temporaries live across basic blocks */
    target_ulong cond; /* conditional branch result (XXX: save it in a
                          temporary register when possible) */

    uint32_t psr;      /* processor state register */
    target_ulong fsr;      /* FPU state register */
    float32 fpr[TARGET_FPREGS];  /* floating point registers */
    uint32_t cwp;      /* index of current register window (extracted
                          from PSR) */
    uint32_t wim;      /* window invalid mask */
    target_ulong tbr;  /* trap base register */
    int      psrs;     /* supervisor mode (extracted from PSR) */
    int      psrps;    /* previous supervisor mode */
    int      psret;    /* enable traps */
    uint32_t psrpil;   /* interrupt blocking level */
    uint32_t pil_in;   /* incoming interrupt level bitmap */
    int      psref;    /* enable fpu */
    target_ulong version;
    int interrupt_index;
    uint32_t nwindows;
    /* NOTE: we allow 8 more registers to handle wrapping */
    target_ulong regbase[MAX_NWINDOWS * 16 + 8];

    CPU_COMMON

    /* MMU regs */
#if defined(TARGET_SPARC64)
    uint64_t lsu;
#define DMMU_E 0x8
#define IMMU_E 0x4
    uint64_t immuregs[16];
    uint64_t dmmuregs[16];
    uint64_t itlb_tag[64];
    uint64_t itlb_tte[64];
    uint64_t dtlb_tag[64];
    uint64_t dtlb_tte[64];
    uint32_t mmu_version;
#else
    uint32_t mmuregs[32];
    uint64_t mxccdata[4];
    uint64_t mxccregs[8];
    uint64_t mmubpregs[4];
    uint64_t prom_addr;
#endif
    /* temporary float registers */
    float64 dt0, dt1;
    float128 qt0, qt1;
    float_status fp_status;
#if defined(TARGET_SPARC64)
#define MAXTL_MAX 8
#define MAXTL_MASK (MAXTL_MAX - 1)
    trap_state *tsptr;
    trap_state ts[MAXTL_MAX];
    uint32_t xcc;               /* Extended integer condition codes */
    uint32_t asi;
    uint32_t pstate;
    uint32_t tl;
    uint32_t maxtl;
    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
    uint64_t agregs[8]; /* alternate general registers */
    uint64_t bgregs[8]; /* backup for normal global registers */
    uint64_t igregs[8]; /* interrupt general registers */
    uint64_t mgregs[8]; /* mmu general registers */
    uint64_t fprs;
    uint64_t tick_cmpr, stick_cmpr;
    void *tick, *stick;
    uint64_t gsr;
    uint32_t gl; // UA2005
    /* UA 2005 hyperprivileged registers */
    uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
    void *hstick; // UA 2005
    uint32_t softint;
#define SOFTINT_TIMER   1
#define SOFTINT_STIMER  (1 << 16)
#endif
    sparc_def_t *def;
} CPUSPARCState;

/* helper.c */
CPUSPARCState *cpu_sparc_init(const char *cpu_model);
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
                                                 ...));
void cpu_lock(void);
void cpu_unlock(void);
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu);
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
void dump_mmu(CPUSPARCState *env);

/* translate.c */
void gen_intermediate_code_init(CPUSPARCState *env);

/* cpu-exec.c */
int cpu_sparc_exec(CPUSPARCState *s);

#define GET_PSR(env) (env->version | (env->psr & PSR_ICC) |             \
                      (env->psref? PSR_EF : 0) |                        \
                      (env->psrpil << 8) |                              \
                      (env->psrs? PSR_S : 0) |                          \
                      (env->psrps? PSR_PS : 0) |                        \
                      (env->psret? PSR_ET : 0) | env->cwp)

#ifndef NO_CPU_IO_DEFS
static inline void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}

static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
{
    /* put the modified wrap registers at their proper location */
    if (env1->cwp == env1->nwindows - 1)
        memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
    env1->cwp = new_cwp;
    /* put the wrap registers at their temporary location */
    if (new_cwp == env1->nwindows - 1)
        memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
    env1->regwptr = env1->regbase + (new_cwp * 16);
}

static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
{
    if (unlikely(cwp >= env1->nwindows))
        cwp -= env1->nwindows;
    return cwp;
}

static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
{
    if (unlikely(cwp < 0))
        cwp += env1->nwindows;
    return cwp;
}
#endif

#define PUT_PSR(env, val) do { int _tmp = val;                          \
        env->psr = _tmp & PSR_ICC;                                      \
        env->psref = (_tmp & PSR_EF)? 1 : 0;                            \
        env->psrpil = (_tmp & PSR_PIL) >> 8;                            \
        env->psrs = (_tmp & PSR_S)? 1 : 0;                              \
        env->psrps = (_tmp & PSR_PS)? 1 : 0;                            \
        env->psret = (_tmp & PSR_ET)? 1 : 0;                            \
        cpu_set_cwp(env, _tmp & PSR_CWP);                               \
    } while (0)

#ifdef TARGET_SPARC64
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
#define PUT_CCR(env, val) do { int _tmp = val;                          \
        env->xcc = (_tmp >> 4) << 20;                                   \
        env->psr = (_tmp & 0xf) << 20;                                  \
    } while (0)
#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)

#ifndef NO_CPU_IO_DEFS
static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
{
    if (unlikely(cwp >= env1->nwindows || cwp < 0))
        cwp = 0;
    cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
}
#endif
#endif

/* cpu-exec.c */
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int is_asi, int size);
int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

#define cpu_init cpu_sparc_init
#define cpu_exec cpu_sparc_exec
#define cpu_gen_code cpu_sparc_gen_code
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list

#define CPU_SAVE_VERSION 5

/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
#ifdef TARGET_SPARC64
#define MMU_MODE2_SUFFIX _hypv
#endif
#define MMU_USER_IDX   0
#define MMU_KERNEL_IDX 1
#define MMU_HYPV_IDX   2

static inline int cpu_mmu_index(CPUState *env1)
{
#if defined(CONFIG_USER_ONLY)
    return MMU_USER_IDX;
#elif !defined(TARGET_SPARC64)
    return env1->psrs;
#else
    if (!env1->psrs)
        return MMU_USER_IDX;
    else if ((env1->hpstate & HS_PRIV) == 0)
        return MMU_KERNEL_IDX;
    else
        return MMU_HYPV_IDX;
#endif
}

static inline int cpu_fpu_enabled(CPUState *env1)
{
#if defined(CONFIG_USER_ONLY)
    return 1;
#elif !defined(TARGET_SPARC64)
    return env1->psref;
#else
    return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
#endif
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
    if (newsp)
        env->regwptr[22] = newsp;
    env->regwptr[0] = 0;
    /* FIXME: Do we also need to clear CF?  */
    /* XXXXX */
    printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
}
#endif

#include "cpu-all.h"
#include "exec-all.h"

/* sum4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);

#ifdef TARGET_SPARC64
/* sun4u.c */
void cpu_tick_set_count(void *opaque, uint64_t count);
uint64_t cpu_tick_get_count(void *opaque);
void cpu_tick_set_limit(void *opaque, uint64_t limit);
#endif

static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
    env->npc = tb->cs_base;
}

static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *flags)
{
    *pc = env->pc;
    *cs_base = env->npc;
#ifdef TARGET_SPARC64
    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
    *flags = ((env->pstate & PS_AM) << 2)
        | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
        | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
#else
    // FPU enable . Supervisor
    *flags = (env->psref << 4) | env->psrs;
#endif
}

#endif
Commit	Line	Data
7a3f1944 FB	1	#ifndef CPU_SPARC_H
	2	#define CPU_SPARC_H
	3
af7bf89b FB	4	#include "config.h"
	5
	6	#if !defined(TARGET_SPARC64)
3cf1e035	7	#define TARGET_LONG_BITS 32
af7bf89b	8	#define TARGET_FPREGS 32
83469015	9	#define TARGET_PAGE_BITS 12 /* 4k */
af7bf89b FB	10	#else
	11	#define TARGET_LONG_BITS 64
	12	#define TARGET_FPREGS 64
33b37802	13	#define TARGET_PAGE_BITS 13 /* 8k */
af7bf89b	14	#endif
3cf1e035	15
92b72cbc BS	16	#define TARGET_PHYS_ADDR_BITS 64
92b72cbc BS	17
c2764719 PB	18	#define CPUState struct CPUSPARCState
c2764719 PB	19
7a3f1944 FB	20	#include "cpu-defs.h"
7a3f1944 FB	21
7a0e1f41 FB	22	#include "softfloat.h"
7a0e1f41 FB	23
1fddef4b FB	24	#define TARGET_HAS_ICE 1
1fddef4b FB	25
9042c0e2	26	#if !defined(TARGET_SPARC64)
0f8a249a	27	#define ELF_MACHINE EM_SPARC
9042c0e2	28	#else
0f8a249a	29	#define ELF_MACHINE EM_SPARCV9
9042c0e2 TS	30	#endif
9042c0e2 TS	31
7a3f1944 FB	32	/#define EXCP_INTERRUPT 0x100/
7a3f1944 FB	33
cf495bcf	34	/* trap definitions */
3475187d	35	#ifndef TARGET_SPARC64
878d3096	36	#define TT_TFAULT 0x01
cf495bcf	37	#define TT_ILL_INSN 0x02
e8af50a3	38	#define TT_PRIV_INSN 0x03
e80cfcfc	39	#define TT_NFPU_INSN 0x04
cf495bcf	40	#define TT_WIN_OVF 0x05
5fafdf24	41	#define TT_WIN_UNF 0x06
d2889a3e	42	#define TT_UNALIGNED 0x07
e8af50a3	43	#define TT_FP_EXCP 0x08
878d3096	44	#define TT_DFAULT 0x09
e32f879d	45	#define TT_TOVF 0x0a
878d3096	46	#define TT_EXTINT 0x10
1b2e93c1	47	#define TT_CODE_ACCESS 0x21
64a88d5d	48	#define TT_UNIMP_FLUSH 0x25
b4f0a316	49	#define TT_DATA_ACCESS 0x29
cf495bcf	50	#define TT_DIV_ZERO 0x2a
fcc72045	51	#define TT_NCP_INSN 0x24
cf495bcf	52	#define TT_TRAP 0x80
3475187d FB	53	#else
3475187d FB	54	#define TT_TFAULT 0x08
1b2e93c1	55	#define TT_CODE_ACCESS 0x0a
3475187d	56	#define TT_ILL_INSN 0x10
64a88d5d	57	#define TT_UNIMP_FLUSH TT_ILL_INSN
3475187d FB	58	#define TT_PRIV_INSN 0x11
	59	#define TT_NFPU_INSN 0x20
	60	#define TT_FP_EXCP 0x21
e32f879d	61	#define TT_TOVF 0x23
3475187d FB	62	#define TT_CLRWIN 0x24
	63	#define TT_DIV_ZERO 0x28
	64	#define TT_DFAULT 0x30
b4f0a316	65	#define TT_DATA_ACCESS 0x32
d2889a3e	66	#define TT_UNALIGNED 0x34
83469015	67	#define TT_PRIV_ACT 0x37
3475187d	68	#define TT_EXTINT 0x40
74b9decc	69	#define TT_IVEC 0x60
e19e4efe BS	70	#define TT_TMISS 0x64
e19e4efe BS	71	#define TT_DMISS 0x68
74b9decc	72	#define TT_DPROT 0x6c
3475187d FB	73	#define TT_SPILL 0x80
	74	#define TT_FILL 0xc0
	75	#define TT_WOTHER 0x10
	76	#define TT_TRAP 0x100
	77	#endif
7a3f1944	78
4b8b8b76 BS	79	#define PSR_NEG_SHIFT 23
	80	#define PSR_NEG (1 << PSR_NEG_SHIFT)
	81	#define PSR_ZERO_SHIFT 22
	82	#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
	83	#define PSR_OVF_SHIFT 21
	84	#define PSR_OVF (1 << PSR_OVF_SHIFT)
	85	#define PSR_CARRY_SHIFT 20
	86	#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
e8af50a3	87	#define PSR_ICC (PSR_NEG\|PSR_ZERO\|PSR_OVF\|PSR_CARRY)
e80cfcfc FB	88	#define PSR_EF (1<<12)
e80cfcfc FB	89	#define PSR_PIL 0xf00
e8af50a3 FB	90	#define PSR_S (1<<7)
	91	#define PSR_PS (1<<6)
	92	#define PSR_ET (1<<5)
	93	#define PSR_CWP 0x1f
e8af50a3 FB	94
	95	/* Trap base register */
	96	#define TBR_BASE_MASK 0xfffff000
	97
3475187d	98	#if defined(TARGET_SPARC64)
83469015 FB	99	#define PS_IG (1<<11)
83469015 FB	100	#define PS_MG (1<<10)
6ef905f6	101	#define PS_RMO (1<<7)
83469015	102	#define PS_RED (1<<5)
3475187d FB	103	#define PS_PEF (1<<4)
	104	#define PS_AM (1<<3)
	105	#define PS_PRIV (1<<2)
	106	#define PS_IE (1<<1)
83469015	107	#define PS_AG (1<<0)
a80dde08 FB	108
a80dde08 FB	109	#define FPRS_FEF (1<<2)
6f27aba6 BS	110
6f27aba6 BS	111	#define HS_PRIV (1<<2)
3475187d FB	112	#endif
3475187d FB	113
e8af50a3	114	/* Fcc */
ba6a9d8c BS	115	#define FSR_RD1 (1ULL << 31)
ba6a9d8c BS	116	#define FSR_RD0 (1ULL << 30)
e8af50a3 FB	117	#define FSR_RD_MASK (FSR_RD1 \| FSR_RD0)
	118	#define FSR_RD_NEAREST 0
	119	#define FSR_RD_ZERO FSR_RD0
	120	#define FSR_RD_POS FSR_RD1
	121	#define FSR_RD_NEG (FSR_RD1 \| FSR_RD0)
	122
ba6a9d8c BS	123	#define FSR_NVM (1ULL << 27)
	124	#define FSR_OFM (1ULL << 26)
	125	#define FSR_UFM (1ULL << 25)
	126	#define FSR_DZM (1ULL << 24)
	127	#define FSR_NXM (1ULL << 23)
e8af50a3 FB	128	#define FSR_TEM_MASK (FSR_NVM \| FSR_OFM \| FSR_UFM \| FSR_DZM \| FSR_NXM)
e8af50a3 FB	129
ba6a9d8c BS	130	#define FSR_NVA (1ULL << 9)
	131	#define FSR_OFA (1ULL << 8)
	132	#define FSR_UFA (1ULL << 7)
	133	#define FSR_DZA (1ULL << 6)
	134	#define FSR_NXA (1ULL << 5)
e8af50a3 FB	135	#define FSR_AEXC_MASK (FSR_NVA \| FSR_OFA \| FSR_UFA \| FSR_DZA \| FSR_NXA)
e8af50a3 FB	136
ba6a9d8c BS	137	#define FSR_NVC (1ULL << 4)
	138	#define FSR_OFC (1ULL << 3)
	139	#define FSR_UFC (1ULL << 2)
	140	#define FSR_DZC (1ULL << 1)
	141	#define FSR_NXC (1ULL << 0)
e8af50a3 FB	142	#define FSR_CEXC_MASK (FSR_NVC \| FSR_OFC \| FSR_UFC \| FSR_DZC \| FSR_NXC)
e8af50a3 FB	143
ba6a9d8c BS	144	#define FSR_FTT2 (1ULL << 16)
	145	#define FSR_FTT1 (1ULL << 15)
	146	#define FSR_FTT0 (1ULL << 14)
47ad35f1 BS	147	//gcc warns about constant overflow for ~FSR_FTT_MASK
	148	//#define FSR_FTT_MASK (FSR_FTT2 \| FSR_FTT1 \| FSR_FTT0)
	149	#ifdef TARGET_SPARC64
	150	#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
	151	#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
3a3b925d BS	152	#define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL
	153	#define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL
	154	#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
47ad35f1 BS	155	#else
	156	#define FSR_FTT_NMASK 0xfffe3fffULL
	157	#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
3a3b925d	158	#define FSR_LDFSR_OLDMASK 0x000fc000ULL
47ad35f1	159	#endif
3a3b925d	160	#define FSR_LDFSR_MASK 0xcfc00fffULL
ba6a9d8c BS	161	#define FSR_FTT_IEEE_EXCP (1ULL << 14)
	162	#define FSR_FTT_UNIMPFPOP (3ULL << 14)
	163	#define FSR_FTT_SEQ_ERROR (4ULL << 14)
	164	#define FSR_FTT_INVAL_FPR (6ULL << 14)
e8af50a3	165
4b8b8b76	166	#define FSR_FCC1_SHIFT 11
ba6a9d8c	167	#define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT)
4b8b8b76	168	#define FSR_FCC0_SHIFT 10
ba6a9d8c	169	#define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT)
e8af50a3 FB	170
e8af50a3 FB	171	/* MMU */
0f8a249a BS	172	#define MMU_E (1<<0)
0f8a249a BS	173	#define MMU_NF (1<<1)
e8af50a3 FB	174
	175	#define PTE_ENTRYTYPE_MASK 3
	176	#define PTE_ACCESS_MASK 0x1c
	177	#define PTE_ACCESS_SHIFT 2
8d5f07fa	178	#define PTE_PPN_SHIFT 7
e8af50a3 FB	179	#define PTE_ADDR_MASK 0xffffff00
e8af50a3 FB	180
0f8a249a BS	181	#define PG_ACCESSED_BIT 5
0f8a249a BS	182	#define PG_MODIFIED_BIT 6
e8af50a3 FB	183	#define PG_CACHE_BIT 7
	184
	185	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	186	#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
	187	#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
	188
1a14026e BS	189	/* 3 <= NWINDOWS <= 32. */
	190	#define MIN_NWINDOWS 3
	191	#define MAX_NWINDOWS 32
cf495bcf	192
6f27aba6	193	#if !defined(TARGET_SPARC64)
6ebbf390	194	#define NB_MMU_MODES 2
6f27aba6 BS	195	#else
6f27aba6 BS	196	#define NB_MMU_MODES 3
375ee38b BS	197	typedef struct trap_state {
	198	uint64_t tpc;
	199	uint64_t tnpc;
	200	uint64_t tstate;
	201	uint32_t tt;
	202	} trap_state;
6f27aba6	203	#endif
6ebbf390	204
5578ceab BS	205	typedef struct sparc_def_t {
	206	const char *name;
	207	target_ulong iu_version;
	208	uint32_t fpu_version;
	209	uint32_t mmu_version;
	210	uint32_t mmu_bm;
	211	uint32_t mmu_ctpr_mask;
	212	uint32_t mmu_cxr_mask;
	213	uint32_t mmu_sfsr_mask;
	214	uint32_t mmu_trcr_mask;
963262de	215	uint32_t mxcc_version;
5578ceab BS	216	uint32_t features;
	217	uint32_t nwindows;
	218	uint32_t maxtl;
	219	} sparc_def_t;
	220
	221	#define CPU_FEATURE_FLOAT (1 << 0)
	222	#define CPU_FEATURE_FLOAT128 (1 << 1)
	223	#define CPU_FEATURE_SWAP (1 << 2)
	224	#define CPU_FEATURE_MUL (1 << 3)
	225	#define CPU_FEATURE_DIV (1 << 4)
	226	#define CPU_FEATURE_FLUSH (1 << 5)
	227	#define CPU_FEATURE_FSQRT (1 << 6)
	228	#define CPU_FEATURE_FMUL (1 << 7)
	229	#define CPU_FEATURE_VIS1 (1 << 8)
	230	#define CPU_FEATURE_VIS2 (1 << 9)
	231	#define CPU_FEATURE_FSMULD (1 << 10)
	232	#define CPU_FEATURE_HYPV (1 << 11)
	233	#define CPU_FEATURE_CMT (1 << 12)
	234	#define CPU_FEATURE_GL (1 << 13)
	235	#ifndef TARGET_SPARC64
	236	#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT \| CPU_FEATURE_SWAP \| \
	237	CPU_FEATURE_MUL \| CPU_FEATURE_DIV \| \
	238	CPU_FEATURE_FLUSH \| CPU_FEATURE_FSQRT \| \
	239	CPU_FEATURE_FMUL \| CPU_FEATURE_FSMULD)
	240	#else
	241	#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT \| CPU_FEATURE_SWAP \| \
	242	CPU_FEATURE_MUL \| CPU_FEATURE_DIV \| \
	243	CPU_FEATURE_FLUSH \| CPU_FEATURE_FSQRT \| \
	244	CPU_FEATURE_FMUL \| CPU_FEATURE_VIS1 \| \
	245	CPU_FEATURE_VIS2 \| CPU_FEATURE_FSMULD)
	246	enum {
	247	mmu_us_12, // Ultrasparc < III (64 entry TLB)
	248	mmu_us_3, // Ultrasparc III (512 entry TLB)
	249	mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
	250	mmu_sun4v, // T1, T2
	251	};
	252	#endif
	253
7a3f1944	254	typedef struct CPUSPARCState {
af7bf89b FB	255	target_ulong gregs[8]; /* general registers */
af7bf89b FB	256	target_ulong regwptr; / pointer to current register window */
af7bf89b FB	257	target_ulong pc; /* program counter */
	258	target_ulong npc; /* next program counter */
	259	target_ulong y; /* multiply/divide register */
dc99a3f2 BS	260
dc99a3f2 BS	261	/* emulator internal flags handling */
d9bdab86	262	target_ulong cc_src, cc_src2;
dc99a3f2 BS	263	target_ulong cc_dst;
dc99a3f2 BS	264
7c60cc4b FB	265	target_ulong t0, t1; /* temporaries live across basic blocks */
	266	target_ulong cond; /* conditional branch result (XXX: save it in a
	267	temporary register when possible) */
	268
cf495bcf	269	uint32_t psr; /* processor state register */
3475187d	270	target_ulong fsr; /* FPU state register */
7c60cc4b	271	float32 fpr[TARGET_FPREGS]; /* floating point registers */
cf495bcf FB	272	uint32_t cwp; /* index of current register window (extracted
	273	from PSR) */
	274	uint32_t wim; /* window invalid mask */
3475187d	275	target_ulong tbr; /* trap base register */
e8af50a3 FB	276	int psrs; /* supervisor mode (extracted from PSR) */
	277	int psrps; /* previous supervisor mode */
	278	int psret; /* enable traps */
327ac2e7 BS	279	uint32_t psrpil; /* interrupt blocking level */
327ac2e7 BS	280	uint32_t pil_in; /* incoming interrupt level bitmap */
e80cfcfc	281	int psref; /* enable fpu */
62724a37	282	target_ulong version;
cf495bcf	283	int interrupt_index;
1a14026e	284	uint32_t nwindows;
cf495bcf	285	/* NOTE: we allow 8 more registers to handle wrapping */
1a14026e	286	target_ulong regbase[MAX_NWINDOWS * 16 + 8];
d720b93d	287
a316d335 FB	288	CPU_COMMON
a316d335 FB	289
e8af50a3	290	/* MMU regs */
3475187d FB	291	#if defined(TARGET_SPARC64)
	292	uint64_t lsu;
	293	#define DMMU_E 0x8
	294	#define IMMU_E 0x4
	295	uint64_t immuregs[16];
	296	uint64_t dmmuregs[16];
	297	uint64_t itlb_tag[64];
	298	uint64_t itlb_tte[64];
	299	uint64_t dtlb_tag[64];
	300	uint64_t dtlb_tte[64];
fb79ceb9	301	uint32_t mmu_version;
3475187d	302	#else
3dd9a152	303	uint32_t mmuregs[32];
952a328f BS	304	uint64_t mxccdata[4];
952a328f BS	305	uint64_t mxccregs[8];
4017190e	306	uint64_t mmubpregs[4];
3ebf5aaf	307	uint64_t prom_addr;
3475187d	308	#endif
e8af50a3	309	/* temporary float registers */
65ce8c2f	310	float64 dt0, dt1;
1f587329	311	float128 qt0, qt1;
7a0e1f41	312	float_status fp_status;
af7bf89b	313	#if defined(TARGET_SPARC64)
c19148bd BS	314	#define MAXTL_MAX 8
c19148bd BS	315	#define MAXTL_MASK (MAXTL_MAX - 1)
375ee38b	316	trap_state *tsptr;
c19148bd	317	trap_state ts[MAXTL_MAX];
0f8a249a	318	uint32_t xcc; /* Extended integer condition codes */
3475187d FB	319	uint32_t asi;
	320	uint32_t pstate;
	321	uint32_t tl;
c19148bd	322	uint32_t maxtl;
3475187d	323	uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
83469015 FB	324	uint64_t agregs[8]; /* alternate general registers */
	325	uint64_t bgregs[8]; /* backup for normal global registers */
	326	uint64_t igregs[8]; /* interrupt general registers */
	327	uint64_t mgregs[8]; /* mmu general registers */
3475187d	328	uint64_t fprs;
83469015	329	uint64_t tick_cmpr, stick_cmpr;
20c9f095	330	void tick, stick;
725cb90b	331	uint64_t gsr;
e9ebed4d BS	332	uint32_t gl; // UA2005
e9ebed4d BS	333	/* UA 2005 hyperprivileged registers */
c19148bd	334	uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
20c9f095	335	void *hstick; // UA 2005
9d926598	336	uint32_t softint;
8fa211e8 BS	337	#define SOFTINT_TIMER 1
8fa211e8 BS	338	#define SOFTINT_STIMER (1 << 16)
3475187d	339	#endif
5578ceab	340	sparc_def_t *def;
7a3f1944	341	} CPUSPARCState;
64a88d5d	342
91736d37	343	/* helper.c */
aaed909a	344	CPUSPARCState cpu_sparc_init(const char cpu_model);
91736d37	345	void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
62724a37 BS	346	void sparc_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt,
62724a37 BS	347	...));
48585ec5 BS	348	void cpu_lock(void);
	349	void cpu_unlock(void);
	350	int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
	351	int mmu_idx, int is_softmmu);
	352	target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
	353	void dump_mmu(CPUSPARCState *env);
91736d37 BS	354
	355	/* translate.c */
	356	void gen_intermediate_code_init(CPUSPARCState *env);
	357
	358	/* cpu-exec.c */
	359	int cpu_sparc_exec(CPUSPARCState *s);
7a3f1944	360
62724a37	361	#define GET_PSR(env) (env->version \| (env->psr & PSR_ICC) \| \
0f8a249a BS	362	(env->psref? PSR_EF : 0) \| \
	363	(env->psrpil << 8) \| \
	364	(env->psrs? PSR_S : 0) \| \
	365	(env->psrps? PSR_PS : 0) \| \
	366	(env->psret? PSR_ET : 0) \| env->cwp)
b4ff5987 FB	367
b4ff5987 FB	368	#ifndef NO_CPU_IO_DEFS
91736d37 BS	369	static inline void memcpy32(target_ulong dst, const target_ulong src)
	370	{
	371	dst[0] = src[0];
	372	dst[1] = src[1];
	373	dst[2] = src[2];
	374	dst[3] = src[3];
	375	dst[4] = src[4];
	376	dst[5] = src[5];
	377	dst[6] = src[6];
	378	dst[7] = src[7];
	379	}
	380
	381	static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
	382	{
	383	/* put the modified wrap registers at their proper location */
	384	if (env1->cwp == env1->nwindows - 1)
	385	memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16);
	386	env1->cwp = new_cwp;
	387	/* put the wrap registers at their temporary location */
	388	if (new_cwp == env1->nwindows - 1)
	389	memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase);
	390	env1->regwptr = env1->regbase + (new_cwp * 16);
	391	}
1a14026e BS	392
	393	static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
	394	{
	395	if (unlikely(cwp >= env1->nwindows))
	396	cwp -= env1->nwindows;
	397	return cwp;
	398	}
	399
	400	static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
	401	{
	402	if (unlikely(cwp < 0))
	403	cwp += env1->nwindows;
	404	return cwp;
	405	}
b4ff5987 FB	406	#endif
b4ff5987 FB	407
0f8a249a BS	408	#define PUT_PSR(env, val) do { int _tmp = val; \
	409	env->psr = _tmp & PSR_ICC; \
	410	env->psref = (_tmp & PSR_EF)? 1 : 0; \
	411	env->psrpil = (_tmp & PSR_PIL) >> 8; \
	412	env->psrs = (_tmp & PSR_S)? 1 : 0; \
	413	env->psrps = (_tmp & PSR_PS)? 1 : 0; \
	414	env->psret = (_tmp & PSR_ET)? 1 : 0; \
d4218d99	415	cpu_set_cwp(env, _tmp & PSR_CWP); \
b4ff5987 FB	416	} while (0)
b4ff5987 FB	417
3475187d	418	#ifdef TARGET_SPARC64
17d996e1	419	#define GET_CCR(env) (((env->xcc >> 20) << 4) \| ((env->psr & PSR_ICC) >> 20))
0f8a249a	420	#define PUT_CCR(env, val) do { int _tmp = val; \
77f193da	421	env->xcc = (_tmp >> 4) << 20; \
0f8a249a	422	env->psr = (_tmp & 0xf) << 20; \
3475187d	423	} while (0)
1a14026e BS	424	#define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp)
1a14026e BS	425
0bbd4a0d	426	#ifndef NO_CPU_IO_DEFS
1a14026e BS	427	static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
	428	{
	429	if (unlikely(cwp >= env1->nwindows \|\| cwp < 0))
	430	cwp = 0;
	431	cpu_set_cwp(env1, env1->nwindows - 1 - cwp);
	432	}
0bbd4a0d	433	#endif
3475187d FB	434	#endif
3475187d FB	435
91736d37	436	/* cpu-exec.c */
5dcb6b91	437	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
e18231a3	438	int is_asi, int size);
f0d5e471	439	int cpu_sparc_signal_handler(int host_signum, void pinfo, void puc);
7a3f1944	440
9467d44c TS	441	#define cpu_init cpu_sparc_init
	442	#define cpu_exec cpu_sparc_exec
	443	#define cpu_gen_code cpu_sparc_gen_code
	444	#define cpu_signal_handler cpu_sparc_signal_handler
c732abe2	445	#define cpu_list sparc_cpu_list
9467d44c	446
0b8f1b10	447	#define CPU_SAVE_VERSION 5
b3c7724c	448
6ebbf390	449	/* MMU modes definitions */
6f27aba6 BS	450	#define MMU_MODE0_SUFFIX _user
	451	#define MMU_MODE1_SUFFIX _kernel
	452	#ifdef TARGET_SPARC64
	453	#define MMU_MODE2_SUFFIX _hypv
	454	#endif
9e31b9e2 BS	455	#define MMU_USER_IDX 0
	456	#define MMU_KERNEL_IDX 1
	457	#define MMU_HYPV_IDX 2
	458
22548760	459	static inline int cpu_mmu_index(CPUState *env1)
6ebbf390	460	{
6f27aba6	461	#if defined(CONFIG_USER_ONLY)
9e31b9e2	462	return MMU_USER_IDX;
6f27aba6	463	#elif !defined(TARGET_SPARC64)
22548760	464	return env1->psrs;
6f27aba6	465	#else
22548760	466	if (!env1->psrs)
9e31b9e2	467	return MMU_USER_IDX;
22548760	468	else if ((env1->hpstate & HS_PRIV) == 0)
9e31b9e2	469	return MMU_KERNEL_IDX;
6f27aba6	470	else
9e31b9e2	471	return MMU_HYPV_IDX;
6f27aba6 BS	472	#endif
	473	}
	474
22548760	475	static inline int cpu_fpu_enabled(CPUState *env1)
6f27aba6 BS	476	{
	477	#if defined(CONFIG_USER_ONLY)
	478	return 1;
	479	#elif !defined(TARGET_SPARC64)
22548760	480	return env1->psref;
6f27aba6	481	#else
22548760	482	return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);
6f27aba6	483	#endif
6ebbf390 JM	484	}
6ebbf390 JM	485
6e68e076 PB	486	#if defined(CONFIG_USER_ONLY)
	487	static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
	488	{
f8ed7070	489	if (newsp)
6e68e076 PB	490	env->regwptr[22] = newsp;
	491	env->regwptr[0] = 0;
	492	/* FIXME: Do we also need to clear CF? */
	493	/* XXXXX */
	494	printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
	495	}
	496	#endif
	497
7a3f1944	498	#include "cpu-all.h"
622ed360	499	#include "exec-all.h"
7a3f1944	500
48585ec5 BS	501	/* sum4m.c, sun4u.c */
	502	void cpu_check_irqs(CPUSPARCState *env);
	503
f4b1a842 BS	504	#ifdef TARGET_SPARC64
	505	/* sun4u.c */
	506	void cpu_tick_set_count(void *opaque, uint64_t count);
	507	uint64_t cpu_tick_get_count(void *opaque);
	508	void cpu_tick_set_limit(void *opaque, uint64_t limit);
	509	#endif
	510
622ed360 AL	511	static inline void cpu_pc_from_tb(CPUState env, TranslationBlock tb)
	512	{
	513	env->pc = tb->pc;
	514	env->npc = tb->cs_base;
	515	}
	516
6b917547 AL	517	static inline void cpu_get_tb_cpu_state(CPUState env, target_ulong pc,
	518	target_ulong cs_base, int flags)
	519	{
	520	*pc = env->pc;
	521	*cs_base = env->npc;
	522	#ifdef TARGET_SPARC64
	523	// AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
	524	*flags = ((env->pstate & PS_AM) << 2)
	525	\| (((env->pstate & PS_PEF) >> 1) \| ((env->fprs & FPRS_FEF) << 2))
	526	\| (env->pstate & PS_PRIV) \| ((env->lsu & (DMMU_E \| IMMU_E)) >> 2);
	527	#else
	528	// FPU enable . Supervisor
	529	*flags = (env->psref << 4) \| env->psrs;
	530	#endif
	531	}
	532
7a3f1944	533	#endif