[qemu.git] / target-sparc / cpu.h

#ifndef CPU_SPARC_H
#define CPU_SPARC_H

#include "config.h"

#if !defined(TARGET_SPARC64)
#define TARGET_LONG_BITS 32
#define TARGET_FPREGS 32
#define TARGET_PAGE_BITS 12 /* 4k */
#else
#define TARGET_LONG_BITS 64
#define TARGET_FPREGS 64
#define TARGET_PAGE_BITS 12 /* XXX */
#endif

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#if !defined(TARGET_SPARC64)
#define ELF_MACHINE	EM_SPARC
#else
#define ELF_MACHINE	EM_SPARCV9
#endif

/*#define EXCP_INTERRUPT 0x100*/

/* trap definitions */
#ifndef TARGET_SPARC64
#define TT_TFAULT   0x01
#define TT_ILL_INSN 0x02
#define TT_PRIV_INSN 0x03
#define TT_NFPU_INSN 0x04
#define TT_WIN_OVF  0x05
#define TT_WIN_UNF  0x06 
#define TT_FP_EXCP  0x08
#define TT_DFAULT   0x09
#define TT_TOVF     0x0a
#define TT_EXTINT   0x10
#define TT_DIV_ZERO 0x2a
#define TT_TRAP     0x80
#else
#define TT_TFAULT   0x08
#define TT_TMISS    0x09
#define TT_ILL_INSN 0x10
#define TT_PRIV_INSN 0x11
#define TT_NFPU_INSN 0x20
#define TT_FP_EXCP  0x21
#define TT_TOVF     0x23
#define TT_CLRWIN   0x24
#define TT_DIV_ZERO 0x28
#define TT_DFAULT   0x30
#define TT_DMISS    0x31
#define TT_DPROT    0x32
#define TT_PRIV_ACT 0x37
#define TT_EXTINT   0x40
#define TT_SPILL    0x80
#define TT_FILL     0xc0
#define TT_WOTHER   0x10
#define TT_TRAP     0x100
#endif

#define PSR_NEG   (1<<23)
#define PSR_ZERO  (1<<22)
#define PSR_OVF   (1<<21)
#define PSR_CARRY (1<<20)
#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
#define PSR_EF    (1<<12)
#define PSR_PIL   0xf00
#define PSR_S     (1<<7)
#define PSR_PS    (1<<6)
#define PSR_ET    (1<<5)
#define PSR_CWP   0x1f

/* Trap base register */
#define TBR_BASE_MASK 0xfffff000

#if defined(TARGET_SPARC64)
#define PS_IG    (1<<11)
#define PS_MG    (1<<10)
#define PS_RED   (1<<5)
#define PS_PEF   (1<<4)
#define PS_AM    (1<<3)
#define PS_PRIV  (1<<2)
#define PS_IE    (1<<1)
#define PS_AG    (1<<0)

#define FPRS_FEF (1<<2)
#endif

/* Fcc */
#define FSR_RD1        (1<<31)
#define FSR_RD0        (1<<30)
#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
#define FSR_RD_NEAREST 0
#define FSR_RD_ZERO    FSR_RD0
#define FSR_RD_POS     FSR_RD1
#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)

#define FSR_NVM   (1<<27)
#define FSR_OFM   (1<<26)
#define FSR_UFM   (1<<25)
#define FSR_DZM   (1<<24)
#define FSR_NXM   (1<<23)
#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)

#define FSR_NVA   (1<<9)
#define FSR_OFA   (1<<8)
#define FSR_UFA   (1<<7)
#define FSR_DZA   (1<<6)
#define FSR_NXA   (1<<5)
#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)

#define FSR_NVC   (1<<4)
#define FSR_OFC   (1<<3)
#define FSR_UFC   (1<<2)
#define FSR_DZC   (1<<1)
#define FSR_NXC   (1<<0)
#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)

#define FSR_FTT2   (1<<16)
#define FSR_FTT1   (1<<15)
#define FSR_FTT0   (1<<14)
#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
#define FSR_FTT_IEEE_EXCP (1 << 14)
#define FSR_FTT_UNIMPFPOP (3 << 14)
#define FSR_FTT_INVAL_FPR (6 << 14)

#define FSR_FCC1  (1<<11)
#define FSR_FCC0  (1<<10)

/* MMU */
#define MMU_E	  (1<<0)
#define MMU_NF	  (1<<1)

#define PTE_ENTRYTYPE_MASK 3
#define PTE_ACCESS_MASK    0x1c
#define PTE_ACCESS_SHIFT   2
#define PTE_PPN_SHIFT      7
#define PTE_ADDR_MASK      0xffffff00

#define PG_ACCESSED_BIT	5
#define PG_MODIFIED_BIT	6
#define PG_CACHE_BIT    7

#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)

/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
#define NWINDOWS  8

typedef struct CPUSPARCState {
    target_ulong gregs[8]; /* general registers */
    target_ulong *regwptr; /* pointer to current register window */
    float32 fpr[TARGET_FPREGS];  /* floating point registers */
    target_ulong pc;       /* program counter */
    target_ulong npc;      /* next program counter */
    target_ulong y;        /* multiply/divide register */
    uint32_t psr;      /* processor state register */
    target_ulong fsr;      /* FPU state register */
    uint32_t cwp;      /* index of current register window (extracted
                          from PSR) */
    uint32_t wim;      /* window invalid mask */
    target_ulong tbr;  /* trap base register */
    int      psrs;     /* supervisor mode (extracted from PSR) */
    int      psrps;    /* previous supervisor mode */
    int      psret;    /* enable traps */
    uint32_t psrpil;   /* interrupt level */
    int      psref;    /* enable fpu */
    jmp_buf  jmp_env;
    int user_mode_only;
    int exception_index;
    int interrupt_index;
    int interrupt_request;
    int halted;
    /* NOTE: we allow 8 more registers to handle wrapping */
    target_ulong regbase[NWINDOWS * 16 + 8];

    CPU_COMMON

    /* MMU regs */
#if defined(TARGET_SPARC64)
    uint64_t lsu;
#define DMMU_E 0x8
#define IMMU_E 0x4
    uint64_t immuregs[16];
    uint64_t dmmuregs[16];
    uint64_t itlb_tag[64];
    uint64_t itlb_tte[64];
    uint64_t dtlb_tag[64];
    uint64_t dtlb_tte[64];
#else
    uint32_t mmuregs[16];
#endif
    /* temporary float registers */
    float32 ft0, ft1;
    float64 dt0, dt1;
    float_status fp_status;
#if defined(TARGET_SPARC64)
#define MAXTL 4
    uint64_t t0, t1, t2;
    uint64_t tpc[MAXTL];
    uint64_t tnpc[MAXTL];
    uint64_t tstate[MAXTL];
    uint32_t tt[MAXTL];
    uint32_t xcc;		/* Extended integer condition codes */
    uint32_t asi;
    uint32_t pstate;
    uint32_t tl;
    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
    uint64_t agregs[8]; /* alternate general registers */
    uint64_t bgregs[8]; /* backup for normal global registers */
    uint64_t igregs[8]; /* interrupt general registers */
    uint64_t mgregs[8]; /* mmu general registers */
    uint64_t version;
    uint64_t fprs;
    uint64_t tick_cmpr, stick_cmpr;
    uint64_t gsr;
#endif
#if !defined(TARGET_SPARC64) && !defined(reg_T2)
    target_ulong t2;
#endif
} CPUSPARCState;
#if defined(TARGET_SPARC64)
#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
#define PUT_FSR32(env, val) do { uint32_t _tmp = val;			\
	env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);	\
    } while (0)
#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
#define PUT_FSR64(env, val) do { uint64_t _tmp = val;	\
	env->fsr = _tmp & 0x3fcfc1c3ffULL;		\
    } while (0)
// Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
#define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) |		\
		      (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
#else
#define GET_FSR32(env) (env->fsr)
#define PUT_FSR32(env, val) do { uint32_t _tmp = val;                   \
        env->fsr = (_tmp & 0xcfc1ffff) | (env->fsr & 0x000e0000);       \
    } while (0)
#endif

CPUSPARCState *cpu_sparc_init(void);
int cpu_sparc_exec(CPUSPARCState *s);
int cpu_sparc_close(CPUSPARCState *s);

/* Fake impl 0, version 4 */
#define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) |	\
		      (env->psref? PSR_EF : 0) |			\
		      (env->psrpil << 8) |				\
		      (env->psrs? PSR_S : 0) |				\
		      (env->psrps? PSR_PS : 0) |			\
		      (env->psret? PSR_ET : 0) | env->cwp)

#ifndef NO_CPU_IO_DEFS
void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
#endif

#define PUT_PSR(env, val) do { int _tmp = val;				\
	env->psr = _tmp & PSR_ICC;					\
	env->psref = (_tmp & PSR_EF)? 1 : 0;				\
	env->psrpil = (_tmp & PSR_PIL) >> 8;				\
	env->psrs = (_tmp & PSR_S)? 1 : 0;				\
	env->psrps = (_tmp & PSR_PS)? 1 : 0;				\
	env->psret = (_tmp & PSR_ET)? 1 : 0;				\
	cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1));		\
    } while (0)

#ifdef TARGET_SPARC64
#define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
#define PUT_CCR(env, val) do { int _tmp = val;				\
	env->xcc = _tmp >> 4;						\
	env->psr = (_tmp & 0xf) << 20;					\
    } while (0)
#endif

int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);

#include "cpu-all.h"

#endif
Commit	Line	Data
7a3f1944 FB	1	#ifndef CPU_SPARC_H
	2	#define CPU_SPARC_H
	3
af7bf89b FB	4	#include "config.h"
	5
	6	#if !defined(TARGET_SPARC64)
3cf1e035	7	#define TARGET_LONG_BITS 32
af7bf89b	8	#define TARGET_FPREGS 32
83469015	9	#define TARGET_PAGE_BITS 12 /* 4k */
af7bf89b FB	10	#else
	11	#define TARGET_LONG_BITS 64
	12	#define TARGET_FPREGS 64
83469015	13	#define TARGET_PAGE_BITS 12 /* XXX */
af7bf89b	14	#endif
3cf1e035	15
7a3f1944 FB	16	#include "cpu-defs.h"
7a3f1944 FB	17
7a0e1f41 FB	18	#include "softfloat.h"
7a0e1f41 FB	19
1fddef4b FB	20	#define TARGET_HAS_ICE 1
1fddef4b FB	21
9042c0e2 TS	22	#if !defined(TARGET_SPARC64)
	23	#define ELF_MACHINE EM_SPARC
	24	#else
	25	#define ELF_MACHINE EM_SPARCV9
	26	#endif
	27
7a3f1944 FB	28	/#define EXCP_INTERRUPT 0x100/
7a3f1944 FB	29
cf495bcf	30	/* trap definitions */
3475187d	31	#ifndef TARGET_SPARC64
878d3096	32	#define TT_TFAULT 0x01
cf495bcf	33	#define TT_ILL_INSN 0x02
e8af50a3	34	#define TT_PRIV_INSN 0x03
e80cfcfc	35	#define TT_NFPU_INSN 0x04
cf495bcf FB	36	#define TT_WIN_OVF 0x05
cf495bcf FB	37	#define TT_WIN_UNF 0x06
e8af50a3	38	#define TT_FP_EXCP 0x08
878d3096	39	#define TT_DFAULT 0x09
e32f879d	40	#define TT_TOVF 0x0a
878d3096	41	#define TT_EXTINT 0x10
cf495bcf FB	42	#define TT_DIV_ZERO 0x2a
cf495bcf FB	43	#define TT_TRAP 0x80
3475187d FB	44	#else
3475187d FB	45	#define TT_TFAULT 0x08
83469015	46	#define TT_TMISS 0x09
3475187d FB	47	#define TT_ILL_INSN 0x10
	48	#define TT_PRIV_INSN 0x11
	49	#define TT_NFPU_INSN 0x20
	50	#define TT_FP_EXCP 0x21
e32f879d	51	#define TT_TOVF 0x23
3475187d FB	52	#define TT_CLRWIN 0x24
	53	#define TT_DIV_ZERO 0x28
	54	#define TT_DFAULT 0x30
83469015 FB	55	#define TT_DMISS 0x31
	56	#define TT_DPROT 0x32
	57	#define TT_PRIV_ACT 0x37
3475187d FB	58	#define TT_EXTINT 0x40
	59	#define TT_SPILL 0x80
	60	#define TT_FILL 0xc0
	61	#define TT_WOTHER 0x10
	62	#define TT_TRAP 0x100
	63	#endif
7a3f1944 FB	64
	65	#define PSR_NEG (1<<23)
	66	#define PSR_ZERO (1<<22)
	67	#define PSR_OVF (1<<21)
	68	#define PSR_CARRY (1<<20)
e8af50a3	69	#define PSR_ICC (PSR_NEG\|PSR_ZERO\|PSR_OVF\|PSR_CARRY)
e80cfcfc FB	70	#define PSR_EF (1<<12)
e80cfcfc FB	71	#define PSR_PIL 0xf00
e8af50a3 FB	72	#define PSR_S (1<<7)
	73	#define PSR_PS (1<<6)
	74	#define PSR_ET (1<<5)
	75	#define PSR_CWP 0x1f
e8af50a3 FB	76
	77	/* Trap base register */
	78	#define TBR_BASE_MASK 0xfffff000
	79
3475187d	80	#if defined(TARGET_SPARC64)
83469015 FB	81	#define PS_IG (1<<11)
	82	#define PS_MG (1<<10)
	83	#define PS_RED (1<<5)
3475187d FB	84	#define PS_PEF (1<<4)
	85	#define PS_AM (1<<3)
	86	#define PS_PRIV (1<<2)
	87	#define PS_IE (1<<1)
83469015	88	#define PS_AG (1<<0)
a80dde08 FB	89
a80dde08 FB	90	#define FPRS_FEF (1<<2)
3475187d FB	91	#endif
3475187d FB	92
e8af50a3 FB	93	/* Fcc */
	94	#define FSR_RD1 (1<<31)
	95	#define FSR_RD0 (1<<30)
	96	#define FSR_RD_MASK (FSR_RD1 \| FSR_RD0)
	97	#define FSR_RD_NEAREST 0
	98	#define FSR_RD_ZERO FSR_RD0
	99	#define FSR_RD_POS FSR_RD1
	100	#define FSR_RD_NEG (FSR_RD1 \| FSR_RD0)
	101
	102	#define FSR_NVM (1<<27)
	103	#define FSR_OFM (1<<26)
	104	#define FSR_UFM (1<<25)
	105	#define FSR_DZM (1<<24)
	106	#define FSR_NXM (1<<23)
	107	#define FSR_TEM_MASK (FSR_NVM \| FSR_OFM \| FSR_UFM \| FSR_DZM \| FSR_NXM)
	108
	109	#define FSR_NVA (1<<9)
	110	#define FSR_OFA (1<<8)
	111	#define FSR_UFA (1<<7)
	112	#define FSR_DZA (1<<6)
	113	#define FSR_NXA (1<<5)
	114	#define FSR_AEXC_MASK (FSR_NVA \| FSR_OFA \| FSR_UFA \| FSR_DZA \| FSR_NXA)
	115
	116	#define FSR_NVC (1<<4)
	117	#define FSR_OFC (1<<3)
	118	#define FSR_UFC (1<<2)
	119	#define FSR_DZC (1<<1)
	120	#define FSR_NXC (1<<0)
	121	#define FSR_CEXC_MASK (FSR_NVC \| FSR_OFC \| FSR_UFC \| FSR_DZC \| FSR_NXC)
	122
	123	#define FSR_FTT2 (1<<16)
	124	#define FSR_FTT1 (1<<15)
	125	#define FSR_FTT0 (1<<14)
	126	#define FSR_FTT_MASK (FSR_FTT2 \| FSR_FTT1 \| FSR_FTT0)
e80cfcfc FB	127	#define FSR_FTT_IEEE_EXCP (1 << 14)
	128	#define FSR_FTT_UNIMPFPOP (3 << 14)
	129	#define FSR_FTT_INVAL_FPR (6 << 14)
e8af50a3 FB	130
	131	#define FSR_FCC1 (1<<11)
	132	#define FSR_FCC0 (1<<10)
	133
	134	/* MMU */
	135	#define MMU_E (1<<0)
	136	#define MMU_NF (1<<1)
	137
	138	#define PTE_ENTRYTYPE_MASK 3
	139	#define PTE_ACCESS_MASK 0x1c
	140	#define PTE_ACCESS_SHIFT 2
8d5f07fa	141	#define PTE_PPN_SHIFT 7
e8af50a3 FB	142	#define PTE_ADDR_MASK 0xffffff00
	143
	144	#define PG_ACCESSED_BIT 5
	145	#define PG_MODIFIED_BIT 6
	146	#define PG_CACHE_BIT 7
	147
	148	#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
	149	#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
	150	#define PG_CACHE_MASK (1 << PG_CACHE_BIT)
	151
1d6e34fd FB	152	/* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
1d6e34fd FB	153	#define NWINDOWS 8
cf495bcf	154
7a3f1944	155	typedef struct CPUSPARCState {
af7bf89b FB	156	target_ulong gregs[8]; /* general registers */
af7bf89b FB	157	target_ulong regwptr; / pointer to current register window */
65ce8c2f	158	float32 fpr[TARGET_FPREGS]; /* floating point registers */
af7bf89b FB	159	target_ulong pc; /* program counter */
	160	target_ulong npc; /* next program counter */
	161	target_ulong y; /* multiply/divide register */
cf495bcf	162	uint32_t psr; /* processor state register */
3475187d	163	target_ulong fsr; /* FPU state register */
cf495bcf FB	164	uint32_t cwp; /* index of current register window (extracted
	165	from PSR) */
	166	uint32_t wim; /* window invalid mask */
3475187d	167	target_ulong tbr; /* trap base register */
e8af50a3 FB	168	int psrs; /* supervisor mode (extracted from PSR) */
	169	int psrps; /* previous supervisor mode */
	170	int psret; /* enable traps */
3475187d	171	uint32_t psrpil; /* interrupt level */
e80cfcfc	172	int psref; /* enable fpu */
cf495bcf FB	173	jmp_buf jmp_env;
	174	int user_mode_only;
	175	int exception_index;
	176	int interrupt_index;
	177	int interrupt_request;
ba3c64fb	178	int halted;
cf495bcf	179	/* NOTE: we allow 8 more registers to handle wrapping */
af7bf89b	180	target_ulong regbase[NWINDOWS * 16 + 8];
d720b93d	181
a316d335 FB	182	CPU_COMMON
a316d335 FB	183
e8af50a3	184	/* MMU regs */
3475187d FB	185	#if defined(TARGET_SPARC64)
	186	uint64_t lsu;
	187	#define DMMU_E 0x8
	188	#define IMMU_E 0x4
	189	uint64_t immuregs[16];
	190	uint64_t dmmuregs[16];
	191	uint64_t itlb_tag[64];
	192	uint64_t itlb_tte[64];
	193	uint64_t dtlb_tag[64];
	194	uint64_t dtlb_tte[64];
	195	#else
e8af50a3	196	uint32_t mmuregs[16];
3475187d	197	#endif
e8af50a3	198	/* temporary float registers */
65ce8c2f FB	199	float32 ft0, ft1;
65ce8c2f FB	200	float64 dt0, dt1;
7a0e1f41	201	float_status fp_status;
af7bf89b	202	#if defined(TARGET_SPARC64)
3475187d FB	203	#define MAXTL 4
	204	uint64_t t0, t1, t2;
	205	uint64_t tpc[MAXTL];
	206	uint64_t tnpc[MAXTL];
	207	uint64_t tstate[MAXTL];
	208	uint32_t tt[MAXTL];
	209	uint32_t xcc; /* Extended integer condition codes */
	210	uint32_t asi;
	211	uint32_t pstate;
	212	uint32_t tl;
	213	uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
83469015 FB	214	uint64_t agregs[8]; /* alternate general registers */
	215	uint64_t bgregs[8]; /* backup for normal global registers */
	216	uint64_t igregs[8]; /* interrupt general registers */
	217	uint64_t mgregs[8]; /* mmu general registers */
3475187d FB	218	uint64_t version;
3475187d FB	219	uint64_t fprs;
83469015	220	uint64_t tick_cmpr, stick_cmpr;
725cb90b	221	uint64_t gsr;
3475187d FB	222	#endif
	223	#if !defined(TARGET_SPARC64) && !defined(reg_T2)
	224	target_ulong t2;
af7bf89b	225	#endif
7a3f1944	226	} CPUSPARCState;
3475187d FB	227	#if defined(TARGET_SPARC64)
	228	#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
	229	#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
	230	env->fsr = (_tmp & 0xcfc1c3ff) \| (env->fsr & 0x3f00000000ULL); \
	231	} while (0)
	232	#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
	233	#define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
	234	env->fsr = _tmp & 0x3fcfc1c3ffULL; \
	235	} while (0)
	236	// Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
	237	#define GET_VER(env) ((0x17ULL << 48) \| (0x11ULL << 32) \| \
	238	(0 << 24) \| (MAXTL << 8) \| (NWINDOWS - 1))
	239	#else
	240	#define GET_FSR32(env) (env->fsr)
3e736bf4 BS	241	#define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
3e736bf4 BS	242	env->fsr = (_tmp & 0xcfc1ffff) \| (env->fsr & 0x000e0000); \
3475187d FB	243	} while (0)
3475187d FB	244	#endif
7a3f1944 FB	245
	246	CPUSPARCState *cpu_sparc_init(void);
	247	int cpu_sparc_exec(CPUSPARCState *s);
	248	int cpu_sparc_close(CPUSPARCState *s);
	249
b4ff5987	250	/* Fake impl 0, version 4 */
af7bf89b	251	#define GET_PSR(env) ((0 << 28) \| (4 << 24) \| (env->psr & PSR_ICC) \| \
b4ff5987 FB	252	(env->psref? PSR_EF : 0) \| \
	253	(env->psrpil << 8) \| \
	254	(env->psrs? PSR_S : 0) \| \
afc7df11	255	(env->psrps? PSR_PS : 0) \| \
b4ff5987 FB	256	(env->psret? PSR_ET : 0) \| env->cwp)
	257
	258	#ifndef NO_CPU_IO_DEFS
	259	void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
	260	#endif
	261
	262	#define PUT_PSR(env, val) do { int _tmp = val; \
af7bf89b	263	env->psr = _tmp & PSR_ICC; \
b4ff5987 FB	264	env->psref = (_tmp & PSR_EF)? 1 : 0; \
	265	env->psrpil = (_tmp & PSR_PIL) >> 8; \
	266	env->psrs = (_tmp & PSR_S)? 1 : 0; \
	267	env->psrps = (_tmp & PSR_PS)? 1 : 0; \
	268	env->psret = (_tmp & PSR_ET)? 1 : 0; \
	269	cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
	270	} while (0)
	271
3475187d FB	272	#ifdef TARGET_SPARC64
	273	#define GET_CCR(env) ((env->xcc << 4) \| (env->psr & PSR_ICC))
	274	#define PUT_CCR(env, val) do { int _tmp = val; \
	275	env->xcc = _tmp >> 4; \
	276	env->psr = (_tmp & 0xf) << 20; \
	277	} while (0)
	278	#endif
	279
5a7b542b	280	int cpu_sparc_signal_handler(int host_signum, void pinfo, void puc);
7a3f1944	281
7a3f1944 FB	282	#include "cpu-all.h"
	283
	284	#endif