[qemu.git] / target-s390x / misc_helper.c

/*
 *  S/390 misc helper routines
 *
 *  Copyright (c) 2009 Ulrich Hecht
 *  Copyright (c) 2009 Alexander Graf
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/memory.h"
#include "qemu/host-utils.h"
#include "helper.h"
#include <string.h>
#include "sysemu/kvm.h"
#include "qemu/timer.h"
#ifdef CONFIG_KVM
#include <linux/kvm.h>
#endif

#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
#include "sysemu/cpus.h"
#include "sysemu/sysemu.h"
#include "hw/s390x/ebcdic.h"
#endif

/* #define DEBUG_HELPER */
#ifdef DEBUG_HELPER
#define HELPER_LOG(x...) qemu_log(x)
#else
#define HELPER_LOG(x...)
#endif

/* Raise an exception dynamically from a helper function.  */
void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
                                     uintptr_t retaddr)
{
    int t;

    env->exception_index = EXCP_PGM;
    env->int_pgm_code = excp;

    /* Use the (ultimate) callers address to find the insn that trapped.  */
    cpu_restore_state(env, retaddr);

    /* Advance past the insn.  */
    t = cpu_ldub_code(env, env->psw.addr);
    env->int_pgm_ilen = t = get_ilen(t);
    env->psw.addr += 2 * t;

    cpu_loop_exit(env);
}

/* Raise an exception statically from a TB.  */
void HELPER(exception)(CPUS390XState *env, uint32_t excp)
{
    HELPER_LOG("%s: exception %d\n", __func__, excp);
    env->exception_index = excp;
    cpu_loop_exit(env);
}

#ifndef CONFIG_USER_ONLY

void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
{
    qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
                  env->psw.addr);

    if (kvm_enabled()) {
#ifdef CONFIG_KVM
        kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code);
#endif
    } else {
        env->int_pgm_code = code;
        env->int_pgm_ilen = ilen;
        env->exception_index = EXCP_PGM;
        cpu_loop_exit(env);
    }
}

/* SCLP service call */
uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2)
{
    int r = sclp_service_call(r1, r2);
    if (r < 0) {
        program_interrupt(env, -r, 4);
        return 0;
    }
    return r;
}

#ifndef CONFIG_USER_ONLY
static void cpu_reset_all(void)
{
    CPUState *cs;
    S390CPUClass *scc;

    CPU_FOREACH(cs) {
        scc = S390_CPU_GET_CLASS(cs);
        scc->cpu_reset(cs);
    }
}

static void cpu_full_reset_all(void)
{
    CPUState *cpu;

    CPU_FOREACH(cpu) {
        cpu_reset(cpu);
    }
}

static int modified_clear_reset(S390CPU *cpu)
{
    S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);

    pause_all_vcpus();
    cpu_synchronize_all_states();
    cpu_full_reset_all();
    io_subsystem_reset();
    scc->load_normal(CPU(cpu));
    cpu_synchronize_all_post_reset();
    resume_all_vcpus();
    return 0;
}

static int load_normal_reset(S390CPU *cpu)
{
    S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);

    pause_all_vcpus();
    cpu_synchronize_all_states();
    cpu_reset_all();
    io_subsystem_reset();
    scc->initial_cpu_reset(CPU(cpu));
    scc->load_normal(CPU(cpu));
    cpu_synchronize_all_post_reset();
    resume_all_vcpus();
    return 0;
}

#define DIAG_308_RC_NO_CONF         0x0102
#define DIAG_308_RC_INVALID         0x0402
void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3)
{
    uint64_t addr =  env->regs[r1];
    uint64_t subcode = env->regs[r3];

    if (env->psw.mask & PSW_MASK_PSTATE) {
        program_interrupt(env, PGM_PRIVILEGED, ILEN_LATER_INC);
        return;
    }

    if ((subcode & ~0x0ffffULL) || (subcode > 6)) {
        program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
        return;
    }

    switch (subcode) {
    case 0:
        modified_clear_reset(s390_env_get_cpu(env));
        break;
    case 1:
        load_normal_reset(s390_env_get_cpu(env));
        break;
    case 5:
        if ((r1 & 1) || (addr & 0x0fffULL)) {
            program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
            return;
        }
        env->regs[r1+1] = DIAG_308_RC_INVALID;
        return;
    case 6:
        if ((r1 & 1) || (addr & 0x0fffULL)) {
            program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
            return;
        }
        env->regs[r1+1] = DIAG_308_RC_NO_CONF;
        return;
    default:
        hw_error("Unhandled diag308 subcode %" PRIx64, subcode);
        break;
    }
}
#endif

/* DIAG */
uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
                      uint64_t code)
{
    uint64_t r;

    switch (num) {
    case 0x500:
        /* KVM hypercall */
        r = s390_virtio_hypercall(env);
        break;
    case 0x44:
        /* yield */
        r = 0;
        break;
    case 0x308:
        /* ipl */
        r = 0;
        break;
    default:
        r = -1;
        break;
    }

    if (r) {
        program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC);
    }

    return r;
}

/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
    uint32_t prefix = a1 & 0x7fffe000;
    env->psa = prefix;
    qemu_log("prefix: %#x\n", prefix);
    tlb_flush_page(env, 0);
    tlb_flush_page(env, TARGET_PAGE_SIZE);
}

static inline uint64_t clock_value(CPUS390XState *env)
{
    uint64_t time;

    time = env->tod_offset +
        time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - env->tod_basetime);

    return time;
}

/* Store Clock */
uint64_t HELPER(stck)(CPUS390XState *env)
{
    return clock_value(env);
}

/* Set Clock Comparator */
void HELPER(sckc)(CPUS390XState *env, uint64_t time)
{
    if (time == -1ULL) {
        return;
    }

    /* difference between now and then */
    time -= clock_value(env);
    /* nanoseconds */
    time = (time * 125) >> 9;

    timer_mod(env->tod_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
}

/* Store Clock Comparator */
uint64_t HELPER(stckc)(CPUS390XState *env)
{
    /* XXX implement */
    return 0;
}

/* Set CPU Timer */
void HELPER(spt)(CPUS390XState *env, uint64_t time)
{
    if (time == -1ULL) {
        return;
    }

    /* nanoseconds */
    time = (time * 125) >> 9;

    timer_mod(env->cpu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
}

/* Store CPU Timer */
uint64_t HELPER(stpt)(CPUS390XState *env)
{
    /* XXX implement */
    return 0;
}

/* Store System Information */
uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0,
                      uint64_t r0, uint64_t r1)
{
    int cc = 0;
    int sel1, sel2;

    if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
        ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
        /* valid function code, invalid reserved bits */
        program_interrupt(env, PGM_SPECIFICATION, 2);
    }

    sel1 = r0 & STSI_R0_SEL1_MASK;
    sel2 = r1 & STSI_R1_SEL2_MASK;

    /* XXX: spec exception if sysib is not 4k-aligned */

    switch (r0 & STSI_LEVEL_MASK) {
    case STSI_LEVEL_1:
        if ((sel1 == 1) && (sel2 == 1)) {
            /* Basic Machine Configuration */
            struct sysib_111 sysib;

            memset(&sysib, 0, sizeof(sysib));
            ebcdic_put(sysib.manuf, "QEMU            ", 16);
            /* same as machine type number in STORE CPU ID */
            ebcdic_put(sysib.type, "QEMU", 4);
            /* same as model number in STORE CPU ID */
            ebcdic_put(sysib.model, "QEMU            ", 16);
            ebcdic_put(sysib.sequence, "QEMU            ", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 1)) {
            /* Basic Machine CPU */
            struct sysib_121 sysib;

            memset(&sysib, 0, sizeof(sysib));
            /* XXX make different for different CPUs? */
            ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            stw_p(&sysib.cpu_addr, env->cpu_num);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 2)) {
            /* Basic Machine CPUs */
            struct sysib_122 sysib;

            memset(&sysib, 0, sizeof(sysib));
            stl_p(&sysib.capability, 0x443afc29);
            /* XXX change when SMP comes */
            stw_p(&sysib.total_cpus, 1);
            stw_p(&sysib.active_cpus, 1);
            stw_p(&sysib.standby_cpus, 0);
            stw_p(&sysib.reserved_cpus, 0);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else {
            cc = 3;
        }
        break;
    case STSI_LEVEL_2:
        {
            if ((sel1 == 2) && (sel2 == 1)) {
                /* LPAR CPU */
                struct sysib_221 sysib;

                memset(&sysib, 0, sizeof(sysib));
                /* XXX make different for different CPUs? */
                ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
                ebcdic_put(sysib.plant, "QEMU", 4);
                stw_p(&sysib.cpu_addr, env->cpu_num);
                stw_p(&sysib.cpu_id, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else if ((sel1 == 2) && (sel2 == 2)) {
                /* LPAR CPUs */
                struct sysib_222 sysib;

                memset(&sysib, 0, sizeof(sysib));
                stw_p(&sysib.lpar_num, 0);
                sysib.lcpuc = 0;
                /* XXX change when SMP comes */
                stw_p(&sysib.total_cpus, 1);
                stw_p(&sysib.conf_cpus, 1);
                stw_p(&sysib.standby_cpus, 0);
                stw_p(&sysib.reserved_cpus, 0);
                ebcdic_put(sysib.name, "QEMU    ", 8);
                stl_p(&sysib.caf, 1000);
                stw_p(&sysib.dedicated_cpus, 0);
                stw_p(&sysib.shared_cpus, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_3:
        {
            if ((sel1 == 2) && (sel2 == 2)) {
                /* VM CPUs */
                struct sysib_322 sysib;

                memset(&sysib, 0, sizeof(sysib));
                sysib.count = 1;
                /* XXX change when SMP comes */
                stw_p(&sysib.vm[0].total_cpus, 1);
                stw_p(&sysib.vm[0].conf_cpus, 1);
                stw_p(&sysib.vm[0].standby_cpus, 0);
                stw_p(&sysib.vm[0].reserved_cpus, 0);
                ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
                stl_p(&sysib.vm[0].caf, 1000);
                ebcdic_put(sysib.vm[0].cpi, "KVM/Linux       ", 16);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_CURRENT:
        env->regs[0] = STSI_LEVEL_3;
        break;
    default:
        cc = 3;
        break;
    }

    return cc;
}

uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
                      uint64_t cpu_addr)
{
    int cc = 0;

    HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
               __func__, order_code, r1, cpu_addr);

    /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
       as parameter (input). Status (output) is always R1. */

    switch (order_code) {
    case SIGP_SET_ARCH:
        /* switch arch */
        break;
    case SIGP_SENSE:
        /* enumerate CPU status */
        if (cpu_addr) {
            /* XXX implement when SMP comes */
            return 3;
        }
        env->regs[r1] &= 0xffffffff00000000ULL;
        cc = 1;
        break;
#if !defined(CONFIG_USER_ONLY)
    case SIGP_RESTART:
        qemu_system_reset_request();
        cpu_loop_exit(env);
        break;
    case SIGP_STOP:
        qemu_system_shutdown_request();
        cpu_loop_exit(env);
        break;
#endif
    default:
        /* unknown sigp */
        fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
        cc = 3;
    }

    return cc;
}
#endif
Commit	Line	Data
10ec5117	1	/*
aea1e885	2	* S/390 misc helper routines
10ec5117	3	*
defb0e31	4	* Copyright (c) 2009 Ulrich Hecht
10ec5117 AG	5	* Copyright (c) 2009 Alexander Graf
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
70539e18	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 AG	19	*/
10ec5117 AG	20
3e457172	21	#include "cpu.h"
022c62cb	22	#include "exec/memory.h"
1de7afc9	23	#include "qemu/host-utils.h"
3208afbe	24	#include "helper.h"
defb0e31	25	#include <string.h>
9c17d615	26	#include "sysemu/kvm.h"
1de7afc9	27	#include "qemu/timer.h"
af2be207 JK	28	#ifdef CONFIG_KVM
	29	#include <linux/kvm.h>
	30	#endif
10ec5117	31
71e47088	32	#if !defined(CONFIG_USER_ONLY)
022c62cb	33	#include "exec/softmmu_exec.h"
f0778475	34	#include "sysemu/cpus.h"
9c17d615	35	#include "sysemu/sysemu.h"
40fa5264	36	#include "hw/s390x/ebcdic.h"
10ec5117	37	#endif
d5a43964	38
defb0e31 AG	39	/* #define DEBUG_HELPER */
	40	#ifdef DEBUG_HELPER
	41	#define HELPER_LOG(x...) qemu_log(x)
	42	#else
	43	#define HELPER_LOG(x...)
	44	#endif
	45
b4e2bd35 RH	46	/* Raise an exception dynamically from a helper function. */
	47	void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
	48	uintptr_t retaddr)
	49	{
	50	int t;
	51
	52	env->exception_index = EXCP_PGM;
	53	env->int_pgm_code = excp;
	54
	55	/* Use the (ultimate) callers address to find the insn that trapped. */
	56	cpu_restore_state(env, retaddr);
	57
	58	/* Advance past the insn. */
	59	t = cpu_ldub_code(env, env->psw.addr);
	60	env->int_pgm_ilen = t = get_ilen(t);
	61	env->psw.addr += 2 * t;
	62
	63	cpu_loop_exit(env);
	64	}
	65
d5a103cd	66	/* Raise an exception statically from a TB. */
089f5c06	67	void HELPER(exception)(CPUS390XState *env, uint32_t excp)
defb0e31	68	{
71e47088	69	HELPER_LOG("%s: exception %d\n", __func__, excp);
defb0e31	70	env->exception_index = excp;
1162c041	71	cpu_loop_exit(env);
defb0e31 AG	72	}
defb0e31 AG	73
defb0e31	74	#ifndef CONFIG_USER_ONLY
a158986d	75
d5a103cd	76	void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
defb0e31	77	{
0d404541 RH	78	qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
0d404541 RH	79	env->psw.addr);
defb0e31 AG	80
defb0e31 AG	81	if (kvm_enabled()) {
af2be207	82	#ifdef CONFIG_KVM
1bc22652	83	kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code);
af2be207	84	#endif
defb0e31 AG	85	} else {
defb0e31 AG	86	env->int_pgm_code = code;
d5a103cd	87	env->int_pgm_ilen = ilen;
defb0e31	88	env->exception_index = EXCP_PGM;
1162c041	89	cpu_loop_exit(env);
defb0e31 AG	90	}
	91	}
	92
defb0e31	93	/* SCLP service call */
dc458df9	94	uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2)
defb0e31	95	{
dc458df9	96	int r = sclp_service_call(r1, r2);
9abf567d CB	97	if (r < 0) {
	98	program_interrupt(env, -r, 4);
	99	return 0;
	100	}
	101	return r;
defb0e31 AG	102	}
defb0e31 AG	103
268846ba	104	#ifndef CONFIG_USER_ONLY
f0778475 CB	105	static void cpu_reset_all(void)
f0778475 CB	106	{
bdc44640	107	CPUState *cs;
f0778475 CB	108	S390CPUClass *scc;
f0778475 CB	109
bdc44640 AF	110	CPU_FOREACH(cs) {
	111	scc = S390_CPU_GET_CLASS(cs);
	112	scc->cpu_reset(cs);
f0778475 CB	113	}
	114	}
	115
d8b30c83 CB	116	static void cpu_full_reset_all(void)
	117	{
	118	CPUState *cpu;
	119
	120	CPU_FOREACH(cpu) {
	121	cpu_reset(cpu);
	122	}
	123	}
	124
	125	static int modified_clear_reset(S390CPU *cpu)
	126	{
	127	S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
	128
	129	pause_all_vcpus();
	130	cpu_synchronize_all_states();
	131	cpu_full_reset_all();
	132	io_subsystem_reset();
	133	scc->load_normal(CPU(cpu));
	134	cpu_synchronize_all_post_reset();
	135	resume_all_vcpus();
	136	return 0;
	137	}
	138
f0778475 CB	139	static int load_normal_reset(S390CPU *cpu)
	140	{
	141	S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
	142
	143	pause_all_vcpus();
	144	cpu_synchronize_all_states();
	145	cpu_reset_all();
	146	io_subsystem_reset();
	147	scc->initial_cpu_reset(CPU(cpu));
	148	scc->load_normal(CPU(cpu));
	149	cpu_synchronize_all_post_reset();
	150	resume_all_vcpus();
	151	return 0;
	152	}
	153
268846ba ED	154	#define DIAG_308_RC_NO_CONF 0x0102
	155	#define DIAG_308_RC_INVALID 0x0402
	156	void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3)
	157	{
	158	uint64_t addr = env->regs[r1];
	159	uint64_t subcode = env->regs[r3];
	160
	161	if (env->psw.mask & PSW_MASK_PSTATE) {
	162	program_interrupt(env, PGM_PRIVILEGED, ILEN_LATER_INC);
	163	return;
	164	}
	165
	166	if ((subcode & ~0x0ffffULL) \|\| (subcode > 6)) {
	167	program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
	168	return;
	169	}
	170
	171	switch (subcode) {
d8b30c83 CB	172	case 0:
	173	modified_clear_reset(s390_env_get_cpu(env));
	174	break;
f0778475 CB	175	case 1:
	176	load_normal_reset(s390_env_get_cpu(env));
	177	break;
268846ba ED	178	case 5:
	179	if ((r1 & 1) \|\| (addr & 0x0fffULL)) {
	180	program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
	181	return;
	182	}
	183	env->regs[r1+1] = DIAG_308_RC_INVALID;
	184	return;
	185	case 6:
	186	if ((r1 & 1) \|\| (addr & 0x0fffULL)) {
	187	program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
	188	return;
	189	}
	190	env->regs[r1+1] = DIAG_308_RC_NO_CONF;
	191	return;
	192	default:
	193	hw_error("Unhandled diag308 subcode %" PRIx64, subcode);
	194	break;
	195	}
	196	}
	197	#endif
	198
defb0e31	199	/* DIAG */
089f5c06 BS	200	uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
089f5c06 BS	201	uint64_t code)
defb0e31 AG	202	{
	203	uint64_t r;
	204
	205	switch (num) {
	206	case 0x500:
	207	/* KVM hypercall */
28e942f8	208	r = s390_virtio_hypercall(env);
defb0e31 AG	209	break;
	210	case 0x44:
	211	/* yield */
	212	r = 0;
	213	break;
	214	case 0x308:
	215	/* ipl */
	216	r = 0;
	217	break;
	218	default:
	219	r = -1;
	220	break;
	221	}
	222
	223	if (r) {
d5a103cd	224	program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC);
defb0e31 AG	225	}
	226
	227	return r;
	228	}
	229
defb0e31	230	/* Set Prefix */
089f5c06	231	void HELPER(spx)(CPUS390XState *env, uint64_t a1)
defb0e31	232	{
e805a0d3 RH	233	uint32_t prefix = a1 & 0x7fffe000;
e805a0d3 RH	234	env->psa = prefix;
defb0e31 AG	235	qemu_log("prefix: %#x\n", prefix);
	236	tlb_flush_page(env, 0);
	237	tlb_flush_page(env, TARGET_PAGE_SIZE);
	238	}
	239
a4e3ad19	240	static inline uint64_t clock_value(CPUS390XState *env)
defb0e31 AG	241	{
	242	uint64_t time;
	243
	244	time = env->tod_offset +
bc72ad67	245	time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - env->tod_basetime);
defb0e31 AG	246
	247	return time;
	248	}
	249
	250	/* Store Clock */
434c91a5	251	uint64_t HELPER(stck)(CPUS390XState *env)
defb0e31	252	{
434c91a5	253	return clock_value(env);
defb0e31 AG	254	}
defb0e31 AG	255
defb0e31	256	/* Set Clock Comparator */
dd3eb7b5	257	void HELPER(sckc)(CPUS390XState *env, uint64_t time)
defb0e31	258	{
defb0e31 AG	259	if (time == -1ULL) {
	260	return;
	261	}
	262
	263	/* difference between now and then */
	264	time -= clock_value(env);
	265	/* nanoseconds */
	266	time = (time * 125) >> 9;
	267
bc72ad67	268	timer_mod(env->tod_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
defb0e31 AG	269	}
	270
	271	/* Store Clock Comparator */
dd3eb7b5	272	uint64_t HELPER(stckc)(CPUS390XState *env)
defb0e31 AG	273	{
defb0e31 AG	274	/* XXX implement */
dd3eb7b5	275	return 0;
defb0e31 AG	276	}
	277
	278	/* Set CPU Timer */
c4f0a863	279	void HELPER(spt)(CPUS390XState *env, uint64_t time)
defb0e31	280	{
defb0e31 AG	281	if (time == -1ULL) {
	282	return;
	283	}
	284
	285	/* nanoseconds */
	286	time = (time * 125) >> 9;
	287
bc72ad67	288	timer_mod(env->cpu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
defb0e31 AG	289	}
	290
	291	/* Store CPU Timer */
c4f0a863	292	uint64_t HELPER(stpt)(CPUS390XState *env)
defb0e31 AG	293	{
defb0e31 AG	294	/* XXX implement */
c4f0a863	295	return 0;
defb0e31 AG	296	}
	297
	298	/* Store System Information */
d14b3e09 RH	299	uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0,
d14b3e09 RH	300	uint64_t r0, uint64_t r1)
defb0e31 AG	301	{
	302	int cc = 0;
	303	int sel1, sel2;
	304
	305	if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
	306	((r0 & STSI_R0_RESERVED_MASK) \|\| (r1 & STSI_R1_RESERVED_MASK))) {
	307	/* valid function code, invalid reserved bits */
	308	program_interrupt(env, PGM_SPECIFICATION, 2);
	309	}
	310
	311	sel1 = r0 & STSI_R0_SEL1_MASK;
	312	sel2 = r1 & STSI_R1_SEL2_MASK;
	313
	314	/* XXX: spec exception if sysib is not 4k-aligned */
	315
	316	switch (r0 & STSI_LEVEL_MASK) {
	317	case STSI_LEVEL_1:
	318	if ((sel1 == 1) && (sel2 == 1)) {
	319	/* Basic Machine Configuration */
	320	struct sysib_111 sysib;
	321
	322	memset(&sysib, 0, sizeof(sysib));
	323	ebcdic_put(sysib.manuf, "QEMU ", 16);
	324	/* same as machine type number in STORE CPU ID */
	325	ebcdic_put(sysib.type, "QEMU", 4);
	326	/* same as model number in STORE CPU ID */
	327	ebcdic_put(sysib.model, "QEMU ", 16);
	328	ebcdic_put(sysib.sequence, "QEMU ", 16);
	329	ebcdic_put(sysib.plant, "QEMU", 4);
71e47088	330	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	331	} else if ((sel1 == 2) && (sel2 == 1)) {
	332	/* Basic Machine CPU */
	333	struct sysib_121 sysib;
	334
	335	memset(&sysib, 0, sizeof(sysib));
	336	/* XXX make different for different CPUs? */
	337	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	338	ebcdic_put(sysib.plant, "QEMU", 4);
	339	stw_p(&sysib.cpu_addr, env->cpu_num);
71e47088	340	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	341	} else if ((sel1 == 2) && (sel2 == 2)) {
	342	/* Basic Machine CPUs */
	343	struct sysib_122 sysib;
	344
	345	memset(&sysib, 0, sizeof(sysib));
	346	stl_p(&sysib.capability, 0x443afc29);
	347	/* XXX change when SMP comes */
	348	stw_p(&sysib.total_cpus, 1);
	349	stw_p(&sysib.active_cpus, 1);
	350	stw_p(&sysib.standby_cpus, 0);
	351	stw_p(&sysib.reserved_cpus, 0);
71e47088	352	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	353	} else {
	354	cc = 3;
	355	}
	356	break;
	357	case STSI_LEVEL_2:
71e47088 BS	358	{
	359	if ((sel1 == 2) && (sel2 == 1)) {
	360	/* LPAR CPU */
	361	struct sysib_221 sysib;
	362
	363	memset(&sysib, 0, sizeof(sysib));
	364	/* XXX make different for different CPUs? */
	365	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	366	ebcdic_put(sysib.plant, "QEMU", 4);
	367	stw_p(&sysib.cpu_addr, env->cpu_num);
	368	stw_p(&sysib.cpu_id, 0);
	369	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	370	} else if ((sel1 == 2) && (sel2 == 2)) {
	371	/* LPAR CPUs */
	372	struct sysib_222 sysib;
	373
	374	memset(&sysib, 0, sizeof(sysib));
	375	stw_p(&sysib.lpar_num, 0);
	376	sysib.lcpuc = 0;
	377	/* XXX change when SMP comes */
	378	stw_p(&sysib.total_cpus, 1);
	379	stw_p(&sysib.conf_cpus, 1);
	380	stw_p(&sysib.standby_cpus, 0);
	381	stw_p(&sysib.reserved_cpus, 0);
	382	ebcdic_put(sysib.name, "QEMU ", 8);
	383	stl_p(&sysib.caf, 1000);
	384	stw_p(&sysib.dedicated_cpus, 0);
	385	stw_p(&sysib.shared_cpus, 0);
	386	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	387	} else {
	388	cc = 3;
	389	}
	390	break;
defb0e31	391	}
defb0e31	392	case STSI_LEVEL_3:
71e47088 BS	393	{
	394	if ((sel1 == 2) && (sel2 == 2)) {
	395	/* VM CPUs */
	396	struct sysib_322 sysib;
	397
	398	memset(&sysib, 0, sizeof(sysib));
	399	sysib.count = 1;
	400	/* XXX change when SMP comes */
	401	stw_p(&sysib.vm[0].total_cpus, 1);
	402	stw_p(&sysib.vm[0].conf_cpus, 1);
	403	stw_p(&sysib.vm[0].standby_cpus, 0);
	404	stw_p(&sysib.vm[0].reserved_cpus, 0);
	405	ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
	406	stl_p(&sysib.vm[0].caf, 1000);
	407	ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
	408	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	409	} else {
	410	cc = 3;
	411	}
	412	break;
defb0e31	413	}
defb0e31 AG	414	case STSI_LEVEL_CURRENT:
	415	env->regs[0] = STSI_LEVEL_3;
	416	break;
	417	default:
	418	cc = 3;
	419	break;
	420	}
	421
	422	return cc;
	423	}
	424
089f5c06 BS	425	uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
089f5c06 BS	426	uint64_t cpu_addr)
defb0e31 AG	427	{
	428	int cc = 0;
	429
	430	HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
71e47088	431	__func__, order_code, r1, cpu_addr);
defb0e31	432
71e47088	433	/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
defb0e31 AG	434	as parameter (input). Status (output) is always R1. */
	435
	436	switch (order_code) {
	437	case SIGP_SET_ARCH:
	438	/* switch arch */
	439	break;
	440	case SIGP_SENSE:
	441	/* enumerate CPU status */
	442	if (cpu_addr) {
	443	/* XXX implement when SMP comes */
	444	return 3;
	445	}
	446	env->regs[r1] &= 0xffffffff00000000ULL;
	447	cc = 1;
	448	break;
71e47088	449	#if !defined(CONFIG_USER_ONLY)
1864b94a AG	450	case SIGP_RESTART:
	451	qemu_system_reset_request();
	452	cpu_loop_exit(env);
	453	break;
	454	case SIGP_STOP:
	455	qemu_system_shutdown_request();
	456	cpu_loop_exit(env);
	457	break;
	458	#endif
defb0e31 AG	459	default:
	460	/* unknown sigp */
	461	fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
	462	cc = 3;
	463	}
	464
	465	return cc;
	466	}
defb0e31	467	#endif