[qemu.git] / target-s390x / misc_helper.c

/*
 *  S/390 misc helper routines
 *
 *  Copyright (c) 2009 Ulrich Hecht
 *  Copyright (c) 2009 Alexander Graf
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/memory.h"
#include "qemu/host-utils.h"
#include "helper.h"
#include <string.h>
#include "sysemu/kvm.h"
#include "qemu/timer.h"
#ifdef CONFIG_KVM
#include <linux/kvm.h>
#endif

#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"
#include "sysemu/sysemu.h"
#endif

/* #define DEBUG_HELPER */
#ifdef DEBUG_HELPER
#define HELPER_LOG(x...) qemu_log(x)
#else
#define HELPER_LOG(x...)
#endif

/* Raise an exception dynamically from a helper function.  */
void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
                                     uintptr_t retaddr)
{
    int t;

    env->exception_index = EXCP_PGM;
    env->int_pgm_code = excp;

    /* Use the (ultimate) callers address to find the insn that trapped.  */
    cpu_restore_state(env, retaddr);

    /* Advance past the insn.  */
    t = cpu_ldub_code(env, env->psw.addr);
    env->int_pgm_ilen = t = get_ilen(t);
    env->psw.addr += 2 * t;

    cpu_loop_exit(env);
}

/* Raise an exception statically from a TB.  */
void HELPER(exception)(CPUS390XState *env, uint32_t excp)
{
    HELPER_LOG("%s: exception %d\n", __func__, excp);
    env->exception_index = excp;
    cpu_loop_exit(env);
}

#ifndef CONFIG_USER_ONLY
void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
{
    qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
                  env->psw.addr);

    if (kvm_enabled()) {
#ifdef CONFIG_KVM
        kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code);
#endif
    } else {
        env->int_pgm_code = code;
        env->int_pgm_ilen = ilen;
        env->exception_index = EXCP_PGM;
        cpu_loop_exit(env);
    }
}

/* SCLP service call */
uint32_t HELPER(servc)(CPUS390XState *env, uint32_t r1, uint64_t r2)
{
    int r;

    r = sclp_service_call(r1, r2);
    if (r < 0) {
        program_interrupt(env, -r, 4);
        return 0;
    }
    return r;
}

/* DIAG */
uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
                      uint64_t code)
{
    uint64_t r;

    switch (num) {
    case 0x500:
        /* KVM hypercall */
        r = s390_virtio_hypercall(env, mem, code);
        break;
    case 0x44:
        /* yield */
        r = 0;
        break;
    case 0x308:
        /* ipl */
        r = 0;
        break;
    default:
        r = -1;
        break;
    }

    if (r) {
        program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC);
    }

    return r;
}

/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
    uint32_t prefix = a1 & 0x7fffe000;
    env->psa = prefix;
    qemu_log("prefix: %#x\n", prefix);
    tlb_flush_page(env, 0);
    tlb_flush_page(env, TARGET_PAGE_SIZE);
}

static inline uint64_t clock_value(CPUS390XState *env)
{
    uint64_t time;

    time = env->tod_offset +
        time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);

    return time;
}

/* Store Clock */
uint64_t HELPER(stck)(CPUS390XState *env)
{
    return clock_value(env);
}

/* Set Clock Comparator */
void HELPER(sckc)(CPUS390XState *env, uint64_t time)
{
    if (time == -1ULL) {
        return;
    }

    /* difference between now and then */
    time -= clock_value(env);
    /* nanoseconds */
    time = (time * 125) >> 9;

    qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
}

/* Store Clock Comparator */
uint64_t HELPER(stckc)(CPUS390XState *env)
{
    /* XXX implement */
    return 0;
}

/* Set CPU Timer */
void HELPER(spt)(CPUS390XState *env, uint64_t time)
{
    if (time == -1ULL) {
        return;
    }

    /* nanoseconds */
    time = (time * 125) >> 9;

    qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
}

/* Store CPU Timer */
uint64_t HELPER(stpt)(CPUS390XState *env)
{
    /* XXX implement */
    return 0;
}

/* Store System Information */
uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint32_t r0,
                      uint32_t r1)
{
    int cc = 0;
    int sel1, sel2;

    if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
        ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
        /* valid function code, invalid reserved bits */
        program_interrupt(env, PGM_SPECIFICATION, 2);
    }

    sel1 = r0 & STSI_R0_SEL1_MASK;
    sel2 = r1 & STSI_R1_SEL2_MASK;

    /* XXX: spec exception if sysib is not 4k-aligned */

    switch (r0 & STSI_LEVEL_MASK) {
    case STSI_LEVEL_1:
        if ((sel1 == 1) && (sel2 == 1)) {
            /* Basic Machine Configuration */
            struct sysib_111 sysib;

            memset(&sysib, 0, sizeof(sysib));
            ebcdic_put(sysib.manuf, "QEMU            ", 16);
            /* same as machine type number in STORE CPU ID */
            ebcdic_put(sysib.type, "QEMU", 4);
            /* same as model number in STORE CPU ID */
            ebcdic_put(sysib.model, "QEMU            ", 16);
            ebcdic_put(sysib.sequence, "QEMU            ", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 1)) {
            /* Basic Machine CPU */
            struct sysib_121 sysib;

            memset(&sysib, 0, sizeof(sysib));
            /* XXX make different for different CPUs? */
            ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            stw_p(&sysib.cpu_addr, env->cpu_num);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 2)) {
            /* Basic Machine CPUs */
            struct sysib_122 sysib;

            memset(&sysib, 0, sizeof(sysib));
            stl_p(&sysib.capability, 0x443afc29);
            /* XXX change when SMP comes */
            stw_p(&sysib.total_cpus, 1);
            stw_p(&sysib.active_cpus, 1);
            stw_p(&sysib.standby_cpus, 0);
            stw_p(&sysib.reserved_cpus, 0);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else {
            cc = 3;
        }
        break;
    case STSI_LEVEL_2:
        {
            if ((sel1 == 2) && (sel2 == 1)) {
                /* LPAR CPU */
                struct sysib_221 sysib;

                memset(&sysib, 0, sizeof(sysib));
                /* XXX make different for different CPUs? */
                ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
                ebcdic_put(sysib.plant, "QEMU", 4);
                stw_p(&sysib.cpu_addr, env->cpu_num);
                stw_p(&sysib.cpu_id, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else if ((sel1 == 2) && (sel2 == 2)) {
                /* LPAR CPUs */
                struct sysib_222 sysib;

                memset(&sysib, 0, sizeof(sysib));
                stw_p(&sysib.lpar_num, 0);
                sysib.lcpuc = 0;
                /* XXX change when SMP comes */
                stw_p(&sysib.total_cpus, 1);
                stw_p(&sysib.conf_cpus, 1);
                stw_p(&sysib.standby_cpus, 0);
                stw_p(&sysib.reserved_cpus, 0);
                ebcdic_put(sysib.name, "QEMU    ", 8);
                stl_p(&sysib.caf, 1000);
                stw_p(&sysib.dedicated_cpus, 0);
                stw_p(&sysib.shared_cpus, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_3:
        {
            if ((sel1 == 2) && (sel2 == 2)) {
                /* VM CPUs */
                struct sysib_322 sysib;

                memset(&sysib, 0, sizeof(sysib));
                sysib.count = 1;
                /* XXX change when SMP comes */
                stw_p(&sysib.vm[0].total_cpus, 1);
                stw_p(&sysib.vm[0].conf_cpus, 1);
                stw_p(&sysib.vm[0].standby_cpus, 0);
                stw_p(&sysib.vm[0].reserved_cpus, 0);
                ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
                stl_p(&sysib.vm[0].caf, 1000);
                ebcdic_put(sysib.vm[0].cpi, "KVM/Linux       ", 16);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_CURRENT:
        env->regs[0] = STSI_LEVEL_3;
        break;
    default:
        cc = 3;
        break;
    }

    return cc;
}

uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
                      uint64_t cpu_addr)
{
    int cc = 0;

    HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
               __func__, order_code, r1, cpu_addr);

    /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
       as parameter (input). Status (output) is always R1. */

    switch (order_code) {
    case SIGP_SET_ARCH:
        /* switch arch */
        break;
    case SIGP_SENSE:
        /* enumerate CPU status */
        if (cpu_addr) {
            /* XXX implement when SMP comes */
            return 3;
        }
        env->regs[r1] &= 0xffffffff00000000ULL;
        cc = 1;
        break;
#if !defined(CONFIG_USER_ONLY)
    case SIGP_RESTART:
        qemu_system_reset_request();
        cpu_loop_exit(env);
        break;
    case SIGP_STOP:
        qemu_system_shutdown_request();
        cpu_loop_exit(env);
        break;
#endif
    default:
        /* unknown sigp */
        fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
        cc = 3;
    }

    return cc;
}
#endif
Commit	Line	Data
10ec5117	1	/*
aea1e885	2	* S/390 misc helper routines
10ec5117	3	*
defb0e31	4	* Copyright (c) 2009 Ulrich Hecht
10ec5117 AG	5	* Copyright (c) 2009 Alexander Graf
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
70539e18	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 AG	19	*/
10ec5117 AG	20
3e457172	21	#include "cpu.h"
022c62cb	22	#include "exec/memory.h"
1de7afc9	23	#include "qemu/host-utils.h"
3208afbe	24	#include "helper.h"
defb0e31	25	#include <string.h>
9c17d615	26	#include "sysemu/kvm.h"
1de7afc9	27	#include "qemu/timer.h"
af2be207 JK	28	#ifdef CONFIG_KVM
	29	#include <linux/kvm.h>
	30	#endif
10ec5117	31
71e47088	32	#if !defined(CONFIG_USER_ONLY)
022c62cb	33	#include "exec/softmmu_exec.h"
9c17d615	34	#include "sysemu/sysemu.h"
10ec5117	35	#endif
d5a43964	36
defb0e31 AG	37	/* #define DEBUG_HELPER */
	38	#ifdef DEBUG_HELPER
	39	#define HELPER_LOG(x...) qemu_log(x)
	40	#else
	41	#define HELPER_LOG(x...)
	42	#endif
	43
b4e2bd35 RH	44	/* Raise an exception dynamically from a helper function. */
	45	void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
	46	uintptr_t retaddr)
	47	{
	48	int t;
	49
	50	env->exception_index = EXCP_PGM;
	51	env->int_pgm_code = excp;
	52
	53	/* Use the (ultimate) callers address to find the insn that trapped. */
	54	cpu_restore_state(env, retaddr);
	55
	56	/* Advance past the insn. */
	57	t = cpu_ldub_code(env, env->psw.addr);
	58	env->int_pgm_ilen = t = get_ilen(t);
	59	env->psw.addr += 2 * t;
	60
	61	cpu_loop_exit(env);
	62	}
	63
d5a103cd	64	/* Raise an exception statically from a TB. */
089f5c06	65	void HELPER(exception)(CPUS390XState *env, uint32_t excp)
defb0e31	66	{
71e47088	67	HELPER_LOG("%s: exception %d\n", __func__, excp);
defb0e31	68	env->exception_index = excp;
1162c041	69	cpu_loop_exit(env);
defb0e31 AG	70	}
defb0e31 AG	71
defb0e31	72	#ifndef CONFIG_USER_ONLY
d5a103cd	73	void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
defb0e31	74	{
0d404541 RH	75	qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
0d404541 RH	76	env->psw.addr);
defb0e31 AG	77
defb0e31 AG	78	if (kvm_enabled()) {
af2be207	79	#ifdef CONFIG_KVM
1bc22652	80	kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code);
af2be207	81	#endif
defb0e31 AG	82	} else {
defb0e31 AG	83	env->int_pgm_code = code;
d5a103cd	84	env->int_pgm_ilen = ilen;
defb0e31	85	env->exception_index = EXCP_PGM;
1162c041	86	cpu_loop_exit(env);
defb0e31 AG	87	}
	88	}
	89
defb0e31	90	/* SCLP service call */
089f5c06	91	uint32_t HELPER(servc)(CPUS390XState *env, uint32_t r1, uint64_t r2)
defb0e31	92	{
9abf567d	93	int r;
defb0e31	94
f6c98f92	95	r = sclp_service_call(r1, r2);
9abf567d CB	96	if (r < 0) {
	97	program_interrupt(env, -r, 4);
	98	return 0;
	99	}
	100	return r;
defb0e31 AG	101	}
	102
	103	/* DIAG */
089f5c06 BS	104	uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
089f5c06 BS	105	uint64_t code)
defb0e31 AG	106	{
	107	uint64_t r;
	108
	109	switch (num) {
	110	case 0x500:
	111	/* KVM hypercall */
	112	r = s390_virtio_hypercall(env, mem, code);
	113	break;
	114	case 0x44:
	115	/* yield */
	116	r = 0;
	117	break;
	118	case 0x308:
	119	/* ipl */
	120	r = 0;
	121	break;
	122	default:
	123	r = -1;
	124	break;
	125	}
	126
	127	if (r) {
d5a103cd	128	program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC);
defb0e31 AG	129	}
	130
	131	return r;
	132	}
	133
defb0e31	134	/* Set Prefix */
089f5c06	135	void HELPER(spx)(CPUS390XState *env, uint64_t a1)
defb0e31	136	{
e805a0d3 RH	137	uint32_t prefix = a1 & 0x7fffe000;
e805a0d3 RH	138	env->psa = prefix;
defb0e31 AG	139	qemu_log("prefix: %#x\n", prefix);
	140	tlb_flush_page(env, 0);
	141	tlb_flush_page(env, TARGET_PAGE_SIZE);
	142	}
	143
a4e3ad19	144	static inline uint64_t clock_value(CPUS390XState *env)
defb0e31 AG	145	{
	146	uint64_t time;
	147
	148	time = env->tod_offset +
71e47088	149	time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
defb0e31 AG	150
	151	return time;
	152	}
	153
	154	/* Store Clock */
434c91a5	155	uint64_t HELPER(stck)(CPUS390XState *env)
defb0e31	156	{
434c91a5	157	return clock_value(env);
defb0e31 AG	158	}
defb0e31 AG	159
defb0e31	160	/* Set Clock Comparator */
dd3eb7b5	161	void HELPER(sckc)(CPUS390XState *env, uint64_t time)
defb0e31	162	{
defb0e31 AG	163	if (time == -1ULL) {
	164	return;
	165	}
	166
	167	/* difference between now and then */
	168	time -= clock_value(env);
	169	/* nanoseconds */
	170	time = (time * 125) >> 9;
	171
	172	qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
	173	}
	174
	175	/* Store Clock Comparator */
dd3eb7b5	176	uint64_t HELPER(stckc)(CPUS390XState *env)
defb0e31 AG	177	{
defb0e31 AG	178	/* XXX implement */
dd3eb7b5	179	return 0;
defb0e31 AG	180	}
	181
	182	/* Set CPU Timer */
c4f0a863	183	void HELPER(spt)(CPUS390XState *env, uint64_t time)
defb0e31	184	{
defb0e31 AG	185	if (time == -1ULL) {
	186	return;
	187	}
	188
	189	/* nanoseconds */
	190	time = (time * 125) >> 9;
	191
	192	qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
	193	}
	194
	195	/* Store CPU Timer */
c4f0a863	196	uint64_t HELPER(stpt)(CPUS390XState *env)
defb0e31 AG	197	{
defb0e31 AG	198	/* XXX implement */
c4f0a863	199	return 0;
defb0e31 AG	200	}
	201
	202	/* Store System Information */
089f5c06 BS	203	uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint32_t r0,
089f5c06 BS	204	uint32_t r1)
defb0e31 AG	205	{
	206	int cc = 0;
	207	int sel1, sel2;
	208
	209	if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
	210	((r0 & STSI_R0_RESERVED_MASK) \|\| (r1 & STSI_R1_RESERVED_MASK))) {
	211	/* valid function code, invalid reserved bits */
	212	program_interrupt(env, PGM_SPECIFICATION, 2);
	213	}
	214
	215	sel1 = r0 & STSI_R0_SEL1_MASK;
	216	sel2 = r1 & STSI_R1_SEL2_MASK;
	217
	218	/* XXX: spec exception if sysib is not 4k-aligned */
	219
	220	switch (r0 & STSI_LEVEL_MASK) {
	221	case STSI_LEVEL_1:
	222	if ((sel1 == 1) && (sel2 == 1)) {
	223	/* Basic Machine Configuration */
	224	struct sysib_111 sysib;
	225
	226	memset(&sysib, 0, sizeof(sysib));
	227	ebcdic_put(sysib.manuf, "QEMU ", 16);
	228	/* same as machine type number in STORE CPU ID */
	229	ebcdic_put(sysib.type, "QEMU", 4);
	230	/* same as model number in STORE CPU ID */
	231	ebcdic_put(sysib.model, "QEMU ", 16);
	232	ebcdic_put(sysib.sequence, "QEMU ", 16);
	233	ebcdic_put(sysib.plant, "QEMU", 4);
71e47088	234	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	235	} else if ((sel1 == 2) && (sel2 == 1)) {
	236	/* Basic Machine CPU */
	237	struct sysib_121 sysib;
	238
	239	memset(&sysib, 0, sizeof(sysib));
	240	/* XXX make different for different CPUs? */
	241	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	242	ebcdic_put(sysib.plant, "QEMU", 4);
	243	stw_p(&sysib.cpu_addr, env->cpu_num);
71e47088	244	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	245	} else if ((sel1 == 2) && (sel2 == 2)) {
	246	/* Basic Machine CPUs */
	247	struct sysib_122 sysib;
	248
	249	memset(&sysib, 0, sizeof(sysib));
	250	stl_p(&sysib.capability, 0x443afc29);
	251	/* XXX change when SMP comes */
	252	stw_p(&sysib.total_cpus, 1);
	253	stw_p(&sysib.active_cpus, 1);
	254	stw_p(&sysib.standby_cpus, 0);
	255	stw_p(&sysib.reserved_cpus, 0);
71e47088	256	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	257	} else {
	258	cc = 3;
	259	}
	260	break;
	261	case STSI_LEVEL_2:
71e47088 BS	262	{
	263	if ((sel1 == 2) && (sel2 == 1)) {
	264	/* LPAR CPU */
	265	struct sysib_221 sysib;
	266
	267	memset(&sysib, 0, sizeof(sysib));
	268	/* XXX make different for different CPUs? */
	269	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	270	ebcdic_put(sysib.plant, "QEMU", 4);
	271	stw_p(&sysib.cpu_addr, env->cpu_num);
	272	stw_p(&sysib.cpu_id, 0);
	273	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	274	} else if ((sel1 == 2) && (sel2 == 2)) {
	275	/* LPAR CPUs */
	276	struct sysib_222 sysib;
	277
	278	memset(&sysib, 0, sizeof(sysib));
	279	stw_p(&sysib.lpar_num, 0);
	280	sysib.lcpuc = 0;
	281	/* XXX change when SMP comes */
	282	stw_p(&sysib.total_cpus, 1);
	283	stw_p(&sysib.conf_cpus, 1);
	284	stw_p(&sysib.standby_cpus, 0);
	285	stw_p(&sysib.reserved_cpus, 0);
	286	ebcdic_put(sysib.name, "QEMU ", 8);
	287	stl_p(&sysib.caf, 1000);
	288	stw_p(&sysib.dedicated_cpus, 0);
	289	stw_p(&sysib.shared_cpus, 0);
	290	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	291	} else {
	292	cc = 3;
	293	}
	294	break;
defb0e31	295	}
defb0e31	296	case STSI_LEVEL_3:
71e47088 BS	297	{
	298	if ((sel1 == 2) && (sel2 == 2)) {
	299	/* VM CPUs */
	300	struct sysib_322 sysib;
	301
	302	memset(&sysib, 0, sizeof(sysib));
	303	sysib.count = 1;
	304	/* XXX change when SMP comes */
	305	stw_p(&sysib.vm[0].total_cpus, 1);
	306	stw_p(&sysib.vm[0].conf_cpus, 1);
	307	stw_p(&sysib.vm[0].standby_cpus, 0);
	308	stw_p(&sysib.vm[0].reserved_cpus, 0);
	309	ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
	310	stl_p(&sysib.vm[0].caf, 1000);
	311	ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
	312	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	313	} else {
	314	cc = 3;
	315	}
	316	break;
defb0e31	317	}
defb0e31 AG	318	case STSI_LEVEL_CURRENT:
	319	env->regs[0] = STSI_LEVEL_3;
	320	break;
	321	default:
	322	cc = 3;
	323	break;
	324	}
	325
	326	return cc;
	327	}
	328
089f5c06 BS	329	uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
089f5c06 BS	330	uint64_t cpu_addr)
defb0e31 AG	331	{
	332	int cc = 0;
	333
	334	HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
71e47088	335	__func__, order_code, r1, cpu_addr);
defb0e31	336
71e47088	337	/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
defb0e31 AG	338	as parameter (input). Status (output) is always R1. */
	339
	340	switch (order_code) {
	341	case SIGP_SET_ARCH:
	342	/* switch arch */
	343	break;
	344	case SIGP_SENSE:
	345	/* enumerate CPU status */
	346	if (cpu_addr) {
	347	/* XXX implement when SMP comes */
	348	return 3;
	349	}
	350	env->regs[r1] &= 0xffffffff00000000ULL;
	351	cc = 1;
	352	break;
71e47088	353	#if !defined(CONFIG_USER_ONLY)
1864b94a AG	354	case SIGP_RESTART:
	355	qemu_system_reset_request();
	356	cpu_loop_exit(env);
	357	break;
	358	case SIGP_STOP:
	359	qemu_system_shutdown_request();
	360	cpu_loop_exit(env);
	361	break;
	362	#endif
defb0e31 AG	363	default:
	364	/* unknown sigp */
	365	fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
	366	cc = 3;
	367	}
	368
	369	return cc;
	370	}
defb0e31	371	#endif