[qemu.git] / target-s390x / misc_helper.c

/*
 *  S/390 misc helper routines
 *
 *  Copyright (c) 2009 Ulrich Hecht
 *  Copyright (c) 2009 Alexander Graf
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "memory.h"
#include "host-utils.h"
#include "helper.h"
#include <string.h>
#include "kvm.h"
#include "qemu-timer.h"
#ifdef CONFIG_KVM
#include <linux/kvm.h>
#endif

#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#include "sysemu.h"
#endif

/* #define DEBUG_HELPER */
#ifdef DEBUG_HELPER
#define HELPER_LOG(x...) qemu_log(x)
#else
#define HELPER_LOG(x...)
#endif

/* raise an exception */
void HELPER(exception)(CPUS390XState *env, uint32_t excp)
{
    HELPER_LOG("%s: exception %d\n", __func__, excp);
    env->exception_index = excp;
    cpu_loop_exit(env);
}

#ifndef CONFIG_USER_ONLY
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
{
    qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
                  env->psw.addr);

    if (kvm_enabled()) {
#ifdef CONFIG_KVM
        kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
#endif
    } else {
        env->int_pgm_code = code;
        env->int_pgm_ilc = ilc;
        env->exception_index = EXCP_PGM;
        cpu_loop_exit(env);
    }
}

/* SCLP service call */
uint32_t HELPER(servc)(CPUS390XState *env, uint32_t r1, uint64_t r2)
{
    int r;

    r = sclp_service_call(r1, r2);
    if (r < 0) {
        program_interrupt(env, -r, 4);
        return 0;
    }
    return r;
}

/* DIAG */
uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
                      uint64_t code)
{
    uint64_t r;

    switch (num) {
    case 0x500:
        /* KVM hypercall */
        r = s390_virtio_hypercall(env, mem, code);
        break;
    case 0x44:
        /* yield */
        r = 0;
        break;
    case 0x308:
        /* ipl */
        r = 0;
        break;
    default:
        r = -1;
        break;
    }

    if (r) {
        program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
    }

    return r;
}

/* Store CPU ID */
void HELPER(stidp)(CPUS390XState *env, uint64_t a1)
{
    cpu_stq_data(env, a1, env->cpu_num);
}

/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
    uint32_t prefix;

    prefix = cpu_ldl_data(env, a1);
    env->psa = prefix & 0xfffff000;
    qemu_log("prefix: %#x\n", prefix);
    tlb_flush_page(env, 0);
    tlb_flush_page(env, TARGET_PAGE_SIZE);
}

/* Set Clock */
uint32_t HELPER(sck)(uint64_t a1)
{
    /* XXX not implemented - is it necessary? */

    return 0;
}

static inline uint64_t clock_value(CPUS390XState *env)
{
    uint64_t time;

    time = env->tod_offset +
        time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);

    return time;
}

/* Store Clock */
uint32_t HELPER(stck)(CPUS390XState *env, uint64_t a1)
{
    cpu_stq_data(env, a1, clock_value(env));

    return 0;
}

/* Store Clock Extended */
uint32_t HELPER(stcke)(CPUS390XState *env, uint64_t a1)
{
    cpu_stb_data(env, a1, 0);
    /* basically the same value as stck */
    cpu_stq_data(env, a1 + 1, clock_value(env) | env->cpu_num);
    /* more fine grained than stck */
    cpu_stq_data(env, a1 + 9, 0);
    /* XXX programmable fields */
    cpu_stw_data(env, a1 + 17, 0);

    return 0;
}

/* Set Clock Comparator */
void HELPER(sckc)(CPUS390XState *env, uint64_t a1)
{
    uint64_t time = cpu_ldq_data(env, a1);

    if (time == -1ULL) {
        return;
    }

    /* difference between now and then */
    time -= clock_value(env);
    /* nanoseconds */
    time = (time * 125) >> 9;

    qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
}

/* Store Clock Comparator */
void HELPER(stckc)(CPUS390XState *env, uint64_t a1)
{
    /* XXX implement */
    cpu_stq_data(env, a1, 0);
}

/* Set CPU Timer */
void HELPER(spt)(CPUS390XState *env, uint64_t a1)
{
    uint64_t time = cpu_ldq_data(env, a1);

    if (time == -1ULL) {
        return;
    }

    /* nanoseconds */
    time = (time * 125) >> 9;

    qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
}

/* Store CPU Timer */
void HELPER(stpt)(CPUS390XState *env, uint64_t a1)
{
    /* XXX implement */
    cpu_stq_data(env, a1, 0);
}

/* Store System Information */
uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint32_t r0,
                      uint32_t r1)
{
    int cc = 0;
    int sel1, sel2;

    if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
        ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
        /* valid function code, invalid reserved bits */
        program_interrupt(env, PGM_SPECIFICATION, 2);
    }

    sel1 = r0 & STSI_R0_SEL1_MASK;
    sel2 = r1 & STSI_R1_SEL2_MASK;

    /* XXX: spec exception if sysib is not 4k-aligned */

    switch (r0 & STSI_LEVEL_MASK) {
    case STSI_LEVEL_1:
        if ((sel1 == 1) && (sel2 == 1)) {
            /* Basic Machine Configuration */
            struct sysib_111 sysib;

            memset(&sysib, 0, sizeof(sysib));
            ebcdic_put(sysib.manuf, "QEMU            ", 16);
            /* same as machine type number in STORE CPU ID */
            ebcdic_put(sysib.type, "QEMU", 4);
            /* same as model number in STORE CPU ID */
            ebcdic_put(sysib.model, "QEMU            ", 16);
            ebcdic_put(sysib.sequence, "QEMU            ", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 1)) {
            /* Basic Machine CPU */
            struct sysib_121 sysib;

            memset(&sysib, 0, sizeof(sysib));
            /* XXX make different for different CPUs? */
            ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
            ebcdic_put(sysib.plant, "QEMU", 4);
            stw_p(&sysib.cpu_addr, env->cpu_num);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else if ((sel1 == 2) && (sel2 == 2)) {
            /* Basic Machine CPUs */
            struct sysib_122 sysib;

            memset(&sysib, 0, sizeof(sysib));
            stl_p(&sysib.capability, 0x443afc29);
            /* XXX change when SMP comes */
            stw_p(&sysib.total_cpus, 1);
            stw_p(&sysib.active_cpus, 1);
            stw_p(&sysib.standby_cpus, 0);
            stw_p(&sysib.reserved_cpus, 0);
            cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
        } else {
            cc = 3;
        }
        break;
    case STSI_LEVEL_2:
        {
            if ((sel1 == 2) && (sel2 == 1)) {
                /* LPAR CPU */
                struct sysib_221 sysib;

                memset(&sysib, 0, sizeof(sysib));
                /* XXX make different for different CPUs? */
                ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
                ebcdic_put(sysib.plant, "QEMU", 4);
                stw_p(&sysib.cpu_addr, env->cpu_num);
                stw_p(&sysib.cpu_id, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else if ((sel1 == 2) && (sel2 == 2)) {
                /* LPAR CPUs */
                struct sysib_222 sysib;

                memset(&sysib, 0, sizeof(sysib));
                stw_p(&sysib.lpar_num, 0);
                sysib.lcpuc = 0;
                /* XXX change when SMP comes */
                stw_p(&sysib.total_cpus, 1);
                stw_p(&sysib.conf_cpus, 1);
                stw_p(&sysib.standby_cpus, 0);
                stw_p(&sysib.reserved_cpus, 0);
                ebcdic_put(sysib.name, "QEMU    ", 8);
                stl_p(&sysib.caf, 1000);
                stw_p(&sysib.dedicated_cpus, 0);
                stw_p(&sysib.shared_cpus, 0);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_3:
        {
            if ((sel1 == 2) && (sel2 == 2)) {
                /* VM CPUs */
                struct sysib_322 sysib;

                memset(&sysib, 0, sizeof(sysib));
                sysib.count = 1;
                /* XXX change when SMP comes */
                stw_p(&sysib.vm[0].total_cpus, 1);
                stw_p(&sysib.vm[0].conf_cpus, 1);
                stw_p(&sysib.vm[0].standby_cpus, 0);
                stw_p(&sysib.vm[0].reserved_cpus, 0);
                ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
                stl_p(&sysib.vm[0].caf, 1000);
                ebcdic_put(sysib.vm[0].cpi, "KVM/Linux       ", 16);
                cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
            } else {
                cc = 3;
            }
            break;
        }
    case STSI_LEVEL_CURRENT:
        env->regs[0] = STSI_LEVEL_3;
        break;
    default:
        cc = 3;
        break;
    }

    return cc;
}

uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
                      uint64_t cpu_addr)
{
    int cc = 0;

    HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
               __func__, order_code, r1, cpu_addr);

    /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
       as parameter (input). Status (output) is always R1. */

    switch (order_code) {
    case SIGP_SET_ARCH:
        /* switch arch */
        break;
    case SIGP_SENSE:
        /* enumerate CPU status */
        if (cpu_addr) {
            /* XXX implement when SMP comes */
            return 3;
        }
        env->regs[r1] &= 0xffffffff00000000ULL;
        cc = 1;
        break;
#if !defined(CONFIG_USER_ONLY)
    case SIGP_RESTART:
        qemu_system_reset_request();
        cpu_loop_exit(env);
        break;
    case SIGP_STOP:
        qemu_system_shutdown_request();
        cpu_loop_exit(env);
        break;
#endif
    default:
        /* unknown sigp */
        fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
        cc = 3;
    }

    return cc;
}
#endif
Commit	Line	Data
10ec5117	1	/*
aea1e885	2	* S/390 misc helper routines
10ec5117	3	*
defb0e31	4	* Copyright (c) 2009 Ulrich Hecht
10ec5117 AG	5	* Copyright (c) 2009 Alexander Graf
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
70539e18	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 AG	19	*/
10ec5117 AG	20
3e457172	21	#include "cpu.h"
9abf567d	22	#include "memory.h"
defb0e31	23	#include "host-utils.h"
3208afbe	24	#include "helper.h"
defb0e31 AG	25	#include <string.h>
	26	#include "kvm.h"
	27	#include "qemu-timer.h"
af2be207 JK	28	#ifdef CONFIG_KVM
	29	#include <linux/kvm.h>
	30	#endif
10ec5117	31
71e47088	32	#if !defined(CONFIG_USER_ONLY)
3e457172	33	#include "softmmu_exec.h"
8ef7f78e	34	#include "sysemu.h"
10ec5117	35	#endif
d5a43964	36
defb0e31 AG	37	/* #define DEBUG_HELPER */
	38	#ifdef DEBUG_HELPER
	39	#define HELPER_LOG(x...) qemu_log(x)
	40	#else
	41	#define HELPER_LOG(x...)
	42	#endif
	43
	44	/* raise an exception */
089f5c06	45	void HELPER(exception)(CPUS390XState *env, uint32_t excp)
defb0e31	46	{
71e47088	47	HELPER_LOG("%s: exception %d\n", __func__, excp);
defb0e31	48	env->exception_index = excp;
1162c041	49	cpu_loop_exit(env);
defb0e31 AG	50	}
defb0e31 AG	51
defb0e31	52	#ifndef CONFIG_USER_ONLY
a78b0504	53	void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
defb0e31	54	{
0d404541 RH	55	qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
0d404541 RH	56	env->psw.addr);
defb0e31 AG	57
defb0e31 AG	58	if (kvm_enabled()) {
af2be207	59	#ifdef CONFIG_KVM
defb0e31	60	kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
af2be207	61	#endif
defb0e31 AG	62	} else {
	63	env->int_pgm_code = code;
	64	env->int_pgm_ilc = ilc;
	65	env->exception_index = EXCP_PGM;
1162c041	66	cpu_loop_exit(env);
defb0e31 AG	67	}
	68	}
	69
defb0e31	70	/* SCLP service call */
089f5c06	71	uint32_t HELPER(servc)(CPUS390XState *env, uint32_t r1, uint64_t r2)
defb0e31	72	{
9abf567d	73	int r;
defb0e31	74
f6c98f92	75	r = sclp_service_call(r1, r2);
9abf567d CB	76	if (r < 0) {
	77	program_interrupt(env, -r, 4);
	78	return 0;
	79	}
	80	return r;
defb0e31 AG	81	}
	82
	83	/* DIAG */
089f5c06 BS	84	uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
089f5c06 BS	85	uint64_t code)
defb0e31 AG	86	{
	87	uint64_t r;
	88
	89	switch (num) {
	90	case 0x500:
	91	/* KVM hypercall */
	92	r = s390_virtio_hypercall(env, mem, code);
	93	break;
	94	case 0x44:
	95	/* yield */
	96	r = 0;
	97	break;
	98	case 0x308:
	99	/* ipl */
	100	r = 0;
	101	break;
	102	default:
	103	r = -1;
	104	break;
	105	}
	106
	107	if (r) {
	108	program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
	109	}
	110
	111	return r;
	112	}
	113
	114	/* Store CPU ID */
089f5c06	115	void HELPER(stidp)(CPUS390XState *env, uint64_t a1)
defb0e31	116	{
089f5c06	117	cpu_stq_data(env, a1, env->cpu_num);
defb0e31 AG	118	}
	119
	120	/* Set Prefix */
089f5c06	121	void HELPER(spx)(CPUS390XState *env, uint64_t a1)
defb0e31 AG	122	{
	123	uint32_t prefix;
	124
089f5c06	125	prefix = cpu_ldl_data(env, a1);
defb0e31 AG	126	env->psa = prefix & 0xfffff000;
	127	qemu_log("prefix: %#x\n", prefix);
	128	tlb_flush_page(env, 0);
	129	tlb_flush_page(env, TARGET_PAGE_SIZE);
	130	}
	131
	132	/* Set Clock */
	133	uint32_t HELPER(sck)(uint64_t a1)
	134	{
	135	/* XXX not implemented - is it necessary? */
	136
	137	return 0;
	138	}
	139
a4e3ad19	140	static inline uint64_t clock_value(CPUS390XState *env)
defb0e31 AG	141	{
	142	uint64_t time;
	143
	144	time = env->tod_offset +
71e47088	145	time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
defb0e31 AG	146
	147	return time;
	148	}
	149
	150	/* Store Clock */
089f5c06	151	uint32_t HELPER(stck)(CPUS390XState *env, uint64_t a1)
defb0e31	152	{
089f5c06	153	cpu_stq_data(env, a1, clock_value(env));
defb0e31 AG	154
	155	return 0;
	156	}
	157
	158	/* Store Clock Extended */
089f5c06	159	uint32_t HELPER(stcke)(CPUS390XState *env, uint64_t a1)
defb0e31	160	{
089f5c06	161	cpu_stb_data(env, a1, 0);
defb0e31	162	/* basically the same value as stck */
089f5c06	163	cpu_stq_data(env, a1 + 1, clock_value(env) \| env->cpu_num);
defb0e31	164	/* more fine grained than stck */
089f5c06	165	cpu_stq_data(env, a1 + 9, 0);
defb0e31	166	/* XXX programmable fields */
089f5c06	167	cpu_stw_data(env, a1 + 17, 0);
defb0e31	168
defb0e31 AG	169	return 0;
	170	}
	171
	172	/* Set Clock Comparator */
089f5c06	173	void HELPER(sckc)(CPUS390XState *env, uint64_t a1)
defb0e31	174	{
089f5c06	175	uint64_t time = cpu_ldq_data(env, a1);
defb0e31 AG	176
	177	if (time == -1ULL) {
	178	return;
	179	}
	180
	181	/* difference between now and then */
	182	time -= clock_value(env);
	183	/* nanoseconds */
	184	time = (time * 125) >> 9;
	185
	186	qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
	187	}
	188
	189	/* Store Clock Comparator */
089f5c06	190	void HELPER(stckc)(CPUS390XState *env, uint64_t a1)
defb0e31 AG	191	{
defb0e31 AG	192	/* XXX implement */
089f5c06	193	cpu_stq_data(env, a1, 0);
defb0e31 AG	194	}
	195
	196	/* Set CPU Timer */
089f5c06	197	void HELPER(spt)(CPUS390XState *env, uint64_t a1)
defb0e31	198	{
089f5c06	199	uint64_t time = cpu_ldq_data(env, a1);
defb0e31 AG	200
	201	if (time == -1ULL) {
	202	return;
	203	}
	204
	205	/* nanoseconds */
	206	time = (time * 125) >> 9;
	207
	208	qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
	209	}
	210
	211	/* Store CPU Timer */
089f5c06	212	void HELPER(stpt)(CPUS390XState *env, uint64_t a1)
defb0e31 AG	213	{
defb0e31 AG	214	/* XXX implement */
089f5c06	215	cpu_stq_data(env, a1, 0);
defb0e31 AG	216	}
	217
	218	/* Store System Information */
089f5c06 BS	219	uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint32_t r0,
089f5c06 BS	220	uint32_t r1)
defb0e31 AG	221	{
	222	int cc = 0;
	223	int sel1, sel2;
	224
	225	if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
	226	((r0 & STSI_R0_RESERVED_MASK) \|\| (r1 & STSI_R1_RESERVED_MASK))) {
	227	/* valid function code, invalid reserved bits */
	228	program_interrupt(env, PGM_SPECIFICATION, 2);
	229	}
	230
	231	sel1 = r0 & STSI_R0_SEL1_MASK;
	232	sel2 = r1 & STSI_R1_SEL2_MASK;
	233
	234	/* XXX: spec exception if sysib is not 4k-aligned */
	235
	236	switch (r0 & STSI_LEVEL_MASK) {
	237	case STSI_LEVEL_1:
	238	if ((sel1 == 1) && (sel2 == 1)) {
	239	/* Basic Machine Configuration */
	240	struct sysib_111 sysib;
	241
	242	memset(&sysib, 0, sizeof(sysib));
	243	ebcdic_put(sysib.manuf, "QEMU ", 16);
	244	/* same as machine type number in STORE CPU ID */
	245	ebcdic_put(sysib.type, "QEMU", 4);
	246	/* same as model number in STORE CPU ID */
	247	ebcdic_put(sysib.model, "QEMU ", 16);
	248	ebcdic_put(sysib.sequence, "QEMU ", 16);
	249	ebcdic_put(sysib.plant, "QEMU", 4);
71e47088	250	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	251	} else if ((sel1 == 2) && (sel2 == 1)) {
	252	/* Basic Machine CPU */
	253	struct sysib_121 sysib;
	254
	255	memset(&sysib, 0, sizeof(sysib));
	256	/* XXX make different for different CPUs? */
	257	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	258	ebcdic_put(sysib.plant, "QEMU", 4);
	259	stw_p(&sysib.cpu_addr, env->cpu_num);
71e47088	260	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	261	} else if ((sel1 == 2) && (sel2 == 2)) {
	262	/* Basic Machine CPUs */
	263	struct sysib_122 sysib;
	264
	265	memset(&sysib, 0, sizeof(sysib));
	266	stl_p(&sysib.capability, 0x443afc29);
	267	/* XXX change when SMP comes */
	268	stw_p(&sysib.total_cpus, 1);
	269	stw_p(&sysib.active_cpus, 1);
	270	stw_p(&sysib.standby_cpus, 0);
	271	stw_p(&sysib.reserved_cpus, 0);
71e47088	272	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
defb0e31 AG	273	} else {
	274	cc = 3;
	275	}
	276	break;
	277	case STSI_LEVEL_2:
71e47088 BS	278	{
	279	if ((sel1 == 2) && (sel2 == 1)) {
	280	/* LPAR CPU */
	281	struct sysib_221 sysib;
	282
	283	memset(&sysib, 0, sizeof(sysib));
	284	/* XXX make different for different CPUs? */
	285	ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
	286	ebcdic_put(sysib.plant, "QEMU", 4);
	287	stw_p(&sysib.cpu_addr, env->cpu_num);
	288	stw_p(&sysib.cpu_id, 0);
	289	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	290	} else if ((sel1 == 2) && (sel2 == 2)) {
	291	/* LPAR CPUs */
	292	struct sysib_222 sysib;
	293
	294	memset(&sysib, 0, sizeof(sysib));
	295	stw_p(&sysib.lpar_num, 0);
	296	sysib.lcpuc = 0;
	297	/* XXX change when SMP comes */
	298	stw_p(&sysib.total_cpus, 1);
	299	stw_p(&sysib.conf_cpus, 1);
	300	stw_p(&sysib.standby_cpus, 0);
	301	stw_p(&sysib.reserved_cpus, 0);
	302	ebcdic_put(sysib.name, "QEMU ", 8);
	303	stl_p(&sysib.caf, 1000);
	304	stw_p(&sysib.dedicated_cpus, 0);
	305	stw_p(&sysib.shared_cpus, 0);
	306	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	307	} else {
	308	cc = 3;
	309	}
	310	break;
defb0e31	311	}
defb0e31	312	case STSI_LEVEL_3:
71e47088 BS	313	{
	314	if ((sel1 == 2) && (sel2 == 2)) {
	315	/* VM CPUs */
	316	struct sysib_322 sysib;
	317
	318	memset(&sysib, 0, sizeof(sysib));
	319	sysib.count = 1;
	320	/* XXX change when SMP comes */
	321	stw_p(&sysib.vm[0].total_cpus, 1);
	322	stw_p(&sysib.vm[0].conf_cpus, 1);
	323	stw_p(&sysib.vm[0].standby_cpus, 0);
	324	stw_p(&sysib.vm[0].reserved_cpus, 0);
	325	ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
	326	stl_p(&sysib.vm[0].caf, 1000);
	327	ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
	328	cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
	329	} else {
	330	cc = 3;
	331	}
	332	break;
defb0e31	333	}
defb0e31 AG	334	case STSI_LEVEL_CURRENT:
	335	env->regs[0] = STSI_LEVEL_3;
	336	break;
	337	default:
	338	cc = 3;
	339	break;
	340	}
	341
	342	return cc;
	343	}
	344
089f5c06 BS	345	uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
089f5c06 BS	346	uint64_t cpu_addr)
defb0e31 AG	347	{
	348	int cc = 0;
	349
	350	HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
71e47088	351	__func__, order_code, r1, cpu_addr);
defb0e31	352
71e47088	353	/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
defb0e31 AG	354	as parameter (input). Status (output) is always R1. */
	355
	356	switch (order_code) {
	357	case SIGP_SET_ARCH:
	358	/* switch arch */
	359	break;
	360	case SIGP_SENSE:
	361	/* enumerate CPU status */
	362	if (cpu_addr) {
	363	/* XXX implement when SMP comes */
	364	return 3;
	365	}
	366	env->regs[r1] &= 0xffffffff00000000ULL;
	367	cc = 1;
	368	break;
71e47088	369	#if !defined(CONFIG_USER_ONLY)
1864b94a AG	370	case SIGP_RESTART:
	371	qemu_system_reset_request();
	372	cpu_loop_exit(env);
	373	break;
	374	case SIGP_STOP:
	375	qemu_system_shutdown_request();
	376	cpu_loop_exit(env);
	377	break;
	378	#endif
defb0e31 AG	379	default:
	380	/* unknown sigp */
	381	fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
	382	cc = 3;
	383	}
	384
	385	return cc;
	386	}
defb0e31	387	#endif