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Properly implement non-execute bit on PowerPC segments and PTEs.
[qemu.git] / target-ppc / helper.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
fdabc366
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
9a64fbe4
FB		 30
31//#define DEBUG_MMU
32//#define DEBUG_BATS
76a66253 33//#define DEBUG_SOFTWARE_TLB
9a64fbe4 34//#define DEBUG_EXCEPTIONS
fdabc366 35//#define FLUSH_ALL_TLBS
9a64fbe4 36
9a64fbe4 37/*****************************************************************************/
3fc6c082 38/* PowerPC MMU emulation */
a541f297 39
d9bce9d9 40#if defined(CONFIG_USER_ONLY)
e96efcfc 41int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 42 int mmu_idx, int is_softmmu)
24741ef3
FB		 43{
44 int exception, error_code;
d9bce9d9 45
24741ef3 46 if (rw == 2) {
e1833e1f 47 exception = POWERPC_EXCP_ISI;
8f793433 48 error_code = 0x40000000;
24741ef3 49 } else {
e1833e1f 50 exception = POWERPC_EXCP_DSI;
8f793433 51 error_code = 0x40000000;
24741ef3
FB		 52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
76a66253 59
24741ef3
FB		 60 return 1;
61}
76a66253 62
9b3c35e0 63target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB		 64{
65 return addr;
66}
36081602 67
24741ef3 68#else
76a66253 69/* Common routines used by software and hardware TLBs emulation */
b068d6a7 70static always_inline int pte_is_valid (target_ulong pte0)
76a66253
JM		 71{
72 return pte0 & 0x80000000 ? 1 : 0;
73}
74
b068d6a7 75static always_inline void pte_invalidate (target_ulong *pte0)
76a66253
JM		 76{
77 *pte0 &= ~0x80000000;
78}
79
caa4039c 80#if defined(TARGET_PPC64)
b068d6a7 81static always_inline int pte64_is_valid (target_ulong pte0)
caa4039c
JM		 82{
83 return pte0 & 0x0000000000000001ULL ? 1 : 0;
84}
85
b068d6a7 86static always_inline void pte64_invalidate (target_ulong *pte0)
caa4039c
JM		 87{
88 *pte0 &= ~0x0000000000000001ULL;
89}
90#endif
91
76a66253
JM		 92#define PTE_PTEM_MASK 0x7FFFFFBF
93#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
caa4039c
JM		 94#if defined(TARGET_PPC64)
95#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97#endif
76a66253 98
b227a8e9
JM		 99static always_inline int pp_check (int key, int pp, int nx)
100{
101 int access;
102
103 /* Compute access rights */
104 /* When pp is 3/7, the result is undefined. Set it to noaccess */
105 access = 0;
106 if (key == 0) {
107 switch (pp) {
108 case 0x0:
109 case 0x1:
110 case 0x2:
111 access |= PAGE_WRITE;
112 /* No break here */
113 case 0x3:
114 case 0x6:
115 access |= PAGE_READ;
116 break;
117 }
118 } else {
119 switch (pp) {
120 case 0x0:
121 case 0x6:
122 access = 0;
123 break;
124 case 0x1:
125 case 0x3:
126 access = PAGE_READ;
127 break;
128 case 0x2:
129 access = PAGE_READ | PAGE_WRITE;
130 break;
131 }
132 }
133 if (nx == 0)
134 access |= PAGE_EXEC;
135
136 return access;
137}
138
139static always_inline int check_prot (int prot, int rw, int access_type)
140{
141 int ret;
142
143 if (access_type == ACCESS_CODE) {
144 if (prot & PAGE_EXEC)
145 ret = 0;
146 else
147 ret = -2;
148 } else if (rw) {
149 if (prot & PAGE_WRITE)
150 ret = 0;
151 else
152 ret = -2;
153 } else {
154 if (prot & PAGE_READ)
155 ret = 0;
156 else
157 ret = -2;
158 }
159
160 return ret;
161}
162
b068d6a7
JM		 163static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
164 target_ulong pte0, target_ulong pte1,
b227a8e9 165 int h, int rw, int type)
76a66253 166{
caa4039c 167 target_ulong ptem, mmask;
b227a8e9 168 int access, ret, pteh, ptev, pp;
76a66253
JM		 169
170 access = 0;
171 ret = -1;
172 /* Check validity and table match */
caa4039c
JM		 173#if defined(TARGET_PPC64)
174 if (is_64b) {
175 ptev = pte64_is_valid(pte0);
176 pteh = (pte0 >> 1) & 1;
177 } else
178#endif
179 {
180 ptev = pte_is_valid(pte0);
181 pteh = (pte0 >> 6) & 1;
182 }
183 if (ptev && h == pteh) {
76a66253 184 /* Check vsid & api */
caa4039c
JM		 185#if defined(TARGET_PPC64)
186 if (is_64b) {
187 ptem = pte0 & PTE64_PTEM_MASK;
188 mmask = PTE64_CHECK_MASK;
b227a8e9
JM		 189 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
190 ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */
191 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
caa4039c
JM		 192 } else
193#endif
194 {
195 ptem = pte0 & PTE_PTEM_MASK;
196 mmask = PTE_CHECK_MASK;
b227a8e9 197 pp = pte1 & 0x00000003;
caa4039c
JM		 198 }
199 if (ptem == ctx->ptem) {
76a66253
JM		 200 if (ctx->raddr != (target_ulong)-1) {
201 /* all matches should have equal RPN, WIMG & PP */
caa4039c
JM		 202 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
203 if (loglevel != 0)
76a66253
JM		 204 fprintf(logfile, "Bad RPN/WIMG/PP\n");
205 return -3;
206 }
207 }
208 /* Compute access rights */
b227a8e9 209 access = pp_check(ctx->key, pp, ctx->nx);
76a66253
JM		 210 /* Keep the matching PTE informations */
211 ctx->raddr = pte1;
212 ctx->prot = access;
b227a8e9
JM		 213 ret = check_prot(ctx->prot, rw, type);
214 if (ret == 0) {
76a66253
JM		 215 /* Access granted */
216#if defined (DEBUG_MMU)
4a057712 217 if (loglevel != 0)
76a66253
JM		 218 fprintf(logfile, "PTE access granted !\n");
219#endif
76a66253
JM		 220 } else {
221 /* Access right violation */
222#if defined (DEBUG_MMU)
4a057712 223 if (loglevel != 0)
76a66253
JM		 224 fprintf(logfile, "PTE access rejected\n");
225#endif
76a66253
JM		 226 }
227 }
228 }
229
230 return ret;
231}
232
b227a8e9
JM		 233static int pte32_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,
234 int h, int rw, int type)
caa4039c 235{
b227a8e9 236 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
caa4039c
JM		 237}
238
239#if defined(TARGET_PPC64)
b227a8e9
JM		 240static int pte64_check (mmu_ctx_t *ctx, target_ulong pte0, target_ulong pte1,
241 int h, int rw, int type)
caa4039c 242{
b227a8e9 243 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
caa4039c
JM		 244}
245#endif
246
76a66253
JM		 247static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
248 int ret, int rw)
249{
250 int store = 0;
251
252 /* Update page flags */
253 if (!(*pte1p & 0x00000100)) {
254 /* Update accessed flag */
255 *pte1p |= 0x00000100;
256 store = 1;
257 }
258 if (!(*pte1p & 0x00000080)) {
259 if (rw == 1 && ret == 0) {
260 /* Update changed flag */
261 *pte1p |= 0x00000080;
262 store = 1;
263 } else {
264 /* Force page fault for first write access */
265 ctx->prot &= ~PAGE_WRITE;
266 }
267 }
268
269 return store;
270}
271
272/* Software driven TLB helpers */
273static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
274 int way, int is_code)
275{
276 int nr;
277
278 /* Select TLB num in a way from address */
279 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
280 /* Select TLB way */
281 nr += env->tlb_per_way * way;
282 /* 6xx have separate TLBs for instructions and data */
283 if (is_code && env->id_tlbs == 1)
284 nr += env->nb_tlb;
285
286 return nr;
287}
288
daf4f96e 289static void ppc6xx_tlb_invalidate_all (CPUState *env)
76a66253 290{
1d0a48fb 291 ppc6xx_tlb_t *tlb;
76a66253
JM		 292 int nr, max;
293
294#if defined (DEBUG_SOFTWARE_TLB) && 0
295 if (loglevel != 0) {
296 fprintf(logfile, "Invalidate all TLBs\n");
297 }
298#endif
299 /* Invalidate all defined software TLB */
300 max = env->nb_tlb;
301 if (env->id_tlbs == 1)
302 max *= 2;
303 for (nr = 0; nr < max; nr++) {
1d0a48fb 304 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 305 pte_invalidate(&tlb->pte0);
306 }
76a66253 307 tlb_flush(env, 1);
76a66253
JM		 308}
309
b068d6a7
JM		 310static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
311 target_ulong eaddr,
312 int is_code,
313 int match_epn)
76a66253 314{
4a057712 315#if !defined(FLUSH_ALL_TLBS)
1d0a48fb 316 ppc6xx_tlb_t *tlb;
76a66253
JM		 317 int way, nr;
318
76a66253
JM		 319 /* Invalidate ITLB + DTLB, all ways */
320 for (way = 0; way < env->nb_ways; way++) {
321 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
1d0a48fb 322 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 323 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
324#if defined (DEBUG_SOFTWARE_TLB)
325 if (loglevel != 0) {
1b9eb036 326 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM		 327 nr, env->nb_tlb, eaddr);
328 }
329#endif
330 pte_invalidate(&tlb->pte0);
331 tlb_flush_page(env, tlb->EPN);
332 }
333 }
334#else
335 /* XXX: PowerPC specification say this is valid as well */
336 ppc6xx_tlb_invalidate_all(env);
337#endif
338}
339
daf4f96e
JM		 340static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
341 int is_code)
76a66253
JM		 342{
343 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
344}
345
346void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
347 target_ulong pte0, target_ulong pte1)
348{
1d0a48fb 349 ppc6xx_tlb_t *tlb;
76a66253
JM		 350 int nr;
351
352 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
1d0a48fb 353 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 354#if defined (DEBUG_SOFTWARE_TLB)
355 if (loglevel != 0) {
5fafdf24 356 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
1b9eb036 357 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM		 358 }
359#endif
360 /* Invalidate any pending reference in Qemu for this virtual address */
361 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
362 tlb->pte0 = pte0;
363 tlb->pte1 = pte1;
364 tlb->EPN = EPN;
76a66253
JM		 365 /* Store last way for LRU mechanism */
366 env->last_way = way;
367}
368
369static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
370 target_ulong eaddr, int rw, int access_type)
371{
1d0a48fb 372 ppc6xx_tlb_t *tlb;
76a66253
JM		 373 int nr, best, way;
374 int ret;
d9bce9d9 375
76a66253
JM		 376 best = -1;
377 ret = -1; /* No TLB found */
378 for (way = 0; way < env->nb_ways; way++) {
379 nr = ppc6xx_tlb_getnum(env, eaddr, way,
380 access_type == ACCESS_CODE ? 1 : 0);
1d0a48fb 381 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 382 /* This test "emulates" the PTE index match for hardware TLBs */
383 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
384#if defined (DEBUG_SOFTWARE_TLB)
385 if (loglevel != 0) {
1b9eb036
JM		 386 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
387 "] <> " ADDRX "\n",
76a66253
JM		 388 nr, env->nb_tlb,
389 pte_is_valid(tlb->pte0) ? "valid" : "inval",
390 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
391 }
392#endif
393 continue;
394 }
395#if defined (DEBUG_SOFTWARE_TLB)
396 if (loglevel != 0) {
1b9eb036
JM		 397 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
398 " %c %c\n",
76a66253
JM		 399 nr, env->nb_tlb,
400 pte_is_valid(tlb->pte0) ? "valid" : "inval",
401 tlb->EPN, eaddr, tlb->pte1,
402 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
403 }
404#endif
b227a8e9 405 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
76a66253
JM		 406 case -3:
407 /* TLB inconsistency */
408 return -1;
409 case -2:
410 /* Access violation */
411 ret = -2;
412 best = nr;
413 break;
414 case -1:
415 default:
416 /* No match */
417 break;
418 case 0:
419 /* access granted */
420 /* XXX: we should go on looping to check all TLBs consistency
421 * but we can speed-up the whole thing as the
422 * result would be undefined if TLBs are not consistent.
423 */
424 ret = 0;
425 best = nr;
426 goto done;
427 }
428 }
429 if (best != -1) {
430 done:
431#if defined (DEBUG_SOFTWARE_TLB)
4a057712 432 if (loglevel != 0) {
76a66253
JM		 433 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
434 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
435 }
436#endif
437 /* Update page flags */
1d0a48fb 438 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
76a66253
JM		 439 }
440
441 return ret;
442}
443
9a64fbe4 444/* Perform BAT hit & translation */
76a66253
JM		 445static int get_bat (CPUState *env, mmu_ctx_t *ctx,
446 target_ulong virtual, int rw, int type)
9a64fbe4 447{
76a66253
JM		 448 target_ulong *BATlt, *BATut, *BATu, *BATl;
449 target_ulong base, BEPIl, BEPIu, bl;
b227a8e9 450 int i, pp;
9a64fbe4
FB		 451 int ret = -1;
452
453#if defined (DEBUG_BATS)
4a057712 454 if (loglevel != 0) {
1b9eb036 455 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 456 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 457 }
9a64fbe4
FB		 458#endif
459 switch (type) {
460 case ACCESS_CODE:
461 BATlt = env->IBAT[1];
462 BATut = env->IBAT[0];
463 break;
464 default:
465 BATlt = env->DBAT[1];
466 BATut = env->DBAT[0];
467 break;
468 }
469#if defined (DEBUG_BATS)
4a057712 470 if (loglevel != 0) {
1b9eb036 471 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 472 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 473 }
9a64fbe4
FB		 474#endif
475 base = virtual & 0xFFFC0000;
476 for (i = 0; i < 4; i++) {
477 BATu = &BATut[i];
478 BATl = &BATlt[i];
479 BEPIu = *BATu & 0xF0000000;
480 BEPIl = *BATu & 0x0FFE0000;
481 bl = (*BATu & 0x00001FFC) << 15;
482#if defined (DEBUG_BATS)
4a057712 483 if (loglevel != 0) {
5fafdf24 484 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
1b9eb036 485 " BATl 0x" ADDRX "\n",
9a64fbe4
FB		 486 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
487 *BATu, *BATl);
9a64fbe4
FB		 488 }
489#endif
490 if ((virtual & 0xF0000000) == BEPIu &&
491 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
492 /* BAT matches */
493 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
494 (msr_pr == 1 && (*BATu & 0x00000001))) {
495 /* Get physical address */
76a66253 496 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 497 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 498 (virtual & 0x0001F000);
b227a8e9
JM		 499 /* Compute access rights */
500 pp = *BATl & 0x00000003;
501 ctx->prot = 0;
502 if (pp != 0) {
503 ctx->prot = PAGE_READ | PAGE_EXEC;
504 if (pp == 0x2)
505 ctx->prot |= PAGE_WRITE;
506 }
507 ret = check_prot(ctx->prot, rw, type);
9a64fbe4 508#if defined (DEBUG_BATS)
b227a8e9 509 if (ret == 0 && loglevel != 0) {
4a057712 510 fprintf(logfile, "BAT %d match: r 0x" PADDRX
1b9eb036 511 " prot=%c%c\n",
76a66253
JM		 512 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
513 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 514 }
515#endif
9a64fbe4
FB		 516 break;
517 }
518 }
519 }
520 if (ret < 0) {
521#if defined (DEBUG_BATS)
4a057712
JM		 522 if (loglevel != 0) {
523 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
524 for (i = 0; i < 4; i++) {
525 BATu = &BATut[i];
526 BATl = &BATlt[i];
527 BEPIu = *BATu & 0xF0000000;
528 BEPIl = *BATu & 0x0FFE0000;
529 bl = (*BATu & 0x00001FFC) << 15;
530 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
531 " BATl 0x" ADDRX " \n\t"
532 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
533 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
534 *BATu, *BATl, BEPIu, BEPIl, bl);
535 }
9a64fbe4
FB		 536 }
537#endif
9a64fbe4 538 }
b227a8e9 539
9a64fbe4
FB		 540 /* No hit */
541 return ret;
542}
543
544/* PTE table lookup */
b227a8e9
JM		 545static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
546 int rw, int type)
9a64fbe4 547{
76a66253
JM		 548 target_ulong base, pte0, pte1;
549 int i, good = -1;
caa4039c 550 int ret, r;
9a64fbe4 551
76a66253
JM		 552 ret = -1; /* No entry found */
553 base = ctx->pg_addr[h];
9a64fbe4 554 for (i = 0; i < 8; i++) {
caa4039c
JM		 555#if defined(TARGET_PPC64)
556 if (is_64b) {
557 pte0 = ldq_phys(base + (i * 16));
558 pte1 = ldq_phys(base + (i * 16) + 8);
b227a8e9 559 r = pte64_check(ctx, pte0, pte1, h, rw, type);
12de9a39
JM		 560#if defined (DEBUG_MMU)
561 if (loglevel != 0) {
562 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
563 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
564 base + (i * 16), pte0, pte1,
565 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
566 ctx->ptem);
567 }
568#endif
caa4039c
JM		 569 } else
570#endif
571 {
572 pte0 = ldl_phys(base + (i * 8));
573 pte1 = ldl_phys(base + (i * 8) + 4);
b227a8e9 574 r = pte32_check(ctx, pte0, pte1, h, rw, type);
9a64fbe4 575#if defined (DEBUG_MMU)
12de9a39
JM		 576 if (loglevel != 0) {
577 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
578 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
579 base + (i * 8), pte0, pte1,
580 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
581 ctx->ptem);
582 }
9a64fbe4 583#endif
12de9a39 584 }
caa4039c 585 switch (r) {
76a66253
JM		 586 case -3:
587 /* PTE inconsistency */
588 return -1;
589 case -2:
590 /* Access violation */
591 ret = -2;
592 good = i;
593 break;
594 case -1:
595 default:
596 /* No PTE match */
597 break;
598 case 0:
599 /* access granted */
600 /* XXX: we should go on looping to check all PTEs consistency
601 * but if we can speed-up the whole thing as the
602 * result would be undefined if PTEs are not consistent.
603 */
604 ret = 0;
605 good = i;
606 goto done;
9a64fbe4
FB		 607 }
608 }
609 if (good != -1) {
76a66253 610 done:
9a64fbe4 611#if defined (DEBUG_MMU)
4a057712
JM		 612 if (loglevel != 0) {
613 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
1b9eb036 614 "ret=%d\n",
76a66253
JM		 615 ctx->raddr, ctx->prot, ret);
616 }
9a64fbe4
FB		 617#endif
618 /* Update page flags */
76a66253 619 pte1 = ctx->raddr;
caa4039c
JM		 620 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
621#if defined(TARGET_PPC64)
622 if (is_64b) {
623 stq_phys_notdirty(base + (good * 16) + 8, pte1);
624 } else
625#endif
626 {
627 stl_phys_notdirty(base + (good * 8) + 4, pte1);
628 }
629 }
9a64fbe4
FB		 630 }
631
632 return ret;
79aceca5
FB		 633}
634
b227a8e9 635static int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
caa4039c 636{
b227a8e9 637 return _find_pte(ctx, 0, h, rw, type);
caa4039c
JM		 638}
639
640#if defined(TARGET_PPC64)
b227a8e9 641static int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
caa4039c 642{
b227a8e9 643 return _find_pte(ctx, 1, h, rw, type);
caa4039c
JM		 644}
645#endif
646
b068d6a7 647static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
b227a8e9 648 int h, int rw, int type)
caa4039c
JM		 649{
650#if defined(TARGET_PPC64)
12de9a39 651 if (env->mmu_model == POWERPC_MMU_64B)
b227a8e9 652 return find_pte64(ctx, h, rw, type);
caa4039c
JM		 653#endif
654
b227a8e9 655 return find_pte32(ctx, h, rw, type);
caa4039c
JM		 656}
657
caa4039c 658#if defined(TARGET_PPC64)
eacc3249
JM		 659static inline int slb_is_valid (uint64_t slb64)
660{
661 return slb64 & 0x0000000008000000ULL ? 1 : 0;
662}
663
664static inline void slb_invalidate (uint64_t *slb64)
665{
666 *slb64 &= ~0x0000000008000000ULL;
667}
668
12de9a39 669static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
caa4039c
JM		 670 target_ulong *vsid, target_ulong *page_mask, int *attr)
671{
672 target_phys_addr_t sr_base;
673 target_ulong mask;
674 uint64_t tmp64;
675 uint32_t tmp;
676 int n, ret;
caa4039c
JM		 677
678 ret = -5;
679 sr_base = env->spr[SPR_ASR];
12de9a39
JM		 680#if defined(DEBUG_SLB)
681 if (loglevel != 0) {
682 fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
683 __func__, eaddr, sr_base);
684 }
685#endif
caa4039c 686 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
eacc3249 687 for (n = 0; n < env->slb_nr; n++) {
caa4039c 688 tmp64 = ldq_phys(sr_base);
12de9a39
JM		 689 tmp = ldl_phys(sr_base + 8);
690#if defined(DEBUG_SLB)
691 if (loglevel != 0) {
b33c17e1
JM		 692 fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"
693 PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
12de9a39
JM		 694 }
695#endif
eacc3249 696 if (slb_is_valid(tmp64)) {
caa4039c
JM		 697 /* SLB entry is valid */
698 switch (tmp64 & 0x0000000006000000ULL) {
699 case 0x0000000000000000ULL:
700 /* 256 MB segment */
701 mask = 0xFFFFFFFFF0000000ULL;
702 break;
703 case 0x0000000002000000ULL:
704 /* 1 TB segment */
705 mask = 0xFFFF000000000000ULL;
706 break;
707 case 0x0000000004000000ULL:
708 case 0x0000000006000000ULL:
709 /* Reserved => segment is invalid */
710 continue;
711 }
712 if ((eaddr & mask) == (tmp64 & mask)) {
713 /* SLB match */
caa4039c
JM		 714 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
715 *page_mask = ~mask;
716 *attr = tmp & 0xFF;
eacc3249 717 ret = n;
caa4039c
JM		 718 break;
719 }
720 }
721 sr_base += 12;
722 }
723
724 return ret;
79aceca5 725}
12de9a39 726
eacc3249
JM		 727void ppc_slb_invalidate_all (CPUPPCState *env)
728{
729 target_phys_addr_t sr_base;
730 uint64_t tmp64;
731 int n, do_invalidate;
732
733 do_invalidate = 0;
734 sr_base = env->spr[SPR_ASR];
735 for (n = 0; n < env->slb_nr; n++) {
736 tmp64 = ldq_phys(sr_base);
737 if (slb_is_valid(tmp64)) {
738 slb_invalidate(&tmp64);
739 stq_phys(sr_base, tmp64);
740 /* XXX: given the fact that segment size is 256 MB or 1TB,
741 * and we still don't have a tlb_flush_mask(env, n, mask)
742 * in Qemu, we just invalidate all TLBs
743 */
744 do_invalidate = 1;
745 }
746 sr_base += 12;
747 }
748 if (do_invalidate)
749 tlb_flush(env, 1);
750}
751
752void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
753{
754 target_phys_addr_t sr_base;
755 target_ulong vsid, page_mask;
756 uint64_t tmp64;
757 int attr;
758 int n;
759
760 n = slb_lookup(env, T0, &vsid, &page_mask, &attr);
761 if (n >= 0) {
762 sr_base = env->spr[SPR_ASR];
763 sr_base += 12 * n;
764 tmp64 = ldq_phys(sr_base);
765 if (slb_is_valid(tmp64)) {
766 slb_invalidate(&tmp64);
767 stq_phys(sr_base, tmp64);
768 /* XXX: given the fact that segment size is 256 MB or 1TB,
769 * and we still don't have a tlb_flush_mask(env, n, mask)
770 * in Qemu, we just invalidate all TLBs
771 */
772 tlb_flush(env, 1);
773 }
774 }
775}
776
12de9a39
JM		 777target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
778{
779 target_phys_addr_t sr_base;
780 target_ulong rt;
781 uint64_t tmp64;
782 uint32_t tmp;
783
784 sr_base = env->spr[SPR_ASR];
785 sr_base += 12 * slb_nr;
786 tmp64 = ldq_phys(sr_base);
787 tmp = ldl_phys(sr_base + 8);
788 if (tmp64 & 0x0000000008000000ULL) {
789 /* SLB entry is valid */
790 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
791 rt = tmp >> 8; /* 65:88 => 40:63 */
792 rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
793 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
794 rt |= ((tmp >> 4) & 0xF) << 27;
795 } else {
796 rt = 0;
797 }
798#if defined(DEBUG_SLB)
799 if (loglevel != 0) {
800 fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
801 ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
802 }
803#endif
804
805 return rt;
806}
807
808void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
809{
810 target_phys_addr_t sr_base;
811 uint64_t tmp64;
812 uint32_t tmp;
813
814 sr_base = env->spr[SPR_ASR];
815 sr_base += 12 * slb_nr;
816 /* Copy Rs bits 37:63 to SLB 62:88 */
817 tmp = rs << 8;
818 tmp64 = (rs >> 24) & 0x7;
819 /* Copy Rs bits 33:36 to SLB 89:92 */
820 tmp |= ((rs >> 27) & 0xF) << 4;
821 /* Set the valid bit */
822 tmp64 |= 1 << 27;
823 /* Set ESID */
824 tmp64 |= (uint32_t)slb_nr << 28;
825#if defined(DEBUG_SLB)
826 if (loglevel != 0) {
827 fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08"
828 PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);
829 }
830#endif
831 /* Write SLB entry to memory */
832 stq_phys(sr_base, tmp64);
833 stl_phys(sr_base + 8, tmp);
834}
caa4039c 835#endif /* defined(TARGET_PPC64) */
79aceca5 836
9a64fbe4 837/* Perform segment based translation */
b068d6a7
JM		 838static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
839 int sdr_sh,
840 target_phys_addr_t hash,
841 target_phys_addr_t mask)
12de9a39
JM		 842{
843 return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
844}
845
76a66253
JM		 846static int get_segment (CPUState *env, mmu_ctx_t *ctx,
847 target_ulong eaddr, int rw, int type)
79aceca5 848{
12de9a39 849 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
caa4039c
JM		 850 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
851#if defined(TARGET_PPC64)
852 int attr;
9a64fbe4 853#endif
b227a8e9 854 int ds, vsid_sh, sdr_sh;
caa4039c
JM		 855 int ret, ret2;
856
857#if defined(TARGET_PPC64)
12de9a39
JM		 858 if (env->mmu_model == POWERPC_MMU_64B) {
859#if defined (DEBUG_MMU)
860 if (loglevel != 0) {
861 fprintf(logfile, "Check SLBs\n");
862 }
863#endif
caa4039c
JM		 864 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
865 if (ret < 0)
866 return ret;
867 ctx->key = ((attr & 0x40) && msr_pr == 1) ||
868 ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
869 ds = 0;
b227a8e9 870 ctx->nx = attr & 0x20 ? 1 : 0;
caa4039c
JM		 871 vsid_mask = 0x00003FFFFFFFFF80ULL;
872 vsid_sh = 7;
873 sdr_sh = 18;
874 sdr_mask = 0x3FF80;
875 } else
876#endif /* defined(TARGET_PPC64) */
877 {
878 sr = env->sr[eaddr >> 28];
879 page_mask = 0x0FFFFFFF;
880 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
881 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
882 ds = sr & 0x80000000 ? 1 : 0;
b227a8e9 883 ctx->nx = sr & 0x10000000 ? 1 : 0;
caa4039c
JM		 884 vsid = sr & 0x00FFFFFF;
885 vsid_mask = 0x01FFFFC0;
886 vsid_sh = 6;
887 sdr_sh = 16;
888 sdr_mask = 0xFFC0;
9a64fbe4 889#if defined (DEBUG_MMU)
caa4039c
JM		 890 if (loglevel != 0) {
891 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
892 " nip=0x" ADDRX " lr=0x" ADDRX
893 " ir=%d dr=%d pr=%d %d t=%d\n",
894 eaddr, (int)(eaddr >> 28), sr, env->nip,
895 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
896 }
9a64fbe4 897#endif
caa4039c 898 }
12de9a39
JM		 899#if defined (DEBUG_MMU)
900 if (loglevel != 0) {
901 fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
b227a8e9 902 ctx->key, ds, ctx->nx, vsid);
12de9a39
JM		 903 }
904#endif
caa4039c
JM		 905 ret = -1;
906 if (!ds) {
9a64fbe4 907 /* Check if instruction fetch is allowed, if needed */
b227a8e9 908 if (type != ACCESS_CODE || ctx->nx == 0) {
9a64fbe4 909 /* Page address translation */
76a66253
JM		 910 /* Primary table address */
911 sdr = env->sdr1;
12de9a39
JM		 912 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
913#if defined(TARGET_PPC64)
914 if (env->mmu_model == POWERPC_MMU_64B) {
915 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
916 /* XXX: this is false for 1 TB segments */
917 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
918 } else
919#endif
920 {
921 htab_mask = sdr & 0x000001FF;
922 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
923 }
924 mask = (htab_mask << sdr_sh) | sdr_mask;
925#if defined (DEBUG_MMU)
926 if (loglevel != 0) {
927 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
928 PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask,
929 page_mask);
930 }
931#endif
caa4039c 932 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
76a66253 933 /* Secondary table address */
caa4039c 934 hash = (~hash) & vsid_mask;
12de9a39
JM		 935#if defined (DEBUG_MMU)
936 if (loglevel != 0) {
937 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
938 PADDRX "\n", sdr, sdr_sh, hash, mask);
939 }
940#endif
caa4039c
JM		 941 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
942#if defined(TARGET_PPC64)
12de9a39 943 if (env->mmu_model == POWERPC_MMU_64B) {
caa4039c
JM		 944 /* Only 5 bits of the page index are used in the AVPN */
945 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
946 } else
947#endif
948 {
949 ctx->ptem = (vsid << 7) | (pgidx >> 10);
950 }
76a66253
JM		 951 /* Initialize real address with an invalid value */
952 ctx->raddr = (target_ulong)-1;
7dbe11ac
JM		 953 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
954 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
76a66253
JM		 955 /* Software TLB search */
956 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
76a66253 957 } else {
9a64fbe4 958#if defined (DEBUG_MMU)
4a057712
JM		 959 if (loglevel != 0) {
960 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
961 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
962 sdr, (uint32_t)vsid, (uint32_t)pgidx,
963 (uint32_t)hash, ctx->pg_addr[0]);
76a66253 964 }
9a64fbe4 965#endif
76a66253 966 /* Primary table lookup */
b227a8e9 967 ret = find_pte(env, ctx, 0, rw, type);
76a66253
JM		 968 if (ret < 0) {
969 /* Secondary table lookup */
9a64fbe4 970#if defined (DEBUG_MMU)
4a057712 971 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
76a66253 972 fprintf(logfile,
4a057712
JM		 973 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
974 "hash=0x%05x pg_addr=0x" PADDRX "\n",
975 sdr, (uint32_t)vsid, (uint32_t)pgidx,
976 (uint32_t)hash, ctx->pg_addr[1]);
76a66253 977 }
9a64fbe4 978#endif
b227a8e9 979 ret2 = find_pte(env, ctx, 1, rw, type);
76a66253
JM		 980 if (ret2 != -1)
981 ret = ret2;
982 }
9a64fbe4 983 }
12de9a39 984#if defined (DEBUG_MMU)
b33c17e1
JM		 985 if (loglevel != 0) {
986 target_phys_addr_t curaddr;
987 uint32_t a0, a1, a2, a3;
988 fprintf(logfile,
989 "Page table: " PADDRX " len " PADDRX "\n",
990 sdr, mask + 0x80);
991 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
992 curaddr += 16) {
993 a0 = ldl_phys(curaddr);
994 a1 = ldl_phys(curaddr + 4);
995 a2 = ldl_phys(curaddr + 8);
996 a3 = ldl_phys(curaddr + 12);
997 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
12de9a39 998 fprintf(logfile,
b33c17e1
JM		 999 PADDRX ": %08x %08x %08x %08x\n",
1000 curaddr, a0, a1, a2, a3);
12de9a39 1001 }
b33c17e1
JM		 1002 }
1003 }
12de9a39 1004#endif
9a64fbe4
FB		 1005 } else {
1006#if defined (DEBUG_MMU)
4a057712 1007 if (loglevel != 0)
76a66253 1008 fprintf(logfile, "No access allowed\n");
9a64fbe4 1009#endif
76a66253 1010 ret = -3;
9a64fbe4
FB		 1011 }
1012 } else {
1013#if defined (DEBUG_MMU)
4a057712 1014 if (loglevel != 0)
76a66253 1015 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 1016#endif
1017 /* Direct-store segment : absolutely *BUGGY* for now */
1018 switch (type) {
1019 case ACCESS_INT:
1020 /* Integer load/store : only access allowed */
1021 break;
1022 case ACCESS_CODE:
1023 /* No code fetch is allowed in direct-store areas */
1024 return -4;
1025 case ACCESS_FLOAT:
1026 /* Floating point load/store */
1027 return -4;
1028 case ACCESS_RES:
1029 /* lwarx, ldarx or srwcx. */
1030 return -4;
1031 case ACCESS_CACHE:
1032 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1033 /* Should make the instruction do no-op.
1034 * As it already do no-op, it's quite easy :-)
1035 */
76a66253 1036 ctx->raddr = eaddr;
9a64fbe4
FB		 1037 return 0;
1038 case ACCESS_EXT:
1039 /* eciwx or ecowx */
1040 return -4;
1041 default:
1042 if (logfile) {
1043 fprintf(logfile, "ERROR: instruction should not need "
1044 "address translation\n");
1045 }
9a64fbe4
FB		 1046 return -4;
1047 }
76a66253
JM		 1048 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1049 ctx->raddr = eaddr;
9a64fbe4
FB		 1050 ret = 2;
1051 } else {
1052 ret = -2;
1053 }
79aceca5 1054 }
9a64fbe4
FB		 1055
1056 return ret;
79aceca5
FB		 1057}
1058
c294fc58
JM		 1059/* Generic TLB check function for embedded PowerPC implementations */
1060static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
1061 target_phys_addr_t *raddrp,
36081602
JM		 1062 target_ulong address,
1063 uint32_t pid, int ext, int i)
c294fc58
JM		 1064{
1065 target_ulong mask;
1066
1067 /* Check valid flag */
1068 if (!(tlb->prot & PAGE_VALID)) {
1069 if (loglevel != 0)
1070 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
1071 return -1;
1072 }
1073 mask = ~(tlb->size - 1);
daf4f96e 1074#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 1075 if (loglevel != 0) {
1076 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
1077 ADDRX " " ADDRX " %d\n",
36081602 1078 __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
c294fc58 1079 }
daf4f96e 1080#endif
c294fc58 1081 /* Check PID */
36081602 1082 if (tlb->PID != 0 && tlb->PID != pid)
c294fc58
JM		 1083 return -1;
1084 /* Check effective address */
1085 if ((address & mask) != tlb->EPN)
1086 return -1;
1087 *raddrp = (tlb->RPN & mask) | (address & ~mask);
9706285b 1088#if (TARGET_PHYS_ADDR_BITS >= 36)
36081602
JM		 1089 if (ext) {
1090 /* Extend the physical address to 36 bits */
1091 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1092 }
9706285b 1093#endif
c294fc58
JM		 1094
1095 return 0;
1096}
1097
1098/* Generic TLB search function for PowerPC embedded implementations */
36081602 1099int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
c294fc58
JM		 1100{
1101 ppcemb_tlb_t *tlb;
1102 target_phys_addr_t raddr;
1103 int i, ret;
1104
1105 /* Default return value is no match */
1106 ret = -1;
a750fc0b 1107 for (i = 0; i < env->nb_tlb; i++) {
c294fc58 1108 tlb = &env->tlb[i].tlbe;
36081602 1109 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
c294fc58
JM		 1110 ret = i;
1111 break;
1112 }
1113 }
1114
1115 return ret;
1116}
1117
daf4f96e
JM		 1118/* Helpers specific to PowerPC 40x implementations */
1119static void ppc4xx_tlb_invalidate_all (CPUState *env)
a750fc0b
JM		 1120{
1121 ppcemb_tlb_t *tlb;
a750fc0b
JM		 1122 int i;
1123
1124 for (i = 0; i < env->nb_tlb; i++) {
1125 tlb = &env->tlb[i].tlbe;
daf4f96e 1126 tlb->prot &= ~PAGE_VALID;
a750fc0b 1127 }
daf4f96e 1128 tlb_flush(env, 1);
a750fc0b
JM		 1129}
1130
daf4f96e
JM		 1131static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
1132 uint32_t pid)
0a032cbe 1133{
daf4f96e 1134#if !defined(FLUSH_ALL_TLBS)
0a032cbe 1135 ppcemb_tlb_t *tlb;
daf4f96e
JM		 1136 target_phys_addr_t raddr;
1137 target_ulong page, end;
0a032cbe
JM		 1138 int i;
1139
1140 for (i = 0; i < env->nb_tlb; i++) {
1141 tlb = &env->tlb[i].tlbe;
daf4f96e 1142 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
0a032cbe
JM		 1143 end = tlb->EPN + tlb->size;
1144 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1145 tlb_flush_page(env, page);
0a032cbe 1146 tlb->prot &= ~PAGE_VALID;
daf4f96e 1147 break;
0a032cbe
JM		 1148 }
1149 }
daf4f96e
JM		 1150#else
1151 ppc4xx_tlb_invalidate_all(env);
1152#endif
0a032cbe
JM		 1153}
1154
36081602 1155int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
e96efcfc 1156 target_ulong address, int rw, int access_type)
a8dea12f
JM		 1157{
1158 ppcemb_tlb_t *tlb;
1159 target_phys_addr_t raddr;
a8dea12f 1160 int i, ret, zsel, zpr;
3b46e624 1161
c55e9aef
JM		 1162 ret = -1;
1163 raddr = -1;
a8dea12f
JM		 1164 for (i = 0; i < env->nb_tlb; i++) {
1165 tlb = &env->tlb[i].tlbe;
36081602
JM		 1166 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1167 env->spr[SPR_40x_PID], 0, i) < 0)
a8dea12f 1168 continue;
a8dea12f
JM		 1169 zsel = (tlb->attr >> 4) & 0xF;
1170 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
daf4f96e 1171#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1172 if (loglevel != 0) {
a8dea12f
JM		 1173 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1174 __func__, i, zsel, zpr, rw, tlb->attr);
1175 }
daf4f96e 1176#endif
b227a8e9
JM		 1177 /* Check execute enable bit */
1178 switch (zpr) {
1179 case 0x2:
1180 if (msr_pr)
1181 goto check_perms;
1182 /* No break here */
1183 case 0x3:
1184 /* All accesses granted */
1185 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1186 ret = 0;
1187 break;
1188 case 0x0:
1189 if (msr_pr) {
1190 ctx->prot = 0;
1191 ret = -2;
a8dea12f
JM		 1192 break;
1193 }
b227a8e9
JM		 1194 /* No break here */
1195 case 0x1:
1196 check_perms:
1197 /* Check from TLB entry */
1198 /* XXX: there is a problem here or in the TLB fill code... */
1199 ctx->prot = tlb->prot;
1200 ctx->prot |= PAGE_EXEC;
1201 ret = check_prot(ctx->prot, rw, access_type);
1202 break;
a8dea12f
JM		 1203 }
1204 if (ret >= 0) {
1205 ctx->raddr = raddr;
daf4f96e 1206#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1207 if (loglevel != 0) {
a8dea12f 1208 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
c55e9aef
JM		 1209 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1210 ret);
a8dea12f 1211 }
daf4f96e 1212#endif
c55e9aef 1213 return 0;
a8dea12f
JM		 1214 }
1215 }
daf4f96e 1216#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1217 if (loglevel != 0) {
c55e9aef
JM		 1218 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1219 " %d %d\n", __func__, address, raddr, ctx->prot,
1220 ret);
1221 }
daf4f96e 1222#endif
3b46e624 1223
a8dea12f
JM		 1224 return ret;
1225}
1226
c294fc58
JM		 1227void store_40x_sler (CPUPPCState *env, uint32_t val)
1228{
1229 /* XXX: TO BE FIXED */
1230 if (val != 0x00000000) {
1231 cpu_abort(env, "Little-endian regions are not supported by now\n");
1232 }
1233 env->spr[SPR_405_SLER] = val;
1234}
1235
5eb7995e
JM		 1236int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1237 target_ulong address, int rw,
1238 int access_type)
1239{
1240 ppcemb_tlb_t *tlb;
1241 target_phys_addr_t raddr;
1242 int i, prot, ret;
1243
1244 ret = -1;
1245 raddr = -1;
1246 for (i = 0; i < env->nb_tlb; i++) {
1247 tlb = &env->tlb[i].tlbe;
1248 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1249 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1250 continue;
1251 if (msr_pr)
1252 prot = tlb->prot & 0xF;
1253 else
1254 prot = (tlb->prot >> 4) & 0xF;
1255 /* Check the address space */
1256 if (access_type == ACCESS_CODE) {
d26bfc9a 1257 if (msr_ir != (tlb->attr & 1))
5eb7995e
JM		 1258 continue;
1259 ctx->prot = prot;
1260 if (prot & PAGE_EXEC) {
1261 ret = 0;
1262 break;
1263 }
1264 ret = -3;
1265 } else {
d26bfc9a 1266 if (msr_dr != (tlb->attr & 1))
5eb7995e
JM		 1267 continue;
1268 ctx->prot = prot;
1269 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1270 ret = 0;
1271 break;
1272 }
1273 ret = -2;
1274 }
1275 }
1276 if (ret >= 0)
1277 ctx->raddr = raddr;
1278
1279 return ret;
1280}
1281
76a66253
JM		 1282static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1283 target_ulong eaddr, int rw)
1284{
1285 int in_plb, ret;
3b46e624 1286
76a66253 1287 ctx->raddr = eaddr;
b227a8e9 1288 ctx->prot = PAGE_READ | PAGE_EXEC;
76a66253 1289 ret = 0;
a750fc0b
JM		 1290 switch (env->mmu_model) {
1291 case POWERPC_MMU_32B:
1292 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1293 case POWERPC_MMU_SOFT_74xx:
a750fc0b
JM		 1294 case POWERPC_MMU_SOFT_4xx:
1295 case POWERPC_MMU_REAL_4xx:
7dbe11ac 1296 case POWERPC_MMU_BOOKE:
caa4039c
JM		 1297 ctx->prot |= PAGE_WRITE;
1298 break;
1299#if defined(TARGET_PPC64)
a750fc0b 1300 case POWERPC_MMU_64B:
caa4039c 1301 /* Real address are 60 bits long */
a750fc0b 1302 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
caa4039c
JM		 1303 ctx->prot |= PAGE_WRITE;
1304 break;
9706285b 1305#endif
a750fc0b 1306 case POWERPC_MMU_SOFT_4xx_Z:
caa4039c
JM		 1307 if (unlikely(msr_pe != 0)) {
1308 /* 403 family add some particular protections,
1309 * using PBL/PBU registers for accesses with no translation.
1310 */
1311 in_plb =
1312 /* Check PLB validity */
1313 (env->pb[0] < env->pb[1] &&
1314 /* and address in plb area */
1315 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1316 (env->pb[2] < env->pb[3] &&
1317 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1318 if (in_plb ^ msr_px) {
1319 /* Access in protected area */
1320 if (rw == 1) {
1321 /* Access is not allowed */
1322 ret = -2;
1323 }
1324 } else {
1325 /* Read-write access is allowed */
1326 ctx->prot |= PAGE_WRITE;
76a66253 1327 }
76a66253 1328 }
e1833e1f 1329 break;
a750fc0b 1330 case POWERPC_MMU_BOOKE_FSL:
caa4039c
JM		 1331 /* XXX: TODO */
1332 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1333 break;
1334 default:
1335 cpu_abort(env, "Unknown or invalid MMU model\n");
1336 return -1;
76a66253
JM		 1337 }
1338
1339 return ret;
1340}
1341
1342int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1343 int rw, int access_type, int check_BATs)
9a64fbe4
FB		 1344{
1345 int ret;
514fb8c1 1346#if 0
4a057712 1347 if (loglevel != 0) {
9a64fbe4
FB		 1348 fprintf(logfile, "%s\n", __func__);
1349 }
d9bce9d9 1350#endif
4b3686fa
FB		 1351 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1352 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 1353 /* No address translation */
76a66253 1354 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4 1355 } else {
c55e9aef 1356 ret = -1;
a750fc0b
JM		 1357 switch (env->mmu_model) {
1358 case POWERPC_MMU_32B:
1359 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1360 case POWERPC_MMU_SOFT_74xx:
a8dea12f 1361 /* Try to find a BAT */
a8dea12f
JM		 1362 if (check_BATs)
1363 ret = get_bat(env, ctx, eaddr, rw, access_type);
c55e9aef
JM		 1364 /* No break here */
1365#if defined(TARGET_PPC64)
a750fc0b 1366 case POWERPC_MMU_64B:
c55e9aef 1367#endif
a8dea12f 1368 if (ret < 0) {
c55e9aef 1369 /* We didn't match any BAT entry or don't have BATs */
a8dea12f
JM		 1370 ret = get_segment(env, ctx, eaddr, rw, access_type);
1371 }
1372 break;
a750fc0b
JM		 1373 case POWERPC_MMU_SOFT_4xx:
1374 case POWERPC_MMU_SOFT_4xx_Z:
36081602 1375 ret = mmu40x_get_physical_address(env, ctx, eaddr,
a8dea12f
JM		 1376 rw, access_type);
1377 break;
a750fc0b 1378 case POWERPC_MMU_BOOKE:
5eb7995e
JM		 1379 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1380 rw, access_type);
1381 break;
a750fc0b 1382 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1383 /* XXX: TODO */
1384 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1385 return -1;
a750fc0b 1386 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1387 cpu_abort(env, "PowerPC 401 does not do any translation\n");
1388 return -1;
c55e9aef
JM		 1389 default:
1390 cpu_abort(env, "Unknown or invalid MMU model\n");
a8dea12f 1391 return -1;
9a64fbe4
FB		 1392 }
1393 }
514fb8c1 1394#if 0
4a057712
JM		 1395 if (loglevel != 0) {
1396 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
c55e9aef 1397 __func__, eaddr, ret, ctx->raddr);
a541f297 1398 }
76a66253 1399#endif
d9bce9d9 1400
9a64fbe4
FB		 1401 return ret;
1402}
1403
9b3c35e0 1404target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 1405{
76a66253 1406 mmu_ctx_t ctx;
a6b025d3 1407
76a66253 1408 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
a6b025d3 1409 return -1;
76a66253
JM		 1410
1411 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 1412}
9a64fbe4 1413
9a64fbe4 1414/* Perform address translation */
e96efcfc 1415int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 1416 int mmu_idx, int is_softmmu)
9a64fbe4 1417{
76a66253 1418 mmu_ctx_t ctx;
a541f297 1419 int access_type;
9a64fbe4 1420 int ret = 0;
d9bce9d9 1421
b769d8fe
FB		 1422 if (rw == 2) {
1423 /* code access */
1424 rw = 0;
1425 access_type = ACCESS_CODE;
1426 } else {
1427 /* data access */
1428 /* XXX: put correct access by using cpu_restore_state()
1429 correctly */
1430 access_type = ACCESS_INT;
1431 // access_type = env->access_type;
1432 }
76a66253 1433 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
9a64fbe4 1434 if (ret == 0) {
b227a8e9
JM		 1435 ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
1436 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1437 mmu_idx, is_softmmu);
9a64fbe4 1438 } else if (ret < 0) {
9a64fbe4 1439#if defined (DEBUG_MMU)
4a057712 1440 if (loglevel != 0)
76a66253 1441 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 1442#endif
1443 if (access_type == ACCESS_CODE) {
9a64fbe4
FB		 1444 switch (ret) {
1445 case -1:
76a66253 1446 /* No matches in page tables or TLB */
a750fc0b
JM		 1447 switch (env->mmu_model) {
1448 case POWERPC_MMU_SOFT_6xx:
8f793433
JM		 1449 env->exception_index = POWERPC_EXCP_IFTLB;
1450 env->error_code = 1 << 18;
76a66253
JM		 1451 env->spr[SPR_IMISS] = address;
1452 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
76a66253 1453 goto tlb_miss;
7dbe11ac 1454 case POWERPC_MMU_SOFT_74xx:
8f793433 1455 env->exception_index = POWERPC_EXCP_IFTLB;
7dbe11ac 1456 goto tlb_miss_74xx;
a750fc0b
JM		 1457 case POWERPC_MMU_SOFT_4xx:
1458 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1459 env->exception_index = POWERPC_EXCP_ITLB;
1460 env->error_code = 0;
a8dea12f
JM		 1461 env->spr[SPR_40x_DEAR] = address;
1462 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1463 break;
a750fc0b 1464 case POWERPC_MMU_32B:
c55e9aef 1465#if defined(TARGET_PPC64)
a750fc0b 1466 case POWERPC_MMU_64B:
c55e9aef 1467#endif
8f793433
JM		 1468 env->exception_index = POWERPC_EXCP_ISI;
1469 env->error_code = 0x40000000;
1470 break;
a750fc0b 1471 case POWERPC_MMU_BOOKE:
c55e9aef
JM		 1472 /* XXX: TODO */
1473 cpu_abort(env, "MMU model not implemented\n");
1474 return -1;
a750fc0b 1475 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1476 /* XXX: TODO */
1477 cpu_abort(env, "MMU model not implemented\n");
1478 return -1;
a750fc0b 1479 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1480 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1481 "exceptions\n");
1482 return -1;
c55e9aef
JM		 1483 default:
1484 cpu_abort(env, "Unknown or invalid MMU model\n");
1485 return -1;
76a66253 1486 }
9a64fbe4
FB		 1487 break;
1488 case -2:
1489 /* Access rights violation */
8f793433
JM		 1490 env->exception_index = POWERPC_EXCP_ISI;
1491 env->error_code = 0x08000000;
9a64fbe4
FB		 1492 break;
1493 case -3:
76a66253 1494 /* No execute protection violation */
8f793433
JM		 1495 env->exception_index = POWERPC_EXCP_ISI;
1496 env->error_code = 0x10000000;
9a64fbe4
FB		 1497 break;
1498 case -4:
1499 /* Direct store exception */
1500 /* No code fetch is allowed in direct-store areas */
8f793433
JM		 1501 env->exception_index = POWERPC_EXCP_ISI;
1502 env->error_code = 0x10000000;
2be0071f 1503 break;
e1833e1f 1504#if defined(TARGET_PPC64)
2be0071f
FB		 1505 case -5:
1506 /* No match in segment table */
8f793433
JM		 1507 env->exception_index = POWERPC_EXCP_ISEG;
1508 env->error_code = 0;
9a64fbe4 1509 break;
e1833e1f 1510#endif
9a64fbe4
FB		 1511 }
1512 } else {
9a64fbe4
FB		 1513 switch (ret) {
1514 case -1:
76a66253 1515 /* No matches in page tables or TLB */
a750fc0b
JM		 1516 switch (env->mmu_model) {
1517 case POWERPC_MMU_SOFT_6xx:
76a66253 1518 if (rw == 1) {
8f793433
JM		 1519 env->exception_index = POWERPC_EXCP_DSTLB;
1520 env->error_code = 1 << 16;
76a66253 1521 } else {
8f793433
JM		 1522 env->exception_index = POWERPC_EXCP_DLTLB;
1523 env->error_code = 0;
76a66253
JM		 1524 }
1525 env->spr[SPR_DMISS] = address;
1526 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1527 tlb_miss:
8f793433 1528 env->error_code |= ctx.key << 19;
76a66253
JM		 1529 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1530 env->spr[SPR_HASH2] = ctx.pg_addr[1];
8f793433 1531 break;
7dbe11ac
JM		 1532 case POWERPC_MMU_SOFT_74xx:
1533 if (rw == 1) {
8f793433 1534 env->exception_index = POWERPC_EXCP_DSTLB;
7dbe11ac 1535 } else {
8f793433 1536 env->exception_index = POWERPC_EXCP_DLTLB;
7dbe11ac
JM		 1537 }
1538 tlb_miss_74xx:
1539 /* Implement LRU algorithm */
8f793433 1540 env->error_code = ctx.key << 19;
7dbe11ac
JM		 1541 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1542 ((env->last_way + 1) & (env->nb_ways - 1));
1543 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
7dbe11ac 1544 break;
a750fc0b
JM		 1545 case POWERPC_MMU_SOFT_4xx:
1546 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1547 env->exception_index = POWERPC_EXCP_DTLB;
1548 env->error_code = 0;
a8dea12f
JM		 1549 env->spr[SPR_40x_DEAR] = address;
1550 if (rw)
1551 env->spr[SPR_40x_ESR] = 0x00800000;
1552 else
1553 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1554 break;
a750fc0b 1555 case POWERPC_MMU_32B:
c55e9aef 1556#if defined(TARGET_PPC64)
a750fc0b 1557 case POWERPC_MMU_64B:
c55e9aef 1558#endif
8f793433
JM		 1559 env->exception_index = POWERPC_EXCP_DSI;
1560 env->error_code = 0;
1561 env->spr[SPR_DAR] = address;
1562 if (rw == 1)
1563 env->spr[SPR_DSISR] = 0x42000000;
1564 else
1565 env->spr[SPR_DSISR] = 0x40000000;
1566 break;
a750fc0b 1567 case POWERPC_MMU_BOOKE:
c55e9aef
JM		 1568 /* XXX: TODO */
1569 cpu_abort(env, "MMU model not implemented\n");
1570 return -1;
a750fc0b 1571 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1572 /* XXX: TODO */
1573 cpu_abort(env, "MMU model not implemented\n");
1574 return -1;
a750fc0b 1575 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1576 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1577 "exceptions\n");
1578 return -1;
c55e9aef
JM		 1579 default:
1580 cpu_abort(env, "Unknown or invalid MMU model\n");
1581 return -1;
76a66253 1582 }
9a64fbe4
FB		 1583 break;
1584 case -2:
1585 /* Access rights violation */
8f793433
JM		 1586 env->exception_index = POWERPC_EXCP_DSI;
1587 env->error_code = 0;
1588 env->spr[SPR_DAR] = address;
1589 if (rw == 1)
1590 env->spr[SPR_DSISR] = 0x0A000000;
1591 else
1592 env->spr[SPR_DSISR] = 0x08000000;
9a64fbe4
FB		 1593 break;
1594 case -4:
1595 /* Direct store exception */
1596 switch (access_type) {
1597 case ACCESS_FLOAT:
1598 /* Floating point load/store */
8f793433
JM		 1599 env->exception_index = POWERPC_EXCP_ALIGN;
1600 env->error_code = POWERPC_EXCP_ALIGN_FP;
1601 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1602 break;
1603 case ACCESS_RES:
8f793433
JM		 1604 /* lwarx, ldarx or stwcx. */
1605 env->exception_index = POWERPC_EXCP_DSI;
1606 env->error_code = 0;
1607 env->spr[SPR_DAR] = address;
1608 if (rw == 1)
1609 env->spr[SPR_DSISR] = 0x06000000;
1610 else
1611 env->spr[SPR_DSISR] = 0x04000000;
9a64fbe4
FB		 1612 break;
1613 case ACCESS_EXT:
1614 /* eciwx or ecowx */
8f793433
JM		 1615 env->exception_index = POWERPC_EXCP_DSI;
1616 env->error_code = 0;
1617 env->spr[SPR_DAR] = address;
1618 if (rw == 1)
1619 env->spr[SPR_DSISR] = 0x06100000;
1620 else
1621 env->spr[SPR_DSISR] = 0x04100000;
9a64fbe4
FB		 1622 break;
1623 default:
76a66253 1624 printf("DSI: invalid exception (%d)\n", ret);
8f793433
JM		 1625 env->exception_index = POWERPC_EXCP_PROGRAM;
1626 env->error_code =
1627 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1628 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1629 break;
1630 }
fdabc366 1631 break;
e1833e1f 1632#if defined(TARGET_PPC64)
2be0071f
FB		 1633 case -5:
1634 /* No match in segment table */
8f793433
JM		 1635 env->exception_index = POWERPC_EXCP_DSEG;
1636 env->error_code = 0;
1637 env->spr[SPR_DAR] = address;
2be0071f 1638 break;
e1833e1f 1639#endif
9a64fbe4 1640 }
9a64fbe4
FB		 1641 }
1642#if 0
8f793433
JM		 1643 printf("%s: set exception to %d %02x\n", __func__,
1644 env->exception, env->error_code);
9a64fbe4 1645#endif
9a64fbe4
FB		 1646 ret = 1;
1647 }
76a66253 1648
9a64fbe4
FB		 1649 return ret;
1650}
1651
3fc6c082
FB		 1652/*****************************************************************************/
1653/* BATs management */
1654#if !defined(FLUSH_ALL_TLBS)
b068d6a7
JM		 1655static always_inline void do_invalidate_BAT (CPUPPCState *env,
1656 target_ulong BATu,
1657 target_ulong mask)
3fc6c082
FB		 1658{
1659 target_ulong base, end, page;
76a66253 1660
3fc6c082
FB		 1661 base = BATu & ~0x0001FFFF;
1662 end = base + mask + 0x00020000;
1663#if defined (DEBUG_BATS)
76a66253 1664 if (loglevel != 0) {
1b9eb036 1665 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM		 1666 base, end, mask);
1667 }
3fc6c082
FB		 1668#endif
1669 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1670 tlb_flush_page(env, page);
1671#if defined (DEBUG_BATS)
1672 if (loglevel != 0)
1673 fprintf(logfile, "Flush done\n");
1674#endif
1675}
1676#endif
1677
b068d6a7
JM		 1678static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1679 int ul, int nr, target_ulong value)
3fc6c082
FB		 1680{
1681#if defined (DEBUG_BATS)
1682 if (loglevel != 0) {
1b9eb036
JM		 1683 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1684 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB		 1685 }
1686#endif
1687}
1688
1689target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1690{
1691 return env->IBAT[0][nr];
1692}
1693
1694target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1695{
1696 return env->IBAT[1][nr];
1697}
1698
1699void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1700{
1701 target_ulong mask;
1702
1703 dump_store_bat(env, 'I', 0, nr, value);
1704 if (env->IBAT[0][nr] != value) {
1705 mask = (value << 15) & 0x0FFE0000UL;
1706#if !defined(FLUSH_ALL_TLBS)
1707 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1708#endif
1709 /* When storing valid upper BAT, mask BEPI and BRPN
1710 * and invalidate all TLBs covered by this BAT
1711 */
1712 mask = (value << 15) & 0x0FFE0000UL;
1713 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1714 (value & ~0x0001FFFFUL & ~mask);
1715 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1716 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1717#if !defined(FLUSH_ALL_TLBS)
1718 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 1719#else
3fc6c082
FB		 1720 tlb_flush(env, 1);
1721#endif
1722 }
1723}
1724
1725void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1726{
1727 dump_store_bat(env, 'I', 1, nr, value);
1728 env->IBAT[1][nr] = value;
1729}
1730
1731target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1732{
1733 return env->DBAT[0][nr];
1734}
1735
1736target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1737{
1738 return env->DBAT[1][nr];
1739}
1740
1741void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1742{
1743 target_ulong mask;
1744
1745 dump_store_bat(env, 'D', 0, nr, value);
1746 if (env->DBAT[0][nr] != value) {
1747 /* When storing valid upper BAT, mask BEPI and BRPN
1748 * and invalidate all TLBs covered by this BAT
1749 */
1750 mask = (value << 15) & 0x0FFE0000UL;
1751#if !defined(FLUSH_ALL_TLBS)
1752 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1753#endif
1754 mask = (value << 15) & 0x0FFE0000UL;
1755 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1756 (value & ~0x0001FFFFUL & ~mask);
1757 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1758 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1759#if !defined(FLUSH_ALL_TLBS)
1760 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1761#else
1762 tlb_flush(env, 1);
1763#endif
1764 }
1765}
1766
1767void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1768{
1769 dump_store_bat(env, 'D', 1, nr, value);
1770 env->DBAT[1][nr] = value;
1771}
1772
0a032cbe
JM		 1773/*****************************************************************************/
1774/* TLB management */
1775void ppc_tlb_invalidate_all (CPUPPCState *env)
1776{
daf4f96e
JM		 1777 switch (env->mmu_model) {
1778 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1779 case POWERPC_MMU_SOFT_74xx:
0a032cbe 1780 ppc6xx_tlb_invalidate_all(env);
daf4f96e
JM		 1781 break;
1782 case POWERPC_MMU_SOFT_4xx:
1783 case POWERPC_MMU_SOFT_4xx_Z:
0a032cbe 1784 ppc4xx_tlb_invalidate_all(env);
daf4f96e 1785 break;
7dbe11ac
JM		 1786 case POWERPC_MMU_REAL_4xx:
1787 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1788 break;
1789 case POWERPC_MMU_BOOKE:
1790 /* XXX: TODO */
1791 cpu_abort(env, "MMU model not implemented\n");
1792 break;
1793 case POWERPC_MMU_BOOKE_FSL:
1794 /* XXX: TODO */
1795 cpu_abort(env, "MMU model not implemented\n");
1796 break;
7dbe11ac 1797 case POWERPC_MMU_32B:
00af685f 1798#if defined(TARGET_PPC64)
7dbe11ac 1799 case POWERPC_MMU_64B:
00af685f 1800#endif /* defined(TARGET_PPC64) */
0a032cbe 1801 tlb_flush(env, 1);
daf4f96e 1802 break;
00af685f
JM		 1803 default:
1804 /* XXX: TODO */
12de9a39 1805 cpu_abort(env, "Unknown MMU model\n");
00af685f 1806 break;
0a032cbe
JM		 1807 }
1808}
1809
daf4f96e
JM		 1810void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1811{
1812#if !defined(FLUSH_ALL_TLBS)
1813 addr &= TARGET_PAGE_MASK;
1814 switch (env->mmu_model) {
1815 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1816 case POWERPC_MMU_SOFT_74xx:
daf4f96e
JM		 1817 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1818 if (env->id_tlbs == 1)
1819 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1820 break;
1821 case POWERPC_MMU_SOFT_4xx:
1822 case POWERPC_MMU_SOFT_4xx_Z:
1823 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1824 break;
7dbe11ac
JM		 1825 case POWERPC_MMU_REAL_4xx:
1826 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1827 break;
1828 case POWERPC_MMU_BOOKE:
1829 /* XXX: TODO */
1830 cpu_abort(env, "MMU model not implemented\n");
1831 break;
1832 case POWERPC_MMU_BOOKE_FSL:
1833 /* XXX: TODO */
7dbe11ac
JM		 1834 cpu_abort(env, "MMU model not implemented\n");
1835 break;
1836 case POWERPC_MMU_32B:
daf4f96e
JM		 1837 /* tlbie invalidate TLBs for all segments */
1838 addr &= ~((target_ulong)-1 << 28);
1839 /* XXX: this case should be optimized,
1840 * giving a mask to tlb_flush_page
1841 */
1842 tlb_flush_page(env, addr | (0x0 << 28));
1843 tlb_flush_page(env, addr | (0x1 << 28));
1844 tlb_flush_page(env, addr | (0x2 << 28));
1845 tlb_flush_page(env, addr | (0x3 << 28));
1846 tlb_flush_page(env, addr | (0x4 << 28));
1847 tlb_flush_page(env, addr | (0x5 << 28));
1848 tlb_flush_page(env, addr | (0x6 << 28));
1849 tlb_flush_page(env, addr | (0x7 << 28));
1850 tlb_flush_page(env, addr | (0x8 << 28));
1851 tlb_flush_page(env, addr | (0x9 << 28));
1852 tlb_flush_page(env, addr | (0xA << 28));
1853 tlb_flush_page(env, addr | (0xB << 28));
1854 tlb_flush_page(env, addr | (0xC << 28));
1855 tlb_flush_page(env, addr | (0xD << 28));
1856 tlb_flush_page(env, addr | (0xE << 28));
1857 tlb_flush_page(env, addr | (0xF << 28));
7dbe11ac 1858 break;
00af685f 1859#if defined(TARGET_PPC64)
7dbe11ac 1860 case POWERPC_MMU_64B:
7dbe11ac
JM		 1861 /* tlbie invalidate TLBs for all segments */
1862 /* XXX: given the fact that there are too many segments to invalidate,
00af685f 1863 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
7dbe11ac
JM		 1864 * we just invalidate all TLBs
1865 */
1866 tlb_flush(env, 1);
1867 break;
00af685f
JM		 1868#endif /* defined(TARGET_PPC64) */
1869 default:
1870 /* XXX: TODO */
12de9a39 1871 cpu_abort(env, "Unknown MMU model\n");
00af685f 1872 break;
daf4f96e
JM		 1873 }
1874#else
1875 ppc_tlb_invalidate_all(env);
1876#endif
1877}
1878
3fc6c082
FB		 1879/*****************************************************************************/
1880/* Special registers manipulation */
d9bce9d9
JM		 1881#if defined(TARGET_PPC64)
1882target_ulong ppc_load_asr (CPUPPCState *env)
1883{
1884 return env->asr;
1885}
1886
1887void ppc_store_asr (CPUPPCState *env, target_ulong value)
1888{
1889 if (env->asr != value) {
1890 env->asr = value;
1891 tlb_flush(env, 1);
1892 }
1893}
1894#endif
1895
3fc6c082
FB		 1896target_ulong do_load_sdr1 (CPUPPCState *env)
1897{
1898 return env->sdr1;
1899}
1900
1901void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1902{
1903#if defined (DEBUG_MMU)
1904 if (loglevel != 0) {
1b9eb036 1905 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
3fc6c082
FB		 1906 }
1907#endif
1908 if (env->sdr1 != value) {
12de9a39
JM		 1909 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1910 * is <= 28
1911 */
3fc6c082 1912 env->sdr1 = value;
76a66253 1913 tlb_flush(env, 1);
3fc6c082
FB		 1914 }
1915}
1916
12de9a39 1917#if 0 // Unused
3fc6c082
FB		 1918target_ulong do_load_sr (CPUPPCState *env, int srnum)
1919{
1920 return env->sr[srnum];
1921}
12de9a39 1922#endif
3fc6c082
FB		 1923
1924void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1925{
1926#if defined (DEBUG_MMU)
1927 if (loglevel != 0) {
1b9eb036
JM		 1928 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1929 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB		 1930 }
1931#endif
1932 if (env->sr[srnum] != value) {
1933 env->sr[srnum] = value;
1934#if !defined(FLUSH_ALL_TLBS) && 0
1935 {
1936 target_ulong page, end;
1937 /* Invalidate 256 MB of virtual memory */
1938 page = (16 << 20) * srnum;
1939 end = page + (16 << 20);
1940 for (; page != end; page += TARGET_PAGE_SIZE)
1941 tlb_flush_page(env, page);
1942 }
1943#else
76a66253 1944 tlb_flush(env, 1);
3fc6c082
FB		 1945#endif
1946 }
1947}
76a66253 1948#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 1949
bfa1e5cf 1950target_ulong ppc_load_xer (CPUPPCState *env)
79aceca5
FB		 1951{
1952 return (xer_so << XER_SO) |
1953 (xer_ov << XER_OV) |
1954 (xer_ca << XER_CA) |
3fc6c082
FB		 1955 (xer_bc << XER_BC) |
1956 (xer_cmp << XER_CMP);
79aceca5
FB		 1957}
1958
bfa1e5cf 1959void ppc_store_xer (CPUPPCState *env, target_ulong value)
79aceca5
FB		 1960{
1961 xer_so = (value >> XER_SO) & 0x01;
1962 xer_ov = (value >> XER_OV) & 0x01;
1963 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082 1964 xer_cmp = (value >> XER_CMP) & 0xFF;
d9bce9d9 1965 xer_bc = (value >> XER_BC) & 0x7F;
79aceca5
FB		 1966}
1967
76a66253 1968/* Swap temporary saved registers with GPRs */
b068d6a7 1969static always_inline void swap_gpr_tgpr (CPUPPCState *env)
79aceca5 1970{
76a66253
JM		 1971 ppc_gpr_t tmp;
1972
1973 tmp = env->gpr[0];
1974 env->gpr[0] = env->tgpr[0];
1975 env->tgpr[0] = tmp;
1976 tmp = env->gpr[1];
1977 env->gpr[1] = env->tgpr[1];
1978 env->tgpr[1] = tmp;
1979 tmp = env->gpr[2];
1980 env->gpr[2] = env->tgpr[2];
1981 env->tgpr[2] = tmp;
1982 tmp = env->gpr[3];
1983 env->gpr[3] = env->tgpr[3];
1984 env->tgpr[3] = tmp;
79aceca5
FB		 1985}
1986
76a66253
JM		 1987/* GDBstub can read and write MSR... */
1988target_ulong do_load_msr (CPUPPCState *env)
79aceca5 1989{
76a66253
JM		 1990 return
1991#if defined (TARGET_PPC64)
d9bce9d9
JM		 1992 ((target_ulong)msr_sf << MSR_SF) |
1993 ((target_ulong)msr_isf << MSR_ISF) |
1994 ((target_ulong)msr_hv << MSR_HV) |
76a66253 1995#endif
d9bce9d9
JM		 1996 ((target_ulong)msr_ucle << MSR_UCLE) |
1997 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1998 ((target_ulong)msr_ap << MSR_AP) |
1999 ((target_ulong)msr_sa << MSR_SA) |
2000 ((target_ulong)msr_key << MSR_KEY) |
25ba3a68 2001 ((target_ulong)msr_pow << MSR_POW) |
d26bfc9a 2002 ((target_ulong)msr_tgpr << MSR_TGPR) | /* TGPR / CE */
d9bce9d9
JM		 2003 ((target_ulong)msr_ile << MSR_ILE) |
2004 ((target_ulong)msr_ee << MSR_EE) |
2005 ((target_ulong)msr_pr << MSR_PR) |
2006 ((target_ulong)msr_fp << MSR_FP) |
2007 ((target_ulong)msr_me << MSR_ME) |
2008 ((target_ulong)msr_fe0 << MSR_FE0) |
2009 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
2010 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
2011 ((target_ulong)msr_fe1 << MSR_FE1) |
2012 ((target_ulong)msr_al << MSR_AL) |
25ba3a68
JM		 2013 ((target_ulong)msr_ep << MSR_EP) |
2014 ((target_ulong)msr_ir << MSR_IR) |
2015 ((target_ulong)msr_dr << MSR_DR) |
2016 ((target_ulong)msr_pe << MSR_PE) |
d9bce9d9
JM		 2017 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
2018 ((target_ulong)msr_ri << MSR_RI) |
2019 ((target_ulong)msr_le << MSR_LE);
3fc6c082
FB		 2020}
2021
a97fed52 2022int do_store_msr (CPUPPCState *env, target_ulong value)
313adae9 2023{
50443c98
FB		 2024 int enter_pm;
2025
3fc6c082
FB		 2026 value &= env->msr_mask;
2027 if (((value >> MSR_IR) & 1) != msr_ir ||
2028 ((value >> MSR_DR) & 1) != msr_dr) {
76a66253 2029 /* Flush all tlb when changing translation mode */
d094807b 2030 tlb_flush(env, 1);
3fc6c082 2031 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 2032 }
4e80effc 2033#if !defined (CONFIG_USER_ONLY)
d26bfc9a
JM		 2034 if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
2035 ((value >> MSR_TGPR) & 1) != msr_tgpr)) {
2036 /* Swap temporary saved registers with GPRs */
2037 swap_gpr_tgpr(env);
76a66253 2038 }
4e80effc
JM		 2039 if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
2040 /* Change the exception prefix on PowerPC 601 */
2041 env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
2042 }
2043#endif
76a66253
JM		 2044#if defined (TARGET_PPC64)
2045 msr_sf = (value >> MSR_SF) & 1;
2046 msr_isf = (value >> MSR_ISF) & 1;
2047 msr_hv = (value >> MSR_HV) & 1;
2048#endif
2049 msr_ucle = (value >> MSR_UCLE) & 1;
2050 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
2051 msr_ap = (value >> MSR_AP) & 1;
2052 msr_sa = (value >> MSR_SA) & 1;
2053 msr_key = (value >> MSR_KEY) & 1;
25ba3a68 2054 msr_pow = (value >> MSR_POW) & 1;
d26bfc9a 2055 msr_tgpr = (value >> MSR_TGPR) & 1; /* TGPR / CE */
76a66253
JM		 2056 msr_ile = (value >> MSR_ILE) & 1;
2057 msr_ee = (value >> MSR_EE) & 1;
2058 msr_pr = (value >> MSR_PR) & 1;
2059 msr_fp = (value >> MSR_FP) & 1;
2060 msr_me = (value >> MSR_ME) & 1;
2061 msr_fe0 = (value >> MSR_FE0) & 1;
2062 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
2063 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
2064 msr_fe1 = (value >> MSR_FE1) & 1;
2065 msr_al = (value >> MSR_AL) & 1;
25ba3a68
JM		 2066 msr_ep = (value >> MSR_EP) & 1;
2067 msr_ir = (value >> MSR_IR) & 1;
2068 msr_dr = (value >> MSR_DR) & 1;
2069 msr_pe = (value >> MSR_PE) & 1;
76a66253
JM		 2070 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
2071 msr_ri = (value >> MSR_RI) & 1;
2072 msr_le = (value >> MSR_LE) & 1;
3fc6c082 2073 do_compute_hflags(env);
50443c98
FB		 2074
2075 enter_pm = 0;
a750fc0b
JM		 2076 switch (env->excp_model) {
2077 case POWERPC_EXCP_603:
2078 case POWERPC_EXCP_603E:
2079 case POWERPC_EXCP_G2:
d9bce9d9
JM		 2080 /* Don't handle SLEEP mode: we should disable all clocks...
2081 * No dynamic power-management.
2082 */
2083 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
2084 enter_pm = 1;
2085 break;
a750fc0b 2086 case POWERPC_EXCP_604:
d9bce9d9
JM		 2087 if (msr_pow == 1)
2088 enter_pm = 1;
2089 break;
a750fc0b 2090 case POWERPC_EXCP_7x0:
76a66253 2091 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
50443c98
FB		 2092 enter_pm = 1;
2093 break;
2094 default:
2095 break;
2096 }
a97fed52
JM		 2097
2098 return enter_pm;
3fc6c082
FB		 2099}
2100
d9bce9d9 2101#if defined(TARGET_PPC64)
a97fed52 2102int ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
d9bce9d9 2103{
a97fed52
JM		 2104 return do_store_msr(env, (do_load_msr(env) & ~0xFFFFFFFFULL) |
2105 (value & 0xFFFFFFFF));
d9bce9d9
JM		 2106}
2107#endif
2108
76a66253 2109void do_compute_hflags (CPUPPCState *env)
3fc6c082 2110{
76a66253 2111 /* Compute current hflags */
4296f459 2112 env->hflags = (msr_vr << MSR_VR) |
c62db105
JM		 2113 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
2114 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
2115 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
76a66253 2116#if defined (TARGET_PPC64)
4296f459
JM		 2117 env->hflags |= msr_cm << MSR_CM;
2118 env->hflags |= (uint64_t)msr_sf << MSR_SF;
2119 env->hflags |= (uint64_t)msr_hv << MSR_HV;
6ebbf390
JM		 2120 /* Precompute MMU index */
2121 if (msr_pr == 0 && msr_hv == 1)
2122 env->mmu_idx = 2;
2123 else
4b3686fa 2124#endif
6ebbf390 2125 env->mmu_idx = 1 - msr_pr;
3fc6c082
FB		 2126}
2127
2128/*****************************************************************************/
2129/* Exception processing */
18fba28c 2130#if defined (CONFIG_USER_ONLY)
9a64fbe4 2131void do_interrupt (CPUState *env)
79aceca5 2132{
e1833e1f
JM		 2133 env->exception_index = POWERPC_EXCP_NONE;
2134 env->error_code = 0;
18fba28c 2135}
47103572 2136
e9df014c 2137void ppc_hw_interrupt (CPUState *env)
47103572 2138{
e1833e1f
JM		 2139 env->exception_index = POWERPC_EXCP_NONE;
2140 env->error_code = 0;
47103572 2141}
76a66253 2142#else /* defined (CONFIG_USER_ONLY) */
36081602 2143static void dump_syscall (CPUState *env)
d094807b 2144{
d9bce9d9 2145 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1b9eb036 2146 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
d094807b
FB		 2147 env->gpr[0], env->gpr[3], env->gpr[4],
2148 env->gpr[5], env->gpr[6], env->nip);
2149}
2150
e1833e1f
JM		 2151/* Note that this function should be greatly optimized
2152 * when called with a constant excp, from ppc_hw_interrupt
2153 */
2154static always_inline void powerpc_excp (CPUState *env,
2155 int excp_model, int excp)
18fba28c 2156{
e1833e1f
JM		 2157 target_ulong msr, vector;
2158 int srr0, srr1, asrr0, asrr1;
79aceca5 2159
b769d8fe 2160 if (loglevel & CPU_LOG_INT) {
1b9eb036
JM		 2161 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
2162 env->nip, excp, env->error_code);
b769d8fe 2163 }
e1833e1f
JM		 2164 msr = do_load_msr(env);
2165 srr0 = SPR_SRR0;
2166 srr1 = SPR_SRR1;
2167 asrr0 = -1;
2168 asrr1 = -1;
2169 msr &= ~((target_ulong)0x783F0000);
9a64fbe4 2170 switch (excp) {
e1833e1f
JM		 2171 case POWERPC_EXCP_NONE:
2172 /* Should never happen */
2173 return;
2174 case POWERPC_EXCP_CRITICAL: /* Critical input */
2175 msr_ri = 0; /* XXX: check this */
2176 switch (excp_model) {
a750fc0b 2177 case POWERPC_EXCP_40x:
e1833e1f
JM		 2178 srr0 = SPR_40x_SRR2;
2179 srr1 = SPR_40x_SRR3;
c62db105 2180 break;
a750fc0b 2181 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2182 srr0 = SPR_BOOKE_CSRR0;
2183 srr1 = SPR_BOOKE_CSRR1;
c62db105 2184 break;
e1833e1f 2185 case POWERPC_EXCP_G2:
c62db105 2186 break;
e1833e1f
JM		 2187 default:
2188 goto excp_invalid;
2be0071f 2189 }
9a64fbe4 2190 goto store_next;
e1833e1f
JM		 2191 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2192 if (msr_me == 0) {
e63ecc6f
JM		 2193 /* Machine check exception is not enabled.
2194 * Enter checkstop state.
2195 */
2196 if (loglevel != 0) {
2197 fprintf(logfile, "Machine check while not allowed. "
2198 "Entering checkstop state\n");
2199 } else {
2200 fprintf(stderr, "Machine check while not allowed. "
2201 "Entering checkstop state\n");
2202 }
2203 env->halted = 1;
2204 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
e1833e1f
JM		 2205 }
2206 msr_ri = 0;
2207 msr_me = 0;
2208#if defined(TARGET_PPC64H)
2209 msr_hv = 1;
2210#endif
2211 /* XXX: should also have something loaded in DAR / DSISR */
2212 switch (excp_model) {
a750fc0b 2213 case POWERPC_EXCP_40x:
e1833e1f
JM		 2214 srr0 = SPR_40x_SRR2;
2215 srr1 = SPR_40x_SRR3;
c62db105 2216 break;
a750fc0b 2217 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2218 srr0 = SPR_BOOKE_MCSRR0;
2219 srr1 = SPR_BOOKE_MCSRR1;
2220 asrr0 = SPR_BOOKE_CSRR0;
2221 asrr1 = SPR_BOOKE_CSRR1;
c62db105
JM		 2222 break;
2223 default:
2224 break;
2be0071f 2225 }
e1833e1f
JM		 2226 goto store_next;
2227 case POWERPC_EXCP_DSI: /* Data storage exception */
a541f297 2228#if defined (DEBUG_EXCEPTIONS)
4a057712 2229 if (loglevel != 0) {
1b9eb036
JM		 2230 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
2231 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 2232 }
e1833e1f
JM		 2233#endif
2234 msr_ri = 0;
2235#if defined(TARGET_PPC64H)
2236 if (lpes1 == 0)
2237 msr_hv = 1;
a541f297
FB		 2238#endif
2239 goto store_next;
e1833e1f 2240 case POWERPC_EXCP_ISI: /* Instruction storage exception */
a541f297 2241#if defined (DEBUG_EXCEPTIONS)
76a66253 2242 if (loglevel != 0) {
1b9eb036
JM		 2243 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
2244 "\n", msr, env->nip);
76a66253 2245 }
a541f297 2246#endif
e1833e1f
JM		 2247 msr_ri = 0;
2248#if defined(TARGET_PPC64H)
2249 if (lpes1 == 0)
2250 msr_hv = 1;
2251#endif
2252 msr |= env->error_code;
9a64fbe4 2253 goto store_next;
e1833e1f
JM		 2254 case POWERPC_EXCP_EXTERNAL: /* External input */
2255 msr_ri = 0;
2256#if defined(TARGET_PPC64H)
2257 if (lpes0 == 1)
2258 msr_hv = 1;
2259#endif
9a64fbe4 2260 goto store_next;
e1833e1f
JM		 2261 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2262 msr_ri = 0;
2263#if defined(TARGET_PPC64H)
2264 if (lpes1 == 0)
2265 msr_hv = 1;
2266#endif
2267 /* XXX: this is false */
2268 /* Get rS/rD and rA from faulting opcode */
2269 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
9a64fbe4 2270 goto store_current;
e1833e1f 2271 case POWERPC_EXCP_PROGRAM: /* Program exception */
9a64fbe4 2272 switch (env->error_code & ~0xF) {
e1833e1f
JM		 2273 case POWERPC_EXCP_FP:
2274 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
9a64fbe4 2275#if defined (DEBUG_EXCEPTIONS)
4a057712 2276 if (loglevel != 0) {
a496775f
JM		 2277 fprintf(logfile, "Ignore floating point exception\n");
2278 }
9a64fbe4
FB		 2279#endif
2280 return;
76a66253 2281 }
e1833e1f
JM		 2282 msr_ri = 0;
2283#if defined(TARGET_PPC64H)
2284 if (lpes1 == 0)
2285 msr_hv = 1;
2286#endif
9a64fbe4
FB		 2287 msr |= 0x00100000;
2288 /* Set FX */
2289 env->fpscr[7] |= 0x8;
2290 /* Finally, update FEX */
2291 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
2292 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
2293 env->fpscr[7] |= 0x4;
e1833e1f
JM		 2294 if (msr_fe0 != msr_fe1) {
2295 msr |= 0x00010000;
2296 goto store_current;
2297 }
76a66253 2298 break;
e1833e1f 2299 case POWERPC_EXCP_INVAL:
a496775f 2300#if defined (DEBUG_EXCEPTIONS)
4a057712 2301 if (loglevel != 0) {
a496775f
JM		 2302 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
2303 env->nip);
2304 }
e1833e1f
JM		 2305#endif
2306 msr_ri = 0;
2307#if defined(TARGET_PPC64H)
2308 if (lpes1 == 0)
2309 msr_hv = 1;
a496775f 2310#endif
9a64fbe4 2311 msr |= 0x00080000;
76a66253 2312 break;
e1833e1f
JM		 2313 case POWERPC_EXCP_PRIV:
2314 msr_ri = 0;
2315#if defined(TARGET_PPC64H)
2316 if (lpes1 == 0)
2317 msr_hv = 1;
2318#endif
9a64fbe4 2319 msr |= 0x00040000;
76a66253 2320 break;
e1833e1f
JM		 2321 case POWERPC_EXCP_TRAP:
2322 msr_ri = 0;
2323#if defined(TARGET_PPC64H)
2324 if (lpes1 == 0)
2325 msr_hv = 1;
2326#endif
9a64fbe4
FB		 2327 msr |= 0x00020000;
2328 break;
2329 default:
2330 /* Should never occur */
e1833e1f
JM		 2331 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2332 env->error_code);
76a66253
JM		 2333 break;
2334 }
9a64fbe4 2335 goto store_next;
e1833e1f
JM		 2336 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2337 msr_ri = 0;
2338#if defined(TARGET_PPC64H)
2339 if (lpes1 == 0)
2340 msr_hv = 1;
2341#endif
2342 goto store_current;
2343 case POWERPC_EXCP_SYSCALL: /* System call exception */
d094807b
FB		 2344 /* NOTE: this is a temporary hack to support graphics OSI
2345 calls from the MOL driver */
e1833e1f 2346 /* XXX: To be removed */
d094807b
FB		 2347 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2348 env->osi_call) {
2349 if (env->osi_call(env) != 0)
2350 return;
2351 }
b769d8fe 2352 if (loglevel & CPU_LOG_INT) {
d094807b 2353 dump_syscall(env);
b769d8fe 2354 }
e1833e1f
JM		 2355 msr_ri = 0;
2356#if defined(TARGET_PPC64H)
2357 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2358 msr_hv = 1;
2359#endif
2360 goto store_next;
2361 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2362 msr_ri = 0;
2363 goto store_current;
2364 case POWERPC_EXCP_DECR: /* Decrementer exception */
2365 msr_ri = 0;
2366#if defined(TARGET_PPC64H)
2367 if (lpes1 == 0)
2368 msr_hv = 1;
2369#endif
2370 goto store_next;
2371 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2372 /* FIT on 4xx */
2373#if defined (DEBUG_EXCEPTIONS)
2374 if (loglevel != 0)
2375 fprintf(logfile, "FIT exception\n");
2376#endif
2377 msr_ri = 0; /* XXX: check this */
9a64fbe4 2378 goto store_next;
e1833e1f
JM		 2379 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2380#if defined (DEBUG_EXCEPTIONS)
2381 if (loglevel != 0)
2382 fprintf(logfile, "WDT exception\n");
2383#endif
2384 switch (excp_model) {
2385 case POWERPC_EXCP_BOOKE:
2386 srr0 = SPR_BOOKE_CSRR0;
2387 srr1 = SPR_BOOKE_CSRR1;
2388 break;
2389 default:
2390 break;
2391 }
2392 msr_ri = 0; /* XXX: check this */
2be0071f 2393 goto store_next;
e1833e1f
JM		 2394 case POWERPC_EXCP_DTLB: /* Data TLB error */
2395 msr_ri = 0; /* XXX: check this */
2396 goto store_next;
2397 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2398 msr_ri = 0; /* XXX: check this */
2399 goto store_next;
2400 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2401 switch (excp_model) {
2402 case POWERPC_EXCP_BOOKE:
2403 srr0 = SPR_BOOKE_DSRR0;
2404 srr1 = SPR_BOOKE_DSRR1;
2405 asrr0 = SPR_BOOKE_CSRR0;
2406 asrr1 = SPR_BOOKE_CSRR1;
2407 break;
2408 default:
2409 break;
2410 }
2be0071f 2411 /* XXX: TODO */
e1833e1f 2412 cpu_abort(env, "Debug exception is not implemented yet !\n");
2be0071f 2413 goto store_next;
e1833e1f
JM		 2414#if defined(TARGET_PPCEMB)
2415 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2416 msr_ri = 0; /* XXX: check this */
2417 goto store_current;
2418 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2be0071f 2419 /* XXX: TODO */
e1833e1f 2420 cpu_abort(env, "Embedded floating point data exception "
2be0071f
FB		 2421 "is not implemented yet !\n");
2422 goto store_next;
e1833e1f 2423 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2be0071f 2424 /* XXX: TODO */
e1833e1f
JM		 2425 cpu_abort(env, "Embedded floating point round exception "
2426 "is not implemented yet !\n");
9a64fbe4 2427 goto store_next;
e1833e1f
JM		 2428 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2429 msr_ri = 0;
2be0071f
FB		 2430 /* XXX: TODO */
2431 cpu_abort(env,
e1833e1f 2432 "Performance counter exception is not implemented yet !\n");
9a64fbe4 2433 goto store_next;
e1833e1f 2434 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
76a66253 2435 /* XXX: TODO */
e1833e1f
JM		 2436 cpu_abort(env,
2437 "Embedded doorbell interrupt is not implemented yet !\n");
2be0071f 2438 goto store_next;
e1833e1f
JM		 2439 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2440 switch (excp_model) {
2441 case POWERPC_EXCP_BOOKE:
2442 srr0 = SPR_BOOKE_CSRR0;
2443 srr1 = SPR_BOOKE_CSRR1;
a750fc0b 2444 break;
2be0071f 2445 default:
2be0071f
FB		 2446 break;
2447 }
e1833e1f
JM		 2448 /* XXX: TODO */
2449 cpu_abort(env, "Embedded doorbell critical interrupt "
2450 "is not implemented yet !\n");
2451 goto store_next;
2452#endif /* defined(TARGET_PPCEMB) */
2453 case POWERPC_EXCP_RESET: /* System reset exception */
2454 msr_ri = 0;
2455#if defined(TARGET_PPC64H)
2456 msr_hv = 1;
2457#endif
e1833e1f
JM		 2458 goto store_next;
2459#if defined(TARGET_PPC64)
2460 case POWERPC_EXCP_DSEG: /* Data segment exception */
2461 msr_ri = 0;
2462#if defined(TARGET_PPC64H)
2463 if (lpes1 == 0)
2464 msr_hv = 1;
2465#endif
e1833e1f
JM		 2466 goto store_next;
2467 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2468 msr_ri = 0;
2469#if defined(TARGET_PPC64H)
2470 if (lpes1 == 0)
2471 msr_hv = 1;
2472#endif
e1833e1f
JM		 2473 goto store_next;
2474#endif /* defined(TARGET_PPC64) */
2475#if defined(TARGET_PPC64H)
2476 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2477 srr0 = SPR_HSRR0;
2478 srr1 = SPR_HSSR1;
2479 msr_hv = 1;
2480 goto store_next;
2481#endif
2482 case POWERPC_EXCP_TRACE: /* Trace exception */
2483 msr_ri = 0;
2484#if defined(TARGET_PPC64H)
2485 if (lpes1 == 0)
2486 msr_hv = 1;
2487#endif
2488 goto store_next;
2489#if defined(TARGET_PPC64H)
2490 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2491 srr0 = SPR_HSRR0;
2492 srr1 = SPR_HSSR1;
2493 msr_hv = 1;
2494 goto store_next;
2495 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2496 srr0 = SPR_HSRR0;
2497 srr1 = SPR_HSSR1;
2498 msr_hv = 1;
2499 /* XXX: TODO */
2500 cpu_abort(env, "Hypervisor instruction storage exception "
2501 "is not implemented yet !\n");
2502 goto store_next;
2503 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2504 srr0 = SPR_HSRR0;
2505 srr1 = SPR_HSSR1;
2506 msr_hv = 1;
2507 goto store_next;
2508 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2509 srr0 = SPR_HSRR0;
2510 srr1 = SPR_HSSR1;
2511 msr_hv = 1;
2512 goto store_next;
2513#endif /* defined(TARGET_PPC64H) */
2514 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2515 msr_ri = 0;
2516#if defined(TARGET_PPC64H)
2517 if (lpes1 == 0)
2518 msr_hv = 1;
2519#endif
2520 goto store_current;
2521 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
a496775f 2522#if defined (DEBUG_EXCEPTIONS)
e1833e1f
JM		 2523 if (loglevel != 0)
2524 fprintf(logfile, "PIT exception\n");
2525#endif
2526 msr_ri = 0; /* XXX: check this */
2527 goto store_next;
2528 case POWERPC_EXCP_IO: /* IO error exception */
2529 /* XXX: TODO */
2530 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2531 goto store_next;
2532 case POWERPC_EXCP_RUNM: /* Run mode exception */
2533 /* XXX: TODO */
2534 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2535 goto store_next;
2536 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2537 /* XXX: TODO */
2538 cpu_abort(env, "602 emulation trap exception "
2539 "is not implemented yet !\n");
2540 goto store_next;
2541 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2542 msr_ri = 0; /* XXX: check this */
2543#if defined(TARGET_PPC64H) /* XXX: check this */
2544 if (lpes1 == 0)
2545 msr_hv = 1;
a496775f 2546#endif
e1833e1f 2547 switch (excp_model) {
a750fc0b
JM		 2548 case POWERPC_EXCP_602:
2549 case POWERPC_EXCP_603:
2550 case POWERPC_EXCP_603E:
2551 case POWERPC_EXCP_G2:
e1833e1f 2552 goto tlb_miss_tgpr;
a750fc0b 2553 case POWERPC_EXCP_7x5:
76a66253 2554 goto tlb_miss;
7dbe11ac
JM		 2555 case POWERPC_EXCP_74xx:
2556 goto tlb_miss_74xx;
2be0071f 2557 default:
e1833e1f 2558 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2be0071f
FB		 2559 break;
2560 }
e1833e1f
JM		 2561 break;
2562 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2563 msr_ri = 0; /* XXX: check this */
2564#if defined(TARGET_PPC64H) /* XXX: check this */
2565 if (lpes1 == 0)
2566 msr_hv = 1;
a496775f 2567#endif
e1833e1f 2568 switch (excp_model) {
a750fc0b
JM		 2569 case POWERPC_EXCP_602:
2570 case POWERPC_EXCP_603:
2571 case POWERPC_EXCP_603E:
2572 case POWERPC_EXCP_G2:
e1833e1f 2573 goto tlb_miss_tgpr;
a750fc0b 2574 case POWERPC_EXCP_7x5:
76a66253 2575 goto tlb_miss;
7dbe11ac
JM		 2576 case POWERPC_EXCP_74xx:
2577 goto tlb_miss_74xx;
2be0071f 2578 default:
e1833e1f 2579 cpu_abort(env, "Invalid data load TLB miss exception\n");
2be0071f
FB		 2580 break;
2581 }
e1833e1f
JM		 2582 break;
2583 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2584 msr_ri = 0; /* XXX: check this */
2585#if defined(TARGET_PPC64H) /* XXX: check this */
2586 if (lpes1 == 0)
2587 msr_hv = 1;
2588#endif
2589 switch (excp_model) {
a750fc0b
JM		 2590 case POWERPC_EXCP_602:
2591 case POWERPC_EXCP_603:
2592 case POWERPC_EXCP_603E:
2593 case POWERPC_EXCP_G2:
e1833e1f 2594 tlb_miss_tgpr:
76a66253
JM		 2595 /* Swap temporary saved registers with GPRs */
2596 swap_gpr_tgpr(env);
2597 msr_tgpr = 1;
e1833e1f
JM		 2598 goto tlb_miss;
2599 case POWERPC_EXCP_7x5:
2600 tlb_miss:
2be0071f
FB		 2601#if defined (DEBUG_SOFTWARE_TLB)
2602 if (loglevel != 0) {
76a66253
JM		 2603 const unsigned char *es;
2604 target_ulong *miss, *cmp;
2605 int en;
1e6784f9 2606 if (excp == POWERPC_EXCP_IFTLB) {
76a66253
JM		 2607 es = "I";
2608 en = 'I';
2609 miss = &env->spr[SPR_IMISS];
2610 cmp = &env->spr[SPR_ICMP];
2611 } else {
1e6784f9 2612 if (excp == POWERPC_EXCP_DLTLB)
76a66253
JM		 2613 es = "DL";
2614 else
2615 es = "DS";
2616 en = 'D';
2617 miss = &env->spr[SPR_DMISS];
2618 cmp = &env->spr[SPR_DCMP];
2619 }
1b9eb036 2620 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
4a057712 2621 " H1 " ADDRX " H2 " ADDRX " %08x\n",
1b9eb036 2622 es, en, *miss, en, *cmp,
76a66253 2623 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB		 2624 env->error_code);
2625 }
9a64fbe4 2626#endif
2be0071f
FB		 2627 msr |= env->crf[0] << 28;
2628 msr |= env->error_code; /* key, D/I, S/L bits */
2629 /* Set way using a LRU mechanism */
76a66253 2630 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
c62db105 2631 break;
7dbe11ac
JM		 2632 case POWERPC_EXCP_74xx:
2633 tlb_miss_74xx:
2634#if defined (DEBUG_SOFTWARE_TLB)
2635 if (loglevel != 0) {
2636 const unsigned char *es;
2637 target_ulong *miss, *cmp;
2638 int en;
2639 if (excp == POWERPC_EXCP_IFTLB) {
2640 es = "I";
2641 en = 'I';
2642 miss = &env->spr[SPR_IMISS];
2643 cmp = &env->spr[SPR_ICMP];
2644 } else {
2645 if (excp == POWERPC_EXCP_DLTLB)
2646 es = "DL";
2647 else
2648 es = "DS";
2649 en = 'D';
2650 miss = &env->spr[SPR_TLBMISS];
2651 cmp = &env->spr[SPR_PTEHI];
2652 }
2653 fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2654 " %08x\n",
2655 es, en, *miss, en, *cmp, env->error_code);
2656 }
2657#endif
2658 msr |= env->error_code; /* key bit */
2659 break;
2be0071f 2660 default:
e1833e1f 2661 cpu_abort(env, "Invalid data store TLB miss exception\n");
2be0071f
FB		 2662 break;
2663 }
e1833e1f
JM		 2664 goto store_next;
2665 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2666 /* XXX: TODO */
2667 cpu_abort(env, "Floating point assist exception "
2668 "is not implemented yet !\n");
2669 goto store_next;
2670 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2671 /* XXX: TODO */
2672 cpu_abort(env, "IABR exception is not implemented yet !\n");
2673 goto store_next;
2674 case POWERPC_EXCP_SMI: /* System management interrupt */
2675 /* XXX: TODO */
2676 cpu_abort(env, "SMI exception is not implemented yet !\n");
2677 goto store_next;
2678 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2679 /* XXX: TODO */
2680 cpu_abort(env, "Thermal management exception "
2681 "is not implemented yet !\n");
2682 goto store_next;
2683 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2684 msr_ri = 0;
2685#if defined(TARGET_PPC64H)
2686 if (lpes1 == 0)
2687 msr_hv = 1;
2688#endif
2689 /* XXX: TODO */
2690 cpu_abort(env,
2691 "Performance counter exception is not implemented yet !\n");
2692 goto store_next;
2693 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2694 /* XXX: TODO */
2695 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2696 goto store_next;
2697 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2698 /* XXX: TODO */
2699 cpu_abort(env,
2700 "970 soft-patch exception is not implemented yet !\n");
2701 goto store_next;
2702 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2703 /* XXX: TODO */
2704 cpu_abort(env,
2705 "970 maintenance exception is not implemented yet !\n");
2706 goto store_next;
2be0071f 2707 default:
e1833e1f
JM		 2708 excp_invalid:
2709 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2710 break;
9a64fbe4 2711 store_current:
2be0071f 2712 /* save current instruction location */
e1833e1f 2713 env->spr[srr0] = env->nip - 4;
9a64fbe4
FB		 2714 break;
2715 store_next:
2be0071f 2716 /* save next instruction location */
e1833e1f 2717 env->spr[srr0] = env->nip;
9a64fbe4
FB		 2718 break;
2719 }
e1833e1f
JM		 2720 /* Save MSR */
2721 env->spr[srr1] = msr;
2722 /* If any alternate SRR register are defined, duplicate saved values */
2723 if (asrr0 != -1)
2724 env->spr[asrr0] = env->spr[srr0];
2725 if (asrr1 != -1)
2726 env->spr[asrr1] = env->spr[srr1];
2be0071f 2727 /* If we disactivated any translation, flush TLBs */
e1833e1f 2728 if (msr_ir || msr_dr)
2be0071f 2729 tlb_flush(env, 1);
9a64fbe4 2730 /* reload MSR with correct bits */
9a64fbe4
FB		 2731 msr_ee = 0;
2732 msr_pr = 0;
2733 msr_fp = 0;
2734 msr_fe0 = 0;
2735 msr_se = 0;
2736 msr_be = 0;
2737 msr_fe1 = 0;
2738 msr_ir = 0;
2739 msr_dr = 0;
e1833e1f
JM		 2740#if 0 /* Fix this: not on all targets */
2741 msr_pmm = 0;
2742#endif
9a64fbe4 2743 msr_le = msr_ile;
e1833e1f
JM		 2744 do_compute_hflags(env);
2745 /* Jump to handler */
2746 vector = env->excp_vectors[excp];
2747 if (vector == (target_ulong)-1) {
2748 cpu_abort(env, "Raised an exception without defined vector %d\n",
2749 excp);
2750 }
2751 vector |= env->excp_prefix;
c62db105 2752#if defined(TARGET_PPC64)
e1833e1f
JM		 2753 if (excp_model == POWERPC_EXCP_BOOKE) {
2754 msr_cm = msr_icm;
2755 if (!msr_cm)
2756 vector = (uint32_t)vector;
c62db105
JM		 2757 } else {
2758 msr_sf = msr_isf;
e1833e1f
JM		 2759 if (!msr_sf)
2760 vector = (uint32_t)vector;
c62db105 2761 }
e1833e1f
JM		 2762#endif
2763 env->nip = vector;
2764 /* Reset exception state */
2765 env->exception_index = POWERPC_EXCP_NONE;
2766 env->error_code = 0;
fb0eaffc 2767}
47103572 2768
e1833e1f 2769void do_interrupt (CPUState *env)
47103572 2770{
e1833e1f
JM		 2771 powerpc_excp(env, env->excp_model, env->exception_index);
2772}
47103572 2773
e1833e1f
JM		 2774void ppc_hw_interrupt (CPUPPCState *env)
2775{
a496775f
JM		 2776#if 1
2777 if (loglevel & CPU_LOG_INT) {
2778 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2779 __func__, env, env->pending_interrupts,
2780 env->interrupt_request, msr_me, msr_ee);
2781 }
47103572 2782#endif
e1833e1f 2783 /* External reset */
47103572 2784 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
47103572 2785 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
e1833e1f
JM		 2786 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2787 return;
2788 }
2789 /* Machine check exception */
2790 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2791 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2792 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2793 return;
47103572 2794 }
e1833e1f
JM		 2795#if 0 /* TODO */
2796 /* External debug exception */
2797 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2798 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2799 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2800 return;
2801 }
2802#endif
2803#if defined(TARGET_PPC64H)
2804 if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
47103572
JM		 2805 /* Hypervisor decrementer exception */
2806 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
47103572 2807 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
e1833e1f
JM		 2808 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2809 return;
2810 }
2811 }
2812#endif
2813 if (msr_ce != 0) {
2814 /* External critical interrupt */
2815 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2816 /* Taking a critical external interrupt does not clear the external
2817 * critical interrupt status
2818 */
2819#if 0
2820 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
47103572 2821#endif
e1833e1f
JM		 2822 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2823 return;
2824 }
2825 }
2826 if (msr_ee != 0) {
2827 /* Watchdog timer on embedded PowerPC */
2828 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2829 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2830 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2831 return;
2832 }
2833#if defined(TARGET_PPCEMB)
2834 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2835 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2836 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2837 return;
2838 }
2839#endif
2840#if defined(TARGET_PPCEMB)
2841 /* External interrupt */
2842 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2843 /* Taking an external interrupt does not clear the external
2844 * interrupt status
2845 */
2846#if 0
2847 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2848#endif
2849 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2850 return;
2851 }
2852#endif
2853 /* Fixed interval timer on embedded PowerPC */
2854 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2855 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2856 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2857 return;
2858 }
2859 /* Programmable interval timer on embedded PowerPC */
2860 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2861 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2862 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2863 return;
2864 }
47103572
JM		 2865 /* Decrementer exception */
2866 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
47103572 2867 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
e1833e1f
JM		 2868 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2869 return;
2870 }
2871#if !defined(TARGET_PPCEMB)
47103572 2872 /* External interrupt */
e1833e1f 2873 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
e9df014c
JM		 2874 /* Taking an external interrupt does not clear the external
2875 * interrupt status
2876 */
2877#if 0
47103572 2878 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
e9df014c 2879#endif
e1833e1f
JM		 2880 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2881 return;
2882 }
d0dfae6e 2883#endif
e1833e1f
JM		 2884#if defined(TARGET_PPCEMB)
2885 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2886 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2887 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2888 return;
47103572 2889 }
47103572 2890#endif
e1833e1f
JM		 2891 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2892 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2893 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2894 return;
2895 }
2896 /* Thermal interrupt */
2897 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2898 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2899 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2900 return;
2901 }
47103572 2902 }
47103572 2903}
18fba28c 2904#endif /* !CONFIG_USER_ONLY */
a496775f
JM		 2905
2906void cpu_dump_EA (target_ulong EA)
2907{
2908 FILE *f;
2909
2910 if (logfile) {
2911 f = logfile;
2912 } else {
2913 f = stdout;
2914 return;
2915 }
4a057712
JM		 2916 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2917}
2918
2919void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2920{
2921 FILE *f;
2922
2923 if (logfile) {
2924 f = logfile;
2925 } else {
2926 f = stdout;
2927 return;
2928 }
2929 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2930 RA, msr);
a496775f
JM		 2931}
2932
0a032cbe
JM		 2933void cpu_ppc_reset (void *opaque)
2934{
2935 CPUPPCState *env;
5eb7995e 2936 int i;
0a032cbe
JM		 2937
2938 env = opaque;
5eb7995e
JM		 2939 /* XXX: some of those flags initialisation values could depend
2940 * on the actual PowerPC implementation
2941 */
2942 for (i = 0; i < 63; i++)
2943 env->msr[i] = 0;
2944#if defined(TARGET_PPC64)
2945 msr_hv = 0; /* Should be 1... */
2946#endif
2947 msr_ap = 0; /* TO BE CHECKED */
2948 msr_sa = 0; /* TO BE CHECKED */
4e80effc 2949 msr_ep = 1;
0a032cbe
JM		 2950#if defined (DO_SINGLE_STEP) && 0
2951 /* Single step trace mode */
2952 msr_se = 1;
2953 msr_be = 1;
0a032cbe
JM		 2954#endif
2955#if defined(CONFIG_USER_ONLY)
5eb7995e 2956 msr_fp = 1; /* Allow floating point exceptions */
0a032cbe 2957 msr_pr = 1;
fe33cc71 2958#else
1c27f8fb 2959 env->nip = env->hreset_vector | env->excp_prefix;
141c8ae2
JM		 2960 if (env->mmu_model != POWERPC_MMU_REAL_4xx)
2961 ppc_tlb_invalidate_all(env);
0a032cbe
JM		 2962#endif
2963 do_compute_hflags(env);
2964 env->reserve = -1;
5eb7995e
JM		 2965 /* Be sure no exception or interrupt is pending */
2966 env->pending_interrupts = 0;
e1833e1f
JM		 2967 env->exception_index = POWERPC_EXCP_NONE;
2968 env->error_code = 0;
5eb7995e
JM		 2969 /* Flush all TLBs */
2970 tlb_flush(env, 1);
0a032cbe
JM		 2971}
2972
2973CPUPPCState *cpu_ppc_init (void)
2974{
2975 CPUPPCState *env;
2976
2977 env = qemu_mallocz(sizeof(CPUPPCState));
2978 if (!env)
2979 return NULL;
2980 cpu_exec_init(env);
0a032cbe
JM		 2981
2982 return env;
2983}
2984
2985void cpu_ppc_close (CPUPPCState *env)
2986{
2987 /* Should also remove all opcode tables... */
2988 free(env);
2989}
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