projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 79aceca5 | 1 | /* |
| 3fc6c082 | 2 | * PowerPC emulation helpers for qemu. |
| 79aceca5 | 3 | * |
| 76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
| 79aceca5 FB |
5 | * |
| 6 | * This library is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU Lesser General Public | |
| 8 | * License as published by the Free Software Foundation; either | |
| 9 | * version 2 of the License, or (at your option) any later version. | |
| 10 | * | |
| 11 | * This library is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | * Lesser General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU Lesser General Public | |
| 17 | * License along with this library; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 19 | */ | |
| fdabc366 FB |
20 | #include <stdarg.h> |
| 21 | #include <stdlib.h> | |
| 22 | #include <stdio.h> | |
| 23 | #include <string.h> | |
| 24 | #include <inttypes.h> | |
| 25 | #include <signal.h> | |
| 26 | #include <assert.h> | |
| 27 | ||
| 28 | #include "cpu.h" | |
| 29 | #include "exec-all.h" | |
| 9a64fbe4 FB |
30 | |
| 31 | //#define DEBUG_MMU | |
| 32 | //#define DEBUG_BATS | |
| 76a66253 | 33 | //#define DEBUG_SOFTWARE_TLB |
| 9a64fbe4 | 34 | //#define DEBUG_EXCEPTIONS |
| fdabc366 | 35 | //#define FLUSH_ALL_TLBS |
| 9a64fbe4 | 36 | |
| 9a64fbe4 | 37 | /*****************************************************************************/ |
| 3fc6c082 | 38 | /* PowerPC MMU emulation */ |
| a541f297 | 39 | |
| d9bce9d9 | 40 | #if defined(CONFIG_USER_ONLY) |
| 24741ef3 FB |
41 | int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
| 42 | int is_user, int is_softmmu) | |
| 43 | { | |
| 44 | int exception, error_code; | |
| d9bce9d9 | 45 | |
| 24741ef3 FB |
46 | if (rw == 2) { |
| 47 | exception = EXCP_ISI; | |
| 48 | error_code = 0; | |
| 49 | } else { | |
| 50 | exception = EXCP_DSI; | |
| 51 | error_code = 0; | |
| 52 | if (rw) | |
| 53 | error_code |= 0x02000000; | |
| 54 | env->spr[SPR_DAR] = address; | |
| 55 | env->spr[SPR_DSISR] = error_code; | |
| 56 | } | |
| 57 | env->exception_index = exception; | |
| 58 | env->error_code = error_code; | |
| 76a66253 | 59 | |
| 24741ef3 FB |
60 | return 1; |
| 61 | } | |
| 76a66253 JM |
62 | |
| 63 | target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr) | |
| 24741ef3 FB |
64 | { |
| 65 | return addr; | |
| 66 | } | |
| 67 | #else | |
| 76a66253 JM |
68 | /* Common routines used by software and hardware TLBs emulation */ |
| 69 | static inline int pte_is_valid (target_ulong pte0) | |
| 70 | { | |
| 71 | return pte0 & 0x80000000 ? 1 : 0; | |
| 72 | } | |
| 73 | ||
| 74 | static inline void pte_invalidate (target_ulong *pte0) | |
| 75 | { | |
| 76 | *pte0 &= ~0x80000000; | |
| 77 | } | |
| 78 | ||
| 79 | #define PTE_PTEM_MASK 0x7FFFFFBF | |
| 80 | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) | |
| 81 | ||
| 82 | static int pte_check (mmu_ctx_t *ctx, | |
| 83 | target_ulong pte0, target_ulong pte1, int h, int rw) | |
| 84 | { | |
| 85 | int access, ret; | |
| 86 | ||
| 87 | access = 0; | |
| 88 | ret = -1; | |
| 89 | /* Check validity and table match */ | |
| 90 | if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) { | |
| 91 | /* Check vsid & api */ | |
| 92 | if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) { | |
| 93 | if (ctx->raddr != (target_ulong)-1) { | |
| 94 | /* all matches should have equal RPN, WIMG & PP */ | |
| 95 | if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) { | |
| 96 | if (loglevel > 0) | |
| 97 | fprintf(logfile, "Bad RPN/WIMG/PP\n"); | |
| 98 | return -3; | |
| 99 | } | |
| 100 | } | |
| 101 | /* Compute access rights */ | |
| 102 | if (ctx->key == 0) { | |
| 103 | access = PAGE_READ; | |
| 104 | if ((pte1 & 0x00000003) != 0x3) | |
| 105 | access |= PAGE_WRITE; | |
| 106 | } else { | |
| 107 | switch (pte1 & 0x00000003) { | |
| 108 | case 0x0: | |
| 109 | access = 0; | |
| 110 | break; | |
| 111 | case 0x1: | |
| 112 | case 0x3: | |
| 113 | access = PAGE_READ; | |
| 114 | break; | |
| 115 | case 0x2: | |
| 116 | access = PAGE_READ | PAGE_WRITE; | |
| 117 | break; | |
| 118 | } | |
| 119 | } | |
| 120 | /* Keep the matching PTE informations */ | |
| 121 | ctx->raddr = pte1; | |
| 122 | ctx->prot = access; | |
| 123 | if ((rw == 0 && (access & PAGE_READ)) || | |
| 124 | (rw == 1 && (access & PAGE_WRITE))) { | |
| 125 | /* Access granted */ | |
| 126 | #if defined (DEBUG_MMU) | |
| 127 | if (loglevel > 0) | |
| 128 | fprintf(logfile, "PTE access granted !\n"); | |
| 129 | #endif | |
| 130 | ret = 0; | |
| 131 | } else { | |
| 132 | /* Access right violation */ | |
| 133 | #if defined (DEBUG_MMU) | |
| 134 | if (loglevel > 0) | |
| 135 | fprintf(logfile, "PTE access rejected\n"); | |
| 136 | #endif | |
| 137 | ret = -2; | |
| 138 | } | |
| 139 | } | |
| 140 | } | |
| 141 | ||
| 142 | return ret; | |
| 143 | } | |
| 144 | ||
| 145 | static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p, | |
| 146 | int ret, int rw) | |
| 147 | { | |
| 148 | int store = 0; | |
| 149 | ||
| 150 | /* Update page flags */ | |
| 151 | if (!(*pte1p & 0x00000100)) { | |
| 152 | /* Update accessed flag */ | |
| 153 | *pte1p |= 0x00000100; | |
| 154 | store = 1; | |
| 155 | } | |
| 156 | if (!(*pte1p & 0x00000080)) { | |
| 157 | if (rw == 1 && ret == 0) { | |
| 158 | /* Update changed flag */ | |
| 159 | *pte1p |= 0x00000080; | |
| 160 | store = 1; | |
| 161 | } else { | |
| 162 | /* Force page fault for first write access */ | |
| 163 | ctx->prot &= ~PAGE_WRITE; | |
| 164 | } | |
| 165 | } | |
| 166 | ||
| 167 | return store; | |
| 168 | } | |
| 169 | ||
| 170 | /* Software driven TLB helpers */ | |
| 171 | static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr, | |
| 172 | int way, int is_code) | |
| 173 | { | |
| 174 | int nr; | |
| 175 | ||
| 176 | /* Select TLB num in a way from address */ | |
| 177 | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1); | |
| 178 | /* Select TLB way */ | |
| 179 | nr += env->tlb_per_way * way; | |
| 180 | /* 6xx have separate TLBs for instructions and data */ | |
| 181 | if (is_code && env->id_tlbs == 1) | |
| 182 | nr += env->nb_tlb; | |
| 183 | ||
| 184 | return nr; | |
| 185 | } | |
| 186 | ||
| 187 | void ppc6xx_tlb_invalidate_all (CPUState *env) | |
| 188 | { | |
| 1d0a48fb | 189 | ppc6xx_tlb_t *tlb; |
| 76a66253 JM |
190 | int nr, max; |
| 191 | ||
| 192 | #if defined (DEBUG_SOFTWARE_TLB) && 0 | |
| 193 | if (loglevel != 0) { | |
| 194 | fprintf(logfile, "Invalidate all TLBs\n"); | |
| 195 | } | |
| 196 | #endif | |
| 197 | /* Invalidate all defined software TLB */ | |
| 198 | max = env->nb_tlb; | |
| 199 | if (env->id_tlbs == 1) | |
| 200 | max *= 2; | |
| 201 | for (nr = 0; nr < max; nr++) { | |
| 1d0a48fb | 202 | tlb = &env->tlb[nr].tlb6; |
| 76a66253 JM |
203 | #if !defined(FLUSH_ALL_TLBS) |
| 204 | tlb_flush_page(env, tlb->EPN); | |
| 205 | #endif | |
| 206 | pte_invalidate(&tlb->pte0); | |
| 207 | } | |
| 208 | #if defined(FLUSH_ALL_TLBS) | |
| 209 | tlb_flush(env, 1); | |
| 210 | #endif | |
| 211 | } | |
| 212 | ||
| 213 | static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env, | |
| 214 | target_ulong eaddr, | |
| 215 | int is_code, int match_epn) | |
| 216 | { | |
| 1d0a48fb | 217 | ppc6xx_tlb_t *tlb; |
| 76a66253 JM |
218 | int way, nr; |
| 219 | ||
| 220 | #if !defined(FLUSH_ALL_TLBS) | |
| 221 | /* Invalidate ITLB + DTLB, all ways */ | |
| 222 | for (way = 0; way < env->nb_ways; way++) { | |
| 223 | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); | |
| 1d0a48fb | 224 | tlb = &env->tlb[nr].tlb6; |
| 76a66253 JM |
225 | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
| 226 | #if defined (DEBUG_SOFTWARE_TLB) | |
| 227 | if (loglevel != 0) { | |
| 1b9eb036 | 228 | fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n", |
| 76a66253 JM |
229 | nr, env->nb_tlb, eaddr); |
| 230 | } | |
| 231 | #endif | |
| 232 | pte_invalidate(&tlb->pte0); | |
| 233 | tlb_flush_page(env, tlb->EPN); | |
| 234 | } | |
| 235 | } | |
| 236 | #else | |
| 237 | /* XXX: PowerPC specification say this is valid as well */ | |
| 238 | ppc6xx_tlb_invalidate_all(env); | |
| 239 | #endif | |
| 240 | } | |
| 241 | ||
| 242 | void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr, | |
| 243 | int is_code) | |
| 244 | { | |
| 245 | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0); | |
| 246 | } | |
| 247 | ||
| 248 | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, | |
| 249 | target_ulong pte0, target_ulong pte1) | |
| 250 | { | |
| 1d0a48fb | 251 | ppc6xx_tlb_t *tlb; |
| 76a66253 JM |
252 | int nr; |
| 253 | ||
| 254 | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); | |
| 1d0a48fb | 255 | tlb = &env->tlb[nr].tlb6; |
| 76a66253 JM |
256 | #if defined (DEBUG_SOFTWARE_TLB) |
| 257 | if (loglevel != 0) { | |
| 1b9eb036 JM |
258 | fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX |
| 259 | " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1); | |
| 76a66253 JM |
260 | } |
| 261 | #endif | |
| 262 | /* Invalidate any pending reference in Qemu for this virtual address */ | |
| 263 | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1); | |
| 264 | tlb->pte0 = pte0; | |
| 265 | tlb->pte1 = pte1; | |
| 266 | tlb->EPN = EPN; | |
| 76a66253 JM |
267 | /* Store last way for LRU mechanism */ |
| 268 | env->last_way = way; | |
| 269 | } | |
| 270 | ||
| 271 | static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx, | |
| 272 | target_ulong eaddr, int rw, int access_type) | |
| 273 | { | |
| 1d0a48fb | 274 | ppc6xx_tlb_t *tlb; |
| 76a66253 JM |
275 | int nr, best, way; |
| 276 | int ret; | |
| d9bce9d9 | 277 | |
| 76a66253 JM |
278 | best = -1; |
| 279 | ret = -1; /* No TLB found */ | |
| 280 | for (way = 0; way < env->nb_ways; way++) { | |
| 281 | nr = ppc6xx_tlb_getnum(env, eaddr, way, | |
| 282 | access_type == ACCESS_CODE ? 1 : 0); | |
| 1d0a48fb | 283 | tlb = &env->tlb[nr].tlb6; |
| 76a66253 JM |
284 | /* This test "emulates" the PTE index match for hardware TLBs */ |
| 285 | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { | |
| 286 | #if defined (DEBUG_SOFTWARE_TLB) | |
| 287 | if (loglevel != 0) { | |
| 1b9eb036 JM |
288 | fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX |
| 289 | "] <> " ADDRX "\n", | |
| 76a66253 JM |
290 | nr, env->nb_tlb, |
| 291 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
| 292 | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); | |
| 293 | } | |
| 294 | #endif | |
| 295 | continue; | |
| 296 | } | |
| 297 | #if defined (DEBUG_SOFTWARE_TLB) | |
| 298 | if (loglevel != 0) { | |
| 1b9eb036 JM |
299 | fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX |
| 300 | " %c %c\n", | |
| 76a66253 JM |
301 | nr, env->nb_tlb, |
| 302 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
| 303 | tlb->EPN, eaddr, tlb->pte1, | |
| 304 | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); | |
| 305 | } | |
| 306 | #endif | |
| 307 | switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) { | |
| 308 | case -3: | |
| 309 | /* TLB inconsistency */ | |
| 310 | return -1; | |
| 311 | case -2: | |
| 312 | /* Access violation */ | |
| 313 | ret = -2; | |
| 314 | best = nr; | |
| 315 | break; | |
| 316 | case -1: | |
| 317 | default: | |
| 318 | /* No match */ | |
| 319 | break; | |
| 320 | case 0: | |
| 321 | /* access granted */ | |
| 322 | /* XXX: we should go on looping to check all TLBs consistency | |
| 323 | * but we can speed-up the whole thing as the | |
| 324 | * result would be undefined if TLBs are not consistent. | |
| 325 | */ | |
| 326 | ret = 0; | |
| 327 | best = nr; | |
| 328 | goto done; | |
| 329 | } | |
| 330 | } | |
| 331 | if (best != -1) { | |
| 332 | done: | |
| 333 | #if defined (DEBUG_SOFTWARE_TLB) | |
| 334 | if (loglevel > 0) { | |
| 335 | fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n", | |
| 336 | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); | |
| 337 | } | |
| 338 | #endif | |
| 339 | /* Update page flags */ | |
| 1d0a48fb | 340 | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
| 76a66253 JM |
341 | } |
| 342 | ||
| 343 | return ret; | |
| 344 | } | |
| 345 | ||
| 9a64fbe4 | 346 | /* Perform BAT hit & translation */ |
| 76a66253 JM |
347 | static int get_bat (CPUState *env, mmu_ctx_t *ctx, |
| 348 | target_ulong virtual, int rw, int type) | |
| 9a64fbe4 | 349 | { |
| 76a66253 JM |
350 | target_ulong *BATlt, *BATut, *BATu, *BATl; |
| 351 | target_ulong base, BEPIl, BEPIu, bl; | |
| 9a64fbe4 FB |
352 | int i; |
| 353 | int ret = -1; | |
| 354 | ||
| 355 | #if defined (DEBUG_BATS) | |
| 356 | if (loglevel > 0) { | |
| 1b9eb036 | 357 | fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__, |
| 76a66253 | 358 | type == ACCESS_CODE ? 'I' : 'D', virtual); |
| 9a64fbe4 | 359 | } |
| 9a64fbe4 FB |
360 | #endif |
| 361 | switch (type) { | |
| 362 | case ACCESS_CODE: | |
| 363 | BATlt = env->IBAT[1]; | |
| 364 | BATut = env->IBAT[0]; | |
| 365 | break; | |
| 366 | default: | |
| 367 | BATlt = env->DBAT[1]; | |
| 368 | BATut = env->DBAT[0]; | |
| 369 | break; | |
| 370 | } | |
| 371 | #if defined (DEBUG_BATS) | |
| 372 | if (loglevel > 0) { | |
| 1b9eb036 | 373 | fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__, |
| 76a66253 | 374 | type == ACCESS_CODE ? 'I' : 'D', virtual); |
| 9a64fbe4 | 375 | } |
| 9a64fbe4 FB |
376 | #endif |
| 377 | base = virtual & 0xFFFC0000; | |
| 378 | for (i = 0; i < 4; i++) { | |
| 379 | BATu = &BATut[i]; | |
| 380 | BATl = &BATlt[i]; | |
| 381 | BEPIu = *BATu & 0xF0000000; | |
| 382 | BEPIl = *BATu & 0x0FFE0000; | |
| 383 | bl = (*BATu & 0x00001FFC) << 15; | |
| 384 | #if defined (DEBUG_BATS) | |
| 385 | if (loglevel > 0) { | |
| 1b9eb036 JM |
386 | fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
| 387 | " BATl 0x" ADDRX "\n", | |
| 9a64fbe4 FB |
388 | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
| 389 | *BATu, *BATl); | |
| 9a64fbe4 FB |
390 | } |
| 391 | #endif | |
| 392 | if ((virtual & 0xF0000000) == BEPIu && | |
| 393 | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) { | |
| 394 | /* BAT matches */ | |
| 395 | if ((msr_pr == 0 && (*BATu & 0x00000002)) || | |
| 396 | (msr_pr == 1 && (*BATu & 0x00000001))) { | |
| 397 | /* Get physical address */ | |
| 76a66253 | 398 | ctx->raddr = (*BATl & 0xF0000000) | |
| 9a64fbe4 | 399 | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
| a541f297 | 400 | (virtual & 0x0001F000); |
| 9a64fbe4 | 401 | if (*BATl & 0x00000001) |
| 76a66253 | 402 | ctx->prot = PAGE_READ; |
| 9a64fbe4 | 403 | if (*BATl & 0x00000002) |
| 76a66253 | 404 | ctx->prot = PAGE_WRITE | PAGE_READ; |
| 9a64fbe4 FB |
405 | #if defined (DEBUG_BATS) |
| 406 | if (loglevel > 0) { | |
| 1b9eb036 JM |
407 | fprintf(logfile, "BAT %d match: r 0x" ADDRX |
| 408 | " prot=%c%c\n", | |
| 76a66253 JM |
409 | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
| 410 | ctx->prot & PAGE_WRITE ? 'W' : '-'); | |
| 9a64fbe4 FB |
411 | } |
| 412 | #endif | |
| 413 | ret = 0; | |
| 414 | break; | |
| 415 | } | |
| 416 | } | |
| 417 | } | |
| 418 | if (ret < 0) { | |
| 419 | #if defined (DEBUG_BATS) | |
| 1b9eb036 | 420 | printf("no BAT match for 0x" ADDRX ":\n", virtual); |
| 9a64fbe4 FB |
421 | for (i = 0; i < 4; i++) { |
| 422 | BATu = &BATut[i]; | |
| 423 | BATl = &BATlt[i]; | |
| 424 | BEPIu = *BATu & 0xF0000000; | |
| 425 | BEPIl = *BATu & 0x0FFE0000; | |
| 426 | bl = (*BATu & 0x00001FFC) << 15; | |
| 1b9eb036 JM |
427 | printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX |
| 428 | " BATl 0x" ADDRX " \n\t" | |
| 429 | "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n", | |
| 9a64fbe4 FB |
430 | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
| 431 | *BATu, *BATl, BEPIu, BEPIl, bl); | |
| 432 | } | |
| 433 | #endif | |
| 9a64fbe4 FB |
434 | } |
| 435 | /* No hit */ | |
| 436 | return ret; | |
| 437 | } | |
| 438 | ||
| 439 | /* PTE table lookup */ | |
| 76a66253 | 440 | static int find_pte (mmu_ctx_t *ctx, int h, int rw) |
| 9a64fbe4 | 441 | { |
| 76a66253 JM |
442 | target_ulong base, pte0, pte1; |
| 443 | int i, good = -1; | |
| 444 | int ret; | |
| 9a64fbe4 | 445 | |
| 76a66253 JM |
446 | ret = -1; /* No entry found */ |
| 447 | base = ctx->pg_addr[h]; | |
| 9a64fbe4 | 448 | for (i = 0; i < 8; i++) { |
| 8df1cd07 FB |
449 | pte0 = ldl_phys(base + (i * 8)); |
| 450 | pte1 = ldl_phys(base + (i * 8) + 4); | |
| 9a64fbe4 | 451 | #if defined (DEBUG_MMU) |
| d094807b | 452 | if (loglevel > 0) { |
| 1b9eb036 JM |
453 | fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX |
| 454 | " 0x" ADDRX " %d %d %d 0x" ADDRX "\n", | |
| 455 | base + (i * 8), pte0, pte1, | |
| 76a66253 JM |
456 | pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem); |
| 457 | } | |
| 9a64fbe4 | 458 | #endif |
| 76a66253 JM |
459 | switch (pte_check(ctx, pte0, pte1, h, rw)) { |
| 460 | case -3: | |
| 461 | /* PTE inconsistency */ | |
| 462 | return -1; | |
| 463 | case -2: | |
| 464 | /* Access violation */ | |
| 465 | ret = -2; | |
| 466 | good = i; | |
| 467 | break; | |
| 468 | case -1: | |
| 469 | default: | |
| 470 | /* No PTE match */ | |
| 471 | break; | |
| 472 | case 0: | |
| 473 | /* access granted */ | |
| 474 | /* XXX: we should go on looping to check all PTEs consistency | |
| 475 | * but if we can speed-up the whole thing as the | |
| 476 | * result would be undefined if PTEs are not consistent. | |
| 477 | */ | |
| 478 | ret = 0; | |
| 479 | good = i; | |
| 480 | goto done; | |
| 9a64fbe4 FB |
481 | } |
| 482 | } | |
| 483 | if (good != -1) { | |
| 76a66253 | 484 | done: |
| 9a64fbe4 | 485 | #if defined (DEBUG_MMU) |
| d094807b | 486 | if (loglevel > 0) { |
| 1b9eb036 JM |
487 | fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x " |
| 488 | "ret=%d\n", | |
| 76a66253 JM |
489 | ctx->raddr, ctx->prot, ret); |
| 490 | } | |
| 9a64fbe4 FB |
491 | #endif |
| 492 | /* Update page flags */ | |
| 76a66253 JM |
493 | pte1 = ctx->raddr; |
| 494 | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) | |
| 495 | stl_phys_notdirty(base + (good * 8) + 4, pte1); | |
| 9a64fbe4 FB |
496 | } |
| 497 | ||
| 498 | return ret; | |
| 79aceca5 FB |
499 | } |
| 500 | ||
| 76a66253 JM |
501 | static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1, |
| 502 | target_phys_addr_t hash, | |
| 503 | target_phys_addr_t mask) | |
| 79aceca5 | 504 | { |
| 9a64fbe4 | 505 | return (sdr1 & 0xFFFF0000) | (hash & mask); |
| 79aceca5 FB |
506 | } |
| 507 | ||
| 9a64fbe4 | 508 | /* Perform segment based translation */ |
| 76a66253 JM |
509 | static int get_segment (CPUState *env, mmu_ctx_t *ctx, |
| 510 | target_ulong eaddr, int rw, int type) | |
| 79aceca5 | 511 | { |
| 76a66253 JM |
512 | target_phys_addr_t sdr, hash, mask; |
| 513 | target_ulong sr, vsid, pgidx; | |
| 9a64fbe4 | 514 | int ret = -1, ret2; |
| 79aceca5 | 515 | |
| 76a66253 | 516 | sr = env->sr[eaddr >> 28]; |
| 9a64fbe4 | 517 | #if defined (DEBUG_MMU) |
| a541f297 | 518 | if (loglevel > 0) { |
| 1b9eb036 JM |
519 | fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x" |
| 520 | ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n", | |
| 76a66253 JM |
521 | eaddr, eaddr >> 28, sr, env->nip, |
| 522 | env->lr, msr_ir, msr_dr, msr_pr, rw, type); | |
| a541f297 | 523 | } |
| 9a64fbe4 | 524 | #endif |
| 76a66253 JM |
525 | ctx->key = (((sr & 0x20000000) && msr_pr == 1) || |
| 526 | ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0; | |
| 9a64fbe4 FB |
527 | if ((sr & 0x80000000) == 0) { |
| 528 | #if defined (DEBUG_MMU) | |
| 76a66253 | 529 | if (loglevel > 0) |
| 1b9eb036 | 530 | fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n", |
| 76a66253 | 531 | ctx->key, sr & 0x10000000); |
| 9a64fbe4 FB |
532 | #endif |
| 533 | /* Check if instruction fetch is allowed, if needed */ | |
| 534 | if (type != ACCESS_CODE || (sr & 0x10000000) == 0) { | |
| 535 | /* Page address translation */ | |
| 76a66253 | 536 | pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF; |
| 9a64fbe4 | 537 | vsid = sr & 0x00FFFFFF; |
| a541f297 | 538 | hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6; |
| 76a66253 JM |
539 | /* Primary table address */ |
| 540 | sdr = env->sdr1; | |
| 9a64fbe4 | 541 | mask = ((sdr & 0x000001FF) << 16) | 0xFFC0; |
| 76a66253 JM |
542 | ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask); |
| 543 | /* Secondary table address */ | |
| 544 | hash = (~hash) & 0x01FFFFC0; | |
| 545 | ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask); | |
| 546 | ctx->ptem = (vsid << 7) | (pgidx >> 10); | |
| 547 | /* Initialize real address with an invalid value */ | |
| 548 | ctx->raddr = (target_ulong)-1; | |
| 549 | if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) { | |
| 550 | /* Software TLB search */ | |
| 551 | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); | |
| 552 | } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) { | |
| 553 | /* XXX: TODO */ | |
| 554 | } else { | |
| 9a64fbe4 | 555 | #if defined (DEBUG_MMU) |
| 76a66253 | 556 | if (loglevel > 0) { |
| 1b9eb036 JM |
557 | fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x " |
| 558 | "api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n", | |
| 559 | sdr, vsid, pgidx, hash, ctx->pg_addr[0]); | |
| 76a66253 | 560 | } |
| 9a64fbe4 | 561 | #endif |
| 76a66253 JM |
562 | /* Primary table lookup */ |
| 563 | ret = find_pte(ctx, 0, rw); | |
| 564 | if (ret < 0) { | |
| 565 | /* Secondary table lookup */ | |
| 9a64fbe4 | 566 | #if defined (DEBUG_MMU) |
| 76a66253 JM |
567 | if (eaddr != 0xEFFFFFFF && loglevel > 0) { |
| 568 | fprintf(logfile, | |
| 1b9eb036 JM |
569 | "1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x " |
| 570 | "hash=0x%05x pg_addr=0x" ADDRX "\n", | |
| 571 | sdr, vsid, pgidx, hash, ctx->pg_addr[1]); | |
| 76a66253 | 572 | } |
| 9a64fbe4 | 573 | #endif |
| 76a66253 JM |
574 | ret2 = find_pte(ctx, 1, rw); |
| 575 | if (ret2 != -1) | |
| 576 | ret = ret2; | |
| 577 | } | |
| 9a64fbe4 | 578 | } |
| 9a64fbe4 FB |
579 | } else { |
| 580 | #if defined (DEBUG_MMU) | |
| 76a66253 JM |
581 | if (loglevel > 0) |
| 582 | fprintf(logfile, "No access allowed\n"); | |
| 9a64fbe4 | 583 | #endif |
| 76a66253 | 584 | ret = -3; |
| 9a64fbe4 FB |
585 | } |
| 586 | } else { | |
| 587 | #if defined (DEBUG_MMU) | |
| a541f297 | 588 | if (loglevel > 0) |
| 76a66253 | 589 | fprintf(logfile, "direct store...\n"); |
| 9a64fbe4 FB |
590 | #endif |
| 591 | /* Direct-store segment : absolutely *BUGGY* for now */ | |
| 592 | switch (type) { | |
| 593 | case ACCESS_INT: | |
| 594 | /* Integer load/store : only access allowed */ | |
| 595 | break; | |
| 596 | case ACCESS_CODE: | |
| 597 | /* No code fetch is allowed in direct-store areas */ | |
| 598 | return -4; | |
| 599 | case ACCESS_FLOAT: | |
| 600 | /* Floating point load/store */ | |
| 601 | return -4; | |
| 602 | case ACCESS_RES: | |
| 603 | /* lwarx, ldarx or srwcx. */ | |
| 604 | return -4; | |
| 605 | case ACCESS_CACHE: | |
| 606 | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ | |
| 607 | /* Should make the instruction do no-op. | |
| 608 | * As it already do no-op, it's quite easy :-) | |
| 609 | */ | |
| 76a66253 | 610 | ctx->raddr = eaddr; |
| 9a64fbe4 FB |
611 | return 0; |
| 612 | case ACCESS_EXT: | |
| 613 | /* eciwx or ecowx */ | |
| 614 | return -4; | |
| 615 | default: | |
| 616 | if (logfile) { | |
| 617 | fprintf(logfile, "ERROR: instruction should not need " | |
| 618 | "address translation\n"); | |
| 619 | } | |
| 620 | printf("ERROR: instruction should not need " | |
| 621 | "address translation\n"); | |
| 622 | return -4; | |
| 623 | } | |
| 76a66253 JM |
624 | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
| 625 | ctx->raddr = eaddr; | |
| 9a64fbe4 FB |
626 | ret = 2; |
| 627 | } else { | |
| 628 | ret = -2; | |
| 629 | } | |
| 79aceca5 | 630 | } |
| 9a64fbe4 FB |
631 | |
| 632 | return ret; | |
| 79aceca5 FB |
633 | } |
| 634 | ||
| 76a66253 JM |
635 | static int check_physical (CPUState *env, mmu_ctx_t *ctx, |
| 636 | target_ulong eaddr, int rw) | |
| 637 | { | |
| 638 | int in_plb, ret; | |
| 639 | ||
| 640 | ctx->raddr = eaddr; | |
| 641 | ctx->prot = PAGE_READ; | |
| 642 | ret = 0; | |
| 643 | if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) { | |
| 644 | /* 403 family add some particular protections, | |
| 645 | * using PBL/PBU registers for accesses with no translation. | |
| 646 | */ | |
| 647 | in_plb = | |
| 648 | /* Check PLB validity */ | |
| 649 | (env->pb[0] < env->pb[1] && | |
| 650 | /* and address in plb area */ | |
| 651 | eaddr >= env->pb[0] && eaddr < env->pb[1]) || | |
| 652 | (env->pb[2] < env->pb[3] && | |
| 653 | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; | |
| 654 | if (in_plb ^ msr_px) { | |
| 655 | /* Access in protected area */ | |
| 656 | if (rw == 1) { | |
| 657 | /* Access is not allowed */ | |
| 658 | ret = -2; | |
| 659 | } | |
| 660 | } else { | |
| 661 | /* Read-write access is allowed */ | |
| 662 | ctx->prot |= PAGE_WRITE; | |
| 663 | } | |
| 664 | } else { | |
| 665 | ctx->prot |= PAGE_WRITE; | |
| 666 | } | |
| 667 | ||
| 668 | return ret; | |
| 669 | } | |
| 670 | ||
| 671 | int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, | |
| 672 | int rw, int access_type, int check_BATs) | |
| 9a64fbe4 FB |
673 | { |
| 674 | int ret; | |
| 514fb8c1 | 675 | #if 0 |
| 9a64fbe4 FB |
676 | if (loglevel > 0) { |
| 677 | fprintf(logfile, "%s\n", __func__); | |
| 678 | } | |
| d9bce9d9 | 679 | #endif |
| 4b3686fa FB |
680 | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
| 681 | (access_type != ACCESS_CODE && msr_dr == 0)) { | |
| 9a64fbe4 | 682 | /* No address translation */ |
| 76a66253 | 683 | ret = check_physical(env, ctx, eaddr, rw); |
| 9a64fbe4 FB |
684 | } else { |
| 685 | /* Try to find a BAT */ | |
| 76a66253 JM |
686 | ret = -1; |
| 687 | if (check_BATs) | |
| 688 | ret = get_bat(env, ctx, eaddr, rw, access_type); | |
| 9a64fbe4 FB |
689 | if (ret < 0) { |
| 690 | /* We didn't match any BAT entry */ | |
| 76a66253 | 691 | ret = get_segment(env, ctx, eaddr, rw, access_type); |
| 9a64fbe4 FB |
692 | } |
| 693 | } | |
| 514fb8c1 | 694 | #if 0 |
| a541f297 | 695 | if (loglevel > 0) { |
| 1b9eb036 | 696 | fprintf(logfile, "%s address " ADDRX " => " ADDRX "\n", |
| 76a66253 | 697 | __func__, eaddr, ctx->raddr); |
| a541f297 | 698 | } |
| 76a66253 | 699 | #endif |
| d9bce9d9 | 700 | |
| 9a64fbe4 FB |
701 | return ret; |
| 702 | } | |
| 703 | ||
| 76a66253 | 704 | target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
| a6b025d3 | 705 | { |
| 76a66253 | 706 | mmu_ctx_t ctx; |
| a6b025d3 | 707 | |
| 76a66253 | 708 | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0)) |
| a6b025d3 | 709 | return -1; |
| 76a66253 JM |
710 | |
| 711 | return ctx.raddr & TARGET_PAGE_MASK; | |
| a6b025d3 | 712 | } |
| 9a64fbe4 | 713 | |
| 9a64fbe4 FB |
714 | /* Perform address translation */ |
| 715 | int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, | |
| a541f297 | 716 | int is_user, int is_softmmu) |
| 9a64fbe4 | 717 | { |
| 76a66253 | 718 | mmu_ctx_t ctx; |
| 9a64fbe4 | 719 | int exception = 0, error_code = 0; |
| a541f297 | 720 | int access_type; |
| 9a64fbe4 | 721 | int ret = 0; |
| d9bce9d9 | 722 | |
| b769d8fe FB |
723 | if (rw == 2) { |
| 724 | /* code access */ | |
| 725 | rw = 0; | |
| 726 | access_type = ACCESS_CODE; | |
| 727 | } else { | |
| 728 | /* data access */ | |
| 729 | /* XXX: put correct access by using cpu_restore_state() | |
| 730 | correctly */ | |
| 731 | access_type = ACCESS_INT; | |
| 732 | // access_type = env->access_type; | |
| 733 | } | |
| 76a66253 | 734 | ret = get_physical_address(env, &ctx, address, rw, access_type, 1); |
| 9a64fbe4 | 735 | if (ret == 0) { |
| 76a66253 JM |
736 | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, |
| 737 | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, | |
| 738 | is_user, is_softmmu); | |
| 9a64fbe4 | 739 | } else if (ret < 0) { |
| 9a64fbe4 | 740 | #if defined (DEBUG_MMU) |
| 76a66253 JM |
741 | if (loglevel > 0) |
| 742 | cpu_dump_state(env, logfile, fprintf, 0); | |
| 9a64fbe4 FB |
743 | #endif |
| 744 | if (access_type == ACCESS_CODE) { | |
| 745 | exception = EXCP_ISI; | |
| 746 | switch (ret) { | |
| 747 | case -1: | |
| 76a66253 JM |
748 | /* No matches in page tables or TLB */ |
| 749 | if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) { | |
| 750 | exception = EXCP_I_TLBMISS; | |
| 751 | env->spr[SPR_IMISS] = address; | |
| 752 | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; | |
| 753 | error_code = 1 << 18; | |
| 754 | goto tlb_miss; | |
| 755 | } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) { | |
| 756 | /* XXX: TODO */ | |
| 757 | } else { | |
| 758 | error_code = 0x40000000; | |
| 759 | } | |
| 9a64fbe4 FB |
760 | break; |
| 761 | case -2: | |
| 762 | /* Access rights violation */ | |
| 2be0071f | 763 | error_code = 0x08000000; |
| 9a64fbe4 FB |
764 | break; |
| 765 | case -3: | |
| 76a66253 | 766 | /* No execute protection violation */ |
| 2be0071f | 767 | error_code = 0x10000000; |
| 9a64fbe4 FB |
768 | break; |
| 769 | case -4: | |
| 770 | /* Direct store exception */ | |
| 771 | /* No code fetch is allowed in direct-store areas */ | |
| 2be0071f FB |
772 | error_code = 0x10000000; |
| 773 | break; | |
| 774 | case -5: | |
| 775 | /* No match in segment table */ | |
| 776 | exception = EXCP_ISEG; | |
| 777 | error_code = 0; | |
| 9a64fbe4 FB |
778 | break; |
| 779 | } | |
| 780 | } else { | |
| 781 | exception = EXCP_DSI; | |
| 782 | switch (ret) { | |
| 783 | case -1: | |
| 76a66253 JM |
784 | /* No matches in page tables or TLB */ |
| 785 | if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) { | |
| 786 | if (rw == 1) { | |
| 787 | exception = EXCP_DS_TLBMISS; | |
| 788 | error_code = 1 << 16; | |
| 789 | } else { | |
| 790 | exception = EXCP_DL_TLBMISS; | |
| 791 | error_code = 0; | |
| 792 | } | |
| 793 | env->spr[SPR_DMISS] = address; | |
| 794 | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; | |
| 795 | tlb_miss: | |
| 796 | error_code |= ctx.key << 19; | |
| 797 | env->spr[SPR_HASH1] = ctx.pg_addr[0]; | |
| 798 | env->spr[SPR_HASH2] = ctx.pg_addr[1]; | |
| 799 | /* Do not alter DAR nor DSISR */ | |
| 800 | goto out; | |
| 801 | } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) { | |
| 802 | /* XXX: TODO */ | |
| 803 | } else { | |
| 804 | error_code = 0x40000000; | |
| 805 | } | |
| 9a64fbe4 FB |
806 | break; |
| 807 | case -2: | |
| 808 | /* Access rights violation */ | |
| 2be0071f | 809 | error_code = 0x08000000; |
| 9a64fbe4 FB |
810 | break; |
| 811 | case -4: | |
| 812 | /* Direct store exception */ | |
| 813 | switch (access_type) { | |
| 814 | case ACCESS_FLOAT: | |
| 815 | /* Floating point load/store */ | |
| 816 | exception = EXCP_ALIGN; | |
| 817 | error_code = EXCP_ALIGN_FP; | |
| 818 | break; | |
| 819 | case ACCESS_RES: | |
| 820 | /* lwarx, ldarx or srwcx. */ | |
| 2be0071f | 821 | error_code = 0x04000000; |
| 9a64fbe4 FB |
822 | break; |
| 823 | case ACCESS_EXT: | |
| 824 | /* eciwx or ecowx */ | |
| 2be0071f | 825 | error_code = 0x04100000; |
| 9a64fbe4 FB |
826 | break; |
| 827 | default: | |
| 76a66253 | 828 | printf("DSI: invalid exception (%d)\n", ret); |
| 9a64fbe4 FB |
829 | exception = EXCP_PROGRAM; |
| 830 | error_code = EXCP_INVAL | EXCP_INVAL_INVAL; | |
| 831 | break; | |
| 832 | } | |
| fdabc366 | 833 | break; |
| 2be0071f FB |
834 | case -5: |
| 835 | /* No match in segment table */ | |
| 836 | exception = EXCP_DSEG; | |
| 837 | error_code = 0; | |
| 838 | break; | |
| 9a64fbe4 | 839 | } |
| fdabc366 | 840 | if (exception == EXCP_DSI && rw == 1) |
| 2be0071f | 841 | error_code |= 0x02000000; |
| 76a66253 JM |
842 | /* Store fault address */ |
| 843 | env->spr[SPR_DAR] = address; | |
| 2be0071f | 844 | env->spr[SPR_DSISR] = error_code; |
| 9a64fbe4 | 845 | } |
| 76a66253 | 846 | out: |
| 9a64fbe4 FB |
847 | #if 0 |
| 848 | printf("%s: set exception to %d %02x\n", | |
| 849 | __func__, exception, error_code); | |
| 850 | #endif | |
| 851 | env->exception_index = exception; | |
| 852 | env->error_code = error_code; | |
| 9a64fbe4 FB |
853 | ret = 1; |
| 854 | } | |
| 76a66253 | 855 | |
| 9a64fbe4 FB |
856 | return ret; |
| 857 | } | |
| 858 | ||
| 3fc6c082 FB |
859 | /*****************************************************************************/ |
| 860 | /* BATs management */ | |
| 861 | #if !defined(FLUSH_ALL_TLBS) | |
| 862 | static inline void do_invalidate_BAT (CPUPPCState *env, | |
| 863 | target_ulong BATu, target_ulong mask) | |
| 864 | { | |
| 865 | target_ulong base, end, page; | |
| 76a66253 | 866 | |
| 3fc6c082 FB |
867 | base = BATu & ~0x0001FFFF; |
| 868 | end = base + mask + 0x00020000; | |
| 869 | #if defined (DEBUG_BATS) | |
| 76a66253 | 870 | if (loglevel != 0) { |
| 1b9eb036 | 871 | fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n", |
| 76a66253 JM |
872 | base, end, mask); |
| 873 | } | |
| 3fc6c082 FB |
874 | #endif |
| 875 | for (page = base; page != end; page += TARGET_PAGE_SIZE) | |
| 876 | tlb_flush_page(env, page); | |
| 877 | #if defined (DEBUG_BATS) | |
| 878 | if (loglevel != 0) | |
| 879 | fprintf(logfile, "Flush done\n"); | |
| 880 | #endif | |
| 881 | } | |
| 882 | #endif | |
| 883 | ||
| 884 | static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr, | |
| 885 | target_ulong value) | |
| 886 | { | |
| 887 | #if defined (DEBUG_BATS) | |
| 888 | if (loglevel != 0) { | |
| 1b9eb036 JM |
889 | fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n", |
| 890 | ID, nr, ul == 0 ? 'u' : 'l', value, env->nip); | |
| 3fc6c082 FB |
891 | } |
| 892 | #endif | |
| 893 | } | |
| 894 | ||
| 895 | target_ulong do_load_ibatu (CPUPPCState *env, int nr) | |
| 896 | { | |
| 897 | return env->IBAT[0][nr]; | |
| 898 | } | |
| 899 | ||
| 900 | target_ulong do_load_ibatl (CPUPPCState *env, int nr) | |
| 901 | { | |
| 902 | return env->IBAT[1][nr]; | |
| 903 | } | |
| 904 | ||
| 905 | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value) | |
| 906 | { | |
| 907 | target_ulong mask; | |
| 908 | ||
| 909 | dump_store_bat(env, 'I', 0, nr, value); | |
| 910 | if (env->IBAT[0][nr] != value) { | |
| 911 | mask = (value << 15) & 0x0FFE0000UL; | |
| 912 | #if !defined(FLUSH_ALL_TLBS) | |
| 913 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
| 914 | #endif | |
| 915 | /* When storing valid upper BAT, mask BEPI and BRPN | |
| 916 | * and invalidate all TLBs covered by this BAT | |
| 917 | */ | |
| 918 | mask = (value << 15) & 0x0FFE0000UL; | |
| 919 | env->IBAT[0][nr] = (value & 0x00001FFFUL) | | |
| 920 | (value & ~0x0001FFFFUL & ~mask); | |
| 921 | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | | |
| 922 | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); | |
| 923 | #if !defined(FLUSH_ALL_TLBS) | |
| 924 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
| 76a66253 | 925 | #else |
| 3fc6c082 FB |
926 | tlb_flush(env, 1); |
| 927 | #endif | |
| 928 | } | |
| 929 | } | |
| 930 | ||
| 931 | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value) | |
| 932 | { | |
| 933 | dump_store_bat(env, 'I', 1, nr, value); | |
| 934 | env->IBAT[1][nr] = value; | |
| 935 | } | |
| 936 | ||
| 937 | target_ulong do_load_dbatu (CPUPPCState *env, int nr) | |
| 938 | { | |
| 939 | return env->DBAT[0][nr]; | |
| 940 | } | |
| 941 | ||
| 942 | target_ulong do_load_dbatl (CPUPPCState *env, int nr) | |
| 943 | { | |
| 944 | return env->DBAT[1][nr]; | |
| 945 | } | |
| 946 | ||
| 947 | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value) | |
| 948 | { | |
| 949 | target_ulong mask; | |
| 950 | ||
| 951 | dump_store_bat(env, 'D', 0, nr, value); | |
| 952 | if (env->DBAT[0][nr] != value) { | |
| 953 | /* When storing valid upper BAT, mask BEPI and BRPN | |
| 954 | * and invalidate all TLBs covered by this BAT | |
| 955 | */ | |
| 956 | mask = (value << 15) & 0x0FFE0000UL; | |
| 957 | #if !defined(FLUSH_ALL_TLBS) | |
| 958 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
| 959 | #endif | |
| 960 | mask = (value << 15) & 0x0FFE0000UL; | |
| 961 | env->DBAT[0][nr] = (value & 0x00001FFFUL) | | |
| 962 | (value & ~0x0001FFFFUL & ~mask); | |
| 963 | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | | |
| 964 | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); | |
| 965 | #if !defined(FLUSH_ALL_TLBS) | |
| 966 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
| 967 | #else | |
| 968 | tlb_flush(env, 1); | |
| 969 | #endif | |
| 970 | } | |
| 971 | } | |
| 972 | ||
| 973 | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value) | |
| 974 | { | |
| 975 | dump_store_bat(env, 'D', 1, nr, value); | |
| 976 | env->DBAT[1][nr] = value; | |
| 977 | } | |
| 978 | ||
| 3fc6c082 FB |
979 | /*****************************************************************************/ |
| 980 | /* Special registers manipulation */ | |
| d9bce9d9 JM |
981 | #if defined(TARGET_PPC64) |
| 982 | target_ulong ppc_load_asr (CPUPPCState *env) | |
| 983 | { | |
| 984 | return env->asr; | |
| 985 | } | |
| 986 | ||
| 987 | void ppc_store_asr (CPUPPCState *env, target_ulong value) | |
| 988 | { | |
| 989 | if (env->asr != value) { | |
| 990 | env->asr = value; | |
| 991 | tlb_flush(env, 1); | |
| 992 | } | |
| 993 | } | |
| 994 | #endif | |
| 995 | ||
| 3fc6c082 FB |
996 | target_ulong do_load_sdr1 (CPUPPCState *env) |
| 997 | { | |
| 998 | return env->sdr1; | |
| 999 | } | |
| 1000 | ||
| 1001 | void do_store_sdr1 (CPUPPCState *env, target_ulong value) | |
| 1002 | { | |
| 1003 | #if defined (DEBUG_MMU) | |
| 1004 | if (loglevel != 0) { | |
| 1b9eb036 | 1005 | fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value); |
| 3fc6c082 FB |
1006 | } |
| 1007 | #endif | |
| 1008 | if (env->sdr1 != value) { | |
| 1009 | env->sdr1 = value; | |
| 76a66253 | 1010 | tlb_flush(env, 1); |
| 3fc6c082 FB |
1011 | } |
| 1012 | } | |
| 1013 | ||
| 1014 | target_ulong do_load_sr (CPUPPCState *env, int srnum) | |
| 1015 | { | |
| 1016 | return env->sr[srnum]; | |
| 1017 | } | |
| 1018 | ||
| 1019 | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value) | |
| 1020 | { | |
| 1021 | #if defined (DEBUG_MMU) | |
| 1022 | if (loglevel != 0) { | |
| 1b9eb036 JM |
1023 | fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n", |
| 1024 | __func__, srnum, value, env->sr[srnum]); | |
| 3fc6c082 FB |
1025 | } |
| 1026 | #endif | |
| 1027 | if (env->sr[srnum] != value) { | |
| 1028 | env->sr[srnum] = value; | |
| 1029 | #if !defined(FLUSH_ALL_TLBS) && 0 | |
| 1030 | { | |
| 1031 | target_ulong page, end; | |
| 1032 | /* Invalidate 256 MB of virtual memory */ | |
| 1033 | page = (16 << 20) * srnum; | |
| 1034 | end = page + (16 << 20); | |
| 1035 | for (; page != end; page += TARGET_PAGE_SIZE) | |
| 1036 | tlb_flush_page(env, page); | |
| 1037 | } | |
| 1038 | #else | |
| 76a66253 | 1039 | tlb_flush(env, 1); |
| 3fc6c082 FB |
1040 | #endif |
| 1041 | } | |
| 1042 | } | |
| 76a66253 | 1043 | #endif /* !defined (CONFIG_USER_ONLY) */ |
| 3fc6c082 | 1044 | |
| 76a66253 | 1045 | uint32_t ppc_load_xer (CPUPPCState *env) |
| 79aceca5 FB |
1046 | { |
| 1047 | return (xer_so << XER_SO) | | |
| 1048 | (xer_ov << XER_OV) | | |
| 1049 | (xer_ca << XER_CA) | | |
| 3fc6c082 FB |
1050 | (xer_bc << XER_BC) | |
| 1051 | (xer_cmp << XER_CMP); | |
| 79aceca5 FB |
1052 | } |
| 1053 | ||
| 76a66253 | 1054 | void ppc_store_xer (CPUPPCState *env, uint32_t value) |
| 79aceca5 FB |
1055 | { |
| 1056 | xer_so = (value >> XER_SO) & 0x01; | |
| 1057 | xer_ov = (value >> XER_OV) & 0x01; | |
| 1058 | xer_ca = (value >> XER_CA) & 0x01; | |
| 3fc6c082 | 1059 | xer_cmp = (value >> XER_CMP) & 0xFF; |
| d9bce9d9 | 1060 | xer_bc = (value >> XER_BC) & 0x7F; |
| 79aceca5 FB |
1061 | } |
| 1062 | ||
| 76a66253 JM |
1063 | /* Swap temporary saved registers with GPRs */ |
| 1064 | static inline void swap_gpr_tgpr (CPUPPCState *env) | |
| 79aceca5 | 1065 | { |
| 76a66253 JM |
1066 | ppc_gpr_t tmp; |
| 1067 | ||
| 1068 | tmp = env->gpr[0]; | |
| 1069 | env->gpr[0] = env->tgpr[0]; | |
| 1070 | env->tgpr[0] = tmp; | |
| 1071 | tmp = env->gpr[1]; | |
| 1072 | env->gpr[1] = env->tgpr[1]; | |
| 1073 | env->tgpr[1] = tmp; | |
| 1074 | tmp = env->gpr[2]; | |
| 1075 | env->gpr[2] = env->tgpr[2]; | |
| 1076 | env->tgpr[2] = tmp; | |
| 1077 | tmp = env->gpr[3]; | |
| 1078 | env->gpr[3] = env->tgpr[3]; | |
| 1079 | env->tgpr[3] = tmp; | |
| 79aceca5 FB |
1080 | } |
| 1081 | ||
| 76a66253 JM |
1082 | /* GDBstub can read and write MSR... */ |
| 1083 | target_ulong do_load_msr (CPUPPCState *env) | |
| 79aceca5 | 1084 | { |
| 76a66253 JM |
1085 | return |
| 1086 | #if defined (TARGET_PPC64) | |
| d9bce9d9 JM |
1087 | ((target_ulong)msr_sf << MSR_SF) | |
| 1088 | ((target_ulong)msr_isf << MSR_ISF) | | |
| 1089 | ((target_ulong)msr_hv << MSR_HV) | | |
| 76a66253 | 1090 | #endif |
| d9bce9d9 JM |
1091 | ((target_ulong)msr_ucle << MSR_UCLE) | |
| 1092 | ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */ | |
| 1093 | ((target_ulong)msr_ap << MSR_AP) | | |
| 1094 | ((target_ulong)msr_sa << MSR_SA) | | |
| 1095 | ((target_ulong)msr_key << MSR_KEY) | | |
| 1096 | ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */ | |
| 1097 | ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */ | |
| 1098 | ((target_ulong)msr_ile << MSR_ILE) | | |
| 1099 | ((target_ulong)msr_ee << MSR_EE) | | |
| 1100 | ((target_ulong)msr_pr << MSR_PR) | | |
| 1101 | ((target_ulong)msr_fp << MSR_FP) | | |
| 1102 | ((target_ulong)msr_me << MSR_ME) | | |
| 1103 | ((target_ulong)msr_fe0 << MSR_FE0) | | |
| 1104 | ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */ | |
| 1105 | ((target_ulong)msr_be << MSR_BE) | /* BE / DE */ | |
| 1106 | ((target_ulong)msr_fe1 << MSR_FE1) | | |
| 1107 | ((target_ulong)msr_al << MSR_AL) | | |
| 1108 | ((target_ulong)msr_ip << MSR_IP) | | |
| 1109 | ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */ | |
| 1110 | ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */ | |
| 1111 | ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */ | |
| 1112 | ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */ | |
| 1113 | ((target_ulong)msr_ri << MSR_RI) | | |
| 1114 | ((target_ulong)msr_le << MSR_LE); | |
| 3fc6c082 FB |
1115 | } |
| 1116 | ||
| 1117 | void do_store_msr (CPUPPCState *env, target_ulong value) | |
| 313adae9 | 1118 | { |
| 50443c98 FB |
1119 | int enter_pm; |
| 1120 | ||
| 3fc6c082 FB |
1121 | value &= env->msr_mask; |
| 1122 | if (((value >> MSR_IR) & 1) != msr_ir || | |
| 1123 | ((value >> MSR_DR) & 1) != msr_dr) { | |
| 76a66253 | 1124 | /* Flush all tlb when changing translation mode */ |
| d094807b | 1125 | tlb_flush(env, 1); |
| 3fc6c082 | 1126 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| a541f297 | 1127 | } |
| 3fc6c082 FB |
1128 | #if 0 |
| 1129 | if (loglevel != 0) { | |
| 1130 | fprintf(logfile, "%s: T0 %08lx\n", __func__, value); | |
| 1131 | } | |
| 1132 | #endif | |
| 76a66253 JM |
1133 | switch (PPC_EXCP(env)) { |
| 1134 | case PPC_FLAGS_EXCP_602: | |
| 1135 | case PPC_FLAGS_EXCP_603: | |
| 1136 | if (((value >> MSR_TGPR) & 1) != msr_tgpr) { | |
| 1137 | /* Swap temporary saved registers with GPRs */ | |
| 1138 | swap_gpr_tgpr(env); | |
| 1139 | } | |
| 1140 | break; | |
| 1141 | default: | |
| 1142 | break; | |
| 1143 | } | |
| 1144 | #if defined (TARGET_PPC64) | |
| 1145 | msr_sf = (value >> MSR_SF) & 1; | |
| 1146 | msr_isf = (value >> MSR_ISF) & 1; | |
| 1147 | msr_hv = (value >> MSR_HV) & 1; | |
| 1148 | #endif | |
| 1149 | msr_ucle = (value >> MSR_UCLE) & 1; | |
| 1150 | msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */ | |
| 1151 | msr_ap = (value >> MSR_AP) & 1; | |
| 1152 | msr_sa = (value >> MSR_SA) & 1; | |
| 1153 | msr_key = (value >> MSR_KEY) & 1; | |
| 1154 | msr_pow = (value >> MSR_POW) & 1; /* POW / WE */ | |
| 1155 | msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */ | |
| 1156 | msr_ile = (value >> MSR_ILE) & 1; | |
| 1157 | msr_ee = (value >> MSR_EE) & 1; | |
| 1158 | msr_pr = (value >> MSR_PR) & 1; | |
| 1159 | msr_fp = (value >> MSR_FP) & 1; | |
| 1160 | msr_me = (value >> MSR_ME) & 1; | |
| 1161 | msr_fe0 = (value >> MSR_FE0) & 1; | |
| 1162 | msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */ | |
| 1163 | msr_be = (value >> MSR_BE) & 1; /* BE / DE */ | |
| 1164 | msr_fe1 = (value >> MSR_FE1) & 1; | |
| 1165 | msr_al = (value >> MSR_AL) & 1; | |
| 1166 | msr_ip = (value >> MSR_IP) & 1; | |
| 1167 | msr_ir = (value >> MSR_IR) & 1; /* IR / IS */ | |
| 1168 | msr_dr = (value >> MSR_DR) & 1; /* DR / DS */ | |
| 1169 | msr_pe = (value >> MSR_PE) & 1; /* PE / EP */ | |
| 1170 | msr_px = (value >> MSR_PX) & 1; /* PX / PMM */ | |
| 1171 | msr_ri = (value >> MSR_RI) & 1; | |
| 1172 | msr_le = (value >> MSR_LE) & 1; | |
| 3fc6c082 | 1173 | do_compute_hflags(env); |
| 50443c98 FB |
1174 | |
| 1175 | enter_pm = 0; | |
| 1176 | switch (PPC_EXCP(env)) { | |
| d9bce9d9 JM |
1177 | case PPC_FLAGS_EXCP_603: |
| 1178 | /* Don't handle SLEEP mode: we should disable all clocks... | |
| 1179 | * No dynamic power-management. | |
| 1180 | */ | |
| 1181 | if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0) | |
| 1182 | enter_pm = 1; | |
| 1183 | break; | |
| 1184 | case PPC_FLAGS_EXCP_604: | |
| 1185 | if (msr_pow == 1) | |
| 1186 | enter_pm = 1; | |
| 1187 | break; | |
| 50443c98 | 1188 | case PPC_FLAGS_EXCP_7x0: |
| 76a66253 | 1189 | if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0) |
| 50443c98 FB |
1190 | enter_pm = 1; |
| 1191 | break; | |
| 1192 | default: | |
| 1193 | break; | |
| 1194 | } | |
| 1195 | if (enter_pm) { | |
| e80e1cc4 | 1196 | /* power save: exit cpu loop */ |
| 50443c98 | 1197 | env->halted = 1; |
| e80e1cc4 FB |
1198 | env->exception_index = EXCP_HLT; |
| 1199 | cpu_loop_exit(); | |
| 1200 | } | |
| 3fc6c082 FB |
1201 | } |
| 1202 | ||
| d9bce9d9 | 1203 | #if defined(TARGET_PPC64) |
| 426613db | 1204 | void ppc_store_msr_32 (CPUPPCState *env, uint32_t value) |
| d9bce9d9 | 1205 | { |
| 426613db JM |
1206 | do_store_msr(env, |
| 1207 | (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF)); | |
| d9bce9d9 JM |
1208 | } |
| 1209 | #endif | |
| 1210 | ||
| 76a66253 | 1211 | void do_compute_hflags (CPUPPCState *env) |
| 3fc6c082 | 1212 | { |
| 76a66253 JM |
1213 | /* Compute current hflags */ |
| 1214 | env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) | | |
| 1215 | (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) | | |
| d9bce9d9 | 1216 | (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | |
| 76a66253 JM |
1217 | (msr_se << MSR_SE) | (msr_be << MSR_BE); |
| 1218 | #if defined (TARGET_PPC64) | |
| d9bce9d9 | 1219 | env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32)); |
| 4b3686fa | 1220 | #endif |
| 3fc6c082 FB |
1221 | } |
| 1222 | ||
| 1223 | /*****************************************************************************/ | |
| 1224 | /* Exception processing */ | |
| 18fba28c | 1225 | #if defined (CONFIG_USER_ONLY) |
| 9a64fbe4 | 1226 | void do_interrupt (CPUState *env) |
| 79aceca5 | 1227 | { |
| 18fba28c FB |
1228 | env->exception_index = -1; |
| 1229 | } | |
| 47103572 JM |
1230 | |
| 1231 | int ppc_hw_interrupt (CPUState *env) | |
| 1232 | { | |
| 1233 | env->exception_index = -1; | |
| 1234 | ||
| 1235 | return 0; | |
| 1236 | } | |
| 76a66253 | 1237 | #else /* defined (CONFIG_USER_ONLY) */ |
| d094807b FB |
1238 | static void dump_syscall(CPUState *env) |
| 1239 | { | |
| d9bce9d9 | 1240 | fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX |
| 1b9eb036 | 1241 | " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n", |
| d094807b FB |
1242 | env->gpr[0], env->gpr[3], env->gpr[4], |
| 1243 | env->gpr[5], env->gpr[6], env->nip); | |
| 1244 | } | |
| 1245 | ||
| 18fba28c FB |
1246 | void do_interrupt (CPUState *env) |
| 1247 | { | |
| 76a66253 | 1248 | target_ulong msr, *srr_0, *srr_1; |
| 18fba28c | 1249 | int excp; |
| 79aceca5 | 1250 | |
| 18fba28c | 1251 | excp = env->exception_index; |
| 3fc6c082 | 1252 | msr = do_load_msr(env); |
| 2be0071f FB |
1253 | /* The default is to use SRR0 & SRR1 to save the exception context */ |
| 1254 | srr_0 = &env->spr[SPR_SRR0]; | |
| 1255 | srr_1 = &env->spr[SPR_SRR1]; | |
| 9a64fbe4 | 1256 | #if defined (DEBUG_EXCEPTIONS) |
| 2be0071f FB |
1257 | if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) { |
| 1258 | if (loglevel != 0) { | |
| 1b9eb036 JM |
1259 | fprintf(logfile, |
| 1260 | "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", | |
| 1261 | env->nip, excp, env->error_code); | |
| 76a66253 | 1262 | cpu_dump_state(env, logfile, fprintf, 0); |
| b769d8fe | 1263 | } |
| 79aceca5 | 1264 | } |
| 9a64fbe4 | 1265 | #endif |
| b769d8fe | 1266 | if (loglevel & CPU_LOG_INT) { |
| 1b9eb036 JM |
1267 | fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n", |
| 1268 | env->nip, excp, env->error_code); | |
| b769d8fe | 1269 | } |
| 2be0071f | 1270 | msr_pow = 0; |
| 9a64fbe4 FB |
1271 | /* Generate informations in save/restore registers */ |
| 1272 | switch (excp) { | |
| 76a66253 | 1273 | /* Generic PowerPC exceptions */ |
| 2be0071f FB |
1274 | case EXCP_RESET: /* 0x0100 */ |
| 1275 | if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) { | |
| 1276 | if (msr_ip) | |
| 1277 | excp += 0xFFC00; | |
| 1278 | excp |= 0xFFC00000; | |
| 1279 | } else { | |
| 1280 | srr_0 = &env->spr[SPR_40x_SRR2]; | |
| 1281 | srr_1 = &env->spr[SPR_40x_SRR3]; | |
| 1282 | } | |
| 9a64fbe4 | 1283 | goto store_next; |
| 2be0071f | 1284 | case EXCP_MACHINE_CHECK: /* 0x0200 */ |
| 9a64fbe4 | 1285 | if (msr_me == 0) { |
| 4b3686fa | 1286 | cpu_abort(env, "Machine check exception while not allowed\n"); |
| 79aceca5 | 1287 | } |
| 76a66253 | 1288 | if (unlikely(PPC_EXCP(env) == PPC_FLAGS_EXCP_40x)) { |
| 2be0071f FB |
1289 | srr_0 = &env->spr[SPR_40x_SRR2]; |
| 1290 | srr_1 = &env->spr[SPR_40x_SRR3]; | |
| 1291 | } | |
| 9a64fbe4 FB |
1292 | msr_me = 0; |
| 1293 | break; | |
| 2be0071f | 1294 | case EXCP_DSI: /* 0x0300 */ |
| 9a64fbe4 FB |
1295 | /* Store exception cause */ |
| 1296 | /* data location address has been stored | |
| 1297 | * when the fault has been detected | |
| 2be0071f | 1298 | */ |
| 76a66253 | 1299 | msr &= ~0xFFFF0000; |
| a541f297 | 1300 | #if defined (DEBUG_EXCEPTIONS) |
| 76a66253 | 1301 | if (loglevel) { |
| 1b9eb036 JM |
1302 | fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX |
| 1303 | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); | |
| 76a66253 | 1304 | } else { |
| 1b9eb036 | 1305 | printf("DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX "\n", |
| 76a66253 JM |
1306 | env->spr[SPR_DSISR], env->spr[SPR_DAR]); |
| 1307 | } | |
| a541f297 FB |
1308 | #endif |
| 1309 | goto store_next; | |
| 2be0071f | 1310 | case EXCP_ISI: /* 0x0400 */ |
| 9a64fbe4 | 1311 | /* Store exception cause */ |
| 76a66253 | 1312 | msr &= ~0xFFFF0000; |
| 2be0071f | 1313 | msr |= env->error_code; |
| a541f297 | 1314 | #if defined (DEBUG_EXCEPTIONS) |
| 76a66253 | 1315 | if (loglevel != 0) { |
| 1b9eb036 JM |
1316 | fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX |
| 1317 | "\n", msr, env->nip); | |
| 76a66253 | 1318 | } |
| a541f297 | 1319 | #endif |
| 9a64fbe4 | 1320 | goto store_next; |
| 2be0071f | 1321 | case EXCP_EXTERNAL: /* 0x0500 */ |
| 9a64fbe4 FB |
1322 | if (msr_ee == 0) { |
| 1323 | #if defined (DEBUG_EXCEPTIONS) | |
| 1324 | if (loglevel > 0) { | |
| 1325 | fprintf(logfile, "Skipping hardware interrupt\n"); | |
| 2be0071f | 1326 | } |
| 9a64fbe4 | 1327 | #endif |
| a541f297 | 1328 | /* Requeue it */ |
| 2be0071f | 1329 | env->interrupt_request |= CPU_INTERRUPT_HARD; |
| 9a64fbe4 | 1330 | return; |
| 2be0071f | 1331 | } |
| 9a64fbe4 | 1332 | goto store_next; |
| 2be0071f | 1333 | case EXCP_ALIGN: /* 0x0600 */ |
| 76a66253 | 1334 | if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) { |
| 2be0071f FB |
1335 | /* Store exception cause */ |
| 1336 | /* Get rS/rD and rA from faulting opcode */ | |
| 1337 | env->spr[SPR_DSISR] |= | |
| 1338 | (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; | |
| 1339 | /* data location address has been stored | |
| 1340 | * when the fault has been detected | |
| 1341 | */ | |
| 1342 | } else { | |
| 1343 | /* IO error exception on PowerPC 601 */ | |
| 1344 | /* XXX: TODO */ | |
| 1345 | cpu_abort(env, | |
| 1346 | "601 IO error exception is not implemented yet !\n"); | |
| 1347 | } | |
| 9a64fbe4 | 1348 | goto store_current; |
| 2be0071f | 1349 | case EXCP_PROGRAM: /* 0x0700 */ |
| 9a64fbe4 FB |
1350 | msr &= ~0xFFFF0000; |
| 1351 | switch (env->error_code & ~0xF) { | |
| 1352 | case EXCP_FP: | |
| 1353 | if (msr_fe0 == 0 && msr_fe1 == 0) { | |
| 1354 | #if defined (DEBUG_EXCEPTIONS) | |
| 1355 | printf("Ignore floating point exception\n"); | |
| 1356 | #endif | |
| 1357 | return; | |
| 76a66253 | 1358 | } |
| 9a64fbe4 FB |
1359 | msr |= 0x00100000; |
| 1360 | /* Set FX */ | |
| 1361 | env->fpscr[7] |= 0x8; | |
| 1362 | /* Finally, update FEX */ | |
| 1363 | if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) & | |
| 1364 | ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3))) | |
| 1365 | env->fpscr[7] |= 0x4; | |
| 76a66253 | 1366 | break; |
| 9a64fbe4 | 1367 | case EXCP_INVAL: |
| 1b9eb036 | 1368 | // printf("Invalid instruction at 0x" ADDRX "\n", env->nip); |
| 9a64fbe4 | 1369 | msr |= 0x00080000; |
| 76a66253 | 1370 | break; |
| 9a64fbe4 FB |
1371 | case EXCP_PRIV: |
| 1372 | msr |= 0x00040000; | |
| 76a66253 | 1373 | break; |
| 9a64fbe4 FB |
1374 | case EXCP_TRAP: |
| 1375 | msr |= 0x00020000; | |
| 1376 | break; | |
| 1377 | default: | |
| 1378 | /* Should never occur */ | |
| 76a66253 JM |
1379 | break; |
| 1380 | } | |
| 9a64fbe4 FB |
1381 | msr |= 0x00010000; |
| 1382 | goto store_current; | |
| 2be0071f | 1383 | case EXCP_NO_FP: /* 0x0800 */ |
| 4ecc3190 | 1384 | msr &= ~0xFFFF0000; |
| 9a64fbe4 FB |
1385 | goto store_current; |
| 1386 | case EXCP_DECR: | |
| 1387 | if (msr_ee == 0) { | |
| 2be0071f | 1388 | #if 1 |
| 9a64fbe4 | 1389 | /* Requeue it */ |
| 2be0071f FB |
1390 | env->interrupt_request |= CPU_INTERRUPT_TIMER; |
| 1391 | #endif | |
| 9a64fbe4 FB |
1392 | return; |
| 1393 | } | |
| 1394 | goto store_next; | |
| 2be0071f | 1395 | case EXCP_SYSCALL: /* 0x0C00 */ |
| d094807b FB |
1396 | /* NOTE: this is a temporary hack to support graphics OSI |
| 1397 | calls from the MOL driver */ | |
| 1398 | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && | |
| 1399 | env->osi_call) { | |
| 1400 | if (env->osi_call(env) != 0) | |
| 1401 | return; | |
| 1402 | } | |
| b769d8fe | 1403 | if (loglevel & CPU_LOG_INT) { |
| d094807b | 1404 | dump_syscall(env); |
| b769d8fe | 1405 | } |
| 9a64fbe4 | 1406 | goto store_next; |
| 2be0071f | 1407 | case EXCP_TRACE: /* 0x0D00 */ |
| 2be0071f FB |
1408 | goto store_next; |
| 1409 | case EXCP_PERF: /* 0x0F00 */ | |
| 1410 | /* XXX: TODO */ | |
| 1411 | cpu_abort(env, | |
| 1412 | "Performance counter exception is not implemented yet !\n"); | |
| 1413 | goto store_next; | |
| 1414 | /* 32 bits PowerPC specific exceptions */ | |
| 1415 | case EXCP_FP_ASSIST: /* 0x0E00 */ | |
| 1416 | /* XXX: TODO */ | |
| 1417 | cpu_abort(env, "Floating point assist exception " | |
| 1418 | "is not implemented yet !\n"); | |
| 1419 | goto store_next; | |
| 76a66253 | 1420 | /* 64 bits PowerPC exceptions */ |
| 2be0071f FB |
1421 | case EXCP_DSEG: /* 0x0380 */ |
| 1422 | /* XXX: TODO */ | |
| 1423 | cpu_abort(env, "Data segment exception is not implemented yet !\n"); | |
| 9a64fbe4 | 1424 | goto store_next; |
| 2be0071f FB |
1425 | case EXCP_ISEG: /* 0x0480 */ |
| 1426 | /* XXX: TODO */ | |
| 1427 | cpu_abort(env, | |
| 1428 | "Instruction segment exception is not implemented yet !\n"); | |
| 9a64fbe4 | 1429 | goto store_next; |
| 2be0071f FB |
1430 | case EXCP_HDECR: /* 0x0980 */ |
| 1431 | if (msr_ee == 0) { | |
| 1432 | #if 1 | |
| 1433 | /* Requeue it */ | |
| 1434 | env->interrupt_request |= CPU_INTERRUPT_TIMER; | |
| 1435 | #endif | |
| 76a66253 | 1436 | return; |
| 2be0071f | 1437 | } |
| 76a66253 JM |
1438 | /* XXX: TODO */ |
| 1439 | cpu_abort(env, "Hypervisor decrementer exception is not implemented " | |
| 1440 | "yet !\n"); | |
| 2be0071f FB |
1441 | goto store_next; |
| 1442 | /* Implementation specific exceptions */ | |
| 1443 | case 0x0A00: | |
| 76a66253 JM |
1444 | if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 || |
| 1445 | env->spr[SPR_PVR] == CPU_PPC_G2LE)) { | |
| 2be0071f FB |
1446 | /* Critical interrupt on G2 */ |
| 1447 | /* XXX: TODO */ | |
| 1448 | cpu_abort(env, "G2 critical interrupt is not implemented yet !\n"); | |
| 1449 | goto store_next; | |
| 1450 | } else { | |
| 1451 | cpu_abort(env, "Invalid exception 0x0A00 !\n"); | |
| 1452 | } | |
| 9a64fbe4 | 1453 | return; |
| 2be0071f FB |
1454 | case 0x0F20: |
| 1455 | switch (PPC_EXCP(env)) { | |
| 1456 | case PPC_FLAGS_EXCP_40x: | |
| 1457 | /* APU unavailable on 405 */ | |
| 1458 | /* XXX: TODO */ | |
| 1459 | cpu_abort(env, | |
| 1460 | "APU unavailable exception is not implemented yet !\n"); | |
| 1461 | goto store_next; | |
| 1462 | case PPC_FLAGS_EXCP_74xx: | |
| 1463 | /* Altivec unavailable */ | |
| 1464 | /* XXX: TODO */ | |
| 1465 | cpu_abort(env, "Altivec unavailable exception " | |
| 1466 | "is not implemented yet !\n"); | |
| 1467 | goto store_next; | |
| 1468 | default: | |
| 1469 | cpu_abort(env, "Invalid exception 0x0F20 !\n"); | |
| 1470 | break; | |
| 1471 | } | |
| 1472 | return; | |
| 1473 | case 0x1000: | |
| 1474 | switch (PPC_EXCP(env)) { | |
| 1475 | case PPC_FLAGS_EXCP_40x: | |
| 1476 | /* PIT on 4xx */ | |
| 1477 | /* XXX: TODO */ | |
| 1478 | cpu_abort(env, "40x PIT exception is not implemented yet !\n"); | |
| 1479 | goto store_next; | |
| 1480 | case PPC_FLAGS_EXCP_602: | |
| 1481 | case PPC_FLAGS_EXCP_603: | |
| 1482 | /* ITLBMISS on 602/603 */ | |
| 2be0071f | 1483 | goto store_gprs; |
| 76a66253 JM |
1484 | case PPC_FLAGS_EXCP_7x5: |
| 1485 | /* ITLBMISS on 745/755 */ | |
| 1486 | goto tlb_miss; | |
| 2be0071f FB |
1487 | default: |
| 1488 | cpu_abort(env, "Invalid exception 0x1000 !\n"); | |
| 1489 | break; | |
| 1490 | } | |
| 1491 | return; | |
| 1492 | case 0x1010: | |
| 1493 | switch (PPC_EXCP(env)) { | |
| 1494 | case PPC_FLAGS_EXCP_40x: | |
| 1495 | /* FIT on 4xx */ | |
| 2be0071f | 1496 | /* XXX: TODO */ |
| 76a66253 | 1497 | cpu_abort(env, "40x FIT exception is not implemented yet !\n"); |
| 2be0071f FB |
1498 | goto store_next; |
| 1499 | default: | |
| 1500 | cpu_abort(env, "Invalid exception 0x1010 !\n"); | |
| 1501 | break; | |
| 1502 | } | |
| 1503 | return; | |
| 1504 | case 0x1020: | |
| 1505 | switch (PPC_EXCP(env)) { | |
| 1506 | case PPC_FLAGS_EXCP_40x: | |
| 1507 | /* Watchdog on 4xx */ | |
| 1508 | /* XXX: TODO */ | |
| 1509 | cpu_abort(env, | |
| 1510 | "40x watchdog exception is not implemented yet !\n"); | |
| 1511 | goto store_next; | |
| 1512 | default: | |
| 1513 | cpu_abort(env, "Invalid exception 0x1020 !\n"); | |
| 1514 | break; | |
| 1515 | } | |
| 1516 | return; | |
| 1517 | case 0x1100: | |
| 1518 | switch (PPC_EXCP(env)) { | |
| 1519 | case PPC_FLAGS_EXCP_40x: | |
| 1520 | /* DTLBMISS on 4xx */ | |
| 1521 | /* XXX: TODO */ | |
| 1522 | cpu_abort(env, | |
| 1523 | "40x DTLBMISS exception is not implemented yet !\n"); | |
| 1524 | goto store_next; | |
| 1525 | case PPC_FLAGS_EXCP_602: | |
| 1526 | case PPC_FLAGS_EXCP_603: | |
| 1527 | /* DLTLBMISS on 602/603 */ | |
| 2be0071f | 1528 | goto store_gprs; |
| 76a66253 JM |
1529 | case PPC_FLAGS_EXCP_7x5: |
| 1530 | /* DLTLBMISS on 745/755 */ | |
| 1531 | goto tlb_miss; | |
| 2be0071f FB |
1532 | default: |
| 1533 | cpu_abort(env, "Invalid exception 0x1100 !\n"); | |
| 1534 | break; | |
| 1535 | } | |
| 1536 | return; | |
| 1537 | case 0x1200: | |
| 1538 | switch (PPC_EXCP(env)) { | |
| 1539 | case PPC_FLAGS_EXCP_40x: | |
| 1540 | /* ITLBMISS on 4xx */ | |
| 1541 | /* XXX: TODO */ | |
| 1542 | cpu_abort(env, | |
| 1543 | "40x ITLBMISS exception is not implemented yet !\n"); | |
| 1544 | goto store_next; | |
| 1545 | case PPC_FLAGS_EXCP_602: | |
| 1546 | case PPC_FLAGS_EXCP_603: | |
| 1547 | /* DSTLBMISS on 602/603 */ | |
| 2be0071f | 1548 | store_gprs: |
| 76a66253 JM |
1549 | /* Swap temporary saved registers with GPRs */ |
| 1550 | swap_gpr_tgpr(env); | |
| 1551 | msr_tgpr = 1; | |
| 2be0071f FB |
1552 | #if defined (DEBUG_SOFTWARE_TLB) |
| 1553 | if (loglevel != 0) { | |
| 76a66253 JM |
1554 | const unsigned char *es; |
| 1555 | target_ulong *miss, *cmp; | |
| 1556 | int en; | |
| 1557 | if (excp == 0x1000) { | |
| 1558 | es = "I"; | |
| 1559 | en = 'I'; | |
| 1560 | miss = &env->spr[SPR_IMISS]; | |
| 1561 | cmp = &env->spr[SPR_ICMP]; | |
| 1562 | } else { | |
| 1563 | if (excp == 0x1100) | |
| 1564 | es = "DL"; | |
| 1565 | else | |
| 1566 | es = "DS"; | |
| 1567 | en = 'D'; | |
| 1568 | miss = &env->spr[SPR_DMISS]; | |
| 1569 | cmp = &env->spr[SPR_DCMP]; | |
| 1570 | } | |
| 1b9eb036 JM |
1571 | fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX |
| 1572 | " H1 " ADDRX " H2 " ADDRX " " ADDRX "\n", | |
| 1573 | es, en, *miss, en, *cmp, | |
| 76a66253 | 1574 | env->spr[SPR_HASH1], env->spr[SPR_HASH2], |
| 2be0071f FB |
1575 | env->error_code); |
| 1576 | } | |
| 9a64fbe4 | 1577 | #endif |
| 76a66253 JM |
1578 | goto tlb_miss; |
| 1579 | case PPC_FLAGS_EXCP_7x5: | |
| 1580 | /* DSTLBMISS on 745/755 */ | |
| 1581 | tlb_miss: | |
| 1582 | msr &= ~0xF83F0000; | |
| 2be0071f FB |
1583 | msr |= env->crf[0] << 28; |
| 1584 | msr |= env->error_code; /* key, D/I, S/L bits */ | |
| 1585 | /* Set way using a LRU mechanism */ | |
| 76a66253 | 1586 | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
| 2be0071f FB |
1587 | goto store_next; |
| 1588 | default: | |
| 1589 | cpu_abort(env, "Invalid exception 0x1200 !\n"); | |
| 1590 | break; | |
| 1591 | } | |
| 1592 | return; | |
| 1593 | case 0x1300: | |
| 1594 | switch (PPC_EXCP(env)) { | |
| 1595 | case PPC_FLAGS_EXCP_601: | |
| 1596 | case PPC_FLAGS_EXCP_602: | |
| 1597 | case PPC_FLAGS_EXCP_603: | |
| 1598 | case PPC_FLAGS_EXCP_604: | |
| 1599 | case PPC_FLAGS_EXCP_7x0: | |
| 1600 | case PPC_FLAGS_EXCP_7x5: | |
| 1601 | /* IABR on 6xx/7xx */ | |
| 1602 | /* XXX: TODO */ | |
| 1603 | cpu_abort(env, "IABR exception is not implemented yet !\n"); | |
| 1604 | goto store_next; | |
| 1605 | default: | |
| 1606 | cpu_abort(env, "Invalid exception 0x1300 !\n"); | |
| 1607 | break; | |
| 1608 | } | |
| 1609 | return; | |
| 1610 | case 0x1400: | |
| 1611 | switch (PPC_EXCP(env)) { | |
| 1612 | case PPC_FLAGS_EXCP_601: | |
| 1613 | case PPC_FLAGS_EXCP_602: | |
| 1614 | case PPC_FLAGS_EXCP_603: | |
| 1615 | case PPC_FLAGS_EXCP_604: | |
| 1616 | case PPC_FLAGS_EXCP_7x0: | |
| 1617 | case PPC_FLAGS_EXCP_7x5: | |
| 1618 | /* SMI on 6xx/7xx */ | |
| 1619 | /* XXX: TODO */ | |
| 1620 | cpu_abort(env, "SMI exception is not implemented yet !\n"); | |
| 1621 | goto store_next; | |
| 1622 | default: | |
| 1623 | cpu_abort(env, "Invalid exception 0x1400 !\n"); | |
| 1624 | break; | |
| 1625 | } | |
| 1626 | return; | |
| 1627 | case 0x1500: | |
| 1628 | switch (PPC_EXCP(env)) { | |
| 1629 | case PPC_FLAGS_EXCP_602: | |
| 1630 | /* Watchdog on 602 */ | |
| 76a66253 | 1631 | /* XXX: TODO */ |
| 2be0071f FB |
1632 | cpu_abort(env, |
| 1633 | "602 watchdog exception is not implemented yet !\n"); | |
| 1634 | goto store_next; | |
| 1635 | case PPC_FLAGS_EXCP_970: | |
| 1636 | /* Soft patch exception on 970 */ | |
| 1637 | /* XXX: TODO */ | |
| 1638 | cpu_abort(env, | |
| 1639 | "970 soft-patch exception is not implemented yet !\n"); | |
| 1640 | goto store_next; | |
| 1641 | case PPC_FLAGS_EXCP_74xx: | |
| 1642 | /* VPU assist on 74xx */ | |
| 1643 | /* XXX: TODO */ | |
| 1644 | cpu_abort(env, "VPU assist exception is not implemented yet !\n"); | |
| 1645 | goto store_next; | |
| 1646 | default: | |
| 1647 | cpu_abort(env, "Invalid exception 0x1500 !\n"); | |
| 1648 | break; | |
| 1649 | } | |
| 1650 | return; | |
| 1651 | case 0x1600: | |
| 1652 | switch (PPC_EXCP(env)) { | |
| 1653 | case PPC_FLAGS_EXCP_602: | |
| 1654 | /* Emulation trap on 602 */ | |
| 1655 | /* XXX: TODO */ | |
| 1656 | cpu_abort(env, "602 emulation trap exception " | |
| 1657 | "is not implemented yet !\n"); | |
| 1658 | goto store_next; | |
| 1659 | case PPC_FLAGS_EXCP_970: | |
| 1660 | /* Maintenance exception on 970 */ | |
| 1661 | /* XXX: TODO */ | |
| 1662 | cpu_abort(env, | |
| 1663 | "970 maintenance exception is not implemented yet !\n"); | |
| 1664 | goto store_next; | |
| 1665 | default: | |
| 1666 | cpu_abort(env, "Invalid exception 0x1600 !\n"); | |
| 1667 | break; | |
| 1668 | } | |
| 1669 | return; | |
| 1670 | case 0x1700: | |
| 1671 | switch (PPC_EXCP(env)) { | |
| 1672 | case PPC_FLAGS_EXCP_7x0: | |
| 1673 | case PPC_FLAGS_EXCP_7x5: | |
| 1674 | /* Thermal management interrupt on G3 */ | |
| 1675 | /* XXX: TODO */ | |
| 1676 | cpu_abort(env, "G3 thermal management exception " | |
| 1677 | "is not implemented yet !\n"); | |
| 1678 | goto store_next; | |
| 1679 | case PPC_FLAGS_EXCP_970: | |
| 1680 | /* VPU assist on 970 */ | |
| 1681 | /* XXX: TODO */ | |
| 1682 | cpu_abort(env, | |
| 1683 | "970 VPU assist exception is not implemented yet !\n"); | |
| 1684 | goto store_next; | |
| 1685 | default: | |
| 1686 | cpu_abort(env, "Invalid exception 0x1700 !\n"); | |
| 1687 | break; | |
| 1688 | } | |
| 1689 | return; | |
| 1690 | case 0x1800: | |
| 1691 | switch (PPC_EXCP(env)) { | |
| 1692 | case PPC_FLAGS_EXCP_970: | |
| 1693 | /* Thermal exception on 970 */ | |
| 1694 | /* XXX: TODO */ | |
| 1695 | cpu_abort(env, "970 thermal management exception " | |
| 1696 | "is not implemented yet !\n"); | |
| 1697 | goto store_next; | |
| 1698 | default: | |
| 1699 | cpu_abort(env, "Invalid exception 0x1800 !\n"); | |
| 1700 | break; | |
| 1701 | } | |
| 1702 | return; | |
| 1703 | case 0x2000: | |
| 1704 | switch (PPC_EXCP(env)) { | |
| 1705 | case PPC_FLAGS_EXCP_40x: | |
| 1706 | /* DEBUG on 4xx */ | |
| 1707 | /* XXX: TODO */ | |
| 1708 | cpu_abort(env, "40x debug exception is not implemented yet !\n"); | |
| 1709 | goto store_next; | |
| 1710 | case PPC_FLAGS_EXCP_601: | |
| 1711 | /* Run mode exception on 601 */ | |
| 1712 | /* XXX: TODO */ | |
| 1713 | cpu_abort(env, | |
| 1714 | "601 run mode exception is not implemented yet !\n"); | |
| 1715 | goto store_next; | |
| 1716 | default: | |
| 1717 | cpu_abort(env, "Invalid exception 0x1800 !\n"); | |
| 1718 | break; | |
| 1719 | } | |
| 1720 | return; | |
| 1721 | /* Other exceptions */ | |
| 1722 | /* Qemu internal exceptions: | |
| 1723 | * we should never come here with those values: abort execution | |
| 1724 | */ | |
| 1725 | default: | |
| 1726 | cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp); | |
| 9a64fbe4 FB |
1727 | return; |
| 1728 | store_current: | |
| 2be0071f FB |
1729 | /* save current instruction location */ |
| 1730 | *srr_0 = (env->nip - 4) & 0xFFFFFFFFULL; | |
| 9a64fbe4 FB |
1731 | break; |
| 1732 | store_next: | |
| 2be0071f FB |
1733 | /* save next instruction location */ |
| 1734 | *srr_0 = env->nip & 0xFFFFFFFFULL; | |
| 9a64fbe4 FB |
1735 | break; |
| 1736 | } | |
| 2be0071f FB |
1737 | /* Save msr */ |
| 1738 | *srr_1 = msr; | |
| 1739 | /* If we disactivated any translation, flush TLBs */ | |
| 1740 | if (msr_ir || msr_dr) { | |
| 1741 | tlb_flush(env, 1); | |
| 1742 | } | |
| 9a64fbe4 | 1743 | /* reload MSR with correct bits */ |
| 9a64fbe4 FB |
1744 | msr_ee = 0; |
| 1745 | msr_pr = 0; | |
| 1746 | msr_fp = 0; | |
| 1747 | msr_fe0 = 0; | |
| 1748 | msr_se = 0; | |
| 1749 | msr_be = 0; | |
| 1750 | msr_fe1 = 0; | |
| 1751 | msr_ir = 0; | |
| 1752 | msr_dr = 0; | |
| 1753 | msr_ri = 0; | |
| 1754 | msr_le = msr_ile; | |
| 2be0071f | 1755 | msr_sf = msr_isf; |
| 3fc6c082 | 1756 | do_compute_hflags(env); |
| 9a64fbe4 | 1757 | /* Jump to handler */ |
| 2be0071f | 1758 | env->nip = excp; |
| 9a64fbe4 | 1759 | env->exception_index = EXCP_NONE; |
| fb0eaffc | 1760 | } |
| 47103572 JM |
1761 | |
| 1762 | int ppc_hw_interrupt (CPUState *env) | |
| 1763 | { | |
| 1764 | int raised = 0; | |
| 1765 | ||
| 1766 | #if 0 | |
| 1767 | printf("%s: %p pending %08x req %08x %08x me %d ee %d\n", | |
| 1768 | __func__, env, env->pending_interrupts, | |
| 1769 | env->interrupt_request, interrupt_request, | |
| 1770 | msr_me, msr_ee); | |
| 1771 | #endif | |
| 1772 | /* Raise it */ | |
| 1773 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { | |
| 1774 | /* External reset / critical input */ | |
| 1775 | env->exception_index = EXCP_RESET; | |
| 1776 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); | |
| 1777 | raised = 1; | |
| 1778 | } | |
| 1779 | if (raised == 0 && msr_me != 0) { | |
| 1780 | /* Machine check exception */ | |
| 1781 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { | |
| 1782 | env->exception_index = EXCP_MACHINE_CHECK; | |
| 1783 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); | |
| 1784 | raised = 1; | |
| 1785 | } | |
| 1786 | } | |
| 1787 | if (raised == 0 && msr_ee != 0) { | |
| 1788 | #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ | |
| 1789 | /* Hypervisor decrementer exception */ | |
| 1790 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { | |
| 1791 | env->exception_index = EXCP_HDECR; | |
| 1792 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); | |
| 1793 | raised = 1; | |
| 1794 | } else | |
| 1795 | #endif | |
| 1796 | /* Decrementer exception */ | |
| 1797 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { | |
| 1798 | env->exception_index = EXCP_DECR; | |
| 1799 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); | |
| 1800 | raised = 1; | |
| 1801 | /* Programmable interval timer on embedded PowerPC */ | |
| 1802 | } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { | |
| 1803 | env->exception_index = EXCP_40x_PIT; | |
| 1804 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); | |
| 1805 | raised = 1; | |
| 1806 | /* Fixed interval timer on embedded PowerPC */ | |
| 1807 | } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { | |
| 1808 | env->exception_index = EXCP_40x_FIT; | |
| 1809 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); | |
| 1810 | raised = 1; | |
| 1811 | /* Watchdog timer on embedded PowerPC */ | |
| 1812 | } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { | |
| 1813 | env->exception_index = EXCP_40x_WATCHDOG; | |
| 1814 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); | |
| 1815 | raised = 1; | |
| 1816 | /* External interrupt */ | |
| 1817 | } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { | |
| 1818 | env->exception_index = EXCP_EXTERNAL; | |
| 1819 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT); | |
| 1820 | raised = 1; | |
| 1821 | } | |
| 1822 | #if 0 // TODO | |
| 1823 | /* External debug exception */ | |
| 1824 | } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { | |
| 1825 | env->exception_index = EXCP_xxx; | |
| 1826 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); | |
| 1827 | raised = 1; | |
| 1828 | #endif | |
| 1829 | } | |
| 1830 | if (raised != 0) { | |
| 1831 | env->error_code = 0; | |
| 1832 | do_interrupt(env); | |
| 1833 | } | |
| 1834 | ||
| 1835 | return raised; | |
| 1836 | } | |
| 18fba28c | 1837 | #endif /* !CONFIG_USER_ONLY */ |