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better fpu state dump
[qemu.git] / target-ppc / helper.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
79aceca5 3 *
3fc6c082 4 * Copyright (c) 2003-2005 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "exec.h"
9a64fbe4
FB		 21
22//#define DEBUG_MMU
23//#define DEBUG_BATS
24//#define DEBUG_EXCEPTIONS
25
9a64fbe4 26/*****************************************************************************/
3fc6c082 27/* PowerPC MMU emulation */
a541f297 28
9a64fbe4
FB		 29/* Perform BAT hit & translation */
30static int get_bat (CPUState *env, uint32_t *real, int *prot,
31 uint32_t virtual, int rw, int type)
32{
33 uint32_t *BATlt, *BATut, *BATu, *BATl;
34 uint32_t base, BEPIl, BEPIu, bl;
35 int i;
36 int ret = -1;
37
38#if defined (DEBUG_BATS)
39 if (loglevel > 0) {
40 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
41 type == ACCESS_CODE ? 'I' : 'D', virtual);
42 }
9a64fbe4
FB		 43#endif
44 switch (type) {
45 case ACCESS_CODE:
46 BATlt = env->IBAT[1];
47 BATut = env->IBAT[0];
48 break;
49 default:
50 BATlt = env->DBAT[1];
51 BATut = env->DBAT[0];
52 break;
53 }
54#if defined (DEBUG_BATS)
55 if (loglevel > 0) {
56 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
57 type == ACCESS_CODE ? 'I' : 'D', virtual);
58 }
9a64fbe4
FB		 59#endif
60 base = virtual & 0xFFFC0000;
61 for (i = 0; i < 4; i++) {
62 BATu = &BATut[i];
63 BATl = &BATlt[i];
64 BEPIu = *BATu & 0xF0000000;
65 BEPIl = *BATu & 0x0FFE0000;
66 bl = (*BATu & 0x00001FFC) << 15;
67#if defined (DEBUG_BATS)
68 if (loglevel > 0) {
69 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
70 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
71 *BATu, *BATl);
9a64fbe4
FB		 72 }
73#endif
74 if ((virtual & 0xF0000000) == BEPIu &&
75 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
76 /* BAT matches */
77 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
78 (msr_pr == 1 && (*BATu & 0x00000001))) {
79 /* Get physical address */
80 *real = (*BATl & 0xF0000000) |
81 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 82 (virtual & 0x0001F000);
9a64fbe4 83 if (*BATl & 0x00000001)
5f21aef2 84 *prot = PAGE_READ;
9a64fbe4 85 if (*BATl & 0x00000002)
5f21aef2 86 *prot = PAGE_WRITE | PAGE_READ;
9a64fbe4
FB		 87#if defined (DEBUG_BATS)
88 if (loglevel > 0) {
89 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
5f21aef2
FB		 90 i, *real, *prot & PAGE_READ ? 'R' : '-',
91 *prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 92 }
93#endif
94 ret = 0;
95 break;
96 }
97 }
98 }
99 if (ret < 0) {
100#if defined (DEBUG_BATS)
101 printf("no BAT match for 0x%08x:\n", virtual);
102 for (i = 0; i < 4; i++) {
103 BATu = &BATut[i];
104 BATl = &BATlt[i];
105 BEPIu = *BATu & 0xF0000000;
106 BEPIl = *BATu & 0x0FFE0000;
107 bl = (*BATu & 0x00001FFC) << 15;
108 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
109 "0x%08x 0x%08x 0x%08x\n",
110 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
111 *BATu, *BATl, BEPIu, BEPIl, bl);
112 }
113#endif
9a64fbe4
FB		 114 }
115 /* No hit */
116 return ret;
117}
118
119/* PTE table lookup */
120static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
121 int h, int key, int rw)
122{
a541f297 123 uint32_t pte0, pte1, keep = 0, access = 0;
9a64fbe4
FB		 124 int i, good = -1, store = 0;
125 int ret = -1; /* No entry found */
126
127 for (i = 0; i < 8; i++) {
8df1cd07
FB		 128 pte0 = ldl_phys(base + (i * 8));
129 pte1 = ldl_phys(base + (i * 8) + 4);
9a64fbe4 130#if defined (DEBUG_MMU)
d094807b 131 if (loglevel > 0) {
a541f297
FB		 132 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
133 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
134 pte0 >> 31, h, (pte0 >> 6) & 1, va);
135 }
9a64fbe4
FB		 136#endif
137 /* Check validity and table match */
138 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
9a64fbe4
FB		 139 /* Check vsid & api */
140 if ((pte0 & 0x7FFFFFBF) == va) {
9a64fbe4
FB		 141 if (good == -1) {
142 good = i;
143 keep = pte1;
144 } else {
145 /* All matches should have equal RPN, WIMG & PP */
146 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
a541f297
FB		 147 if (loglevel > 0)
148 fprintf(logfile, "Bad RPN/WIMG/PP\n");
9a64fbe4
FB		 149 return -1;
150 }
151 }
152 /* Check access rights */
153 if (key == 0) {
5f21aef2 154 access = PAGE_READ;
9a64fbe4 155 if ((pte1 & 0x00000003) != 0x3)
5f21aef2 156 access |= PAGE_WRITE;
9a64fbe4
FB		 157 } else {
158 switch (pte1 & 0x00000003) {
159 case 0x0:
a541f297 160 access = 0;
9a64fbe4
FB		 161 break;
162 case 0x1:
163 case 0x3:
5f21aef2 164 access = PAGE_READ;
9a64fbe4
FB		 165 break;
166 case 0x2:
5f21aef2 167 access = PAGE_READ | PAGE_WRITE;
9a64fbe4
FB		 168 break;
169 }
170 }
a541f297 171 if (ret < 0) {
5f21aef2
FB		 172 if ((rw == 0 && (access & PAGE_READ)) ||
173 (rw == 1 && (access & PAGE_WRITE))) {
9a64fbe4 174#if defined (DEBUG_MMU)
a541f297
FB		 175 if (loglevel > 0)
176 fprintf(logfile, "PTE access granted !\n");
9a64fbe4 177#endif
d094807b
FB		 178 good = i;
179 keep = pte1;
180 ret = 0;
a541f297
FB		 181 } else {
182 /* Access right violation */
d094807b 183 ret = -2;
9a64fbe4 184#if defined (DEBUG_MMU)
a541f297
FB		 185 if (loglevel > 0)
186 fprintf(logfile, "PTE access rejected\n");
9a64fbe4 187#endif
d094807b 188 }
a541f297
FB		 189 *prot = access;
190 }
9a64fbe4
FB		 191 }
192 }
193 }
194 if (good != -1) {
195 *RPN = keep & 0xFFFFF000;
196#if defined (DEBUG_MMU)
d094807b 197 if (loglevel > 0) {
a541f297 198 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
9a64fbe4 199 *RPN, *prot, ret);
a541f297 200 }
9a64fbe4
FB		 201#endif
202 /* Update page flags */
203 if (!(keep & 0x00000100)) {
a541f297 204 /* Access flag */
9a64fbe4
FB		 205 keep |= 0x00000100;
206 store = 1;
207 }
d094807b 208 if (!(keep & 0x00000080)) {
a541f297
FB		 209 if (rw && ret == 0) {
210 /* Change flag */
9a64fbe4
FB		 211 keep |= 0x00000080;
212 store = 1;
a541f297
FB		 213 } else {
214 /* Force page fault for first write access */
5f21aef2 215 *prot &= ~PAGE_WRITE;
9a64fbe4
FB		 216 }
217 }
a541f297 218 if (store) {
8df1cd07 219 stl_phys_notdirty(base + (good * 8) + 4, keep);
a541f297 220 }
9a64fbe4
FB		 221 }
222
223 return ret;
79aceca5
FB		 224}
225
9a64fbe4 226static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
79aceca5 227{
9a64fbe4 228 return (sdr1 & 0xFFFF0000) | (hash & mask);
79aceca5
FB		 229}
230
9a64fbe4
FB		 231/* Perform segment based translation */
232static int get_segment (CPUState *env, uint32_t *real, int *prot,
233 uint32_t virtual, int rw, int type)
79aceca5 234{
9a64fbe4
FB		 235 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
236 uint32_t hash, mask;
237 uint32_t sr;
238 int key;
239 int ret = -1, ret2;
79aceca5 240
9a64fbe4
FB		 241 sr = env->sr[virtual >> 28];
242#if defined (DEBUG_MMU)
a541f297
FB		 243 if (loglevel > 0) {
244 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
245 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
246 virtual, virtual >> 28, sr, env->nip,
247 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
248 }
9a64fbe4 249#endif
a541f297
FB		 250 key = (((sr & 0x20000000) && msr_pr == 1) ||
251 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
9a64fbe4
FB		 252 if ((sr & 0x80000000) == 0) {
253#if defined (DEBUG_MMU)
d094807b 254 if (loglevel > 0)
a541f297
FB		 255 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
256 key, sr & 0x10000000);
9a64fbe4
FB		 257#endif
258 /* Check if instruction fetch is allowed, if needed */
259 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
260 /* Page address translation */
261 vsid = sr & 0x00FFFFFF;
262 pgidx = (virtual >> 12) & 0xFFFF;
a541f297
FB		 263 sdr = env->sdr1;
264 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
9a64fbe4
FB		 265 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
266 pg_addr = get_pgaddr(sdr, hash, mask);
267 ptem = (vsid << 7) | (pgidx >> 10);
268#if defined (DEBUG_MMU)
a541f297
FB		 269 if (loglevel > 0) {
270 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
271 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
272 pg_addr);
273 }
9a64fbe4
FB		 274#endif
275 /* Primary table lookup */
276 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
277 if (ret < 0) {
278 /* Secondary table lookup */
279 hash = (~hash) & 0x01FFFFC0;
280 pg_addr = get_pgaddr(sdr, hash, mask);
281#if defined (DEBUG_MMU)
a541f297
FB		 282 if (virtual != 0xEFFFFFFF && loglevel > 0) {
283 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
284 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
285 hash, pg_addr);
286 }
9a64fbe4
FB		 287#endif
288 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
289 if (ret2 != -1)
290 ret = ret2;
291 }
9a64fbe4
FB		 292 } else {
293#if defined (DEBUG_MMU)
a541f297
FB		 294 if (loglevel > 0)
295 fprintf(logfile, "No access allowed\n");
9a64fbe4 296#endif
a541f297 297 ret = -3;
9a64fbe4
FB		 298 }
299 } else {
300#if defined (DEBUG_MMU)
a541f297
FB		 301 if (loglevel > 0)
302 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 303#endif
304 /* Direct-store segment : absolutely *BUGGY* for now */
305 switch (type) {
306 case ACCESS_INT:
307 /* Integer load/store : only access allowed */
308 break;
309 case ACCESS_CODE:
310 /* No code fetch is allowed in direct-store areas */
311 return -4;
312 case ACCESS_FLOAT:
313 /* Floating point load/store */
314 return -4;
315 case ACCESS_RES:
316 /* lwarx, ldarx or srwcx. */
317 return -4;
318 case ACCESS_CACHE:
319 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
320 /* Should make the instruction do no-op.
321 * As it already do no-op, it's quite easy :-)
322 */
323 *real = virtual;
324 return 0;
325 case ACCESS_EXT:
326 /* eciwx or ecowx */
327 return -4;
328 default:
329 if (logfile) {
330 fprintf(logfile, "ERROR: instruction should not need "
331 "address translation\n");
332 }
333 printf("ERROR: instruction should not need "
334 "address translation\n");
335 return -4;
336 }
337 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
338 *real = virtual;
339 ret = 2;
340 } else {
341 ret = -2;
342 }
79aceca5 343 }
9a64fbe4
FB		 344
345 return ret;
79aceca5
FB		 346}
347
9a64fbe4
FB		 348int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
349 uint32_t address, int rw, int access_type)
350{
351 int ret;
514fb8c1 352#if 0
9a64fbe4
FB		 353 if (loglevel > 0) {
354 fprintf(logfile, "%s\n", __func__);
355 }
514fb8c1 356#endif
4b3686fa
FB		 357 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
358 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 359 /* No address translation */
a541f297 360 *physical = address & ~0xFFF;
5f21aef2 361 *prot = PAGE_READ | PAGE_WRITE;
9a64fbe4
FB		 362 ret = 0;
363 } else {
364 /* Try to find a BAT */
365 ret = get_bat(env, physical, prot, address, rw, access_type);
366 if (ret < 0) {
367 /* We didn't match any BAT entry */
368 ret = get_segment(env, physical, prot, address, rw, access_type);
369 }
370 }
514fb8c1 371#if 0
a541f297
FB		 372 if (loglevel > 0) {
373 fprintf(logfile, "%s address %08x => %08x\n",
374 __func__, address, *physical);
375 }
514fb8c1 376#endif
9a64fbe4
FB		 377 return ret;
378}
379
a6b025d3
FB		 380#if defined(CONFIG_USER_ONLY)
381target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
382{
383 return addr;
384}
385#else
386target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
387{
388 uint32_t phys_addr;
389 int prot;
390
391 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
392 return -1;
393 return phys_addr;
394}
395#endif
9a64fbe4
FB		 396
397#if !defined(CONFIG_USER_ONLY)
398
399#define MMUSUFFIX _mmu
400#define GETPC() (__builtin_return_address(0))
401
402#define SHIFT 0
403#include "softmmu_template.h"
404
405#define SHIFT 1
406#include "softmmu_template.h"
407
408#define SHIFT 2
409#include "softmmu_template.h"
410
411#define SHIFT 3
412#include "softmmu_template.h"
413
414/* try to fill the TLB and return an exception if error. If retaddr is
415 NULL, it means that the function was called in C code (i.e. not
416 from generated code or from helper.c) */
417/* XXX: fix it to restore all registers */
0fa85d43 418void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
9a64fbe4
FB		 419{
420 TranslationBlock *tb;
9a64fbe4 421 CPUState *saved_env;
a541f297
FB		 422 unsigned long pc;
423 int ret;
9a64fbe4
FB		 424
425 /* XXX: hack to restore env in all cases, even if not called from
426 generated code */
427 saved_env = env;
428 env = cpu_single_env;
b769d8fe 429#if 0
9a64fbe4
FB		 430 {
431 unsigned long tlb_addrr, tlb_addrw;
432 int index;
433 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
434 tlb_addrr = env->tlb_read[is_user][index].address;
435 tlb_addrw = env->tlb_write[is_user][index].address;
4b3686fa
FB		 436 if (loglevel) {
437 fprintf(logfile,
438 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
9a64fbe4
FB		 439 "(0x%08lx 0x%08lx)\n", __func__, env,
440 &env->tlb_read[is_user][index], index, addr,
441 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
442 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
4b3686fa 443 }
9a64fbe4 444 }
b769d8fe 445#endif
a541f297 446 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
9a64fbe4
FB		 447 if (ret) {
448 if (retaddr) {
449 /* now we have a real cpu fault */
450 pc = (unsigned long)retaddr;
451 tb = tb_find_pc(pc);
452 if (tb) {
453 /* the PC is inside the translated code. It means that we have
454 a virtual CPU fault */
b324e814 455 cpu_restore_state(tb, env, pc, NULL);
9a64fbe4
FB		 456 }
457 }
9fddaa0c 458 do_raise_exception_err(env->exception_index, env->error_code);
9a64fbe4 459 }
b769d8fe 460#if 0
9a64fbe4
FB		 461 {
462 unsigned long tlb_addrr, tlb_addrw;
463 int index;
464 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
465 tlb_addrr = env->tlb_read[is_user][index].address;
466 tlb_addrw = env->tlb_write[is_user][index].address;
9a64fbe4
FB		 467 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
468 "(0x%08lx 0x%08lx)\n", __func__, env,
469 &env->tlb_read[is_user][index], index, addr,
470 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
471 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
9a64fbe4 472 }
b769d8fe 473#endif
9a64fbe4
FB		 474 env = saved_env;
475}
476
a541f297 477void cpu_ppc_init_mmu(CPUState *env)
9a64fbe4
FB		 478{
479 /* Nothing to do: all translation are disabled */
480}
481#endif
482
483/* Perform address translation */
484int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
a541f297 485 int is_user, int is_softmmu)
9a64fbe4
FB		 486{
487 uint32_t physical;
488 int prot;
489 int exception = 0, error_code = 0;
a541f297 490 int access_type;
9a64fbe4
FB		 491 int ret = 0;
492
b769d8fe
FB		 493 if (rw == 2) {
494 /* code access */
495 rw = 0;
496 access_type = ACCESS_CODE;
497 } else {
498 /* data access */
499 /* XXX: put correct access by using cpu_restore_state()
500 correctly */
501 access_type = ACCESS_INT;
502 // access_type = env->access_type;
503 }
9a64fbe4
FB		 504 if (env->user_mode_only) {
505 /* user mode only emulation */
1ef59d0a 506 ret = -2;
9a64fbe4
FB		 507 goto do_fault;
508 }
509 ret = get_physical_address(env, &physical, &prot,
510 address, rw, access_type);
511 if (ret == 0) {
a541f297
FB		 512 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
513 is_user, is_softmmu);
9a64fbe4
FB		 514 } else if (ret < 0) {
515 do_fault:
516#if defined (DEBUG_MMU)
a541f297 517 if (loglevel > 0)
7fe48483 518 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 519#endif
520 if (access_type == ACCESS_CODE) {
521 exception = EXCP_ISI;
522 switch (ret) {
523 case -1:
524 /* No matches in page tables */
2be0071f 525 error_code = 0x40000000;
9a64fbe4
FB		 526 break;
527 case -2:
528 /* Access rights violation */
2be0071f 529 error_code = 0x08000000;
9a64fbe4
FB		 530 break;
531 case -3:
a541f297 532 /* No execute protection violation */
2be0071f 533 error_code = 0x10000000;
9a64fbe4
FB		 534 break;
535 case -4:
536 /* Direct store exception */
537 /* No code fetch is allowed in direct-store areas */
2be0071f
FB		 538 error_code = 0x10000000;
539 break;
540 case -5:
541 /* No match in segment table */
542 exception = EXCP_ISEG;
543 error_code = 0;
9a64fbe4
FB		 544 break;
545 }
546 } else {
547 exception = EXCP_DSI;
548 switch (ret) {
549 case -1:
550 /* No matches in page tables */
2be0071f 551 error_code = 0x40000000;
9a64fbe4
FB		 552 break;
553 case -2:
554 /* Access rights violation */
2be0071f 555 error_code = 0x08000000;
9a64fbe4
FB		 556 break;
557 case -4:
558 /* Direct store exception */
559 switch (access_type) {
560 case ACCESS_FLOAT:
561 /* Floating point load/store */
562 exception = EXCP_ALIGN;
563 error_code = EXCP_ALIGN_FP;
564 break;
565 case ACCESS_RES:
566 /* lwarx, ldarx or srwcx. */
2be0071f 567 error_code = 0x04000000;
9a64fbe4
FB		 568 break;
569 case ACCESS_EXT:
570 /* eciwx or ecowx */
2be0071f 571 error_code = 0x04100000;
9a64fbe4
FB		 572 break;
573 default:
a541f297 574 printf("DSI: invalid exception (%d)\n", ret);
9a64fbe4
FB		 575 exception = EXCP_PROGRAM;
576 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
577 break;
578 }
2be0071f
FB		 579 case -5:
580 /* No match in segment table */
581 exception = EXCP_DSEG;
582 error_code = 0;
583 break;
9a64fbe4
FB		 584 }
585 if (rw)
2be0071f 586 error_code |= 0x02000000;
a541f297 587 /* Store fault address */
3fc6c082 588 env->spr[SPR_DAR] = address;
2be0071f 589 env->spr[SPR_DSISR] = error_code;
9a64fbe4
FB		 590 }
591#if 0
592 printf("%s: set exception to %d %02x\n",
593 __func__, exception, error_code);
594#endif
595 env->exception_index = exception;
596 env->error_code = error_code;
9a64fbe4
FB		 597 ret = 1;
598 }
9a64fbe4
FB		 599 return ret;
600}
601
3fc6c082
FB		 602/*****************************************************************************/
603/* BATs management */
604#if !defined(FLUSH_ALL_TLBS)
605static inline void do_invalidate_BAT (CPUPPCState *env,
606 target_ulong BATu, target_ulong mask)
607{
608 target_ulong base, end, page;
609 base = BATu & ~0x0001FFFF;
610 end = base + mask + 0x00020000;
611#if defined (DEBUG_BATS)
612 if (loglevel != 0)
613 fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n", base, end, mask);
614#endif
615 for (page = base; page != end; page += TARGET_PAGE_SIZE)
616 tlb_flush_page(env, page);
617#if defined (DEBUG_BATS)
618 if (loglevel != 0)
619 fprintf(logfile, "Flush done\n");
620#endif
621}
622#endif
623
624static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
625 target_ulong value)
626{
627#if defined (DEBUG_BATS)
628 if (loglevel != 0) {
629 fprintf(logfile, "Set %cBAT%d%c to 0x%08lx (0x%08lx)\n",
630 ID, nr, ul == 0 ? 'u' : 'l', (unsigned long)value,
631 (unsigned long)env->nip);
632 }
633#endif
634}
635
636target_ulong do_load_ibatu (CPUPPCState *env, int nr)
637{
638 return env->IBAT[0][nr];
639}
640
641target_ulong do_load_ibatl (CPUPPCState *env, int nr)
642{
643 return env->IBAT[1][nr];
644}
645
646void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
647{
648 target_ulong mask;
649
650 dump_store_bat(env, 'I', 0, nr, value);
651 if (env->IBAT[0][nr] != value) {
652 mask = (value << 15) & 0x0FFE0000UL;
653#if !defined(FLUSH_ALL_TLBS)
654 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
655#endif
656 /* When storing valid upper BAT, mask BEPI and BRPN
657 * and invalidate all TLBs covered by this BAT
658 */
659 mask = (value << 15) & 0x0FFE0000UL;
660 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
661 (value & ~0x0001FFFFUL & ~mask);
662 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
663 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
664#if !defined(FLUSH_ALL_TLBS)
665 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
666#endif
667#if defined(FLUSH_ALL_TLBS)
668 tlb_flush(env, 1);
669#endif
670 }
671}
672
673void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
674{
675 dump_store_bat(env, 'I', 1, nr, value);
676 env->IBAT[1][nr] = value;
677}
678
679target_ulong do_load_dbatu (CPUPPCState *env, int nr)
680{
681 return env->DBAT[0][nr];
682}
683
684target_ulong do_load_dbatl (CPUPPCState *env, int nr)
685{
686 return env->DBAT[1][nr];
687}
688
689void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
690{
691 target_ulong mask;
692
693 dump_store_bat(env, 'D', 0, nr, value);
694 if (env->DBAT[0][nr] != value) {
695 /* When storing valid upper BAT, mask BEPI and BRPN
696 * and invalidate all TLBs covered by this BAT
697 */
698 mask = (value << 15) & 0x0FFE0000UL;
699#if !defined(FLUSH_ALL_TLBS)
700 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
701#endif
702 mask = (value << 15) & 0x0FFE0000UL;
703 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
704 (value & ~0x0001FFFFUL & ~mask);
705 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
706 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
707#if !defined(FLUSH_ALL_TLBS)
708 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
709#else
710 tlb_flush(env, 1);
711#endif
712 }
713}
714
715void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
716{
717 dump_store_bat(env, 'D', 1, nr, value);
718 env->DBAT[1][nr] = value;
719}
720
721static inline void invalidate_all_tlbs (CPUPPCState *env)
722{
723 /* XXX: this needs to be completed for sotware driven TLB support */
724 tlb_flush(env, 1);
725}
726
727/*****************************************************************************/
728/* Special registers manipulation */
729target_ulong do_load_nip (CPUPPCState *env)
730{
731 return env->nip;
732}
733
734void do_store_nip (CPUPPCState *env, target_ulong value)
735{
736 env->nip = value;
737}
738
739target_ulong do_load_sdr1 (CPUPPCState *env)
740{
741 return env->sdr1;
742}
743
744void do_store_sdr1 (CPUPPCState *env, target_ulong value)
745{
746#if defined (DEBUG_MMU)
747 if (loglevel != 0) {
748 fprintf(logfile, "%s: 0x%08lx\n", __func__, (unsigned long)value);
749 }
750#endif
751 if (env->sdr1 != value) {
752 env->sdr1 = value;
753 invalidate_all_tlbs(env);
754 }
755}
756
757target_ulong do_load_sr (CPUPPCState *env, int srnum)
758{
759 return env->sr[srnum];
760}
761
762void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
763{
764#if defined (DEBUG_MMU)
765 if (loglevel != 0) {
766 fprintf(logfile, "%s: reg=%d 0x%08lx %08lx\n",
767 __func__, srnum, (unsigned long)value, env->sr[srnum]);
768 }
769#endif
770 if (env->sr[srnum] != value) {
771 env->sr[srnum] = value;
772#if !defined(FLUSH_ALL_TLBS) && 0
773 {
774 target_ulong page, end;
775 /* Invalidate 256 MB of virtual memory */
776 page = (16 << 20) * srnum;
777 end = page + (16 << 20);
778 for (; page != end; page += TARGET_PAGE_SIZE)
779 tlb_flush_page(env, page);
780 }
781#else
782 invalidate_all_tlbs(env);
783#endif
784 }
785}
786
787uint32_t do_load_cr (CPUPPCState *env)
788{
789 return (env->crf[0] << 28) |
790 (env->crf[1] << 24) |
791 (env->crf[2] << 20) |
792 (env->crf[3] << 16) |
793 (env->crf[4] << 12) |
794 (env->crf[5] << 8) |
795 (env->crf[6] << 4) |
796 (env->crf[7] << 0);
797}
798
799void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask)
800{
801 int i, sh;
802
803 for (i = 0, sh = 7; i < 8; i++, sh --) {
804 if (mask & (1 << sh))
805 env->crf[i] = (value >> (sh * 4)) & 0xFUL;
806 }
807}
808
809uint32_t do_load_xer (CPUPPCState *env)
79aceca5
FB		 810{
811 return (xer_so << XER_SO) |
812 (xer_ov << XER_OV) |
813 (xer_ca << XER_CA) |
3fc6c082
FB		 814 (xer_bc << XER_BC) |
815 (xer_cmp << XER_CMP);
79aceca5
FB		 816}
817
3fc6c082 818void do_store_xer (CPUPPCState *env, uint32_t value)
79aceca5
FB		 819{
820 xer_so = (value >> XER_SO) & 0x01;
821 xer_ov = (value >> XER_OV) & 0x01;
822 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082
FB		 823 xer_cmp = (value >> XER_CMP) & 0xFF;
824 xer_bc = (value >> XER_BC) & 0x3F;
79aceca5
FB		 825}
826
3fc6c082 827target_ulong do_load_msr (CPUPPCState *env)
79aceca5 828{
3fc6c082
FB		 829 return (msr_vr << MSR_VR) |
830 (msr_ap << MSR_AP) |
831 (msr_sa << MSR_SA) |
832 (msr_key << MSR_KEY) |
833 (msr_pow << MSR_POW) |
834 (msr_tlb << MSR_TLB) |
79aceca5
FB		 835 (msr_ile << MSR_ILE) |
836 (msr_ee << MSR_EE) |
837 (msr_pr << MSR_PR) |
838 (msr_fp << MSR_FP) |
839 (msr_me << MSR_ME) |
840 (msr_fe0 << MSR_FE0) |
841 (msr_se << MSR_SE) |
842 (msr_be << MSR_BE) |
843 (msr_fe1 << MSR_FE1) |
3fc6c082 844 (msr_al << MSR_AL) |
79aceca5
FB		 845 (msr_ip << MSR_IP) |
846 (msr_ir << MSR_IR) |
847 (msr_dr << MSR_DR) |
3fc6c082
FB		 848 (msr_pe << MSR_PE) |
849 (msr_px << MSR_PX) |
79aceca5
FB		 850 (msr_ri << MSR_RI) |
851 (msr_le << MSR_LE);
852}
853
3fc6c082 854void do_compute_hflags (CPUPPCState *env)
79aceca5 855{
3fc6c082
FB		 856 /* Compute current hflags */
857 env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
858 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
859 (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
860 (msr_se << MSR_SE) | (msr_be << MSR_BE);
861}
862
863void do_store_msr (CPUPPCState *env, target_ulong value)
4b3686fa 864 {
3fc6c082
FB		 865 value &= env->msr_mask;
866 if (((value >> MSR_IR) & 1) != msr_ir ||
867 ((value >> MSR_DR) & 1) != msr_dr) {
868 /* Flush all tlb when changing translation mode
869 * When using software driven TLB, we may also need to reload
870 * all defined TLBs
871 */
d094807b 872 tlb_flush(env, 1);
3fc6c082 873 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 874 }
3fc6c082
FB		 875#if 0
876 if (loglevel != 0) {
877 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
878 }
879#endif
880 msr_vr = (value >> MSR_VR) & 1;
881 msr_ap = (value >> MSR_AP) & 1;
882 msr_sa = (value >> MSR_SA) & 1;
883 msr_key = (value >> MSR_KEY) & 1;
884 msr_pow = (value >> MSR_POW) & 1;
885 msr_tlb = (value >> MSR_TLB) & 1;
886 msr_ile = (value >> MSR_ILE) & 1;
887 msr_ee = (value >> MSR_EE) & 1;
888 msr_pr = (value >> MSR_PR) & 1;
889 msr_fp = (value >> MSR_FP) & 1;
890 msr_me = (value >> MSR_ME) & 1;
891 msr_fe0 = (value >> MSR_FE0) & 1;
892 msr_se = (value >> MSR_SE) & 1;
893 msr_be = (value >> MSR_BE) & 1;
894 msr_fe1 = (value >> MSR_FE1) & 1;
895 msr_al = (value >> MSR_AL) & 1;
896 msr_ip = (value >> MSR_IP) & 1;
897 msr_ir = (value >> MSR_IR) & 1;
898 msr_dr = (value >> MSR_DR) & 1;
899 msr_pe = (value >> MSR_PE) & 1;
900 msr_px = (value >> MSR_PX) & 1;
901 msr_ri = (value >> MSR_RI) & 1;
902 msr_le = (value >> MSR_LE) & 1;
903 do_compute_hflags(env);
904}
905
906float64 do_load_fpscr (CPUPPCState *env)
907{
908 /* The 32 MSB of the target fpr are undefined.
909 * They'll be zero...
910 */
911 union {
912 float64 d;
913 struct {
914 uint32_t u[2];
915 } s;
916 } u;
917 int i;
918
919#ifdef WORDS_BIGENDIAN
920#define WORD0 0
921#define WORD1 1
922#else
923#define WORD0 1
924#define WORD1 0
4b3686fa 925#endif
3fc6c082
FB		 926 u.s.u[WORD0] = 0;
927 u.s.u[WORD1] = 0;
928 for (i = 0; i < 8; i++)
929 u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
930 return u.d;
79aceca5
FB		 931}
932
3fc6c082
FB		 933void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask)
934{
935 /*
936 * We use only the 32 LSB of the incoming fpr
937 */
938 union {
939 double d;
940 struct {
941 uint32_t u[2];
942 } s;
943 } u;
944 int i, rnd_type;
945
946 u.d = f;
947 if (mask & 0x80)
948 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
949 for (i = 1; i < 7; i++) {
950 if (mask & (1 << (7 - i)))
951 env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
952 }
953 /* TODO: update FEX & VX */
954 /* Set rounding mode */
955 switch (env->fpscr[0] & 0x3) {
956 case 0:
957 /* Best approximation (round to nearest) */
958 rnd_type = float_round_nearest_even;
959 break;
960 case 1:
961 /* Smaller magnitude (round toward zero) */
962 rnd_type = float_round_to_zero;
963 break;
964 case 2:
965 /* Round toward +infinite */
966 rnd_type = float_round_up;
967 break;
968 default:
969 case 3:
970 /* Round toward -infinite */
971 rnd_type = float_round_down;
972 break;
973 }
974 set_float_rounding_mode(rnd_type, &env->fp_status);
975}
976
977/*****************************************************************************/
978/* Exception processing */
18fba28c 979#if defined (CONFIG_USER_ONLY)
9a64fbe4 980void do_interrupt (CPUState *env)
79aceca5 981{
18fba28c
FB		 982 env->exception_index = -1;
983}
9a64fbe4 984#else
d094807b
FB		 985static void dump_syscall(CPUState *env)
986{
987 fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
988 env->gpr[0], env->gpr[3], env->gpr[4],
989 env->gpr[5], env->gpr[6], env->nip);
990}
991
18fba28c
FB		 992void do_interrupt (CPUState *env)
993{
2be0071f 994 target_ulong msr, *srr_0, *srr_1, tmp;
18fba28c 995 int excp;
79aceca5 996
18fba28c 997 excp = env->exception_index;
3fc6c082 998 msr = do_load_msr(env);
2be0071f
FB		 999 /* The default is to use SRR0 & SRR1 to save the exception context */
1000 srr_0 = &env->spr[SPR_SRR0];
1001 srr_1 = &env->spr[SPR_SRR1];
9a64fbe4 1002#if defined (DEBUG_EXCEPTIONS)
2be0071f
FB		 1003 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1004 if (loglevel != 0) {
1005 fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
1006 (unsigned long)env->nip, excp, env->error_code);
1007 cpu_dump_state(env, logfile, fprintf, 0);
b769d8fe 1008 }
79aceca5 1009 }
9a64fbe4 1010#endif
b769d8fe 1011 if (loglevel & CPU_LOG_INT) {
2be0071f
FB		 1012 fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
1013 (unsigned long)env->nip, excp, env->error_code);
b769d8fe 1014 }
2be0071f 1015 msr_pow = 0;
9a64fbe4
FB		 1016 /* Generate informations in save/restore registers */
1017 switch (excp) {
2be0071f
FB		 1018 /* Generic PowerPC exceptions */
1019 case EXCP_RESET: /* 0x0100 */
1020 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
1021 if (msr_ip)
1022 excp += 0xFFC00;
1023 excp |= 0xFFC00000;
1024 } else {
1025 srr_0 = &env->spr[SPR_40x_SRR2];
1026 srr_1 = &env->spr[SPR_40x_SRR3];
1027 }
9a64fbe4 1028 goto store_next;
2be0071f 1029 case EXCP_MACHINE_CHECK: /* 0x0200 */
9a64fbe4 1030 if (msr_me == 0) {
4b3686fa 1031 cpu_abort(env, "Machine check exception while not allowed\n");
79aceca5 1032 }
2be0071f
FB		 1033 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_40x) {
1034 srr_0 = &env->spr[SPR_40x_SRR2];
1035 srr_1 = &env->spr[SPR_40x_SRR3];
1036 }
9a64fbe4
FB		 1037 msr_me = 0;
1038 break;
2be0071f 1039 case EXCP_DSI: /* 0x0300 */
9a64fbe4
FB		 1040 /* Store exception cause */
1041 /* data location address has been stored
1042 * when the fault has been detected
2be0071f 1043 */
a541f297 1044 msr &= ~0xFFFF0000;
a541f297
FB		 1045#if defined (DEBUG_EXCEPTIONS)
1046 if (loglevel) {
1047 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
3fc6c082 1048 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
a541f297 1049 } else {
2be0071f
FB		 1050 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
1051 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
a541f297
FB		 1052 }
1053#endif
1054 goto store_next;
2be0071f 1055 case EXCP_ISI: /* 0x0400 */
9a64fbe4 1056 /* Store exception cause */
a541f297 1057 msr &= ~0xFFFF0000;
2be0071f 1058 msr |= env->error_code;
a541f297 1059#if defined (DEBUG_EXCEPTIONS)
2be0071f 1060 if (loglevel != 0) {
a541f297
FB		 1061 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
1062 msr, env->nip);
a541f297
FB		 1063 }
1064#endif
9a64fbe4 1065 goto store_next;
2be0071f 1066 case EXCP_EXTERNAL: /* 0x0500 */
9a64fbe4
FB		 1067 if (msr_ee == 0) {
1068#if defined (DEBUG_EXCEPTIONS)
1069 if (loglevel > 0) {
1070 fprintf(logfile, "Skipping hardware interrupt\n");
2be0071f 1071 }
9a64fbe4 1072#endif
a541f297 1073 /* Requeue it */
2be0071f 1074 env->interrupt_request |= CPU_INTERRUPT_HARD;
9a64fbe4 1075 return;
2be0071f 1076 }
9a64fbe4 1077 goto store_next;
2be0071f
FB		 1078 case EXCP_ALIGN: /* 0x0600 */
1079 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_601) {
1080 /* Store exception cause */
1081 /* Get rS/rD and rA from faulting opcode */
1082 env->spr[SPR_DSISR] |=
1083 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1084 /* data location address has been stored
1085 * when the fault has been detected
1086 */
1087 } else {
1088 /* IO error exception on PowerPC 601 */
1089 /* XXX: TODO */
1090 cpu_abort(env,
1091 "601 IO error exception is not implemented yet !\n");
1092 }
9a64fbe4 1093 goto store_current;
2be0071f 1094 case EXCP_PROGRAM: /* 0x0700 */
9a64fbe4
FB		 1095 msr &= ~0xFFFF0000;
1096 switch (env->error_code & ~0xF) {
1097 case EXCP_FP:
1098 if (msr_fe0 == 0 && msr_fe1 == 0) {
1099#if defined (DEBUG_EXCEPTIONS)
1100 printf("Ignore floating point exception\n");
1101#endif
1102 return;
79aceca5 1103 }
9a64fbe4
FB		 1104 msr |= 0x00100000;
1105 /* Set FX */
1106 env->fpscr[7] |= 0x8;
1107 /* Finally, update FEX */
1108 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1109 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1110 env->fpscr[7] |= 0x4;
1111 break;
1112 case EXCP_INVAL:
4b3686fa 1113 // printf("Invalid instruction at 0x%08x\n", env->nip);
9a64fbe4
FB		 1114 msr |= 0x00080000;
1115 break;
1116 case EXCP_PRIV:
1117 msr |= 0x00040000;
1118 break;
1119 case EXCP_TRAP:
1120 msr |= 0x00020000;
1121 break;
1122 default:
1123 /* Should never occur */
1124 break;
79aceca5 1125 }
9a64fbe4
FB		 1126 msr |= 0x00010000;
1127 goto store_current;
2be0071f 1128 case EXCP_NO_FP: /* 0x0800 */
4ecc3190 1129 msr &= ~0xFFFF0000;
9a64fbe4
FB		 1130 goto store_current;
1131 case EXCP_DECR:
1132 if (msr_ee == 0) {
2be0071f 1133#if 1
9a64fbe4 1134 /* Requeue it */
2be0071f
FB		 1135 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1136#endif
9a64fbe4
FB		 1137 return;
1138 }
1139 goto store_next;
2be0071f 1140 case EXCP_SYSCALL: /* 0x0C00 */
d094807b
FB		 1141 /* NOTE: this is a temporary hack to support graphics OSI
1142 calls from the MOL driver */
1143 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1144 env->osi_call) {
1145 if (env->osi_call(env) != 0)
1146 return;
1147 }
b769d8fe 1148 if (loglevel & CPU_LOG_INT) {
d094807b 1149 dump_syscall(env);
b769d8fe 1150 }
9a64fbe4 1151 goto store_next;
2be0071f
FB		 1152 case EXCP_TRACE: /* 0x0D00 */
1153 /* XXX: TODO */
1154 cpu_abort(env, "Trace exception is not implemented yet !\n");
1155 goto store_next;
1156 case EXCP_PERF: /* 0x0F00 */
1157 /* XXX: TODO */
1158 cpu_abort(env,
1159 "Performance counter exception is not implemented yet !\n");
1160 goto store_next;
1161 /* 32 bits PowerPC specific exceptions */
1162 case EXCP_FP_ASSIST: /* 0x0E00 */
1163 /* XXX: TODO */
1164 cpu_abort(env, "Floating point assist exception "
1165 "is not implemented yet !\n");
1166 goto store_next;
1167 /* 64 bits PowerPC exceptions */
1168 case EXCP_DSEG: /* 0x0380 */
1169 /* XXX: TODO */
1170 cpu_abort(env, "Data segment exception is not implemented yet !\n");
9a64fbe4 1171 goto store_next;
2be0071f
FB		 1172 case EXCP_ISEG: /* 0x0480 */
1173 /* XXX: TODO */
1174 cpu_abort(env,
1175 "Instruction segment exception is not implemented yet !\n");
9a64fbe4 1176 goto store_next;
2be0071f
FB		 1177 case EXCP_HDECR: /* 0x0980 */
1178 if (msr_ee == 0) {
1179#if 1
1180 /* Requeue it */
1181 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1182#endif
9a64fbe4 1183 return;
2be0071f
FB		 1184 }
1185 cpu_abort(env,
1186 "Hypervisor decrementer exception is not implemented yet !\n");
1187 goto store_next;
1188 /* Implementation specific exceptions */
1189 case 0x0A00:
1190 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_602) {
1191 /* Critical interrupt on G2 */
1192 /* XXX: TODO */
1193 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1194 goto store_next;
1195 } else {
1196 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1197 }
9a64fbe4 1198 return;
2be0071f
FB		 1199 case 0x0F20:
1200 switch (PPC_EXCP(env)) {
1201 case PPC_FLAGS_EXCP_40x:
1202 /* APU unavailable on 405 */
1203 /* XXX: TODO */
1204 cpu_abort(env,
1205 "APU unavailable exception is not implemented yet !\n");
1206 goto store_next;
1207 case PPC_FLAGS_EXCP_74xx:
1208 /* Altivec unavailable */
1209 /* XXX: TODO */
1210 cpu_abort(env, "Altivec unavailable exception "
1211 "is not implemented yet !\n");
1212 goto store_next;
1213 default:
1214 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1215 break;
1216 }
1217 return;
1218 case 0x1000:
1219 switch (PPC_EXCP(env)) {
1220 case PPC_FLAGS_EXCP_40x:
1221 /* PIT on 4xx */
1222 /* XXX: TODO */
1223 cpu_abort(env, "40x PIT exception is not implemented yet !\n");
1224 goto store_next;
1225 case PPC_FLAGS_EXCP_602:
1226 case PPC_FLAGS_EXCP_603:
1227 /* ITLBMISS on 602/603 */
1228 msr &= ~0xF00F0000;
1229 msr_tgpr = 1;
1230 goto store_gprs;
1231 default:
1232 cpu_abort(env, "Invalid exception 0x1000 !\n");
1233 break;
1234 }
1235 return;
1236 case 0x1010:
1237 switch (PPC_EXCP(env)) {
1238 case PPC_FLAGS_EXCP_40x:
1239 /* FIT on 4xx */
1240 cpu_abort(env, "40x FIT exception is not implemented yet !\n");
1241 /* XXX: TODO */
1242 goto store_next;
1243 default:
1244 cpu_abort(env, "Invalid exception 0x1010 !\n");
1245 break;
1246 }
1247 return;
1248 case 0x1020:
1249 switch (PPC_EXCP(env)) {
1250 case PPC_FLAGS_EXCP_40x:
1251 /* Watchdog on 4xx */
1252 /* XXX: TODO */
1253 cpu_abort(env,
1254 "40x watchdog exception is not implemented yet !\n");
1255 goto store_next;
1256 default:
1257 cpu_abort(env, "Invalid exception 0x1020 !\n");
1258 break;
1259 }
1260 return;
1261 case 0x1100:
1262 switch (PPC_EXCP(env)) {
1263 case PPC_FLAGS_EXCP_40x:
1264 /* DTLBMISS on 4xx */
1265 /* XXX: TODO */
1266 cpu_abort(env,
1267 "40x DTLBMISS exception is not implemented yet !\n");
1268 goto store_next;
1269 case PPC_FLAGS_EXCP_602:
1270 case PPC_FLAGS_EXCP_603:
1271 /* DLTLBMISS on 602/603 */
1272 msr &= ~0xF00F0000;
1273 msr_tgpr = 1;
1274 goto store_gprs;
1275 default:
1276 cpu_abort(env, "Invalid exception 0x1100 !\n");
1277 break;
1278 }
1279 return;
1280 case 0x1200:
1281 switch (PPC_EXCP(env)) {
1282 case PPC_FLAGS_EXCP_40x:
1283 /* ITLBMISS on 4xx */
1284 /* XXX: TODO */
1285 cpu_abort(env,
1286 "40x ITLBMISS exception is not implemented yet !\n");
1287 goto store_next;
1288 case PPC_FLAGS_EXCP_602:
1289 case PPC_FLAGS_EXCP_603:
1290 /* DSTLBMISS on 602/603 */
1291 msr &= ~0xF00F0000;
1292 msr_tgpr = 1;
1293 store_gprs:
1294#if defined (DEBUG_SOFTWARE_TLB)
1295 if (loglevel != 0) {
1296 fprintf(logfile, "6xx %sTLB miss: IM %08x DM %08x IC %08x "
1297 "DC %08x H1 %08x H2 %08x %08x\n",
1298 excp == 0x1000 ? "I" : excp == 0x1100 ? "DL" : "DS",
1299 env->spr[SPR_IMISS], env->spr[SPR_DMISS],
1300 env->spr[SPR_ICMP], env->spr[SPR_DCMP],
1301 env->spr[SPR_DHASH1], env->spr[SPR_DHASH2],
1302 env->error_code);
1303 }
9a64fbe4 1304#endif
2be0071f
FB		 1305 /* Swap temporary saved registers with GPRs */
1306 tmp = env->gpr[0];
1307 env->gpr[0] = env->tgpr[0];
1308 env->tgpr[0] = tmp;
1309 tmp = env->gpr[1];
1310 env->gpr[1] = env->tgpr[1];
1311 env->tgpr[1] = tmp;
1312 tmp = env->gpr[2];
1313 env->gpr[2] = env->tgpr[2];
1314 env->tgpr[2] = tmp;
1315 tmp = env->gpr[3];
1316 env->gpr[3] = env->tgpr[3];
1317 env->tgpr[3] = tmp;
1318 msr |= env->crf[0] << 28;
1319 msr |= env->error_code; /* key, D/I, S/L bits */
1320 /* Set way using a LRU mechanism */
1321 msr |= (env->last_way ^ 1) << 17;
1322 goto store_next;
1323 default:
1324 cpu_abort(env, "Invalid exception 0x1200 !\n");
1325 break;
1326 }
1327 return;
1328 case 0x1300:
1329 switch (PPC_EXCP(env)) {
1330 case PPC_FLAGS_EXCP_601:
1331 case PPC_FLAGS_EXCP_602:
1332 case PPC_FLAGS_EXCP_603:
1333 case PPC_FLAGS_EXCP_604:
1334 case PPC_FLAGS_EXCP_7x0:
1335 case PPC_FLAGS_EXCP_7x5:
1336 /* IABR on 6xx/7xx */
1337 /* XXX: TODO */
1338 cpu_abort(env, "IABR exception is not implemented yet !\n");
1339 goto store_next;
1340 default:
1341 cpu_abort(env, "Invalid exception 0x1300 !\n");
1342 break;
1343 }
1344 return;
1345 case 0x1400:
1346 switch (PPC_EXCP(env)) {
1347 case PPC_FLAGS_EXCP_601:
1348 case PPC_FLAGS_EXCP_602:
1349 case PPC_FLAGS_EXCP_603:
1350 case PPC_FLAGS_EXCP_604:
1351 case PPC_FLAGS_EXCP_7x0:
1352 case PPC_FLAGS_EXCP_7x5:
1353 /* SMI on 6xx/7xx */
1354 /* XXX: TODO */
1355 cpu_abort(env, "SMI exception is not implemented yet !\n");
1356 goto store_next;
1357 default:
1358 cpu_abort(env, "Invalid exception 0x1400 !\n");
1359 break;
1360 }
1361 return;
1362 case 0x1500:
1363 switch (PPC_EXCP(env)) {
1364 case PPC_FLAGS_EXCP_602:
1365 /* Watchdog on 602 */
1366 cpu_abort(env,
1367 "602 watchdog exception is not implemented yet !\n");
1368 goto store_next;
1369 case PPC_FLAGS_EXCP_970:
1370 /* Soft patch exception on 970 */
1371 /* XXX: TODO */
1372 cpu_abort(env,
1373 "970 soft-patch exception is not implemented yet !\n");
1374 goto store_next;
1375 case PPC_FLAGS_EXCP_74xx:
1376 /* VPU assist on 74xx */
1377 /* XXX: TODO */
1378 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1379 goto store_next;
1380 default:
1381 cpu_abort(env, "Invalid exception 0x1500 !\n");
1382 break;
1383 }
1384 return;
1385 case 0x1600:
1386 switch (PPC_EXCP(env)) {
1387 case PPC_FLAGS_EXCP_602:
1388 /* Emulation trap on 602 */
1389 /* XXX: TODO */
1390 cpu_abort(env, "602 emulation trap exception "
1391 "is not implemented yet !\n");
1392 goto store_next;
1393 case PPC_FLAGS_EXCP_970:
1394 /* Maintenance exception on 970 */
1395 /* XXX: TODO */
1396 cpu_abort(env,
1397 "970 maintenance exception is not implemented yet !\n");
1398 goto store_next;
1399 default:
1400 cpu_abort(env, "Invalid exception 0x1600 !\n");
1401 break;
1402 }
1403 return;
1404 case 0x1700:
1405 switch (PPC_EXCP(env)) {
1406 case PPC_FLAGS_EXCP_7x0:
1407 case PPC_FLAGS_EXCP_7x5:
1408 /* Thermal management interrupt on G3 */
1409 /* XXX: TODO */
1410 cpu_abort(env, "G3 thermal management exception "
1411 "is not implemented yet !\n");
1412 goto store_next;
1413 case PPC_FLAGS_EXCP_970:
1414 /* VPU assist on 970 */
1415 /* XXX: TODO */
1416 cpu_abort(env,
1417 "970 VPU assist exception is not implemented yet !\n");
1418 goto store_next;
1419 default:
1420 cpu_abort(env, "Invalid exception 0x1700 !\n");
1421 break;
1422 }
1423 return;
1424 case 0x1800:
1425 switch (PPC_EXCP(env)) {
1426 case PPC_FLAGS_EXCP_970:
1427 /* Thermal exception on 970 */
1428 /* XXX: TODO */
1429 cpu_abort(env, "970 thermal management exception "
1430 "is not implemented yet !\n");
1431 goto store_next;
1432 default:
1433 cpu_abort(env, "Invalid exception 0x1800 !\n");
1434 break;
1435 }
1436 return;
1437 case 0x2000:
1438 switch (PPC_EXCP(env)) {
1439 case PPC_FLAGS_EXCP_40x:
1440 /* DEBUG on 4xx */
1441 /* XXX: TODO */
1442 cpu_abort(env, "40x debug exception is not implemented yet !\n");
1443 goto store_next;
1444 case PPC_FLAGS_EXCP_601:
1445 /* Run mode exception on 601 */
1446 /* XXX: TODO */
1447 cpu_abort(env,
1448 "601 run mode exception is not implemented yet !\n");
1449 goto store_next;
1450 default:
1451 cpu_abort(env, "Invalid exception 0x1800 !\n");
1452 break;
1453 }
1454 return;
1455 /* Other exceptions */
1456 /* Qemu internal exceptions:
1457 * we should never come here with those values: abort execution
1458 */
1459 default:
1460 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
9a64fbe4
FB		 1461 return;
1462 store_current:
2be0071f
FB		 1463 /* save current instruction location */
1464 *srr_0 = (env->nip - 4) & 0xFFFFFFFFULL;
9a64fbe4
FB		 1465 break;
1466 store_next:
2be0071f
FB		 1467 /* save next instruction location */
1468 *srr_0 = env->nip & 0xFFFFFFFFULL;
9a64fbe4
FB		 1469 break;
1470 }
2be0071f
FB		 1471 /* Save msr */
1472 *srr_1 = msr;
1473 /* If we disactivated any translation, flush TLBs */
1474 if (msr_ir || msr_dr) {
1475 tlb_flush(env, 1);
1476 }
9a64fbe4 1477 /* reload MSR with correct bits */
9a64fbe4
FB		 1478 msr_ee = 0;
1479 msr_pr = 0;
1480 msr_fp = 0;
1481 msr_fe0 = 0;
1482 msr_se = 0;
1483 msr_be = 0;
1484 msr_fe1 = 0;
1485 msr_ir = 0;
1486 msr_dr = 0;
1487 msr_ri = 0;
1488 msr_le = msr_ile;
2be0071f 1489 msr_sf = msr_isf;
3fc6c082 1490 do_compute_hflags(env);
9a64fbe4 1491 /* Jump to handler */
2be0071f 1492 env->nip = excp;
9a64fbe4 1493 env->exception_index = EXCP_NONE;
9a64fbe4
FB		 1494 /* ensure that no TB jump will be modified as
1495 the program flow was changed */
1496#ifdef __sparc__
1497 tmp_T0 = 0;
1498#else
1499 T0 = 0;
9a64fbe4 1500#endif
2be0071f 1501 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
fb0eaffc 1502}
18fba28c 1503#endif /* !CONFIG_USER_ONLY */
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