]> Git Repo - qemu.git/blame - target/sparc/translate.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20171025' into staging
[qemu.git] / target / sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <[email protected]>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
57fec1fe 27#include "tcg-op.h"
f08b6170 28#include "exec/cpu_ldst.h"
7a3f1944 29
2ef6175a 30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
0cc1f4bf 34#include "asi.h"
a7e30d84
LV		 35
36
7a3f1944
FB		 37#define DEBUG_DISAS
38
72cbca10
FB		 39#define DYNAMIC_PC 1 /* dynamic pc value */
40#define JUMP_PC 2 /* dynamic pc value which takes only two values
41 according to jump_pc[T2] */
42
1a2fb1c0 43/* global register indexes */
1bcea73e 44static TCGv_ptr cpu_regwptr;
25517f99
PB		 45static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
46static TCGv_i32 cpu_cc_op;
a7812ae4 47static TCGv_i32 cpu_psr;
d2dc4069
RH		 48static TCGv cpu_fsr, cpu_pc, cpu_npc;
49static TCGv cpu_regs[32];
255e1fcb
BS		 50static TCGv cpu_y;
51#ifndef CONFIG_USER_ONLY
52static TCGv cpu_tbr;
53#endif
5793f2a4 54static TCGv cpu_cond;
dc99a3f2 55#ifdef TARGET_SPARC64
a6d567e5 56static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 57static TCGv cpu_gsr;
255e1fcb 58static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4 59static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
255e1fcb
BS		 60#else
61static TCGv cpu_wim;
dc99a3f2 62#endif
714547bb 63/* Floating point registers */
30038fd8 64static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 65
022c62cb 66#include "exec/gen-icount.h"
2e70f6ef 67
7a3f1944 68typedef struct DisasContext {
0f8a249a
BS		 69 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
70 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 71 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 72 int is_br;
e8af50a3 73 int mem_idx;
c9b459aa
AT		 74 bool fpu_enabled;
75 bool address_mask_32bit;
76 bool singlestep;
77#ifndef CONFIG_USER_ONLY
78 bool supervisor;
79#ifdef TARGET_SPARC64
80 bool hypervisor;
81#endif
82#endif
83
8393617c 84 uint32_t cc_op; /* current CC operation */
cf495bcf 85 struct TranslationBlock *tb;
5578ceab 86 sparc_def_t *def;
30038fd8 87 TCGv_i32 t32[3];
88023616 88 TCGv ttl[5];
30038fd8 89 int n_t32;
88023616 90 int n_ttl;
a6d567e5 91#ifdef TARGET_SPARC64
f9c816c0 92 int fprs_dirty;
a6d567e5
RH		 93 int asi;
94#endif
7a3f1944
FB		 95} DisasContext;
96
416fcaea
RH		 97typedef struct {
98 TCGCond cond;
99 bool is_bool;
100 bool g1, g2;
101 TCGv c1, c2;
102} DisasCompare;
103
3475187d 104// This function uses non-native bit order
dc1a6971
BS		 105#define GET_FIELD(X, FROM, TO) \
106 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 107
3475187d 108// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 109#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 110 GET_FIELD(X, 31 - (TO), 31 - (FROM))
111
112#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 113#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 114
115#ifdef TARGET_SPARC64
0387d928 116#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 117#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 118#else
c185970a 119#define DFPREG(r) (r & 0x1e)
1f587329 120#define QFPREG(r) (r & 0x1c)
3475187d
FB		 121#endif
122
b158a785
BS		 123#define UA2005_HTRAP_MASK 0xff
124#define V8_TRAP_MASK 0x7f
125
3475187d
FB		 126static int sign_extend(int x, int len)
127{
128 len = 32 - len;
129 return (x << len) >> len;
130}
131
7a3f1944
FB		 132#define IS_IMM (insn & (1<<13))
133
2ae23e17
RH		 134static inline TCGv_i32 get_temp_i32(DisasContext *dc)
135{
136 TCGv_i32 t;
137 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
138 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
139 return t;
140}
141
142static inline TCGv get_temp_tl(DisasContext *dc)
143{
144 TCGv t;
145 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
146 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
147 return t;
148}
149
f9c816c0 150static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
141ae5c1
RH		 151{
152#if defined(TARGET_SPARC64)
f9c816c0
RH		 153 int bit = (rd < 32) ? 1 : 2;
154 /* If we know we've already set this bit within the TB,
155 we can avoid setting it again. */
156 if (!(dc->fprs_dirty & bit)) {
157 dc->fprs_dirty |= bit;
158 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
159 }
141ae5c1
RH		 160#endif
161}
162
ff07ec83 163/* floating point registers moves */
208ae657
RH		 164static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
165{
30038fd8
RH		 166#if TCG_TARGET_REG_BITS == 32
167 if (src & 1) {
168 return TCGV_LOW(cpu_fpr[src / 2]);
169 } else {
170 return TCGV_HIGH(cpu_fpr[src / 2]);
171 }
172#else
dc41aa7d 173 TCGv_i32 ret = get_temp_i32(dc);
30038fd8 174 if (src & 1) {
dc41aa7d 175 tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 176 } else {
dc41aa7d 177 tcg_gen_extrh_i64_i32(ret, cpu_fpr[src / 2]);
30038fd8 178 }
dc41aa7d 179 return ret;
30038fd8 180#endif
208ae657
RH		 181}
182
183static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
184{
30038fd8
RH		 185#if TCG_TARGET_REG_BITS == 32
186 if (dst & 1) {
187 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
188 } else {
189 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
190 }
191#else
dc41aa7d 192 TCGv_i64 t = (TCGv_i64)v;
30038fd8
RH		 193 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
194 (dst & 1 ? 0 : 32), 32);
195#endif
f9c816c0 196 gen_update_fprs_dirty(dc, dst);
208ae657
RH		 197}
198
ba5f5179 199static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 200{
ba5f5179 201 return get_temp_i32(dc);
208ae657
RH		 202}
203
96eda024
RH		 204static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
205{
96eda024 206 src = DFPREG(src);
30038fd8 207 return cpu_fpr[src / 2];
96eda024
RH		 208}
209
210static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
211{
212 dst = DFPREG(dst);
30038fd8 213 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
f9c816c0 214 gen_update_fprs_dirty(dc, dst);
96eda024
RH		 215}
216
3886b8a3 217static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 218{
3886b8a3 219 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 220}
221
ff07ec83
BS		 222static void gen_op_load_fpr_QT0(unsigned int src)
223{
30038fd8
RH		 224 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
225 offsetof(CPU_QuadU, ll.upper));
226 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
227 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 228}
229
230static void gen_op_load_fpr_QT1(unsigned int src)
231{
30038fd8
RH		 232 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
233 offsetof(CPU_QuadU, ll.upper));
234 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
235 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 236}
237
238static void gen_op_store_QT0_fpr(unsigned int dst)
239{
30038fd8
RH		 240 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
241 offsetof(CPU_QuadU, ll.upper));
242 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
243 offsetof(CPU_QuadU, ll.lower));
ff07ec83 244}
1f587329 245
f939ffe5
RH		 246static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
247 TCGv_i64 v1, TCGv_i64 v2)
248{
249 dst = QFPREG(dst);
250
251 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
252 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
253 gen_update_fprs_dirty(dc, dst);
254}
255
ac11f776 256#ifdef TARGET_SPARC64
f939ffe5
RH		 257static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
258{
259 src = QFPREG(src);
260 return cpu_fpr[src / 2];
261}
262
263static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
264{
265 src = QFPREG(src);
266 return cpu_fpr[src / 2 + 1];
267}
268
f9c816c0 269static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
ac11f776
RH		 270{
271 rd = QFPREG(rd);
272 rs = QFPREG(rs);
273
30038fd8
RH		 274 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
275 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
f9c816c0 276 gen_update_fprs_dirty(dc, rd);
ac11f776
RH		 277}
278#endif
279
81ad8ba2
BS		 280/* moves */
281#ifdef CONFIG_USER_ONLY
3475187d 282#define supervisor(dc) 0
81ad8ba2 283#ifdef TARGET_SPARC64
e9ebed4d 284#define hypervisor(dc) 0
81ad8ba2 285#endif
3475187d 286#else
81ad8ba2 287#ifdef TARGET_SPARC64
c9b459aa
AT		 288#define hypervisor(dc) (dc->hypervisor)
289#define supervisor(dc) (dc->supervisor | dc->hypervisor)
6f27aba6 290#else
c9b459aa 291#define supervisor(dc) (dc->supervisor)
3475187d 292#endif
81ad8ba2
BS		 293#endif
294
2cade6a3
BS		 295#ifdef TARGET_SPARC64
296#ifndef TARGET_ABI32
297#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 298#else
2cade6a3
BS		 299#define AM_CHECK(dc) (1)
300#endif
1a2fb1c0 301#endif
3391c818 302
2cade6a3
BS		 303static inline void gen_address_mask(DisasContext *dc, TCGv addr)
304{
305#ifdef TARGET_SPARC64
306 if (AM_CHECK(dc))
307 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
308#endif
309}
310
88023616
RH		 311static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
312{
d2dc4069
RH		 313 if (reg > 0) {
314 assert(reg < 32);
315 return cpu_regs[reg];
316 } else {
88023616 317 TCGv t = get_temp_tl(dc);
d2dc4069 318 tcg_gen_movi_tl(t, 0);
88023616 319 return t;
88023616
RH		 320 }
321}
322
323static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
324{
325 if (reg > 0) {
d2dc4069
RH		 326 assert(reg < 32);
327 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 328 }
329}
330
331static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
332{
d2dc4069
RH		 333 if (reg > 0) {
334 assert(reg < 32);
335 return cpu_regs[reg];
88023616 336 } else {
d2dc4069 337 return get_temp_tl(dc);
88023616
RH		 338 }
339}
340
90aa39a1
SF		 341static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
342 target_ulong npc)
343{
344 if (unlikely(s->singlestep)) {
345 return false;
346 }
347
348#ifndef CONFIG_USER_ONLY
349 return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
350 (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
351#else
352 return true;
353#endif
354}
355
5fafdf24 356static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 357 target_ulong pc, target_ulong npc)
358{
90aa39a1 359 if (use_goto_tb(s, pc, npc)) {
6e256c93 360 /* jump to same page: we can use a direct jump */
57fec1fe 361 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 362 tcg_gen_movi_tl(cpu_pc, pc);
363 tcg_gen_movi_tl(cpu_npc, npc);
90aa39a1 364 tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
6e256c93
FB		 365 } else {
366 /* jump to another page: currently not optimized */
2f5680ee
BS		 367 tcg_gen_movi_tl(cpu_pc, pc);
368 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 369 tcg_gen_exit_tb(0);
6e256c93
FB		 370 }
371}
372
19f329ad 373// XXX suboptimal
a7812ae4 374static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 375{
8911f501 376 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 377 tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
19f329ad
BS		 378}
379
a7812ae4 380static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 381{
8911f501 382 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 383 tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
19f329ad
BS		 384}
385
a7812ae4 386static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 387{
8911f501 388 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 389 tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
19f329ad
BS		 390}
391
a7812ae4 392static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 393{
8911f501 394 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 395 tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
19f329ad
BS		 396}
397
4af984a7 398static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 399{
4af984a7 400 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 401 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 402 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 403 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 404}
405
70c48285 406static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 407{
70c48285
RH		 408 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
409
410 /* Carry is computed from a previous add: (dst < src) */
411#if TARGET_LONG_BITS == 64
412 cc_src1_32 = tcg_temp_new_i32();
413 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 414 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
415 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 416#else
417 cc_src1_32 = cpu_cc_dst;
418 cc_src2_32 = cpu_cc_src;
419#endif
420
421 carry_32 = tcg_temp_new_i32();
422 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
423
424#if TARGET_LONG_BITS == 64
425 tcg_temp_free_i32(cc_src1_32);
426 tcg_temp_free_i32(cc_src2_32);
427#endif
428
429 return carry_32;
41d72852
BS		 430}
431
70c48285 432static TCGv_i32 gen_sub32_carry32(void)
41d72852 433{
70c48285
RH		 434 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
435
436 /* Carry is computed from a previous borrow: (src1 < src2) */
437#if TARGET_LONG_BITS == 64
438 cc_src1_32 = tcg_temp_new_i32();
439 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 440 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
441 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 442#else
443 cc_src1_32 = cpu_cc_src;
444 cc_src2_32 = cpu_cc_src2;
445#endif
446
447 carry_32 = tcg_temp_new_i32();
448 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
449
450#if TARGET_LONG_BITS == 64
451 tcg_temp_free_i32(cc_src1_32);
452 tcg_temp_free_i32(cc_src2_32);
453#endif
454
455 return carry_32;
456}
457
458static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
459 TCGv src2, int update_cc)
460{
461 TCGv_i32 carry_32;
462 TCGv carry;
463
464 switch (dc->cc_op) {
465 case CC_OP_DIV:
466 case CC_OP_LOGIC:
467 /* Carry is known to be zero. Fall back to plain ADD. */
468 if (update_cc) {
469 gen_op_add_cc(dst, src1, src2);
470 } else {
471 tcg_gen_add_tl(dst, src1, src2);
472 }
473 return;
474
475 case CC_OP_ADD:
476 case CC_OP_TADD:
477 case CC_OP_TADDTV:
15fe216f
RH		 478 if (TARGET_LONG_BITS == 32) {
479 /* We can re-use the host's hardware carry generation by using
480 an ADD2 opcode. We discard the low part of the output.
481 Ideally we'd combine this operation with the add that
482 generated the carry in the first place. */
483 carry = tcg_temp_new();
484 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
485 tcg_temp_free(carry);
70c48285
RH		 486 goto add_done;
487 }
70c48285
RH		 488 carry_32 = gen_add32_carry32();
489 break;
490
491 case CC_OP_SUB:
492 case CC_OP_TSUB:
493 case CC_OP_TSUBTV:
494 carry_32 = gen_sub32_carry32();
495 break;
496
497 default:
498 /* We need external help to produce the carry. */
499 carry_32 = tcg_temp_new_i32();
2ffd9176 500 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 501 break;
502 }
503
504#if TARGET_LONG_BITS == 64
505 carry = tcg_temp_new();
506 tcg_gen_extu_i32_i64(carry, carry_32);
507#else
508 carry = carry_32;
509#endif
510
511 tcg_gen_add_tl(dst, src1, src2);
512 tcg_gen_add_tl(dst, dst, carry);
513
514 tcg_temp_free_i32(carry_32);
515#if TARGET_LONG_BITS == 64
516 tcg_temp_free(carry);
517#endif
518
70c48285 519 add_done:
70c48285
RH		 520 if (update_cc) {
521 tcg_gen_mov_tl(cpu_cc_src, src1);
522 tcg_gen_mov_tl(cpu_cc_src2, src2);
523 tcg_gen_mov_tl(cpu_cc_dst, dst);
524 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
525 dc->cc_op = CC_OP_ADDX;
526 }
dc99a3f2
BS		 527}
528
41d72852 529static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 530{
4af984a7 531 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 532 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 533 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 534 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 535}
536
70c48285
RH		 537static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
538 TCGv src2, int update_cc)
41d72852 539{
70c48285
RH		 540 TCGv_i32 carry_32;
541 TCGv carry;
41d72852 542
70c48285
RH		 543 switch (dc->cc_op) {
544 case CC_OP_DIV:
545 case CC_OP_LOGIC:
546 /* Carry is known to be zero. Fall back to plain SUB. */
547 if (update_cc) {
548 gen_op_sub_cc(dst, src1, src2);
549 } else {
550 tcg_gen_sub_tl(dst, src1, src2);
551 }
552 return;
553
554 case CC_OP_ADD:
555 case CC_OP_TADD:
556 case CC_OP_TADDTV:
557 carry_32 = gen_add32_carry32();
558 break;
559
560 case CC_OP_SUB:
561 case CC_OP_TSUB:
562 case CC_OP_TSUBTV:
15fe216f
RH		 563 if (TARGET_LONG_BITS == 32) {
564 /* We can re-use the host's hardware carry generation by using
565 a SUB2 opcode. We discard the low part of the output.
566 Ideally we'd combine this operation with the add that
567 generated the carry in the first place. */
568 carry = tcg_temp_new();
569 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
570 tcg_temp_free(carry);
70c48285
RH		 571 goto sub_done;
572 }
70c48285
RH		 573 carry_32 = gen_sub32_carry32();
574 break;
575
576 default:
577 /* We need external help to produce the carry. */
578 carry_32 = tcg_temp_new_i32();
2ffd9176 579 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 580 break;
581 }
582
583#if TARGET_LONG_BITS == 64
584 carry = tcg_temp_new();
585 tcg_gen_extu_i32_i64(carry, carry_32);
586#else
587 carry = carry_32;
588#endif
589
590 tcg_gen_sub_tl(dst, src1, src2);
591 tcg_gen_sub_tl(dst, dst, carry);
592
593 tcg_temp_free_i32(carry_32);
594#if TARGET_LONG_BITS == 64
595 tcg_temp_free(carry);
596#endif
597
70c48285 598 sub_done:
70c48285
RH		 599 if (update_cc) {
600 tcg_gen_mov_tl(cpu_cc_src, src1);
601 tcg_gen_mov_tl(cpu_cc_src2, src2);
602 tcg_gen_mov_tl(cpu_cc_dst, dst);
603 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
604 dc->cc_op = CC_OP_SUBX;
605 }
dc99a3f2
BS		 606}
607
4af984a7 608static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 609{
de9e9d9f 610 TCGv r_temp, zero, t0;
d9bdab86 611
a7812ae4 612 r_temp = tcg_temp_new();
de9e9d9f 613 t0 = tcg_temp_new();
d9bdab86
BS		 614
615 /* old op:
616 if (!(env->y & 1))
617 T1 = 0;
618 */
6cb675b0 619 zero = tcg_const_tl(0);
72ccba79 620 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 621 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 622 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 623 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
624 zero, cpu_cc_src2);
625 tcg_temp_free(zero);
d9bdab86
BS		 626
627 // b2 = T0 & 1;
628 // env->y = (b2 << 31) | (env->y >> 1);
0b1183e3 629 tcg_gen_extract_tl(t0, cpu_y, 1, 31);
08d64e0d 630 tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
d9bdab86
BS		 631
632 // b1 = N ^ V;
de9e9d9f 633 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 634 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 635 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 636 tcg_temp_free(r_temp);
d9bdab86
BS		 637
638 // T0 = (b1 << 31) | (T0 >> 1);
639 // src1 = T0;
de9e9d9f 640 tcg_gen_shli_tl(t0, t0, 31);
6f551262 641 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 642 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
643 tcg_temp_free(t0);
d9bdab86 644
5c6a0628 645 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 646
5c6a0628 647 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 648}
649
fb170183 650static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 651{
528692a8 652#if TARGET_LONG_BITS == 32
fb170183 653 if (sign_ext) {
528692a8 654 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 655 } else {
528692a8 656 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 657 }
528692a8
RH		 658#else
659 TCGv t0 = tcg_temp_new_i64();
660 TCGv t1 = tcg_temp_new_i64();
fb170183 661
528692a8
RH		 662 if (sign_ext) {
663 tcg_gen_ext32s_i64(t0, src1);
664 tcg_gen_ext32s_i64(t1, src2);
665 } else {
666 tcg_gen_ext32u_i64(t0, src1);
667 tcg_gen_ext32u_i64(t1, src2);
668 }
fb170183 669
528692a8
RH		 670 tcg_gen_mul_i64(dst, t0, t1);
671 tcg_temp_free(t0);
672 tcg_temp_free(t1);
fb170183 673
528692a8
RH		 674 tcg_gen_shri_i64(cpu_y, dst, 32);
675#endif
8879d139
BS		 676}
677
fb170183 678static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 679{
fb170183
IK		 680 /* zero-extend truncated operands before multiplication */
681 gen_op_multiply(dst, src1, src2, 0);
682}
8879d139 683
fb170183
IK		 684static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
685{
686 /* sign-extend truncated operands before multiplication */
687 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 688}
689
19f329ad
BS		 690// 1
691static inline void gen_op_eval_ba(TCGv dst)
692{
693 tcg_gen_movi_tl(dst, 1);
694}
695
696// Z
a7812ae4 697static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 698{
699 gen_mov_reg_Z(dst, src);
700}
701
702// Z | (N ^ V)
a7812ae4 703static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 704{
de9e9d9f
RH		 705 TCGv t0 = tcg_temp_new();
706 gen_mov_reg_N(t0, src);
19f329ad 707 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 708 tcg_gen_xor_tl(dst, dst, t0);
709 gen_mov_reg_Z(t0, src);
710 tcg_gen_or_tl(dst, dst, t0);
711 tcg_temp_free(t0);
19f329ad
BS		 712}
713
714// N ^ V
a7812ae4 715static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 716{
de9e9d9f
RH		 717 TCGv t0 = tcg_temp_new();
718 gen_mov_reg_V(t0, src);
19f329ad 719 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 720 tcg_gen_xor_tl(dst, dst, t0);
721 tcg_temp_free(t0);
19f329ad
BS		 722}
723
724// C | Z
a7812ae4 725static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 726{
de9e9d9f
RH		 727 TCGv t0 = tcg_temp_new();
728 gen_mov_reg_Z(t0, src);
19f329ad 729 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 730 tcg_gen_or_tl(dst, dst, t0);
731 tcg_temp_free(t0);
19f329ad
BS		 732}
733
734// C
a7812ae4 735static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 736{
737 gen_mov_reg_C(dst, src);
738}
739
740// V
a7812ae4 741static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 742{
743 gen_mov_reg_V(dst, src);
744}
745
746// 0
747static inline void gen_op_eval_bn(TCGv dst)
748{
749 tcg_gen_movi_tl(dst, 0);
750}
751
752// N
a7812ae4 753static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 754{
755 gen_mov_reg_N(dst, src);
756}
757
758// !Z
a7812ae4 759static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 760{
761 gen_mov_reg_Z(dst, src);
762 tcg_gen_xori_tl(dst, dst, 0x1);
763}
764
765// !(Z | (N ^ V))
a7812ae4 766static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 767{
de9e9d9f 768 gen_op_eval_ble(dst, src);
19f329ad
BS		 769 tcg_gen_xori_tl(dst, dst, 0x1);
770}
771
772// !(N ^ V)
a7812ae4 773static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 774{
de9e9d9f 775 gen_op_eval_bl(dst, src);
19f329ad
BS		 776 tcg_gen_xori_tl(dst, dst, 0x1);
777}
778
779// !(C | Z)
a7812ae4 780static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 781{
de9e9d9f 782 gen_op_eval_bleu(dst, src);
19f329ad
BS		 783 tcg_gen_xori_tl(dst, dst, 0x1);
784}
785
786// !C
a7812ae4 787static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 788{
789 gen_mov_reg_C(dst, src);
790 tcg_gen_xori_tl(dst, dst, 0x1);
791}
792
793// !N
a7812ae4 794static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 795{
796 gen_mov_reg_N(dst, src);
797 tcg_gen_xori_tl(dst, dst, 0x1);
798}
799
800// !V
a7812ae4 801static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 802{
803 gen_mov_reg_V(dst, src);
804 tcg_gen_xori_tl(dst, dst, 0x1);
805}
806
807/*
808 FPSR bit field FCC1 | FCC0:
809 0 =
810 1 <
811 2 >
812 3 unordered
813*/
814static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
815 unsigned int fcc_offset)
816{
ba6a9d8c 817 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 818 tcg_gen_andi_tl(reg, reg, 0x1);
819}
820
821static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
822 unsigned int fcc_offset)
823{
ba6a9d8c 824 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 825 tcg_gen_andi_tl(reg, reg, 0x1);
826}
827
828// !0: FCC0 | FCC1
829static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
830 unsigned int fcc_offset)
831{
de9e9d9f 832 TCGv t0 = tcg_temp_new();
19f329ad 833 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 834 gen_mov_reg_FCC1(t0, src, fcc_offset);
835 tcg_gen_or_tl(dst, dst, t0);
836 tcg_temp_free(t0);
19f329ad
BS		 837}
838
839// 1 or 2: FCC0 ^ FCC1
840static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
841 unsigned int fcc_offset)
842{
de9e9d9f 843 TCGv t0 = tcg_temp_new();
19f329ad 844 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 845 gen_mov_reg_FCC1(t0, src, fcc_offset);
846 tcg_gen_xor_tl(dst, dst, t0);
847 tcg_temp_free(t0);
19f329ad
BS		 848}
849
850// 1 or 3: FCC0
851static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
852 unsigned int fcc_offset)
853{
854 gen_mov_reg_FCC0(dst, src, fcc_offset);
855}
856
857// 1: FCC0 & !FCC1
858static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
859 unsigned int fcc_offset)
860{
de9e9d9f 861 TCGv t0 = tcg_temp_new();
19f329ad 862 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 863 gen_mov_reg_FCC1(t0, src, fcc_offset);
864 tcg_gen_andc_tl(dst, dst, t0);
865 tcg_temp_free(t0);
19f329ad
BS		 866}
867
868// 2 or 3: FCC1
869static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
870 unsigned int fcc_offset)
871{
872 gen_mov_reg_FCC1(dst, src, fcc_offset);
873}
874
875// 2: !FCC0 & FCC1
876static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
877 unsigned int fcc_offset)
878{
de9e9d9f 879 TCGv t0 = tcg_temp_new();
19f329ad 880 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 881 gen_mov_reg_FCC1(t0, src, fcc_offset);
882 tcg_gen_andc_tl(dst, t0, dst);
883 tcg_temp_free(t0);
19f329ad
BS		 884}
885
886// 3: FCC0 & FCC1
887static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
888 unsigned int fcc_offset)
889{
de9e9d9f 890 TCGv t0 = tcg_temp_new();
19f329ad 891 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 892 gen_mov_reg_FCC1(t0, src, fcc_offset);
893 tcg_gen_and_tl(dst, dst, t0);
894 tcg_temp_free(t0);
19f329ad
BS		 895}
896
897// 0: !(FCC0 | FCC1)
898static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
899 unsigned int fcc_offset)
900{
de9e9d9f 901 TCGv t0 = tcg_temp_new();
19f329ad 902 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 903 gen_mov_reg_FCC1(t0, src, fcc_offset);
904 tcg_gen_or_tl(dst, dst, t0);
19f329ad 905 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 906 tcg_temp_free(t0);
19f329ad
BS		 907}
908
909// 0 or 3: !(FCC0 ^ FCC1)
910static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
911 unsigned int fcc_offset)
912{
de9e9d9f 913 TCGv t0 = tcg_temp_new();
19f329ad 914 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 915 gen_mov_reg_FCC1(t0, src, fcc_offset);
916 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 917 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 918 tcg_temp_free(t0);
19f329ad
BS		 919}
920
921// 0 or 2: !FCC0
922static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
923 unsigned int fcc_offset)
924{
925 gen_mov_reg_FCC0(dst, src, fcc_offset);
926 tcg_gen_xori_tl(dst, dst, 0x1);
927}
928
929// !1: !(FCC0 & !FCC1)
930static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
931 unsigned int fcc_offset)
932{
de9e9d9f 933 TCGv t0 = tcg_temp_new();
19f329ad 934 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 935 gen_mov_reg_FCC1(t0, src, fcc_offset);
936 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 937 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 938 tcg_temp_free(t0);
19f329ad
BS		 939}
940
941// 0 or 1: !FCC1
942static inline void gen_op_eval_fble(TCGv dst, TCGv src,
943 unsigned int fcc_offset)
944{
945 gen_mov_reg_FCC1(dst, src, fcc_offset);
946 tcg_gen_xori_tl(dst, dst, 0x1);
947}
948
949// !2: !(!FCC0 & FCC1)
950static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
951 unsigned int fcc_offset)
952{
de9e9d9f 953 TCGv t0 = tcg_temp_new();
19f329ad 954 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 955 gen_mov_reg_FCC1(t0, src, fcc_offset);
956 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 957 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 958 tcg_temp_free(t0);
19f329ad
BS		 959}
960
961// !3: !(FCC0 & FCC1)
962static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
963 unsigned int fcc_offset)
964{
de9e9d9f 965 TCGv t0 = tcg_temp_new();
19f329ad 966 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 967 gen_mov_reg_FCC1(t0, src, fcc_offset);
968 tcg_gen_and_tl(dst, dst, t0);
19f329ad 969 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 970 tcg_temp_free(t0);
19f329ad
BS		 971}
972
46525e1f 973static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 974 target_ulong pc2, TCGv r_cond)
83469015 975{
42a268c2 976 TCGLabel *l1 = gen_new_label();
83469015 977
cb63669a 978 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 979
6e256c93 980 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 981
982 gen_set_label(l1);
6e256c93 983 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 984}
985
bfa31b76 986static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 987{
42a268c2 988 TCGLabel *l1 = gen_new_label();
bfa31b76 989 target_ulong npc = dc->npc;
83469015 990
bfa31b76 991 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 992
bfa31b76 993 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 994
995 gen_set_label(l1);
bfa31b76
RH		 996 gen_goto_tb(dc, 1, npc + 4, npc + 8);
997
998 dc->is_br = 1;
83469015
FB		 999}
1000
2bf2e019
RH		 1001static void gen_branch_n(DisasContext *dc, target_ulong pc1)
1002{
1003 target_ulong npc = dc->npc;
1004
1005 if (likely(npc != DYNAMIC_PC)) {
1006 dc->pc = npc;
1007 dc->jump_pc[0] = pc1;
1008 dc->jump_pc[1] = npc + 4;
1009 dc->npc = JUMP_PC;
1010 } else {
1011 TCGv t, z;
1012
1013 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1014
1015 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1016 t = tcg_const_tl(pc1);
1017 z = tcg_const_tl(0);
1018 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
1019 tcg_temp_free(t);
1020 tcg_temp_free(z);
1021
1022 dc->pc = DYNAMIC_PC;
1023 }
1024}
1025
2e655fe7 1026static inline void gen_generic_branch(DisasContext *dc)
83469015 1027{
61316742
RH		 1028 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1029 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1030 TCGv zero = tcg_const_tl(0);
19f329ad 1031
61316742 1032 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1033
61316742
RH		 1034 tcg_temp_free(npc0);
1035 tcg_temp_free(npc1);
1036 tcg_temp_free(zero);
83469015
FB		 1037}
1038
4af984a7
BS		 1039/* call this function before using the condition register as it may
1040 have been set for a jump */
dee8913c 1041static inline void flush_cond(DisasContext *dc)
83469015
FB		 1042{
1043 if (dc->npc == JUMP_PC) {
2e655fe7 1044 gen_generic_branch(dc);
83469015
FB		 1045 dc->npc = DYNAMIC_PC;
1046 }
1047}
1048
934da7ee 1049static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1050{
1051 if (dc->npc == JUMP_PC) {
2e655fe7 1052 gen_generic_branch(dc);
72cbca10
FB		 1053 dc->npc = DYNAMIC_PC;
1054 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1055 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1056 }
1057}
1058
20132b96 1059static inline void update_psr(DisasContext *dc)
72cbca10 1060{
cfa90513
BS		 1061 if (dc->cc_op != CC_OP_FLAGS) {
1062 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1063 gen_helper_compute_psr(cpu_env);
cfa90513 1064 }
20132b96
RH		 1065}
1066
1067static inline void save_state(DisasContext *dc)
1068{
1069 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1070 save_npc(dc);
72cbca10
FB		 1071}
1072
4fbe0067
RH		 1073static void gen_exception(DisasContext *dc, int which)
1074{
1075 TCGv_i32 t;
1076
1077 save_state(dc);
1078 t = tcg_const_i32(which);
1079 gen_helper_raise_exception(cpu_env, t);
1080 tcg_temp_free_i32(t);
1081 dc->is_br = 1;
1082}
1083
35e94905
RH		 1084static void gen_check_align(TCGv addr, int mask)
1085{
1086 TCGv_i32 r_mask = tcg_const_i32(mask);
1087 gen_helper_check_align(cpu_env, addr, r_mask);
1088 tcg_temp_free_i32(r_mask);
1089}
1090
13a6dd00 1091static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1092{
1093 if (dc->npc == JUMP_PC) {
2e655fe7 1094 gen_generic_branch(dc);
48d5c82b 1095 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1096 dc->pc = DYNAMIC_PC;
1097 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1098 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1099 dc->pc = DYNAMIC_PC;
1100 } else {
1101 dc->pc = dc->npc;
1102 }
1103}
1104
38bc628b
BS		 1105static inline void gen_op_next_insn(void)
1106{
48d5c82b
BS		 1107 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1108 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1109}
1110
416fcaea
RH		 1111static void free_compare(DisasCompare *cmp)
1112{
1113 if (!cmp->g1) {
1114 tcg_temp_free(cmp->c1);
1115 }
1116 if (!cmp->g2) {
1117 tcg_temp_free(cmp->c2);
1118 }
1119}
1120
2a484ecf 1121static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1122 DisasContext *dc)
19f329ad 1123{
2a484ecf 1124 static int subcc_cond[16] = {
96b5a3d3 1125 TCG_COND_NEVER,
2a484ecf
RH		 1126 TCG_COND_EQ,
1127 TCG_COND_LE,
1128 TCG_COND_LT,
1129 TCG_COND_LEU,
1130 TCG_COND_LTU,
1131 -1, /* neg */
1132 -1, /* overflow */
96b5a3d3 1133 TCG_COND_ALWAYS,
2a484ecf
RH		 1134 TCG_COND_NE,
1135 TCG_COND_GT,
1136 TCG_COND_GE,
1137 TCG_COND_GTU,
1138 TCG_COND_GEU,
1139 -1, /* pos */
1140 -1, /* no overflow */
1141 };
1142
96b5a3d3
RH		 1143 static int logic_cond[16] = {
1144 TCG_COND_NEVER,
1145 TCG_COND_EQ, /* eq: Z */
1146 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1147 TCG_COND_LT, /* lt: N ^ V -> N */
1148 TCG_COND_EQ, /* leu: C | Z -> Z */
1149 TCG_COND_NEVER, /* ltu: C -> 0 */
1150 TCG_COND_LT, /* neg: N */
1151 TCG_COND_NEVER, /* vs: V -> 0 */
1152 TCG_COND_ALWAYS,
1153 TCG_COND_NE, /* ne: !Z */
1154 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1155 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1156 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1157 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1158 TCG_COND_GE, /* pos: !N */
1159 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1160 };
1161
a7812ae4 1162 TCGv_i32 r_src;
416fcaea
RH		 1163 TCGv r_dst;
1164
3475187d 1165#ifdef TARGET_SPARC64
2a484ecf 1166 if (xcc) {
dc99a3f2 1167 r_src = cpu_xcc;
2a484ecf 1168 } else {
dc99a3f2 1169 r_src = cpu_psr;
2a484ecf 1170 }
3475187d 1171#else
dc99a3f2 1172 r_src = cpu_psr;
3475187d 1173#endif
2a484ecf 1174
8393617c 1175 switch (dc->cc_op) {
96b5a3d3
RH		 1176 case CC_OP_LOGIC:
1177 cmp->cond = logic_cond[cond];
1178 do_compare_dst_0:
1179 cmp->is_bool = false;
1180 cmp->g2 = false;
1181 cmp->c2 = tcg_const_tl(0);
1182#ifdef TARGET_SPARC64
1183 if (!xcc) {
1184 cmp->g1 = false;
1185 cmp->c1 = tcg_temp_new();
1186 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1187 break;
1188 }
1189#endif
1190 cmp->g1 = true;
1191 cmp->c1 = cpu_cc_dst;
1192 break;
1193
2a484ecf
RH		 1194 case CC_OP_SUB:
1195 switch (cond) {
1196 case 6: /* neg */
1197 case 14: /* pos */
1198 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1199 goto do_compare_dst_0;
2a484ecf 1200
2a484ecf
RH		 1201 case 7: /* overflow */
1202 case 15: /* !overflow */
1203 goto do_dynamic;
1204
1205 default:
1206 cmp->cond = subcc_cond[cond];
1207 cmp->is_bool = false;
1208#ifdef TARGET_SPARC64
1209 if (!xcc) {
1210 /* Note that sign-extension works for unsigned compares as
1211 long as both operands are sign-extended. */
1212 cmp->g1 = cmp->g2 = false;
1213 cmp->c1 = tcg_temp_new();
1214 cmp->c2 = tcg_temp_new();
1215 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1216 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1217 break;
2a484ecf
RH		 1218 }
1219#endif
1220 cmp->g1 = cmp->g2 = true;
1221 cmp->c1 = cpu_cc_src;
1222 cmp->c2 = cpu_cc_src2;
1223 break;
1224 }
8393617c 1225 break;
2a484ecf 1226
8393617c 1227 default:
2a484ecf 1228 do_dynamic:
2ffd9176 1229 gen_helper_compute_psr(cpu_env);
8393617c 1230 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1231 /* FALLTHRU */
1232
1233 case CC_OP_FLAGS:
1234 /* We're going to generate a boolean result. */
1235 cmp->cond = TCG_COND_NE;
1236 cmp->is_bool = true;
1237 cmp->g1 = cmp->g2 = false;
1238 cmp->c1 = r_dst = tcg_temp_new();
1239 cmp->c2 = tcg_const_tl(0);
1240
1241 switch (cond) {
1242 case 0x0:
1243 gen_op_eval_bn(r_dst);
1244 break;
1245 case 0x1:
1246 gen_op_eval_be(r_dst, r_src);
1247 break;
1248 case 0x2:
1249 gen_op_eval_ble(r_dst, r_src);
1250 break;
1251 case 0x3:
1252 gen_op_eval_bl(r_dst, r_src);
1253 break;
1254 case 0x4:
1255 gen_op_eval_bleu(r_dst, r_src);
1256 break;
1257 case 0x5:
1258 gen_op_eval_bcs(r_dst, r_src);
1259 break;
1260 case 0x6:
1261 gen_op_eval_bneg(r_dst, r_src);
1262 break;
1263 case 0x7:
1264 gen_op_eval_bvs(r_dst, r_src);
1265 break;
1266 case 0x8:
1267 gen_op_eval_ba(r_dst);
1268 break;
1269 case 0x9:
1270 gen_op_eval_bne(r_dst, r_src);
1271 break;
1272 case 0xa:
1273 gen_op_eval_bg(r_dst, r_src);
1274 break;
1275 case 0xb:
1276 gen_op_eval_bge(r_dst, r_src);
1277 break;
1278 case 0xc:
1279 gen_op_eval_bgu(r_dst, r_src);
1280 break;
1281 case 0xd:
1282 gen_op_eval_bcc(r_dst, r_src);
1283 break;
1284 case 0xe:
1285 gen_op_eval_bpos(r_dst, r_src);
1286 break;
1287 case 0xf:
1288 gen_op_eval_bvc(r_dst, r_src);
1289 break;
1290 }
19f329ad
BS		 1291 break;
1292 }
1293}
7a3f1944 1294
416fcaea 1295static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1296{
19f329ad 1297 unsigned int offset;
416fcaea
RH		 1298 TCGv r_dst;
1299
1300 /* For now we still generate a straight boolean result. */
1301 cmp->cond = TCG_COND_NE;
1302 cmp->is_bool = true;
1303 cmp->g1 = cmp->g2 = false;
1304 cmp->c1 = r_dst = tcg_temp_new();
1305 cmp->c2 = tcg_const_tl(0);
19f329ad 1306
19f329ad
BS		 1307 switch (cc) {
1308 default:
1309 case 0x0:
1310 offset = 0;
1311 break;
1312 case 0x1:
1313 offset = 32 - 10;
1314 break;
1315 case 0x2:
1316 offset = 34 - 10;
1317 break;
1318 case 0x3:
1319 offset = 36 - 10;
1320 break;
1321 }
1322
1323 switch (cond) {
1324 case 0x0:
1325 gen_op_eval_bn(r_dst);
1326 break;
1327 case 0x1:
87e92502 1328 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1329 break;
1330 case 0x2:
87e92502 1331 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1332 break;
1333 case 0x3:
87e92502 1334 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1335 break;
1336 case 0x4:
87e92502 1337 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1338 break;
1339 case 0x5:
87e92502 1340 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1341 break;
1342 case 0x6:
87e92502 1343 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1344 break;
1345 case 0x7:
87e92502 1346 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1347 break;
1348 case 0x8:
1349 gen_op_eval_ba(r_dst);
1350 break;
1351 case 0x9:
87e92502 1352 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1353 break;
1354 case 0xa:
87e92502 1355 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1356 break;
1357 case 0xb:
87e92502 1358 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1359 break;
1360 case 0xc:
87e92502 1361 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1362 break;
1363 case 0xd:
87e92502 1364 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1365 break;
1366 case 0xe:
87e92502 1367 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1368 break;
1369 case 0xf:
87e92502 1370 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1371 break;
1372 }
e8af50a3 1373}
00f219bf 1374
416fcaea
RH		 1375static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1376 DisasContext *dc)
1377{
1378 DisasCompare cmp;
1379 gen_compare(&cmp, cc, cond, dc);
1380
1381 /* The interface is to return a boolean in r_dst. */
1382 if (cmp.is_bool) {
1383 tcg_gen_mov_tl(r_dst, cmp.c1);
1384 } else {
1385 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1386 }
1387
1388 free_compare(&cmp);
1389}
1390
1391static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1392{
1393 DisasCompare cmp;
1394 gen_fcompare(&cmp, cc, cond);
1395
1396 /* The interface is to return a boolean in r_dst. */
1397 if (cmp.is_bool) {
1398 tcg_gen_mov_tl(r_dst, cmp.c1);
1399 } else {
1400 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1401 }
1402
1403 free_compare(&cmp);
1404}
1405
19f329ad 1406#ifdef TARGET_SPARC64
00f219bf
BS		 1407// Inverted logic
1408static const int gen_tcg_cond_reg[8] = {
1409 -1,
1410 TCG_COND_NE,
1411 TCG_COND_GT,
1412 TCG_COND_GE,
1413 -1,
1414 TCG_COND_EQ,
1415 TCG_COND_LE,
1416 TCG_COND_LT,
1417};
19f329ad 1418
416fcaea
RH		 1419static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1420{
1421 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1422 cmp->is_bool = false;
1423 cmp->g1 = true;
1424 cmp->g2 = false;
1425 cmp->c1 = r_src;
1426 cmp->c2 = tcg_const_tl(0);
1427}
1428
4af984a7 1429static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1430{
416fcaea
RH		 1431 DisasCompare cmp;
1432 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1433
416fcaea
RH		 1434 /* The interface is to return a boolean in r_dst. */
1435 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1436
1437 free_compare(&cmp);
19f329ad 1438}
3475187d 1439#endif
cf495bcf 1440
d4a288ef 1441static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1442{
cf495bcf 1443 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1444 target_ulong target = dc->pc + offset;
5fafdf24 1445
22036a49
AT		 1446#ifdef TARGET_SPARC64
1447 if (unlikely(AM_CHECK(dc))) {
1448 target &= 0xffffffffULL;
1449 }
1450#endif
cf495bcf 1451 if (cond == 0x0) {
0f8a249a
BS		 1452 /* unconditional not taken */
1453 if (a) {
1454 dc->pc = dc->npc + 4;
1455 dc->npc = dc->pc + 4;
1456 } else {
1457 dc->pc = dc->npc;
1458 dc->npc = dc->pc + 4;
1459 }
cf495bcf 1460 } else if (cond == 0x8) {
0f8a249a
BS		 1461 /* unconditional taken */
1462 if (a) {
1463 dc->pc = target;
1464 dc->npc = dc->pc + 4;
1465 } else {
1466 dc->pc = dc->npc;
1467 dc->npc = target;
c27e2752 1468 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1469 }
cf495bcf 1470 } else {
dee8913c 1471 flush_cond(dc);
d4a288ef 1472 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1473 if (a) {
bfa31b76 1474 gen_branch_a(dc, target);
0f8a249a 1475 } else {
2bf2e019 1476 gen_branch_n(dc, target);
0f8a249a 1477 }
cf495bcf 1478 }
7a3f1944
FB		 1479}
1480
d4a288ef 1481static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1482{
1483 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1484 target_ulong target = dc->pc + offset;
1485
22036a49
AT		 1486#ifdef TARGET_SPARC64
1487 if (unlikely(AM_CHECK(dc))) {
1488 target &= 0xffffffffULL;
1489 }
1490#endif
e8af50a3 1491 if (cond == 0x0) {
0f8a249a
BS		 1492 /* unconditional not taken */
1493 if (a) {
1494 dc->pc = dc->npc + 4;
1495 dc->npc = dc->pc + 4;
1496 } else {
1497 dc->pc = dc->npc;
1498 dc->npc = dc->pc + 4;
1499 }
e8af50a3 1500 } else if (cond == 0x8) {
0f8a249a
BS		 1501 /* unconditional taken */
1502 if (a) {
1503 dc->pc = target;
1504 dc->npc = dc->pc + 4;
1505 } else {
1506 dc->pc = dc->npc;
1507 dc->npc = target;
c27e2752 1508 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1509 }
e8af50a3 1510 } else {
dee8913c 1511 flush_cond(dc);
d4a288ef 1512 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1513 if (a) {
bfa31b76 1514 gen_branch_a(dc, target);
0f8a249a 1515 } else {
2bf2e019 1516 gen_branch_n(dc, target);
0f8a249a 1517 }
e8af50a3
FB		 1518 }
1519}
1520
3475187d 1521#ifdef TARGET_SPARC64
4af984a7 1522static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1523 TCGv r_reg)
7a3f1944 1524{
3475187d
FB		 1525 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1526 target_ulong target = dc->pc + offset;
1527
22036a49
AT		 1528 if (unlikely(AM_CHECK(dc))) {
1529 target &= 0xffffffffULL;
1530 }
dee8913c 1531 flush_cond(dc);
d4a288ef 1532 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1533 if (a) {
bfa31b76 1534 gen_branch_a(dc, target);
3475187d 1535 } else {
2bf2e019 1536 gen_branch_n(dc, target);
3475187d 1537 }
7a3f1944
FB		 1538}
1539
a7812ae4 1540static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1541{
714547bb
BS		 1542 switch (fccno) {
1543 case 0:
7385aed2 1544 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1545 break;
1546 case 1:
7385aed2 1547 gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1548 break;
1549 case 2:
7385aed2 1550 gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1551 break;
1552 case 3:
7385aed2 1553 gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1554 break;
1555 }
7e8c2b6c
BS		 1556}
1557
03fb8cfc 1558static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1559{
a7812ae4
PB		 1560 switch (fccno) {
1561 case 0:
7385aed2 1562 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1563 break;
1564 case 1:
7385aed2 1565 gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1566 break;
1567 case 2:
7385aed2 1568 gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1569 break;
1570 case 3:
7385aed2 1571 gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1572 break;
1573 }
7e8c2b6c
BS		 1574}
1575
7e8c2b6c
BS		 1576static inline void gen_op_fcmpq(int fccno)
1577{
a7812ae4
PB		 1578 switch (fccno) {
1579 case 0:
7385aed2 1580 gen_helper_fcmpq(cpu_fsr, cpu_env);
a7812ae4
PB		 1581 break;
1582 case 1:
7385aed2 1583 gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1584 break;
1585 case 2:
7385aed2 1586 gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1587 break;
1588 case 3:
7385aed2 1589 gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1590 break;
1591 }
7e8c2b6c 1592}
7e8c2b6c 1593
a7812ae4 1594static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1595{
714547bb
BS		 1596 switch (fccno) {
1597 case 0:
7385aed2 1598 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1599 break;
1600 case 1:
7385aed2 1601 gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1602 break;
1603 case 2:
7385aed2 1604 gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1605 break;
1606 case 3:
7385aed2 1607 gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1608 break;
1609 }
7e8c2b6c
BS		 1610}
1611
03fb8cfc 1612static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1613{
a7812ae4
PB		 1614 switch (fccno) {
1615 case 0:
7385aed2 1616 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1617 break;
1618 case 1:
7385aed2 1619 gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1620 break;
1621 case 2:
7385aed2 1622 gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1623 break;
1624 case 3:
7385aed2 1625 gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1626 break;
1627 }
7e8c2b6c
BS		 1628}
1629
7e8c2b6c
BS		 1630static inline void gen_op_fcmpeq(int fccno)
1631{
a7812ae4
PB		 1632 switch (fccno) {
1633 case 0:
7385aed2 1634 gen_helper_fcmpeq(cpu_fsr, cpu_env);
a7812ae4
PB		 1635 break;
1636 case 1:
7385aed2 1637 gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1638 break;
1639 case 2:
7385aed2 1640 gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1641 break;
1642 case 3:
7385aed2 1643 gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1644 break;
1645 }
7e8c2b6c 1646}
7e8c2b6c
BS		 1647
1648#else
1649
714547bb 1650static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1651{
7385aed2 1652 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1653}
1654
03fb8cfc 1655static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1656{
7385aed2 1657 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1658}
1659
7e8c2b6c
BS		 1660static inline void gen_op_fcmpq(int fccno)
1661{
7385aed2 1662 gen_helper_fcmpq(cpu_fsr, cpu_env);
7e8c2b6c 1663}
7e8c2b6c 1664
714547bb 1665static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1666{
7385aed2 1667 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1668}
1669
03fb8cfc 1670static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1671{
7385aed2 1672 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1673}
1674
7e8c2b6c
BS		 1675static inline void gen_op_fcmpeq(int fccno)
1676{
7385aed2 1677 gen_helper_fcmpeq(cpu_fsr, cpu_env);
7e8c2b6c
BS		 1678}
1679#endif
1680
4fbe0067 1681static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1682{
47ad35f1 1683 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1684 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1685 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1686}
1687
5b12f1e8 1688static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1689{
1690#if !defined(CONFIG_USER_ONLY)
1691 if (!dc->fpu_enabled) {
4fbe0067 1692 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1693 return 1;
1694 }
1695#endif
1696 return 0;
1697}
1698
7e8c2b6c
BS		 1699static inline void gen_op_clear_ieee_excp_and_FTT(void)
1700{
47ad35f1 1701 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1702}
1703
61f17f6e
RH		 1704static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1705 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1706{
1707 TCGv_i32 dst, src;
1708
61f17f6e 1709 src = gen_load_fpr_F(dc, rs);
ba5f5179 1710 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1711
1712 gen(dst, cpu_env, src);
7385aed2 1713 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1714
61f17f6e
RH		 1715 gen_store_fpr_F(dc, rd, dst);
1716}
1717
1718static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1719 void (*gen)(TCGv_i32, TCGv_i32))
1720{
1721 TCGv_i32 dst, src;
1722
1723 src = gen_load_fpr_F(dc, rs);
ba5f5179 1724 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1725
1726 gen(dst, src);
1727
1728 gen_store_fpr_F(dc, rd, dst);
1729}
1730
1731static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1732 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1733{
1734 TCGv_i32 dst, src1, src2;
1735
61f17f6e
RH		 1736 src1 = gen_load_fpr_F(dc, rs1);
1737 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1738 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1739
1740 gen(dst, cpu_env, src1, src2);
7385aed2 1741 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1742
61f17f6e
RH		 1743 gen_store_fpr_F(dc, rd, dst);
1744}
1745
1746#ifdef TARGET_SPARC64
1747static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1748 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1749{
1750 TCGv_i32 dst, src1, src2;
1751
1752 src1 = gen_load_fpr_F(dc, rs1);
1753 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1754 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1755
1756 gen(dst, src1, src2);
1757
1758 gen_store_fpr_F(dc, rd, dst);
1759}
1760#endif
1761
1762static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1763 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1764{
1765 TCGv_i64 dst, src;
1766
61f17f6e 1767 src = gen_load_fpr_D(dc, rs);
3886b8a3 1768 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1769
1770 gen(dst, cpu_env, src);
7385aed2 1771 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1772
61f17f6e
RH		 1773 gen_store_fpr_D(dc, rd, dst);
1774}
1775
1776#ifdef TARGET_SPARC64
1777static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1778 void (*gen)(TCGv_i64, TCGv_i64))
1779{
1780 TCGv_i64 dst, src;
1781
1782 src = gen_load_fpr_D(dc, rs);
3886b8a3 1783 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1784
1785 gen(dst, src);
1786
1787 gen_store_fpr_D(dc, rd, dst);
1788}
1789#endif
1790
1791static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1792 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1793{
1794 TCGv_i64 dst, src1, src2;
1795
61f17f6e
RH		 1796 src1 = gen_load_fpr_D(dc, rs1);
1797 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1798 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1799
1800 gen(dst, cpu_env, src1, src2);
7385aed2 1801 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1802
61f17f6e
RH		 1803 gen_store_fpr_D(dc, rd, dst);
1804}
1805
1806#ifdef TARGET_SPARC64
1807static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1808 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1809{
1810 TCGv_i64 dst, src1, src2;
1811
1812 src1 = gen_load_fpr_D(dc, rs1);
1813 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1814 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1815
1816 gen(dst, src1, src2);
1817
1818 gen_store_fpr_D(dc, rd, dst);
1819}
f888300b 1820
2dedf314
RH		 1821static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1822 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1823{
1824 TCGv_i64 dst, src1, src2;
1825
1826 src1 = gen_load_fpr_D(dc, rs1);
1827 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1828 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1829
1830 gen(dst, cpu_gsr, src1, src2);
1831
1832 gen_store_fpr_D(dc, rd, dst);
1833}
1834
f888300b
RH		 1835static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1836 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1837{
1838 TCGv_i64 dst, src0, src1, src2;
1839
1840 src1 = gen_load_fpr_D(dc, rs1);
1841 src2 = gen_load_fpr_D(dc, rs2);
1842 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1843 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1844
1845 gen(dst, src0, src1, src2);
1846
1847 gen_store_fpr_D(dc, rd, dst);
1848}
61f17f6e
RH		 1849#endif
1850
1851static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1852 void (*gen)(TCGv_ptr))
1853{
61f17f6e
RH		 1854 gen_op_load_fpr_QT1(QFPREG(rs));
1855
1856 gen(cpu_env);
7385aed2 1857 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1858
61f17f6e 1859 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1860 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1861}
1862
1863#ifdef TARGET_SPARC64
1864static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1865 void (*gen)(TCGv_ptr))
1866{
1867 gen_op_load_fpr_QT1(QFPREG(rs));
1868
1869 gen(cpu_env);
1870
1871 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1872 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1873}
1874#endif
1875
1876static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1877 void (*gen)(TCGv_ptr))
1878{
61f17f6e
RH		 1879 gen_op_load_fpr_QT0(QFPREG(rs1));
1880 gen_op_load_fpr_QT1(QFPREG(rs2));
1881
1882 gen(cpu_env);
7385aed2 1883 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1884
61f17f6e 1885 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1886 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1887}
1888
1889static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1890 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1891{
1892 TCGv_i64 dst;
1893 TCGv_i32 src1, src2;
1894
61f17f6e
RH		 1895 src1 = gen_load_fpr_F(dc, rs1);
1896 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1897 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1898
1899 gen(dst, cpu_env, src1, src2);
7385aed2 1900 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1901
61f17f6e
RH		 1902 gen_store_fpr_D(dc, rd, dst);
1903}
1904
1905static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1906 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1907{
1908 TCGv_i64 src1, src2;
1909
61f17f6e
RH		 1910 src1 = gen_load_fpr_D(dc, rs1);
1911 src2 = gen_load_fpr_D(dc, rs2);
1912
1913 gen(cpu_env, src1, src2);
7385aed2 1914 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1915
61f17f6e 1916 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1917 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1918}
1919
1920#ifdef TARGET_SPARC64
1921static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1922 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1923{
1924 TCGv_i64 dst;
1925 TCGv_i32 src;
1926
61f17f6e 1927 src = gen_load_fpr_F(dc, rs);
3886b8a3 1928 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1929
1930 gen(dst, cpu_env, src);
7385aed2 1931 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1932
61f17f6e
RH		 1933 gen_store_fpr_D(dc, rd, dst);
1934}
1935#endif
1936
1937static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1938 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1939{
1940 TCGv_i64 dst;
1941 TCGv_i32 src;
1942
1943 src = gen_load_fpr_F(dc, rs);
3886b8a3 1944 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1945
1946 gen(dst, cpu_env, src);
1947
1948 gen_store_fpr_D(dc, rd, dst);
1949}
1950
1951static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1952 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1953{
1954 TCGv_i32 dst;
1955 TCGv_i64 src;
1956
61f17f6e 1957 src = gen_load_fpr_D(dc, rs);
ba5f5179 1958 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1959
1960 gen(dst, cpu_env, src);
7385aed2 1961 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1962
61f17f6e
RH		 1963 gen_store_fpr_F(dc, rd, dst);
1964}
1965
1966static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1967 void (*gen)(TCGv_i32, TCGv_ptr))
1968{
1969 TCGv_i32 dst;
1970
61f17f6e 1971 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1972 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1973
1974 gen(dst, cpu_env);
7385aed2 1975 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1976
61f17f6e
RH		 1977 gen_store_fpr_F(dc, rd, dst);
1978}
1979
1980static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1981 void (*gen)(TCGv_i64, TCGv_ptr))
1982{
1983 TCGv_i64 dst;
1984
61f17f6e 1985 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1986 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1987
1988 gen(dst, cpu_env);
7385aed2 1989 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1990
61f17f6e
RH		 1991 gen_store_fpr_D(dc, rd, dst);
1992}
1993
1994static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1995 void (*gen)(TCGv_ptr, TCGv_i32))
1996{
1997 TCGv_i32 src;
1998
1999 src = gen_load_fpr_F(dc, rs);
2000
2001 gen(cpu_env, src);
2002
2003 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2004 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2005}
2006
2007static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
2008 void (*gen)(TCGv_ptr, TCGv_i64))
2009{
2010 TCGv_i64 src;
2011
2012 src = gen_load_fpr_D(dc, rs);
2013
2014 gen(cpu_env, src);
2015
2016 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2017 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2018}
2019
4fb554bc
RH		 2020static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
2021 TCGv addr, int mmu_idx, TCGMemOp memop)
2022{
4fb554bc 2023 gen_address_mask(dc, addr);
da1bcae6 2024 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
4fb554bc
RH		 2025}
2026
fbb4bbb6
RH		 2027static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
2028{
da1bcae6 2029 TCGv m1 = tcg_const_tl(0xff);
fbb4bbb6 2030 gen_address_mask(dc, addr);
da1bcae6
RH		 2031 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
2032 tcg_temp_free(m1);
fbb4bbb6
RH		 2033}
2034
1a2fb1c0 2035/* asi moves */
22e70060 2036#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
7ec1e5ea
RH		 2037typedef enum {
2038 GET_ASI_HELPER,
2039 GET_ASI_EXCP,
f0913be0 2040 GET_ASI_DIRECT,
e4dc0052 2041 GET_ASI_DTWINX,
ca5ce572
RH		 2042 GET_ASI_BLOCK,
2043 GET_ASI_SHORT,
34810610
RH		 2044 GET_ASI_BCOPY,
2045 GET_ASI_BFILL,
7ec1e5ea
RH		 2046} ASIType;
2047
2048typedef struct {
2049 ASIType type;
a6d567e5 2050 int asi;
f0913be0
RH		 2051 int mem_idx;
2052 TCGMemOp memop;
7ec1e5ea 2053} DisasASI;
1a2fb1c0 2054
f0913be0 2055static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
7ec1e5ea
RH		 2056{
2057 int asi = GET_FIELD(insn, 19, 26);
2058 ASIType type = GET_ASI_HELPER;
f0913be0 2059 int mem_idx = dc->mem_idx;
7ec1e5ea
RH		 2060
2061#ifndef TARGET_SPARC64
2062 /* Before v9, all asis are immediate and privileged. */
1a2fb1c0 2063 if (IS_IMM) {
22e70060 2064 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2065 type = GET_ASI_EXCP;
2066 } else if (supervisor(dc)
2067 /* Note that LEON accepts ASI_USERDATA in user mode, for
2068 use with CASA. Also note that previous versions of
0cc1f4bf
RH		 2069 QEMU allowed (and old versions of gcc emitted) ASI_P
2070 for LEON, which is incorrect. */
2071 || (asi == ASI_USERDATA
7ec1e5ea 2072 && (dc->def->features & CPU_FEATURE_CASA))) {
f0913be0
RH		 2073 switch (asi) {
2074 case ASI_USERDATA: /* User data access */
2075 mem_idx = MMU_USER_IDX;
2076 type = GET_ASI_DIRECT;
2077 break;
2078 case ASI_KERNELDATA: /* Supervisor data access */
2079 mem_idx = MMU_KERNEL_IDX;
2080 type = GET_ASI_DIRECT;
2081 break;
7f87c905
RH		 2082 case ASI_M_BYPASS: /* MMU passthrough */
2083 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
2084 mem_idx = MMU_PHYS_IDX;
2085 type = GET_ASI_DIRECT;
2086 break;
34810610
RH		 2087 case ASI_M_BCOPY: /* Block copy, sta access */
2088 mem_idx = MMU_KERNEL_IDX;
2089 type = GET_ASI_BCOPY;
2090 break;
2091 case ASI_M_BFILL: /* Block fill, stda access */
2092 mem_idx = MMU_KERNEL_IDX;
2093 type = GET_ASI_BFILL;
2094 break;
f0913be0 2095 }
1a2fb1c0 2096 } else {
7ec1e5ea
RH		 2097 gen_exception(dc, TT_PRIV_INSN);
2098 type = GET_ASI_EXCP;
2099 }
2100#else
2101 if (IS_IMM) {
2102 asi = dc->asi;
1a2fb1c0 2103 }
f0913be0
RH		 2104 /* With v9, all asis below 0x80 are privileged. */
2105 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
2106 down that bit into DisasContext. For the moment that's ok,
2107 since the direct implementations below doesn't have any ASIs
2108 in the restricted [0x30, 0x7f] range, and the check will be
2109 done properly in the helper. */
2110 if (!supervisor(dc) && asi < 0x80) {
2111 gen_exception(dc, TT_PRIV_ACT);
2112 type = GET_ASI_EXCP;
2113 } else {
2114 switch (asi) {
7f87c905
RH		 2115 case ASI_REAL: /* Bypass */
2116 case ASI_REAL_IO: /* Bypass, non-cacheable */
2117 case ASI_REAL_L: /* Bypass LE */
2118 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2119 case ASI_TWINX_REAL: /* Real address, twinx */
2120 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
34a6e13d
RH		 2121 case ASI_QUAD_LDD_PHYS:
2122 case ASI_QUAD_LDD_PHYS_L:
7f87c905
RH		 2123 mem_idx = MMU_PHYS_IDX;
2124 break;
f0913be0
RH		 2125 case ASI_N: /* Nucleus */
2126 case ASI_NL: /* Nucleus LE */
e4dc0052
RH		 2127 case ASI_TWINX_N:
2128 case ASI_TWINX_NL:
34a6e13d
RH		 2129 case ASI_NUCLEUS_QUAD_LDD:
2130 case ASI_NUCLEUS_QUAD_LDD_L:
9a10756d 2131 if (hypervisor(dc)) {
84f8f587 2132 mem_idx = MMU_PHYS_IDX;
9a10756d
AT		 2133 } else {
2134 mem_idx = MMU_NUCLEUS_IDX;
2135 }
f0913be0
RH		 2136 break;
2137 case ASI_AIUP: /* As if user primary */
2138 case ASI_AIUPL: /* As if user primary LE */
e4dc0052
RH		 2139 case ASI_TWINX_AIUP:
2140 case ASI_TWINX_AIUP_L:
ca5ce572
RH		 2141 case ASI_BLK_AIUP_4V:
2142 case ASI_BLK_AIUP_L_4V:
2143 case ASI_BLK_AIUP:
2144 case ASI_BLK_AIUPL:
f0913be0
RH		 2145 mem_idx = MMU_USER_IDX;
2146 break;
2147 case ASI_AIUS: /* As if user secondary */
2148 case ASI_AIUSL: /* As if user secondary LE */
e4dc0052
RH		 2149 case ASI_TWINX_AIUS:
2150 case ASI_TWINX_AIUS_L:
ca5ce572
RH		 2151 case ASI_BLK_AIUS_4V:
2152 case ASI_BLK_AIUS_L_4V:
2153 case ASI_BLK_AIUS:
2154 case ASI_BLK_AIUSL:
f0913be0
RH		 2155 mem_idx = MMU_USER_SECONDARY_IDX;
2156 break;
2157 case ASI_S: /* Secondary */
2158 case ASI_SL: /* Secondary LE */
e4dc0052
RH		 2159 case ASI_TWINX_S:
2160 case ASI_TWINX_SL:
ca5ce572
RH		 2161 case ASI_BLK_COMMIT_S:
2162 case ASI_BLK_S:
2163 case ASI_BLK_SL:
2164 case ASI_FL8_S:
2165 case ASI_FL8_SL:
2166 case ASI_FL16_S:
2167 case ASI_FL16_SL:
f0913be0
RH		 2168 if (mem_idx == MMU_USER_IDX) {
2169 mem_idx = MMU_USER_SECONDARY_IDX;
2170 } else if (mem_idx == MMU_KERNEL_IDX) {
2171 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2172 }
2173 break;
2174 case ASI_P: /* Primary */
2175 case ASI_PL: /* Primary LE */
e4dc0052
RH		 2176 case ASI_TWINX_P:
2177 case ASI_TWINX_PL:
ca5ce572
RH		 2178 case ASI_BLK_COMMIT_P:
2179 case ASI_BLK_P:
2180 case ASI_BLK_PL:
2181 case ASI_FL8_P:
2182 case ASI_FL8_PL:
2183 case ASI_FL16_P:
2184 case ASI_FL16_PL:
f0913be0
RH		 2185 break;
2186 }
2187 switch (asi) {
7f87c905
RH		 2188 case ASI_REAL:
2189 case ASI_REAL_IO:
2190 case ASI_REAL_L:
2191 case ASI_REAL_IO_L:
f0913be0
RH		 2192 case ASI_N:
2193 case ASI_NL:
2194 case ASI_AIUP:
2195 case ASI_AIUPL:
2196 case ASI_AIUS:
2197 case ASI_AIUSL:
2198 case ASI_S:
2199 case ASI_SL:
2200 case ASI_P:
2201 case ASI_PL:
2202 type = GET_ASI_DIRECT;
2203 break;
7f87c905
RH		 2204 case ASI_TWINX_REAL:
2205 case ASI_TWINX_REAL_L:
e4dc0052
RH		 2206 case ASI_TWINX_N:
2207 case ASI_TWINX_NL:
2208 case ASI_TWINX_AIUP:
2209 case ASI_TWINX_AIUP_L:
2210 case ASI_TWINX_AIUS:
2211 case ASI_TWINX_AIUS_L:
2212 case ASI_TWINX_P:
2213 case ASI_TWINX_PL:
2214 case ASI_TWINX_S:
2215 case ASI_TWINX_SL:
34a6e13d
RH		 2216 case ASI_QUAD_LDD_PHYS:
2217 case ASI_QUAD_LDD_PHYS_L:
2218 case ASI_NUCLEUS_QUAD_LDD:
2219 case ASI_NUCLEUS_QUAD_LDD_L:
e4dc0052
RH		 2220 type = GET_ASI_DTWINX;
2221 break;
ca5ce572
RH		 2222 case ASI_BLK_COMMIT_P:
2223 case ASI_BLK_COMMIT_S:
2224 case ASI_BLK_AIUP_4V:
2225 case ASI_BLK_AIUP_L_4V:
2226 case ASI_BLK_AIUP:
2227 case ASI_BLK_AIUPL:
2228 case ASI_BLK_AIUS_4V:
2229 case ASI_BLK_AIUS_L_4V:
2230 case ASI_BLK_AIUS:
2231 case ASI_BLK_AIUSL:
2232 case ASI_BLK_S:
2233 case ASI_BLK_SL:
2234 case ASI_BLK_P:
2235 case ASI_BLK_PL:
2236 type = GET_ASI_BLOCK;
2237 break;
2238 case ASI_FL8_S:
2239 case ASI_FL8_SL:
2240 case ASI_FL8_P:
2241 case ASI_FL8_PL:
2242 memop = MO_UB;
2243 type = GET_ASI_SHORT;
2244 break;
2245 case ASI_FL16_S:
2246 case ASI_FL16_SL:
2247 case ASI_FL16_P:
2248 case ASI_FL16_PL:
2249 memop = MO_TEUW;
2250 type = GET_ASI_SHORT;
2251 break;
f0913be0
RH		 2252 }
2253 /* The little-endian asis all have bit 3 set. */
2254 if (asi & 8) {
2255 memop ^= MO_BSWAP;
2256 }
2257 }
7ec1e5ea
RH		 2258#endif
2259
f0913be0 2260 return (DisasASI){ type, asi, mem_idx, memop };
0425bee5
BS		 2261}
2262
22e70060 2263static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
1d65b0f5 2264 int insn, TCGMemOp memop)
0425bee5 2265{
f0913be0 2266 DisasASI da = get_asi(dc, insn, memop);
0425bee5 2267
7ec1e5ea
RH		 2268 switch (da.type) {
2269 case GET_ASI_EXCP:
2270 break;
e4dc0052
RH		 2271 case GET_ASI_DTWINX: /* Reserved for ldda. */
2272 gen_exception(dc, TT_ILL_INSN);
2273 break;
f0913be0
RH		 2274 case GET_ASI_DIRECT:
2275 gen_address_mask(dc, addr);
2276 tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
2277 break;
7ec1e5ea
RH		 2278 default:
2279 {
2280 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2281 TCGv_i32 r_mop = tcg_const_i32(memop);
7ec1e5ea
RH		 2282
2283 save_state(dc);
22e70060 2284#ifdef TARGET_SPARC64
6850811e 2285 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop);
22e70060 2286#else
7ec1e5ea
RH		 2287 {
2288 TCGv_i64 t64 = tcg_temp_new_i64();
6850811e 2289 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
7ec1e5ea
RH		 2290 tcg_gen_trunc_i64_tl(dst, t64);
2291 tcg_temp_free_i64(t64);
2292 }
22e70060 2293#endif
6850811e 2294 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2295 tcg_temp_free_i32(r_asi);
2296 }
2297 break;
2298 }
1a2fb1c0
BS		 2299}
2300
22e70060 2301static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
1d65b0f5 2302 int insn, TCGMemOp memop)
1a2fb1c0 2303{
f0913be0 2304 DisasASI da = get_asi(dc, insn, memop);
1a2fb1c0 2305
7ec1e5ea
RH		 2306 switch (da.type) {
2307 case GET_ASI_EXCP:
2308 break;
e4dc0052 2309 case GET_ASI_DTWINX: /* Reserved for stda. */
3390537b 2310#ifndef TARGET_SPARC64
e4dc0052
RH		 2311 gen_exception(dc, TT_ILL_INSN);
2312 break;
3390537b
AT		 2313#else
2314 if (!(dc->def->features & CPU_FEATURE_HYPV)) {
2315 /* Pre OpenSPARC CPUs don't have these */
2316 gen_exception(dc, TT_ILL_INSN);
2317 return;
2318 }
2319 /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
2320 * are ST_BLKINIT_ ASIs */
2321 /* fall through */
2322#endif
f0913be0
RH		 2323 case GET_ASI_DIRECT:
2324 gen_address_mask(dc, addr);
2325 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
2326 break;
34810610
RH		 2327#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
2328 case GET_ASI_BCOPY:
2329 /* Copy 32 bytes from the address in SRC to ADDR. */
2330 /* ??? The original qemu code suggests 4-byte alignment, dropping
2331 the low bits, but the only place I can see this used is in the
2332 Linux kernel with 32 byte alignment, which would make more sense
2333 as a cacheline-style operation. */
2334 {
2335 TCGv saddr = tcg_temp_new();
2336 TCGv daddr = tcg_temp_new();
2337 TCGv four = tcg_const_tl(4);
2338 TCGv_i32 tmp = tcg_temp_new_i32();
2339 int i;
2340
2341 tcg_gen_andi_tl(saddr, src, -4);
2342 tcg_gen_andi_tl(daddr, addr, -4);
2343 for (i = 0; i < 32; i += 4) {
2344 /* Since the loads and stores are paired, allow the
2345 copy to happen in the host endianness. */
2346 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
2347 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
2348 tcg_gen_add_tl(saddr, saddr, four);
2349 tcg_gen_add_tl(daddr, daddr, four);
2350 }
2351
2352 tcg_temp_free(saddr);
2353 tcg_temp_free(daddr);
2354 tcg_temp_free(four);
2355 tcg_temp_free_i32(tmp);
2356 }
2357 break;
2358#endif
7ec1e5ea
RH		 2359 default:
2360 {
2361 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2362 TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE);
7ec1e5ea
RH		 2363
2364 save_state(dc);
22e70060 2365#ifdef TARGET_SPARC64
6850811e 2366 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop);
22e70060 2367#else
7ec1e5ea
RH		 2368 {
2369 TCGv_i64 t64 = tcg_temp_new_i64();
2370 tcg_gen_extu_tl_i64(t64, src);
6850811e 2371 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
7ec1e5ea
RH		 2372 tcg_temp_free_i64(t64);
2373 }
22e70060 2374#endif
6850811e 2375 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2376 tcg_temp_free_i32(r_asi);
2377
2378 /* A write to a TLB register may alter page maps. End the TB. */
2379 dc->npc = DYNAMIC_PC;
2380 }
2381 break;
2382 }
1a2fb1c0
BS		 2383}
2384
22e70060
RH		 2385static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2386 TCGv addr, int insn)
1a2fb1c0 2387{
f0913be0 2388 DisasASI da = get_asi(dc, insn, MO_TEUL);
22e70060 2389
7ec1e5ea
RH		 2390 switch (da.type) {
2391 case GET_ASI_EXCP:
2392 break;
4fb554bc
RH		 2393 case GET_ASI_DIRECT:
2394 gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
2395 break;
7ec1e5ea 2396 default:
4fb554bc
RH		 2397 /* ??? Should be DAE_invalid_asi. */
2398 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2399 break;
2400 }
1a2fb1c0
BS		 2401}
2402
5a7267b6 2403static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060
RH		 2404 int insn, int rd)
2405{
f0913be0 2406 DisasASI da = get_asi(dc, insn, MO_TEUL);
5a7267b6 2407 TCGv oldv;
22e70060 2408
7268adeb
RH		 2409 switch (da.type) {
2410 case GET_ASI_EXCP:
7ec1e5ea 2411 return;
7268adeb 2412 case GET_ASI_DIRECT:
7268adeb 2413 oldv = tcg_temp_new();
5a7267b6
RH		 2414 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2415 da.mem_idx, da.memop);
7268adeb 2416 gen_store_gpr(dc, rd, oldv);
7268adeb 2417 tcg_temp_free(oldv);
7268adeb
RH		 2418 break;
2419 default:
2420 /* ??? Should be DAE_invalid_asi. */
2421 gen_exception(dc, TT_DATA_ACCESS);
2422 break;
7ec1e5ea 2423 }
22e70060
RH		 2424}
2425
2426static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2427{
f0913be0 2428 DisasASI da = get_asi(dc, insn, MO_UB);
22e70060 2429
7ec1e5ea
RH		 2430 switch (da.type) {
2431 case GET_ASI_EXCP:
2432 break;
fbb4bbb6
RH		 2433 case GET_ASI_DIRECT:
2434 gen_ldstub(dc, dst, addr, da.mem_idx);
2435 break;
7ec1e5ea 2436 default:
3db010c3
RH		 2437 /* ??? In theory, this should be raise DAE_invalid_asi.
2438 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
87d757d6 2439 if (tb_cflags(dc->tb) & CF_PARALLEL) {
3db010c3
RH		 2440 gen_helper_exit_atomic(cpu_env);
2441 } else {
2442 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2443 TCGv_i32 r_mop = tcg_const_i32(MO_UB);
2444 TCGv_i64 s64, t64;
2445
2446 save_state(dc);
2447 t64 = tcg_temp_new_i64();
2448 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2449
2450 s64 = tcg_const_i64(0xff);
2451 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop);
2452 tcg_temp_free_i64(s64);
2453 tcg_temp_free_i32(r_mop);
2454 tcg_temp_free_i32(r_asi);
2455
2456 tcg_gen_trunc_i64_tl(dst, t64);
2457 tcg_temp_free_i64(t64);
2458
2459 /* End the TB. */
2460 dc->npc = DYNAMIC_PC;
2461 }
7ec1e5ea
RH		 2462 break;
2463 }
22e70060
RH		 2464}
2465#endif
2466
2467#ifdef TARGET_SPARC64
2468static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2469 int insn, int size, int rd)
1a2fb1c0 2470{
f0913be0 2471 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2472 TCGv_i32 d32;
cb21b4da 2473 TCGv_i64 d64;
1a2fb1c0 2474
7ec1e5ea
RH		 2475 switch (da.type) {
2476 case GET_ASI_EXCP:
2477 break;
7705091c
RH		 2478
2479 case GET_ASI_DIRECT:
2480 gen_address_mask(dc, addr);
2481 switch (size) {
2482 case 4:
2483 d32 = gen_dest_fpr_F(dc);
2484 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
2485 gen_store_fpr_F(dc, rd, d32);
2486 break;
2487 case 8:
cb21b4da
RH		 2488 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2489 da.memop | MO_ALIGN_4);
7705091c
RH		 2490 break;
2491 case 16:
cb21b4da
RH		 2492 d64 = tcg_temp_new_i64();
2493 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
7705091c 2494 tcg_gen_addi_tl(addr, addr, 8);
cb21b4da
RH		 2495 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2496 da.memop | MO_ALIGN_4);
2497 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2498 tcg_temp_free_i64(d64);
7705091c
RH		 2499 break;
2500 default:
2501 g_assert_not_reached();
2502 }
2503 break;
2504
ca5ce572
RH		 2505 case GET_ASI_BLOCK:
2506 /* Valid for lddfa on aligned registers only. */
2507 if (size == 8 && (rd & 7) == 0) {
80883227 2508 TCGMemOp memop;
ca5ce572
RH		 2509 TCGv eight;
2510 int i;
2511
ca5ce572
RH		 2512 gen_address_mask(dc, addr);
2513
80883227
RH		 2514 /* The first operation checks required alignment. */
2515 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2516 eight = tcg_const_tl(8);
2517 for (i = 0; ; ++i) {
2518 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2519 da.mem_idx, memop);
ca5ce572
RH		 2520 if (i == 7) {
2521 break;
2522 }
2523 tcg_gen_add_tl(addr, addr, eight);
80883227 2524 memop = da.memop;
ca5ce572
RH		 2525 }
2526 tcg_temp_free(eight);
2527 } else {
2528 gen_exception(dc, TT_ILL_INSN);
2529 }
2530 break;
2531
2532 case GET_ASI_SHORT:
2533 /* Valid for lddfa only. */
2534 if (size == 8) {
2535 gen_address_mask(dc, addr);
2536 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2537 } else {
2538 gen_exception(dc, TT_ILL_INSN);
2539 }
2540 break;
2541
7ec1e5ea
RH		 2542 default:
2543 {
2544 TCGv_i32 r_asi = tcg_const_i32(da.asi);
f2fe396f 2545 TCGv_i32 r_mop = tcg_const_i32(da.memop);
7ec1e5ea
RH		 2546
2547 save_state(dc);
f2fe396f
RH		 2548 /* According to the table in the UA2011 manual, the only
2549 other asis that are valid for ldfa/lddfa/ldqfa are
2550 the NO_FAULT asis. We still need a helper for these,
2551 but we can just use the integer asi helper for them. */
2552 switch (size) {
2553 case 4:
cb21b4da
RH		 2554 d64 = tcg_temp_new_i64();
2555 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
2556 d32 = gen_dest_fpr_F(dc);
2557 tcg_gen_extrl_i64_i32(d32, d64);
2558 tcg_temp_free_i64(d64);
2559 gen_store_fpr_F(dc, rd, d32);
f2fe396f
RH		 2560 break;
2561 case 8:
2562 gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop);
2563 break;
2564 case 16:
cb21b4da
RH		 2565 d64 = tcg_temp_new_i64();
2566 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
f2fe396f
RH		 2567 tcg_gen_addi_tl(addr, addr, 8);
2568 gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop);
cb21b4da
RH		 2569 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2570 tcg_temp_free_i64(d64);
f2fe396f
RH		 2571 break;
2572 default:
2573 g_assert_not_reached();
2574 }
2575 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2576 tcg_temp_free_i32(r_asi);
2577 }
2578 break;
2579 }
1a2fb1c0
BS		 2580}
2581
22e70060
RH		 2582static void gen_stf_asi(DisasContext *dc, TCGv addr,
2583 int insn, int size, int rd)
1a2fb1c0 2584{
f0913be0 2585 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2586 TCGv_i32 d32;
1a2fb1c0 2587
7ec1e5ea
RH		 2588 switch (da.type) {
2589 case GET_ASI_EXCP:
2590 break;
7705091c
RH		 2591
2592 case GET_ASI_DIRECT:
2593 gen_address_mask(dc, addr);
2594 switch (size) {
2595 case 4:
2596 d32 = gen_load_fpr_F(dc, rd);
2597 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
2598 break;
2599 case 8:
cb21b4da
RH		 2600 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2601 da.memop | MO_ALIGN_4);
7705091c
RH		 2602 break;
2603 case 16:
cb21b4da
RH		 2604 /* Only 4-byte alignment required. However, it is legal for the
2605 cpu to signal the alignment fault, and the OS trap handler is
2606 required to fix it up. Requiring 16-byte alignment here avoids
2607 having to probe the second page before performing the first
2608 write. */
f939ffe5
RH		 2609 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2610 da.memop | MO_ALIGN_16);
7705091c
RH		 2611 tcg_gen_addi_tl(addr, addr, 8);
2612 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2613 break;
2614 default:
2615 g_assert_not_reached();
2616 }
2617 break;
2618
ca5ce572
RH		 2619 case GET_ASI_BLOCK:
2620 /* Valid for stdfa on aligned registers only. */
2621 if (size == 8 && (rd & 7) == 0) {
80883227 2622 TCGMemOp memop;
ca5ce572
RH		 2623 TCGv eight;
2624 int i;
2625
ca5ce572
RH		 2626 gen_address_mask(dc, addr);
2627
80883227
RH		 2628 /* The first operation checks required alignment. */
2629 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2630 eight = tcg_const_tl(8);
2631 for (i = 0; ; ++i) {
2632 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2633 da.mem_idx, memop);
ca5ce572
RH		 2634 if (i == 7) {
2635 break;
2636 }
2637 tcg_gen_add_tl(addr, addr, eight);
80883227 2638 memop = da.memop;
ca5ce572
RH		 2639 }
2640 tcg_temp_free(eight);
2641 } else {
2642 gen_exception(dc, TT_ILL_INSN);
2643 }
2644 break;
2645
2646 case GET_ASI_SHORT:
2647 /* Valid for stdfa only. */
2648 if (size == 8) {
2649 gen_address_mask(dc, addr);
2650 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2651 } else {
2652 gen_exception(dc, TT_ILL_INSN);
2653 }
2654 break;
2655
7ec1e5ea 2656 default:
f2fe396f
RH		 2657 /* According to the table in the UA2011 manual, the only
2658 other asis that are valid for ldfa/lddfa/ldqfa are
2659 the PST* asis, which aren't currently handled. */
2660 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2661 break;
2662 }
1a2fb1c0
BS		 2663}
2664
e4dc0052 2665static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2666{
f0913be0 2667 DisasASI da = get_asi(dc, insn, MO_TEQ);
e4dc0052
RH		 2668 TCGv_i64 hi = gen_dest_gpr(dc, rd);
2669 TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
1a2fb1c0 2670
7ec1e5ea
RH		 2671 switch (da.type) {
2672 case GET_ASI_EXCP:
e4dc0052
RH		 2673 return;
2674
2675 case GET_ASI_DTWINX:
e4dc0052 2676 gen_address_mask(dc, addr);
80883227 2677 tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2678 tcg_gen_addi_tl(addr, addr, 8);
2679 tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
7ec1e5ea 2680 break;
e4dc0052
RH		 2681
2682 case GET_ASI_DIRECT:
2683 {
2684 TCGv_i64 tmp = tcg_temp_new_i64();
2685
2686 gen_address_mask(dc, addr);
2687 tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
2688
2689 /* Note that LE ldda acts as if each 32-bit register
2690 result is byte swapped. Having just performed one
2691 64-bit bswap, we need now to swap the writebacks. */
2692 if ((da.memop & MO_BSWAP) == MO_TE) {
2693 tcg_gen_extr32_i64(lo, hi, tmp);
2694 } else {
2695 tcg_gen_extr32_i64(hi, lo, tmp);
2696 }
2697 tcg_temp_free_i64(tmp);
2698 }
2699 break;
2700
7ec1e5ea 2701 default:
918d9a2c
RH		 2702 /* ??? In theory we've handled all of the ASIs that are valid
2703 for ldda, and this should raise DAE_invalid_asi. However,
2704 real hardware allows others. This can be seen with e.g.
2705 FreeBSD 10.3 wrt ASI_IC_TAG. */
7ec1e5ea
RH		 2706 {
2707 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2708 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2709 TCGv_i64 tmp = tcg_temp_new_i64();
7ec1e5ea
RH		 2710
2711 save_state(dc);
918d9a2c 2712 gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop);
7ec1e5ea 2713 tcg_temp_free_i32(r_asi);
918d9a2c 2714 tcg_temp_free_i32(r_mop);
3f4288eb 2715
918d9a2c
RH		 2716 /* See above. */
2717 if ((da.memop & MO_BSWAP) == MO_TE) {
2718 tcg_gen_extr32_i64(lo, hi, tmp);
2719 } else {
2720 tcg_gen_extr32_i64(hi, lo, tmp);
2721 }
2722 tcg_temp_free_i64(tmp);
7ec1e5ea
RH		 2723 }
2724 break;
2725 }
e4dc0052
RH		 2726
2727 gen_store_gpr(dc, rd, hi);
2728 gen_store_gpr(dc, rd + 1, lo);
0425bee5
BS		 2729}
2730
22e70060
RH		 2731static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2732 int insn, int rd)
0425bee5 2733{
f0913be0 2734 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2735 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2736
7ec1e5ea
RH		 2737 switch (da.type) {
2738 case GET_ASI_EXCP:
2739 break;
e4dc0052
RH		 2740
2741 case GET_ASI_DTWINX:
e4dc0052 2742 gen_address_mask(dc, addr);
80883227 2743 tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2744 tcg_gen_addi_tl(addr, addr, 8);
2745 tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
2746 break;
2747
2748 case GET_ASI_DIRECT:
2749 {
2750 TCGv_i64 t64 = tcg_temp_new_i64();
2751
2752 /* Note that LE stda acts as if each 32-bit register result is
2753 byte swapped. We will perform one 64-bit LE store, so now
2754 we must swap the order of the construction. */
2755 if ((da.memop & MO_BSWAP) == MO_TE) {
2756 tcg_gen_concat32_i64(t64, lo, hi);
2757 } else {
2758 tcg_gen_concat32_i64(t64, hi, lo);
2759 }
2760 gen_address_mask(dc, addr);
2761 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2762 tcg_temp_free_i64(t64);
2763 }
2764 break;
2765
7ec1e5ea 2766 default:
918d9a2c
RH		 2767 /* ??? In theory we've handled all of the ASIs that are valid
2768 for stda, and this should raise DAE_invalid_asi. */
7ec1e5ea
RH		 2769 {
2770 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2771 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2772 TCGv_i64 t64 = tcg_temp_new_i64();
7ec1e5ea 2773
918d9a2c
RH		 2774 /* See above. */
2775 if ((da.memop & MO_BSWAP) == MO_TE) {
2776 tcg_gen_concat32_i64(t64, lo, hi);
2777 } else {
2778 tcg_gen_concat32_i64(t64, hi, lo);
2779 }
7ec1e5ea 2780
918d9a2c 2781 save_state(dc);
6850811e
RH		 2782 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2783 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2784 tcg_temp_free_i32(r_asi);
2785 tcg_temp_free_i64(t64);
2786 }
2787 break;
2788 }
1a2fb1c0
BS		 2789}
2790
7268adeb 2791static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060 2792 int insn, int rd)
1a2fb1c0 2793{
f0913be0 2794 DisasASI da = get_asi(dc, insn, MO_TEQ);
5a7267b6 2795 TCGv oldv;
1a2fb1c0 2796
7268adeb
RH		 2797 switch (da.type) {
2798 case GET_ASI_EXCP:
7ec1e5ea 2799 return;
7268adeb
RH		 2800 case GET_ASI_DIRECT:
2801 oldv = tcg_temp_new();
5a7267b6
RH		 2802 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2803 da.mem_idx, da.memop);
7268adeb
RH		 2804 gen_store_gpr(dc, rd, oldv);
2805 tcg_temp_free(oldv);
7268adeb
RH		 2806 break;
2807 default:
2808 /* ??? Should be DAE_invalid_asi. */
2809 gen_exception(dc, TT_DATA_ACCESS);
2810 break;
2811 }
1a2fb1c0
BS		 2812}
2813
2814#elif !defined(CONFIG_USER_ONLY)
e4dc0052 2815static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2816{
d2dc4069
RH		 2817 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2818 whereby "rd + 1" elicits "error: array subscript is above array".
2819 Since we have already asserted that rd is even, the semantics
2820 are unchanged. */
7ec1e5ea 2821 TCGv lo = gen_dest_gpr(dc, rd | 1);
e4dc0052 2822 TCGv hi = gen_dest_gpr(dc, rd);
7ec1e5ea 2823 TCGv_i64 t64 = tcg_temp_new_i64();
f0913be0 2824 DisasASI da = get_asi(dc, insn, MO_TEQ);
7ec1e5ea
RH		 2825
2826 switch (da.type) {
2827 case GET_ASI_EXCP:
2828 tcg_temp_free_i64(t64);
2829 return;
e4dc0052
RH		 2830 case GET_ASI_DIRECT:
2831 gen_address_mask(dc, addr);
2832 tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
2833 break;
7ec1e5ea
RH		 2834 default:
2835 {
2836 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2837 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2838
2839 save_state(dc);
6850811e
RH		 2840 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2841 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2842 tcg_temp_free_i32(r_asi);
2843 }
2844 break;
2845 }
c7785e16 2846
7ec1e5ea 2847 tcg_gen_extr_i64_i32(lo, hi, t64);
1ec789ab 2848 tcg_temp_free_i64(t64);
7ec1e5ea 2849 gen_store_gpr(dc, rd | 1, lo);
c7785e16 2850 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2851}
2852
22e70060
RH		 2853static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2854 int insn, int rd)
0425bee5 2855{
f0913be0 2856 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2857 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2858 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2859
1ec789ab 2860 tcg_gen_concat_tl_i64(t64, lo, hi);
7ec1e5ea
RH		 2861
2862 switch (da.type) {
2863 case GET_ASI_EXCP:
2864 break;
e4dc0052
RH		 2865 case GET_ASI_DIRECT:
2866 gen_address_mask(dc, addr);
2867 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2868 break;
34810610
RH		 2869 case GET_ASI_BFILL:
2870 /* Store 32 bytes of T64 to ADDR. */
2871 /* ??? The original qemu code suggests 8-byte alignment, dropping
2872 the low bits, but the only place I can see this used is in the
2873 Linux kernel with 32 byte alignment, which would make more sense
2874 as a cacheline-style operation. */
2875 {
2876 TCGv d_addr = tcg_temp_new();
2877 TCGv eight = tcg_const_tl(8);
2878 int i;
2879
2880 tcg_gen_andi_tl(d_addr, addr, -8);
2881 for (i = 0; i < 32; i += 8) {
2882 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
2883 tcg_gen_add_tl(d_addr, d_addr, eight);
2884 }
2885
2886 tcg_temp_free(d_addr);
2887 tcg_temp_free(eight);
2888 }
2889 break;
7ec1e5ea
RH		 2890 default:
2891 {
2892 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2893 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2894
2895 save_state(dc);
6850811e
RH		 2896 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2897 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2898 tcg_temp_free_i32(r_asi);
2899 }
2900 break;
2901 }
2902
1ec789ab 2903 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2904}
2905#endif
2906
9d1d4e34 2907static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2908{
9d1d4e34
RH		 2909 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2910 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2911}
2912
9d1d4e34 2913static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2914{
a49d9390 2915 if (IS_IMM) { /* immediate */
42a8aa83 2916 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2917 TCGv t = get_temp_tl(dc);
2918 tcg_gen_movi_tl(t, simm);
2919 return t;
2920 } else { /* register */
42a8aa83 2921 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2922 return gen_load_gpr(dc, rs2);
a49d9390 2923 }
a49d9390
BS		 2924}
2925
8194f35a 2926#ifdef TARGET_SPARC64
7e480893
RH		 2927static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2928{
2929 TCGv_i32 c32, zero, dst, s1, s2;
2930
2931 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2932 or fold the comparison down to 32 bits and use movcond_i32. Choose
2933 the later. */
2934 c32 = tcg_temp_new_i32();
2935 if (cmp->is_bool) {
ecc7b3aa 2936 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2937 } else {
2938 TCGv_i64 c64 = tcg_temp_new_i64();
2939 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2940 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2941 tcg_temp_free_i64(c64);
2942 }
2943
2944 s1 = gen_load_fpr_F(dc, rs);
2945 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2946 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2947 zero = tcg_const_i32(0);
2948
2949 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2950
2951 tcg_temp_free_i32(c32);
2952 tcg_temp_free_i32(zero);
2953 gen_store_fpr_F(dc, rd, dst);
2954}
2955
2956static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2957{
3886b8a3 2958 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2959 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2960 gen_load_fpr_D(dc, rs),
2961 gen_load_fpr_D(dc, rd));
2962 gen_store_fpr_D(dc, rd, dst);
2963}
2964
2965static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2966{
2967 int qd = QFPREG(rd);
2968 int qs = QFPREG(rs);
2969
2970 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2971 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2972 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2973 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2974
f9c816c0 2975 gen_update_fprs_dirty(dc, qd);
7e480893
RH		 2976}
2977
a2035e83 2978#ifndef CONFIG_USER_ONLY
1bcea73e 2979static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
8194f35a 2980{
b551ec04 2981 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2982
2983 /* load env->tl into r_tl */
b551ec04 2984 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2985
2986 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2987 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2988
2989 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2990 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2991 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2992
2993 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2994 {
2995 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2996 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2997 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2998 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2999 }
8194f35a 3000
b551ec04 3001 tcg_temp_free_i32(r_tl);
8194f35a 3002}
a2035e83 3003#endif
6c073553
RH		 3004
3005static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
3006 int width, bool cc, bool left)
3007{
3008 TCGv lo1, lo2, t1, t2;
3009 uint64_t amask, tabl, tabr;
3010 int shift, imask, omask;
3011
3012 if (cc) {
3013 tcg_gen_mov_tl(cpu_cc_src, s1);
3014 tcg_gen_mov_tl(cpu_cc_src2, s2);
3015 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
3016 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3017 dc->cc_op = CC_OP_SUB;
3018 }
3019
3020 /* Theory of operation: there are two tables, left and right (not to
3021 be confused with the left and right versions of the opcode). These
3022 are indexed by the low 3 bits of the inputs. To make things "easy",
3023 these tables are loaded into two constants, TABL and TABR below.
3024 The operation index = (input & imask) << shift calculates the index
3025 into the constant, while val = (table >> index) & omask calculates
3026 the value we're looking for. */
3027 switch (width) {
3028 case 8:
3029 imask = 0x7;
3030 shift = 3;
3031 omask = 0xff;
3032 if (left) {
3033 tabl = 0x80c0e0f0f8fcfeffULL;
3034 tabr = 0xff7f3f1f0f070301ULL;
3035 } else {
3036 tabl = 0x0103070f1f3f7fffULL;
3037 tabr = 0xfffefcf8f0e0c080ULL;
3038 }
3039 break;
3040 case 16:
3041 imask = 0x6;
3042 shift = 1;
3043 omask = 0xf;
3044 if (left) {
3045 tabl = 0x8cef;
3046 tabr = 0xf731;
3047 } else {
3048 tabl = 0x137f;
3049 tabr = 0xfec8;
3050 }
3051 break;
3052 case 32:
3053 imask = 0x4;
3054 shift = 0;
3055 omask = 0x3;
3056 if (left) {
3057 tabl = (2 << 2) | 3;
3058 tabr = (3 << 2) | 1;
3059 } else {
3060 tabl = (1 << 2) | 3;
3061 tabr = (3 << 2) | 2;
3062 }
3063 break;
3064 default:
3065 abort();
3066 }
3067
3068 lo1 = tcg_temp_new();
3069 lo2 = tcg_temp_new();
3070 tcg_gen_andi_tl(lo1, s1, imask);
3071 tcg_gen_andi_tl(lo2, s2, imask);
3072 tcg_gen_shli_tl(lo1, lo1, shift);
3073 tcg_gen_shli_tl(lo2, lo2, shift);
3074
3075 t1 = tcg_const_tl(tabl);
3076 t2 = tcg_const_tl(tabr);
3077 tcg_gen_shr_tl(lo1, t1, lo1);
3078 tcg_gen_shr_tl(lo2, t2, lo2);
3079 tcg_gen_andi_tl(dst, lo1, omask);
3080 tcg_gen_andi_tl(lo2, lo2, omask);
3081
3082 amask = -8;
3083 if (AM_CHECK(dc)) {
3084 amask &= 0xffffffffULL;
3085 }
3086 tcg_gen_andi_tl(s1, s1, amask);
3087 tcg_gen_andi_tl(s2, s2, amask);
3088
3089 /* We want to compute
3090 dst = (s1 == s2 ? lo1 : lo1 & lo2).
3091 We've already done dst = lo1, so this reduces to
3092 dst &= (s1 == s2 ? -1 : lo2)
3093 Which we perform by
3094 lo2 |= -(s1 == s2)
3095 dst &= lo2
3096 */
3097 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
3098 tcg_gen_neg_tl(t1, t1);
3099 tcg_gen_or_tl(lo2, lo2, t1);
3100 tcg_gen_and_tl(dst, dst, lo2);
3101
3102 tcg_temp_free(lo1);
3103 tcg_temp_free(lo2);
3104 tcg_temp_free(t1);
3105 tcg_temp_free(t2);
3106}
add545ab
RH		 3107
3108static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
3109{
3110 TCGv tmp = tcg_temp_new();
3111
3112 tcg_gen_add_tl(tmp, s1, s2);
3113 tcg_gen_andi_tl(dst, tmp, -8);
3114 if (left) {
3115 tcg_gen_neg_tl(tmp, tmp);
3116 }
3117 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
3118
3119 tcg_temp_free(tmp);
3120}
50c796f9
RH		 3121
3122static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
3123{
3124 TCGv t1, t2, shift;
3125
3126 t1 = tcg_temp_new();
3127 t2 = tcg_temp_new();
3128 shift = tcg_temp_new();
3129
3130 tcg_gen_andi_tl(shift, gsr, 7);
3131 tcg_gen_shli_tl(shift, shift, 3);
3132 tcg_gen_shl_tl(t1, s1, shift);
3133
3134 /* A shift of 64 does not produce 0 in TCG. Divide this into a
3135 shift of (up to 63) followed by a constant shift of 1. */
3136 tcg_gen_xori_tl(shift, shift, 63);
3137 tcg_gen_shr_tl(t2, s2, shift);
3138 tcg_gen_shri_tl(t2, t2, 1);
3139
3140 tcg_gen_or_tl(dst, t1, t2);
3141
3142 tcg_temp_free(t1);
3143 tcg_temp_free(t2);
3144 tcg_temp_free(shift);
3145}
8194f35a
IK		 3146#endif
3147
64a88d5d 3148#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 3149 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3150 goto illegal_insn;
3151#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 3152 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3153 goto nfpu_insn;
3154
0bee699e 3155/* before an instruction, dc->pc must be static */
0184e266 3156static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 3157{
0184e266 3158 unsigned int opc, rs1, rs2, rd;
a4273524 3159 TCGv cpu_src1, cpu_src2;
208ae657 3160 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 3161 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 3162 target_long simm;
7a3f1944 3163
cf495bcf 3164 opc = GET_FIELD(insn, 0, 1);
cf495bcf 3165 rd = GET_FIELD(insn, 2, 6);
6ae20372 3166
cf495bcf 3167 switch (opc) {
0f8a249a
BS		 3168 case 0: /* branches/sethi */
3169 {
3170 unsigned int xop = GET_FIELD(insn, 7, 9);
3171 int32_t target;
3172 switch (xop) {
3475187d 3173#ifdef TARGET_SPARC64
0f8a249a
BS		 3174 case 0x1: /* V9 BPcc */
3175 {
3176 int cc;
3177
3178 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 3179 target = sign_extend(target, 19);
0f8a249a
BS		 3180 target <<= 2;
3181 cc = GET_FIELD_SP(insn, 20, 21);
3182 if (cc == 0)
d4a288ef 3183 do_branch(dc, target, insn, 0);
0f8a249a 3184 else if (cc == 2)
d4a288ef 3185 do_branch(dc, target, insn, 1);
0f8a249a
BS		 3186 else
3187 goto illegal_insn;
3188 goto jmp_insn;
3189 }
3190 case 0x3: /* V9 BPr */
3191 {
3192 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 3193 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 3194 target = sign_extend(target, 16);
3195 target <<= 2;
9d1d4e34 3196 cpu_src1 = get_src1(dc, insn);
d4a288ef 3197 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 3198 goto jmp_insn;
3199 }
3200 case 0x5: /* V9 FBPcc */
3201 {
3202 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 3203 if (gen_trap_ifnofpu(dc)) {
a80dde08 3204 goto jmp_insn;
5b12f1e8 3205 }
0f8a249a
BS		 3206 target = GET_FIELD_SP(insn, 0, 18);
3207 target = sign_extend(target, 19);
3208 target <<= 2;
d4a288ef 3209 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 3210 goto jmp_insn;
3211 }
a4d17f19 3212#else
0f8a249a
BS		 3213 case 0x7: /* CBN+x */
3214 {
3215 goto ncp_insn;
3216 }
3217#endif
3218 case 0x2: /* BN+x */
3219 {
3220 target = GET_FIELD(insn, 10, 31);
3221 target = sign_extend(target, 22);
3222 target <<= 2;
d4a288ef 3223 do_branch(dc, target, insn, 0);
0f8a249a
BS		 3224 goto jmp_insn;
3225 }
3226 case 0x6: /* FBN+x */
3227 {
5b12f1e8 3228 if (gen_trap_ifnofpu(dc)) {
a80dde08 3229 goto jmp_insn;
5b12f1e8 3230 }
0f8a249a
BS		 3231 target = GET_FIELD(insn, 10, 31);
3232 target = sign_extend(target, 22);
3233 target <<= 2;
d4a288ef 3234 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 3235 goto jmp_insn;
3236 }
3237 case 0x4: /* SETHI */
97ea2859
RH		 3238 /* Special-case %g0 because that's the canonical nop. */
3239 if (rd) {
0f8a249a 3240 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 3241 TCGv t = gen_dest_gpr(dc, rd);
3242 tcg_gen_movi_tl(t, value << 10);
3243 gen_store_gpr(dc, rd, t);
0f8a249a 3244 }
0f8a249a
BS		 3245 break;
3246 case 0x0: /* UNIMPL */
3247 default:
3475187d 3248 goto illegal_insn;
0f8a249a
BS		 3249 }
3250 break;
3251 }
3252 break;
dc1a6971
BS		 3253 case 1: /*CALL*/
3254 {
0f8a249a 3255 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 3256 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 3257
97ea2859
RH		 3258 tcg_gen_movi_tl(o7, dc->pc);
3259 gen_store_gpr(dc, 15, o7);
0f8a249a 3260 target += dc->pc;
13a6dd00 3261 gen_mov_pc_npc(dc);
22036a49
AT		 3262#ifdef TARGET_SPARC64
3263 if (unlikely(AM_CHECK(dc))) {
3264 target &= 0xffffffffULL;
3265 }
3266#endif
0f8a249a
BS		 3267 dc->npc = target;
3268 }
3269 goto jmp_insn;
3270 case 2: /* FPU & Logical Operations */
3271 {
3272 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 3273 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 3274 TCGv cpu_tmp0;
5793f2a4 3275
0f8a249a 3276 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 3277 int cond = GET_FIELD(insn, 3, 6);
3278 TCGv_i32 trap;
42a268c2
RH		 3279 TCGLabel *l1 = NULL;
3280 int mask;
3475187d 3281
bd49ed41
RH		 3282 if (cond == 0) {
3283 /* Trap never. */
3284 break;
cf495bcf 3285 }
b04d9890 3286
bd49ed41 3287 save_state(dc);
b04d9890 3288
bd49ed41
RH		 3289 if (cond != 8) {
3290 /* Conditional trap. */
3a49e759 3291 DisasCompare cmp;
3475187d 3292#ifdef TARGET_SPARC64
0f8a249a
BS		 3293 /* V9 icc/xcc */
3294 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 3295 if (cc == 0) {
3296 gen_compare(&cmp, 0, cond, dc);
3297 } else if (cc == 2) {
3298 gen_compare(&cmp, 1, cond, dc);
3299 } else {
0f8a249a 3300 goto illegal_insn;
3a49e759 3301 }
3475187d 3302#else
3a49e759 3303 gen_compare(&cmp, 0, cond, dc);
3475187d 3304#endif
b158a785 3305 l1 = gen_new_label();
3a49e759
RH		 3306 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
3307 cmp.c1, cmp.c2, l1);
3308 free_compare(&cmp);
bd49ed41 3309 }
b158a785 3310
bd49ed41
RH		 3311 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3312 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3313
3314 /* Don't use the normal temporaries, as they may well have
3315 gone out of scope with the branch above. While we're
3316 doing that we might as well pre-truncate to 32-bit. */
3317 trap = tcg_temp_new_i32();
3318
3319 rs1 = GET_FIELD_SP(insn, 14, 18);
3320 if (IS_IMM) {
5c65df36 3321 rs2 = GET_FIELD_SP(insn, 0, 7);
bd49ed41
RH		 3322 if (rs1 == 0) {
3323 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
3324 /* Signal that the trap value is fully constant. */
3325 mask = 0;
3326 } else {
97ea2859 3327 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 3328 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3329 tcg_gen_addi_i32(trap, trap, rs2);
3330 }
3331 } else {
97ea2859 3332 TCGv t1, t2;
bd49ed41 3333 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 3334 t1 = gen_load_gpr(dc, rs1);
3335 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 3336 tcg_gen_add_tl(t1, t1, t2);
3337 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3338 }
3339 if (mask != 0) {
3340 tcg_gen_andi_i32(trap, trap, mask);
3341 tcg_gen_addi_i32(trap, trap, TT_TRAP);
3342 }
3343
3344 gen_helper_raise_exception(cpu_env, trap);
3345 tcg_temp_free_i32(trap);
b158a785 3346
fe1755cb
RH		 3347 if (cond == 8) {
3348 /* An unconditional trap ends the TB. */
3349 dc->is_br = 1;
3350 goto jmp_insn;
3351 } else {
3352 /* A conditional trap falls through to the next insn. */
b158a785 3353 gen_set_label(l1);
fe1755cb 3354 break;
cf495bcf
FB		 3355 }
3356 } else if (xop == 0x28) {
3357 rs1 = GET_FIELD(insn, 13, 17);
3358 switch(rs1) {
3359 case 0: /* rdy */
65fe7b09
BS		 3360#ifndef TARGET_SPARC64
3361 case 0x01 ... 0x0e: /* undefined in the SPARCv8
3362 manual, rdy on the microSPARC
3363 II */
3364 case 0x0f: /* stbar in the SPARCv8 manual,
3365 rdy on the microSPARC II */
3366 case 0x10 ... 0x1f: /* implementation-dependent in the
3367 SPARCv8 manual, rdy on the
3368 microSPARC II */
4a2ba232
FC		 3369 /* Read Asr17 */
3370 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 3371 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 3372 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 3373 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
3374 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 3375 break;
3376 }
65fe7b09 3377#endif
97ea2859 3378 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 3379 break;
3475187d 3380#ifdef TARGET_SPARC64
0f8a249a 3381 case 0x2: /* V9 rdccr */
20132b96 3382 update_psr(dc);
063c3675 3383 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 3384 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3385 break;
0f8a249a 3386 case 0x3: /* V9 rdasi */
a6d567e5 3387 tcg_gen_movi_tl(cpu_dst, dc->asi);
97ea2859 3388 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3389 break;
0f8a249a 3390 case 0x4: /* V9 rdtick */
ccd4a219 3391 {
a7812ae4 3392 TCGv_ptr r_tickptr;
c9a46442 3393 TCGv_i32 r_const;
ccd4a219 3394
a7812ae4 3395 r_tickptr = tcg_temp_new_ptr();
c9a46442 3396 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3397 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3398 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3399 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3400 r_const);
a7812ae4 3401 tcg_temp_free_ptr(r_tickptr);
c9a46442 3402 tcg_temp_free_i32(r_const);
97ea2859 3403 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3404 }
3475187d 3405 break;
0f8a249a 3406 case 0x5: /* V9 rdpc */
2ea815ca 3407 {
97ea2859 3408 TCGv t = gen_dest_gpr(dc, rd);
22036a49 3409 if (unlikely(AM_CHECK(dc))) {
97ea2859 3410 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 3411 } else {
97ea2859 3412 tcg_gen_movi_tl(t, dc->pc);
22036a49 3413 }
97ea2859 3414 gen_store_gpr(dc, rd, t);
2ea815ca 3415 }
0f8a249a
BS		 3416 break;
3417 case 0x6: /* V9 rdfprs */
255e1fcb 3418 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 3419 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3420 break;
65fe7b09
BS		 3421 case 0xf: /* V9 membar */
3422 break; /* no effect */
0f8a249a 3423 case 0x13: /* Graphics Status */
5b12f1e8 3424 if (gen_trap_ifnofpu(dc)) {
725cb90b 3425 goto jmp_insn;
5b12f1e8 3426 }
97ea2859 3427 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 3428 break;
9d926598 3429 case 0x16: /* Softint */
e86ceb0d
RH		 3430 tcg_gen_ld32s_tl(cpu_dst, cpu_env,
3431 offsetof(CPUSPARCState, softint));
97ea2859 3432 gen_store_gpr(dc, rd, cpu_dst);
9d926598 3433 break;
0f8a249a 3434 case 0x17: /* Tick compare */
97ea2859 3435 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 3436 break;
0f8a249a 3437 case 0x18: /* System tick */
ccd4a219 3438 {
a7812ae4 3439 TCGv_ptr r_tickptr;
c9a46442 3440 TCGv_i32 r_const;
ccd4a219 3441
a7812ae4 3442 r_tickptr = tcg_temp_new_ptr();
c9a46442 3443 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3444 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3445 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 3446 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3447 r_const);
a7812ae4 3448 tcg_temp_free_ptr(r_tickptr);
c9a46442 3449 tcg_temp_free_i32(r_const);
97ea2859 3450 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3451 }
83469015 3452 break;
0f8a249a 3453 case 0x19: /* System tick compare */
97ea2859 3454 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 3455 break;
b8e31b3c
AT		 3456 case 0x1a: /* UltraSPARC-T1 Strand status */
3457 /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
3458 * this ASR as impl. dep
3459 */
3460 CHECK_IU_FEATURE(dc, HYPV);
3461 {
3462 TCGv t = gen_dest_gpr(dc, rd);
3463 tcg_gen_movi_tl(t, 1UL);
3464 gen_store_gpr(dc, rd, t);
3465 }
3466 break;
0f8a249a
BS		 3467 case 0x10: /* Performance Control */
3468 case 0x11: /* Performance Instrumentation Counter */
3469 case 0x12: /* Dispatch Control */
3470 case 0x14: /* Softint set, WO */
3471 case 0x15: /* Softint clear, WO */
3475187d
FB		 3472#endif
3473 default:
cf495bcf
FB		 3474 goto illegal_insn;
3475 }
e8af50a3 3476#if !defined(CONFIG_USER_ONLY)
e9ebed4d 3477 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 3478#ifndef TARGET_SPARC64
20132b96 3479 if (!supervisor(dc)) {
0f8a249a 3480 goto priv_insn;
20132b96
RH		 3481 }
3482 update_psr(dc);
063c3675 3483 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 3484#else
fb79ceb9 3485 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3486 if (!hypervisor(dc))
3487 goto priv_insn;
3488 rs1 = GET_FIELD(insn, 13, 17);
3489 switch (rs1) {
3490 case 0: // hpstate
f7f17ef7
AT		 3491 tcg_gen_ld_i64(cpu_dst, cpu_env,
3492 offsetof(CPUSPARCState, hpstate));
e9ebed4d
BS		 3493 break;
3494 case 1: // htstate
3495 // gen_op_rdhtstate();
3496 break;
3497 case 3: // hintp
255e1fcb 3498 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 3499 break;
3500 case 5: // htba
255e1fcb 3501 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 3502 break;
3503 case 6: // hver
255e1fcb 3504 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 3505 break;
3506 case 31: // hstick_cmpr
255e1fcb 3507 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 3508 break;
3509 default:
3510 goto illegal_insn;
3511 }
3512#endif
97ea2859 3513 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 3514 break;
3475187d 3515 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 3516 if (!supervisor(dc)) {
0f8a249a 3517 goto priv_insn;
de9e9d9f
RH		 3518 }
3519 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 3520#ifdef TARGET_SPARC64
3521 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3522 switch (rs1) {
3523 case 0: // tpc
375ee38b 3524 {
a7812ae4 3525 TCGv_ptr r_tsptr;
375ee38b 3526
a7812ae4 3527 r_tsptr = tcg_temp_new_ptr();
8194f35a 3528 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 3529 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3530 offsetof(trap_state, tpc));
a7812ae4 3531 tcg_temp_free_ptr(r_tsptr);
375ee38b 3532 }
0f8a249a
BS		 3533 break;
3534 case 1: // tnpc
375ee38b 3535 {
a7812ae4 3536 TCGv_ptr r_tsptr;
375ee38b 3537
a7812ae4 3538 r_tsptr = tcg_temp_new_ptr();
8194f35a 3539 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3540 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3541 offsetof(trap_state, tnpc));
a7812ae4 3542 tcg_temp_free_ptr(r_tsptr);
375ee38b 3543 }
0f8a249a
BS		 3544 break;
3545 case 2: // tstate
375ee38b 3546 {
a7812ae4 3547 TCGv_ptr r_tsptr;
375ee38b 3548
a7812ae4 3549 r_tsptr = tcg_temp_new_ptr();
8194f35a 3550 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3551 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3552 offsetof(trap_state, tstate));
a7812ae4 3553 tcg_temp_free_ptr(r_tsptr);
375ee38b 3554 }
0f8a249a
BS		 3555 break;
3556 case 3: // tt
375ee38b 3557 {
45778f99 3558 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 3559
8194f35a 3560 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 3561 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
3562 offsetof(trap_state, tt));
a7812ae4 3563 tcg_temp_free_ptr(r_tsptr);
375ee38b 3564 }
0f8a249a
BS		 3565 break;
3566 case 4: // tick
ccd4a219 3567 {
a7812ae4 3568 TCGv_ptr r_tickptr;
c9a46442 3569 TCGv_i32 r_const;
ccd4a219 3570
a7812ae4 3571 r_tickptr = tcg_temp_new_ptr();
c9a46442 3572 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3573 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3574 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3575 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
3576 r_tickptr, r_const);
a7812ae4 3577 tcg_temp_free_ptr(r_tickptr);
c9a46442 3578 tcg_temp_free_i32(r_const);
ccd4a219 3579 }
0f8a249a
BS		 3580 break;
3581 case 5: // tba
255e1fcb 3582 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 3583 break;
3584 case 6: // pstate
45778f99
RH		 3585 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3586 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 3587 break;
3588 case 7: // tl
45778f99
RH		 3589 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3590 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3591 break;
3592 case 8: // pil
45778f99
RH		 3593 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3594 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3595 break;
3596 case 9: // cwp
063c3675 3597 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 3598 break;
3599 case 10: // cansave
45778f99
RH		 3600 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3601 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3602 break;
3603 case 11: // canrestore
45778f99
RH		 3604 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3605 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3606 break;
3607 case 12: // cleanwin
45778f99
RH		 3608 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3609 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3610 break;
3611 case 13: // otherwin
45778f99
RH		 3612 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3613 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3614 break;
3615 case 14: // wstate
45778f99
RH		 3616 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3617 offsetof(CPUSPARCState, wstate));
0f8a249a 3618 break;
e9ebed4d 3619 case 16: // UA2005 gl
fb79ceb9 3620 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 3621 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3622 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3623 break;
3624 case 26: // UA2005 strand status
fb79ceb9 3625 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3626 if (!hypervisor(dc))
3627 goto priv_insn;
527067d8 3628 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 3629 break;
0f8a249a 3630 case 31: // ver
255e1fcb 3631 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 3632 break;
3633 case 15: // fq
3634 default:
3635 goto illegal_insn;
3636 }
3475187d 3637#else
255e1fcb 3638 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 3639#endif
97ea2859 3640 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 3641 break;
3475187d
FB		 3642 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
3643#ifdef TARGET_SPARC64
063c3675 3644 gen_helper_flushw(cpu_env);
3475187d 3645#else
0f8a249a
BS		 3646 if (!supervisor(dc))
3647 goto priv_insn;
97ea2859 3648 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 3649#endif
e8af50a3
FB		 3650 break;
3651#endif
0f8a249a 3652 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 3653 if (gen_trap_ifnofpu(dc)) {
a80dde08 3654 goto jmp_insn;
5b12f1e8 3655 }
0f8a249a 3656 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 3657 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3658 rs2 = GET_FIELD(insn, 27, 31);
3659 xop = GET_FIELD(insn, 18, 26);
02c79d78 3660
0f8a249a 3661 switch (xop) {
dc1a6971 3662 case 0x1: /* fmovs */
208ae657
RH		 3663 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3664 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 3665 break;
3666 case 0x5: /* fnegs */
61f17f6e 3667 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 3668 break;
3669 case 0x9: /* fabss */
61f17f6e 3670 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 3671 break;
3672 case 0x29: /* fsqrts */
3673 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3674 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 3675 break;
3676 case 0x2a: /* fsqrtd */
3677 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3678 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 3679 break;
3680 case 0x2b: /* fsqrtq */
3681 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3682 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 3683 break;
3684 case 0x41: /* fadds */
61f17f6e 3685 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 3686 break;
3687 case 0x42: /* faddd */
61f17f6e 3688 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 3689 break;
3690 case 0x43: /* faddq */
3691 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3692 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 3693 break;
3694 case 0x45: /* fsubs */
61f17f6e 3695 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 3696 break;
3697 case 0x46: /* fsubd */
61f17f6e 3698 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3699 break;
3700 case 0x47: /* fsubq */
3701 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3702 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3703 break;
3704 case 0x49: /* fmuls */
3705 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3706 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3707 break;
3708 case 0x4a: /* fmuld */
3709 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3710 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3711 break;
3712 case 0x4b: /* fmulq */
3713 CHECK_FPU_FEATURE(dc, FLOAT128);
3714 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3715 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3716 break;
3717 case 0x4d: /* fdivs */
61f17f6e 3718 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3719 break;
3720 case 0x4e: /* fdivd */
61f17f6e 3721 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3722 break;
3723 case 0x4f: /* fdivq */
3724 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3725 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3726 break;
3727 case 0x69: /* fsmuld */
3728 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3729 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3730 break;
3731 case 0x6e: /* fdmulq */
3732 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3733 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3734 break;
3735 case 0xc4: /* fitos */
61f17f6e 3736 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3737 break;
3738 case 0xc6: /* fdtos */
61f17f6e 3739 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3740 break;
3741 case 0xc7: /* fqtos */
3742 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3743 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3744 break;
3745 case 0xc8: /* fitod */
61f17f6e 3746 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3747 break;
3748 case 0xc9: /* fstod */
61f17f6e 3749 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3750 break;
3751 case 0xcb: /* fqtod */
3752 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3753 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3754 break;
3755 case 0xcc: /* fitoq */
3756 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3757 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3758 break;
3759 case 0xcd: /* fstoq */
3760 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3761 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3762 break;
3763 case 0xce: /* fdtoq */
3764 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3765 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3766 break;
3767 case 0xd1: /* fstoi */
61f17f6e 3768 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3769 break;
3770 case 0xd2: /* fdtoi */
61f17f6e 3771 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3772 break;
3773 case 0xd3: /* fqtoi */
3774 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3775 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3776 break;
3475187d 3777#ifdef TARGET_SPARC64
dc1a6971 3778 case 0x2: /* V9 fmovd */
96eda024
RH		 3779 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3780 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3781 break;
3782 case 0x3: /* V9 fmovq */
3783 CHECK_FPU_FEATURE(dc, FLOAT128);
f9c816c0 3784 gen_move_Q(dc, rd, rs2);
dc1a6971
BS		 3785 break;
3786 case 0x6: /* V9 fnegd */
61f17f6e 3787 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3788 break;
3789 case 0x7: /* V9 fnegq */
3790 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3791 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3792 break;
3793 case 0xa: /* V9 fabsd */
61f17f6e 3794 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3795 break;
3796 case 0xb: /* V9 fabsq */
3797 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3798 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3799 break;
3800 case 0x81: /* V9 fstox */
61f17f6e 3801 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3802 break;
3803 case 0x82: /* V9 fdtox */
61f17f6e 3804 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3805 break;
3806 case 0x83: /* V9 fqtox */
3807 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3808 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3809 break;
3810 case 0x84: /* V9 fxtos */
61f17f6e 3811 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3812 break;
3813 case 0x88: /* V9 fxtod */
61f17f6e 3814 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3815 break;
3816 case 0x8c: /* V9 fxtoq */
3817 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3818 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3819 break;
0f8a249a 3820#endif
dc1a6971
BS		 3821 default:
3822 goto illegal_insn;
0f8a249a
BS		 3823 }
3824 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3825#ifdef TARGET_SPARC64
0f8a249a 3826 int cond;
3475187d 3827#endif
5b12f1e8 3828 if (gen_trap_ifnofpu(dc)) {
a80dde08 3829 goto jmp_insn;
5b12f1e8 3830 }
0f8a249a 3831 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3832 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3833 rs2 = GET_FIELD(insn, 27, 31);
3834 xop = GET_FIELD(insn, 18, 26);
dcf24905 3835
690995a6
RH		 3836#ifdef TARGET_SPARC64
3837#define FMOVR(sz) \
3838 do { \
3839 DisasCompare cmp; \
e7c8afb9 3840 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3841 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3842 gen_compare_reg(&cmp, cond, cpu_src1); \
3843 gen_fmov##sz(dc, &cmp, rd, rs2); \
3844 free_compare(&cmp); \
3845 } while (0)
3846
3847 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3848 FMOVR(s);
0f8a249a
BS		 3849 break;
3850 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3851 FMOVR(d);
0f8a249a
BS		 3852 break;
3853 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3854 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3855 FMOVR(q);
1f587329 3856 break;
0f8a249a 3857 }
690995a6 3858#undef FMOVR
0f8a249a
BS		 3859#endif
3860 switch (xop) {
3475187d 3861#ifdef TARGET_SPARC64
7e480893
RH		 3862#define FMOVCC(fcc, sz) \
3863 do { \
3864 DisasCompare cmp; \
714547bb 3865 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3866 gen_fcompare(&cmp, fcc, cond); \
3867 gen_fmov##sz(dc, &cmp, rd, rs2); \
3868 free_compare(&cmp); \
3869 } while (0)
3870
0f8a249a 3871 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3872 FMOVCC(0, s);
0f8a249a
BS		 3873 break;
3874 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3875 FMOVCC(0, d);
0f8a249a
BS		 3876 break;
3877 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3878 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3879 FMOVCC(0, q);
1f587329 3880 break;
0f8a249a 3881 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3882 FMOVCC(1, s);
0f8a249a
BS		 3883 break;
3884 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3885 FMOVCC(1, d);
0f8a249a
BS		 3886 break;
3887 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3888 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3889 FMOVCC(1, q);
1f587329 3890 break;
0f8a249a 3891 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3892 FMOVCC(2, s);
0f8a249a
BS		 3893 break;
3894 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3895 FMOVCC(2, d);
0f8a249a
BS		 3896 break;
3897 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3898 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3899 FMOVCC(2, q);
1f587329 3900 break;
0f8a249a 3901 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3902 FMOVCC(3, s);
0f8a249a
BS		 3903 break;
3904 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3905 FMOVCC(3, d);
0f8a249a
BS		 3906 break;
3907 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3908 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3909 FMOVCC(3, q);
1f587329 3910 break;
7e480893
RH		 3911#undef FMOVCC
3912#define FMOVCC(xcc, sz) \
3913 do { \
3914 DisasCompare cmp; \
714547bb 3915 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3916 gen_compare(&cmp, xcc, cond, dc); \
3917 gen_fmov##sz(dc, &cmp, rd, rs2); \
3918 free_compare(&cmp); \
3919 } while (0)
19f329ad 3920
0f8a249a 3921 case 0x101: /* V9 fmovscc %icc */
7e480893 3922 FMOVCC(0, s);
0f8a249a
BS		 3923 break;
3924 case 0x102: /* V9 fmovdcc %icc */
7e480893 3925 FMOVCC(0, d);
b7d69dc2 3926 break;
0f8a249a 3927 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3928 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3929 FMOVCC(0, q);
1f587329 3930 break;
0f8a249a 3931 case 0x181: /* V9 fmovscc %xcc */
7e480893 3932 FMOVCC(1, s);
0f8a249a
BS		 3933 break;
3934 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3935 FMOVCC(1, d);
0f8a249a
BS		 3936 break;
3937 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3938 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3939 FMOVCC(1, q);
1f587329 3940 break;
7e480893 3941#undef FMOVCC
1f587329
BS		 3942#endif
3943 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3944 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3945 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3946 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3947 break;
1f587329 3948 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3949 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3950 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3951 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3952 break;
1f587329 3953 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3954 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3955 gen_op_load_fpr_QT0(QFPREG(rs1));
3956 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3957 gen_op_fcmpq(rd & 3);
1f587329 3958 break;
0f8a249a 3959 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3960 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3961 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3962 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3963 break;
3964 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3965 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3966 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3967 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3968 break;
1f587329 3969 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3970 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3971 gen_op_load_fpr_QT0(QFPREG(rs1));
3972 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3973 gen_op_fcmpeq(rd & 3);
1f587329 3974 break;
0f8a249a
BS		 3975 default:
3976 goto illegal_insn;
3977 }
0f8a249a 3978 } else if (xop == 0x2) {
97ea2859 3979 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3980 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3981 if (rs1 == 0) {
97ea2859 3982 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3983 if (IS_IMM) { /* immediate */
67526b20 3984 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3985 tcg_gen_movi_tl(dst, simm);
3986 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3987 } else { /* register */
3988 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3989 if (rs2 == 0) {
3990 tcg_gen_movi_tl(dst, 0);
3991 gen_store_gpr(dc, rd, dst);
3992 } else {
3993 cpu_src2 = gen_load_gpr(dc, rs2);
3994 gen_store_gpr(dc, rd, cpu_src2);
3995 }
0f8a249a 3996 }
0f8a249a 3997 } else {
9d1d4e34 3998 cpu_src1 = get_src1(dc, insn);
0f8a249a 3999 if (IS_IMM) { /* immediate */
67526b20 4000 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 4001 tcg_gen_ori_tl(dst, cpu_src1, simm);
4002 gen_store_gpr(dc, rd, dst);
0f8a249a 4003 } else { /* register */
0f8a249a 4004 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 4005 if (rs2 == 0) {
4006 /* mov shortcut: or x, %g0, y -> mov x, y */
4007 gen_store_gpr(dc, rd, cpu_src1);
4008 } else {
4009 cpu_src2 = gen_load_gpr(dc, rs2);
4010 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
4011 gen_store_gpr(dc, rd, dst);
4012 }
0f8a249a 4013 }
0f8a249a 4014 }
83469015 4015#ifdef TARGET_SPARC64
0f8a249a 4016 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 4017 cpu_src1 = get_src1(dc, insn);
0f8a249a 4018 if (IS_IMM) { /* immediate */
67526b20 4019 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4020 if (insn & (1 << 12)) {
67526b20 4021 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4022 } else {
67526b20 4023 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 4024 }
0f8a249a 4025 } else { /* register */
83469015 4026 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4027 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4028 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4029 if (insn & (1 << 12)) {
6ae20372 4030 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 4031 } else {
6ae20372 4032 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 4033 }
01b1fa6d 4034 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 4035 }
97ea2859 4036 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4037 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 4038 cpu_src1 = get_src1(dc, insn);
0f8a249a 4039 if (IS_IMM) { /* immediate */
67526b20 4040 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4041 if (insn & (1 << 12)) {
67526b20 4042 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4043 } else {
6ae20372 4044 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 4045 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4046 }
0f8a249a 4047 } else { /* register */
83469015 4048 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4049 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4050 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4051 if (insn & (1 << 12)) {
6ae20372
BS		 4052 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4053 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4054 } else {
6ae20372
BS		 4055 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4056 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
4057 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4058 }
83469015 4059 }
97ea2859 4060 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4061 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 4062 cpu_src1 = get_src1(dc, insn);
0f8a249a 4063 if (IS_IMM) { /* immediate */
67526b20 4064 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4065 if (insn & (1 << 12)) {
67526b20 4066 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4067 } else {
97ea2859 4068 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 4069 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4070 }
0f8a249a 4071 } else { /* register */
83469015 4072 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4073 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4074 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4075 if (insn & (1 << 12)) {
6ae20372
BS		 4076 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4077 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4078 } else {
6ae20372 4079 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 4080 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 4081 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4082 }
83469015 4083 }
97ea2859 4084 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 4085#endif
fcc72045 4086 } else if (xop < 0x36) {
cf495bcf 4087 if (xop < 0x20) {
9d1d4e34
RH		 4088 cpu_src1 = get_src1(dc, insn);
4089 cpu_src2 = get_src2(dc, insn);
cf495bcf 4090 switch (xop & ~0x10) {
b89e94af 4091 case 0x0: /* add */
97ea2859
RH		 4092 if (xop & 0x10) {
4093 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
4094 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4095 dc->cc_op = CC_OP_ADD;
41d72852 4096 } else {
97ea2859 4097 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4098 }
cf495bcf 4099 break;
b89e94af 4100 case 0x1: /* and */
97ea2859 4101 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4102 if (xop & 0x10) {
38482a77
BS		 4103 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4104 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4105 dc->cc_op = CC_OP_LOGIC;
41d72852 4106 }
cf495bcf 4107 break;
b89e94af 4108 case 0x2: /* or */
97ea2859 4109 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4110 if (xop & 0x10) {
38482a77
BS		 4111 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4112 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4113 dc->cc_op = CC_OP_LOGIC;
8393617c 4114 }
0f8a249a 4115 break;
b89e94af 4116 case 0x3: /* xor */
97ea2859 4117 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4118 if (xop & 0x10) {
38482a77
BS		 4119 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4120 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4121 dc->cc_op = CC_OP_LOGIC;
8393617c 4122 }
cf495bcf 4123 break;
b89e94af 4124 case 0x4: /* sub */
97ea2859
RH		 4125 if (xop & 0x10) {
4126 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
4127 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
4128 dc->cc_op = CC_OP_SUB;
41d72852 4129 } else {
97ea2859 4130 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4131 }
cf495bcf 4132 break;
b89e94af 4133 case 0x5: /* andn */
97ea2859 4134 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4135 if (xop & 0x10) {
38482a77
BS		 4136 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4137 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4138 dc->cc_op = CC_OP_LOGIC;
8393617c 4139 }
cf495bcf 4140 break;
b89e94af 4141 case 0x6: /* orn */
97ea2859 4142 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4143 if (xop & 0x10) {
38482a77
BS		 4144 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4145 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4146 dc->cc_op = CC_OP_LOGIC;
8393617c 4147 }
cf495bcf 4148 break;
b89e94af 4149 case 0x7: /* xorn */
97ea2859 4150 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4151 if (xop & 0x10) {
38482a77
BS		 4152 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4153 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4154 dc->cc_op = CC_OP_LOGIC;
8393617c 4155 }
cf495bcf 4156 break;
b89e94af 4157 case 0x8: /* addx, V9 addc */
70c48285
RH		 4158 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4159 (xop & 0x10));
cf495bcf 4160 break;
ded3ab80 4161#ifdef TARGET_SPARC64
0f8a249a 4162 case 0x9: /* V9 mulx */
97ea2859 4163 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 4164 break;
4165#endif
b89e94af 4166 case 0xa: /* umul */
64a88d5d 4167 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4168 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4169 if (xop & 0x10) {
38482a77
BS		 4170 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4171 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4172 dc->cc_op = CC_OP_LOGIC;
8393617c 4173 }
cf495bcf 4174 break;
b89e94af 4175 case 0xb: /* smul */
64a88d5d 4176 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4177 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4178 if (xop & 0x10) {
38482a77
BS		 4179 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4180 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4181 dc->cc_op = CC_OP_LOGIC;
8393617c 4182 }
cf495bcf 4183 break;
b89e94af 4184 case 0xc: /* subx, V9 subc */
70c48285
RH		 4185 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4186 (xop & 0x10));
cf495bcf 4187 break;
ded3ab80 4188#ifdef TARGET_SPARC64
0f8a249a 4189 case 0xd: /* V9 udivx */
c28ae41e 4190 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 4191 break;
4192#endif
b89e94af 4193 case 0xe: /* udiv */
64a88d5d 4194 CHECK_IU_FEATURE(dc, DIV);
8393617c 4195 if (xop & 0x10) {
7a5e4488
BS		 4196 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
4197 cpu_src2);
6c78ea32 4198 dc->cc_op = CC_OP_DIV;
0fcec41e 4199 } else {
7a5e4488
BS		 4200 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
4201 cpu_src2);
8393617c 4202 }
cf495bcf 4203 break;
b89e94af 4204 case 0xf: /* sdiv */
64a88d5d 4205 CHECK_IU_FEATURE(dc, DIV);
8393617c 4206 if (xop & 0x10) {
7a5e4488
BS		 4207 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
4208 cpu_src2);
6c78ea32 4209 dc->cc_op = CC_OP_DIV;
0fcec41e 4210 } else {
7a5e4488
BS		 4211 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
4212 cpu_src2);
8393617c 4213 }
cf495bcf
FB		 4214 break;
4215 default:
4216 goto illegal_insn;
4217 }
97ea2859 4218 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4219 } else {
9d1d4e34
RH		 4220 cpu_src1 = get_src1(dc, insn);
4221 cpu_src2 = get_src2(dc, insn);
cf495bcf 4222 switch (xop) {
0f8a249a 4223 case 0x20: /* taddcc */
a2ea4aa9 4224 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4225 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4226 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
4227 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 4228 break;
4229 case 0x21: /* tsubcc */
a2ea4aa9 4230 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4231 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4232 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
4233 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 4234 break;
4235 case 0x22: /* taddcctv */
a2ea4aa9
RH		 4236 gen_helper_taddcctv(cpu_dst, cpu_env,
4237 cpu_src1, cpu_src2);
97ea2859 4238 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4239 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 4240 break;
4241 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 4242 gen_helper_tsubcctv(cpu_dst, cpu_env,
4243 cpu_src1, cpu_src2);
97ea2859 4244 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4245 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 4246 break;
cf495bcf 4247 case 0x24: /* mulscc */
20132b96 4248 update_psr(dc);
6ae20372 4249 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4250 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 4251 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4252 dc->cc_op = CC_OP_ADD;
cf495bcf 4253 break;
83469015 4254#ifndef TARGET_SPARC64
0f8a249a 4255 case 0x25: /* sll */
e35298cd 4256 if (IS_IMM) { /* immediate */
67526b20
BS		 4257 simm = GET_FIELDs(insn, 20, 31);
4258 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4259 } else { /* register */
de9e9d9f 4260 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4261 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4262 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
4263 }
97ea2859 4264 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4265 break;
83469015 4266 case 0x26: /* srl */
e35298cd 4267 if (IS_IMM) { /* immediate */
67526b20
BS		 4268 simm = GET_FIELDs(insn, 20, 31);
4269 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4270 } else { /* register */
de9e9d9f 4271 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4272 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4273 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
4274 }
97ea2859 4275 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4276 break;
83469015 4277 case 0x27: /* sra */
e35298cd 4278 if (IS_IMM) { /* immediate */
67526b20
BS		 4279 simm = GET_FIELDs(insn, 20, 31);
4280 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4281 } else { /* register */
de9e9d9f 4282 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4283 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4284 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
4285 }
97ea2859 4286 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4287 break;
83469015 4288#endif
cf495bcf
FB		 4289 case 0x30:
4290 {
de9e9d9f 4291 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 4292 switch(rd) {
3475187d 4293 case 0: /* wry */
5068cbd9
BS		 4294 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4295 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 4296 break;
65fe7b09
BS		 4297#ifndef TARGET_SPARC64
4298 case 0x01 ... 0x0f: /* undefined in the
4299 SPARCv8 manual, nop
4300 on the microSPARC
4301 II */
4302 case 0x10 ... 0x1f: /* implementation-dependent
4303 in the SPARCv8
4304 manual, nop on the
4305 microSPARC II */
d1c36ba7
RH		 4306 if ((rd == 0x13) && (dc->def->features &
4307 CPU_FEATURE_POWERDOWN)) {
4308 /* LEON3 power-down */
1cf892ca 4309 save_state(dc);
d1c36ba7
RH		 4310 gen_helper_power_down(cpu_env);
4311 }
65fe7b09
BS		 4312 break;
4313#else
0f8a249a 4314 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 4315 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4316 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 4317 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4318 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 4319 break;
4320 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 4321 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4322 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
a6d567e5
RH		 4323 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4324 offsetof(CPUSPARCState, asi));
4325 /* End TB to notice changed ASI. */
4326 save_state(dc);
4327 gen_op_next_insn();
4328 tcg_gen_exit_tb(0);
4329 dc->is_br = 1;
0f8a249a
BS		 4330 break;
4331 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 4332 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4333 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
f9c816c0 4334 dc->fprs_dirty = 0;
66442b07 4335 save_state(dc);
3299908c 4336 gen_op_next_insn();
57fec1fe 4337 tcg_gen_exit_tb(0);
3299908c 4338 dc->is_br = 1;
0f8a249a
BS		 4339 break;
4340 case 0xf: /* V9 sir, nop if user */
3475187d 4341#if !defined(CONFIG_USER_ONLY)
6ad6135d 4342 if (supervisor(dc)) {
1a2fb1c0 4343 ; // XXX
6ad6135d 4344 }
3475187d 4345#endif
0f8a249a
BS		 4346 break;
4347 case 0x13: /* Graphics Status */
5b12f1e8 4348 if (gen_trap_ifnofpu(dc)) {
725cb90b 4349 goto jmp_insn;
5b12f1e8 4350 }
255e1fcb 4351 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 4352 break;
9d926598
BS		 4353 case 0x14: /* Softint set */
4354 if (!supervisor(dc))
4355 goto illegal_insn;
aeff993c
RH		 4356 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4357 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4358 break;
4359 case 0x15: /* Softint clear */
4360 if (!supervisor(dc))
4361 goto illegal_insn;
aeff993c
RH		 4362 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4363 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4364 break;
4365 case 0x16: /* Softint write */
4366 if (!supervisor(dc))
4367 goto illegal_insn;
aeff993c
RH		 4368 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4369 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 4370 break;
0f8a249a 4371 case 0x17: /* Tick compare */
83469015 4372#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4373 if (!supervisor(dc))
4374 goto illegal_insn;
83469015 4375#endif
ccd4a219 4376 {
a7812ae4 4377 TCGv_ptr r_tickptr;
ccd4a219 4378
255e1fcb 4379 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 4380 cpu_src2);
a7812ae4 4381 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4382 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4383 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4384 gen_helper_tick_set_limit(r_tickptr,
4385 cpu_tick_cmpr);
4386 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4387 }
0f8a249a
BS		 4388 break;
4389 case 0x18: /* System tick */
83469015 4390#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4391 if (!supervisor(dc))
4392 goto illegal_insn;
83469015 4393#endif
ccd4a219 4394 {
a7812ae4 4395 TCGv_ptr r_tickptr;
ccd4a219 4396
7b04bd5c 4397 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 4398 cpu_src2);
a7812ae4 4399 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4400 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4401 offsetof(CPUSPARCState, stick));
a7812ae4 4402 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 4403 cpu_tmp0);
a7812ae4 4404 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4405 }
0f8a249a
BS		 4406 break;
4407 case 0x19: /* System tick compare */
83469015 4408#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4409 if (!supervisor(dc))
4410 goto illegal_insn;
3475187d 4411#endif
ccd4a219 4412 {
a7812ae4 4413 TCGv_ptr r_tickptr;
ccd4a219 4414
255e1fcb 4415 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 4416 cpu_src2);
a7812ae4 4417 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4418 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4419 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 4420 gen_helper_tick_set_limit(r_tickptr,
4421 cpu_stick_cmpr);
4422 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4423 }
0f8a249a 4424 break;
83469015 4425
0f8a249a 4426 case 0x10: /* Performance Control */
77f193da
BS		 4427 case 0x11: /* Performance Instrumentation
4428 Counter */
0f8a249a 4429 case 0x12: /* Dispatch Control */
83469015 4430#endif
3475187d 4431 default:
cf495bcf
FB		 4432 goto illegal_insn;
4433 }
4434 }
4435 break;
e8af50a3 4436#if !defined(CONFIG_USER_ONLY)
af7bf89b 4437 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 4438 {
0f8a249a
BS		 4439 if (!supervisor(dc))
4440 goto priv_insn;
3475187d 4441#ifdef TARGET_SPARC64
0f8a249a
BS		 4442 switch (rd) {
4443 case 0:
063c3675 4444 gen_helper_saved(cpu_env);
0f8a249a
BS		 4445 break;
4446 case 1:
063c3675 4447 gen_helper_restored(cpu_env);
0f8a249a 4448 break;
e9ebed4d
BS		 4449 case 2: /* UA2005 allclean */
4450 case 3: /* UA2005 otherw */
4451 case 4: /* UA2005 normalw */
4452 case 5: /* UA2005 invalw */
4453 // XXX
0f8a249a 4454 default:
3475187d
FB		 4455 goto illegal_insn;
4456 }
4457#else
de9e9d9f 4458 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 4459 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4460 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 4461 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4462 dc->cc_op = CC_OP_FLAGS;
66442b07 4463 save_state(dc);
9e61bde5 4464 gen_op_next_insn();
57fec1fe 4465 tcg_gen_exit_tb(0);
0f8a249a 4466 dc->is_br = 1;
3475187d 4467#endif
e8af50a3
FB		 4468 }
4469 break;
af7bf89b 4470 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 4471 {
0f8a249a
BS		 4472 if (!supervisor(dc))
4473 goto priv_insn;
de9e9d9f 4474 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4475 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 4476#ifdef TARGET_SPARC64
0f8a249a
BS		 4477 switch (rd) {
4478 case 0: // tpc
375ee38b 4479 {
a7812ae4 4480 TCGv_ptr r_tsptr;
375ee38b 4481
a7812ae4 4482 r_tsptr = tcg_temp_new_ptr();
8194f35a 4483 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4484 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4485 offsetof(trap_state, tpc));
a7812ae4 4486 tcg_temp_free_ptr(r_tsptr);
375ee38b 4487 }
0f8a249a
BS		 4488 break;
4489 case 1: // tnpc
375ee38b 4490 {
a7812ae4 4491 TCGv_ptr r_tsptr;
375ee38b 4492
a7812ae4 4493 r_tsptr = tcg_temp_new_ptr();
8194f35a 4494 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4495 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4496 offsetof(trap_state, tnpc));
a7812ae4 4497 tcg_temp_free_ptr(r_tsptr);
375ee38b 4498 }
0f8a249a
BS		 4499 break;
4500 case 2: // tstate
375ee38b 4501 {
a7812ae4 4502 TCGv_ptr r_tsptr;
375ee38b 4503
a7812ae4 4504 r_tsptr = tcg_temp_new_ptr();
8194f35a 4505 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4506 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 4507 offsetof(trap_state,
4508 tstate));
a7812ae4 4509 tcg_temp_free_ptr(r_tsptr);
375ee38b 4510 }
0f8a249a
BS		 4511 break;
4512 case 3: // tt
375ee38b 4513 {
a7812ae4 4514 TCGv_ptr r_tsptr;
375ee38b 4515
a7812ae4 4516 r_tsptr = tcg_temp_new_ptr();
8194f35a 4517 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 4518 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
4519 offsetof(trap_state, tt));
a7812ae4 4520 tcg_temp_free_ptr(r_tsptr);
375ee38b 4521 }
0f8a249a
BS		 4522 break;
4523 case 4: // tick
ccd4a219 4524 {
a7812ae4 4525 TCGv_ptr r_tickptr;
ccd4a219 4526
a7812ae4 4527 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4528 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4529 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4530 gen_helper_tick_set_count(r_tickptr,
4531 cpu_tmp0);
4532 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4533 }
0f8a249a
BS		 4534 break;
4535 case 5: // tba
255e1fcb 4536 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 4537 break;
4538 case 6: // pstate
6234ac09
RH		 4539 save_state(dc);
4540 gen_helper_wrpstate(cpu_env, cpu_tmp0);
4541 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4542 break;
4543 case 7: // tl
6234ac09 4544 save_state(dc);
7b9e066b 4545 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 4546 offsetof(CPUSPARCState, tl));
4547 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4548 break;
4549 case 8: // pil
063c3675 4550 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 4551 break;
4552 case 9: // cwp
063c3675 4553 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 4554 break;
4555 case 10: // cansave
7b9e066b
RH		 4556 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4557 offsetof(CPUSPARCState,
4558 cansave));
0f8a249a
BS		 4559 break;
4560 case 11: // canrestore
7b9e066b
RH		 4561 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4562 offsetof(CPUSPARCState,
4563 canrestore));
0f8a249a
BS		 4564 break;
4565 case 12: // cleanwin
7b9e066b
RH		 4566 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4567 offsetof(CPUSPARCState,
4568 cleanwin));
0f8a249a
BS		 4569 break;
4570 case 13: // otherwin
7b9e066b
RH		 4571 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4572 offsetof(CPUSPARCState,
4573 otherwin));
0f8a249a
BS		 4574 break;
4575 case 14: // wstate
7b9e066b
RH		 4576 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4577 offsetof(CPUSPARCState,
4578 wstate));
0f8a249a 4579 break;
e9ebed4d 4580 case 16: // UA2005 gl
fb79ceb9 4581 CHECK_IU_FEATURE(dc, GL);
cbc3a6a4 4582 gen_helper_wrgl(cpu_env, cpu_tmp0);
e9ebed4d
BS		 4583 break;
4584 case 26: // UA2005 strand status
fb79ceb9 4585 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4586 if (!hypervisor(dc))
4587 goto priv_insn;
527067d8 4588 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 4589 break;
0f8a249a
BS		 4590 default:
4591 goto illegal_insn;
4592 }
3475187d 4593#else
7b9e066b
RH		 4594 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
4595 if (dc->def->nwindows != 32) {
4596 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 4597 (1 << dc->def->nwindows) - 1);
7b9e066b 4598 }
3475187d 4599#endif
e8af50a3
FB		 4600 }
4601 break;
e9ebed4d 4602 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 4603 {
e9ebed4d 4604#ifndef TARGET_SPARC64
0f8a249a
BS		 4605 if (!supervisor(dc))
4606 goto priv_insn;
255e1fcb 4607 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 4608#else
fb79ceb9 4609 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4610 if (!hypervisor(dc))
4611 goto priv_insn;
de9e9d9f 4612 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4613 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 4614 switch (rd) {
4615 case 0: // hpstate
f7f17ef7
AT		 4616 tcg_gen_st_i64(cpu_tmp0, cpu_env,
4617 offsetof(CPUSPARCState,
4618 hpstate));
66442b07 4619 save_state(dc);
e9ebed4d 4620 gen_op_next_insn();
57fec1fe 4621 tcg_gen_exit_tb(0);
e9ebed4d
BS		 4622 dc->is_br = 1;
4623 break;
4624 case 1: // htstate
4625 // XXX gen_op_wrhtstate();
4626 break;
4627 case 3: // hintp
255e1fcb 4628 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 4629 break;
4630 case 5: // htba
255e1fcb 4631 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 4632 break;
4633 case 31: // hstick_cmpr
ccd4a219 4634 {
a7812ae4 4635 TCGv_ptr r_tickptr;
ccd4a219 4636
255e1fcb 4637 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 4638 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4639 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4640 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 4641 gen_helper_tick_set_limit(r_tickptr,
4642 cpu_hstick_cmpr);
4643 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4644 }
e9ebed4d
BS		 4645 break;
4646 case 6: // hver readonly
4647 default:
4648 goto illegal_insn;
4649 }
4650#endif
e8af50a3
FB		 4651 }
4652 break;
4653#endif
3475187d 4654#ifdef TARGET_SPARC64
0f8a249a
BS		 4655 case 0x2c: /* V9 movcc */
4656 {
4657 int cc = GET_FIELD_SP(insn, 11, 12);
4658 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 4659 DisasCompare cmp;
97ea2859 4660 TCGv dst;
00f219bf 4661
0f8a249a 4662 if (insn & (1 << 18)) {
f52879b4
RH		 4663 if (cc == 0) {
4664 gen_compare(&cmp, 0, cond, dc);
4665 } else if (cc == 2) {
4666 gen_compare(&cmp, 1, cond, dc);
4667 } else {
0f8a249a 4668 goto illegal_insn;
f52879b4 4669 }
0f8a249a 4670 } else {
f52879b4 4671 gen_fcompare(&cmp, cc, cond);
0f8a249a 4672 }
00f219bf 4673
f52879b4
RH		 4674 /* The get_src2 above loaded the normal 13-bit
4675 immediate field, not the 11-bit field we have
4676 in movcc. But it did handle the reg case. */
4677 if (IS_IMM) {
67526b20 4678 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 4679 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 4680 }
f52879b4 4681
97ea2859
RH		 4682 dst = gen_load_gpr(dc, rd);
4683 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 4684 cmp.c1, cmp.c2,
97ea2859 4685 cpu_src2, dst);
f52879b4 4686 free_compare(&cmp);
97ea2859 4687 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4688 break;
4689 }
4690 case 0x2d: /* V9 sdivx */
c28ae41e 4691 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 4692 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 4693 break;
4694 case 0x2e: /* V9 popc */
08da3180 4695 tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
97ea2859
RH		 4696 gen_store_gpr(dc, rd, cpu_dst);
4697 break;
0f8a249a
BS		 4698 case 0x2f: /* V9 movr */
4699 {
4700 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 4701 DisasCompare cmp;
97ea2859 4702 TCGv dst;
00f219bf 4703
c33f80f5 4704 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4705
c33f80f5
RH		 4706 /* The get_src2 above loaded the normal 13-bit
4707 immediate field, not the 10-bit field we have
4708 in movr. But it did handle the reg case. */
4709 if (IS_IMM) {
67526b20 4710 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4711 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4712 }
c33f80f5 4713
97ea2859
RH		 4714 dst = gen_load_gpr(dc, rd);
4715 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4716 cmp.c1, cmp.c2,
97ea2859 4717 cpu_src2, dst);
c33f80f5 4718 free_compare(&cmp);
97ea2859 4719 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4720 break;
4721 }
4722#endif
4723 default:
4724 goto illegal_insn;
4725 }
4726 }
3299908c
BS		 4727 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4728#ifdef TARGET_SPARC64
4729 int opf = GET_FIELD_SP(insn, 5, 13);
4730 rs1 = GET_FIELD(insn, 13, 17);
4731 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4732 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4733 goto jmp_insn;
5b12f1e8 4734 }
3299908c
BS		 4735
4736 switch (opf) {
e9ebed4d 4737 case 0x000: /* VIS I edge8cc */
6c073553 4738 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4739 cpu_src1 = gen_load_gpr(dc, rs1);
4740 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4741 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4742 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4743 break;
e9ebed4d 4744 case 0x001: /* VIS II edge8n */
6c073553 4745 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4746 cpu_src1 = gen_load_gpr(dc, rs1);
4747 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4748 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4749 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4750 break;
e9ebed4d 4751 case 0x002: /* VIS I edge8lcc */
6c073553 4752 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4753 cpu_src1 = gen_load_gpr(dc, rs1);
4754 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4755 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4756 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4757 break;
e9ebed4d 4758 case 0x003: /* VIS II edge8ln */
6c073553 4759 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4760 cpu_src1 = gen_load_gpr(dc, rs1);
4761 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4762 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4763 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4764 break;
e9ebed4d 4765 case 0x004: /* VIS I edge16cc */
6c073553 4766 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4767 cpu_src1 = gen_load_gpr(dc, rs1);
4768 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4769 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4770 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4771 break;
e9ebed4d 4772 case 0x005: /* VIS II edge16n */
6c073553 4773 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4774 cpu_src1 = gen_load_gpr(dc, rs1);
4775 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4776 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4777 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4778 break;
e9ebed4d 4779 case 0x006: /* VIS I edge16lcc */
6c073553 4780 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4781 cpu_src1 = gen_load_gpr(dc, rs1);
4782 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4783 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4784 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4785 break;
e9ebed4d 4786 case 0x007: /* VIS II edge16ln */
6c073553 4787 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4788 cpu_src1 = gen_load_gpr(dc, rs1);
4789 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4790 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4791 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4792 break;
e9ebed4d 4793 case 0x008: /* VIS I edge32cc */
6c073553 4794 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4795 cpu_src1 = gen_load_gpr(dc, rs1);
4796 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4797 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4798 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4799 break;
e9ebed4d 4800 case 0x009: /* VIS II edge32n */
6c073553 4801 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4802 cpu_src1 = gen_load_gpr(dc, rs1);
4803 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4804 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4805 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4806 break;
e9ebed4d 4807 case 0x00a: /* VIS I edge32lcc */
6c073553 4808 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4809 cpu_src1 = gen_load_gpr(dc, rs1);
4810 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4811 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4812 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4813 break;
e9ebed4d 4814 case 0x00b: /* VIS II edge32ln */
6c073553 4815 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4816 cpu_src1 = gen_load_gpr(dc, rs1);
4817 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4818 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4819 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4820 break;
e9ebed4d 4821 case 0x010: /* VIS I array8 */
64a88d5d 4822 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4823 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4824 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4825 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4826 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4827 break;
4828 case 0x012: /* VIS I array16 */
64a88d5d 4829 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4830 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4831 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4832 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4833 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4834 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4835 break;
4836 case 0x014: /* VIS I array32 */
64a88d5d 4837 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4838 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4839 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4840 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4841 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4842 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4843 break;
3299908c 4844 case 0x018: /* VIS I alignaddr */
64a88d5d 4845 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4846 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4847 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4848 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4849 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4850 break;
4851 case 0x01a: /* VIS I alignaddrl */
add545ab 4852 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4853 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4854 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4855 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4856 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4857 break;
4858 case 0x019: /* VIS II bmask */
793a137a 4859 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4860 cpu_src1 = gen_load_gpr(dc, rs1);
4861 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4862 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4863 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4864 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4865 break;
e9ebed4d 4866 case 0x020: /* VIS I fcmple16 */
64a88d5d 4867 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4868 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4869 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4870 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4871 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4872 break;
4873 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4874 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4875 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4876 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4877 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4878 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4879 break;
e9ebed4d 4880 case 0x024: /* VIS I fcmple32 */
64a88d5d 4881 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4882 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4883 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4884 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4885 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4886 break;
4887 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4888 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4889 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4890 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4891 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4892 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4893 break;
4894 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4895 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4896 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4897 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4898 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4899 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4900 break;
4901 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4902 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4903 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4904 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4905 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4906 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4907 break;
4908 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4909 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4910 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4911 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4912 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4913 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4914 break;
4915 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4916 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4917 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4918 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4919 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4920 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4921 break;
4922 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4923 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4924 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4925 break;
4926 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4927 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4928 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4929 break;
4930 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4931 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4932 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4933 break;
4934 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4935 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4936 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4937 break;
4938 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4939 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4940 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4941 break;
4942 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4943 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4944 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4945 break;
4946 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4947 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4948 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4949 break;
4950 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4951 CHECK_FPU_FEATURE(dc, VIS1);
4952 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4953 break;
e9ebed4d 4954 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4955 CHECK_FPU_FEATURE(dc, VIS1);
4956 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4957 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4958 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4959 gen_store_fpr_F(dc, rd, cpu_dst_32);
4960 break;
e9ebed4d 4961 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4962 CHECK_FPU_FEATURE(dc, VIS1);
4963 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4964 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4965 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4966 gen_store_fpr_F(dc, rd, cpu_dst_32);
4967 break;
f888300b
RH		 4968 case 0x03e: /* VIS I pdist */
4969 CHECK_FPU_FEATURE(dc, VIS1);
4970 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4971 break;
3299908c 4972 case 0x048: /* VIS I faligndata */
64a88d5d 4973 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4974 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4975 break;
e9ebed4d 4976 case 0x04b: /* VIS I fpmerge */
64a88d5d 4977 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4978 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4979 break;
4980 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4981 CHECK_FPU_FEATURE(dc, VIS2);
4982 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4983 break;
e9ebed4d 4984 case 0x04d: /* VIS I fexpand */
64a88d5d 4985 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4986 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4987 break;
4988 case 0x050: /* VIS I fpadd16 */
64a88d5d 4989 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4990 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4991 break;
4992 case 0x051: /* VIS I fpadd16s */
64a88d5d 4993 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4994 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4995 break;
4996 case 0x052: /* VIS I fpadd32 */
64a88d5d 4997 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4998 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4999 break;
5000 case 0x053: /* VIS I fpadd32s */
64a88d5d 5001 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5002 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 5003 break;
5004 case 0x054: /* VIS I fpsub16 */
64a88d5d 5005 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5006 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 5007 break;
5008 case 0x055: /* VIS I fpsub16s */
64a88d5d 5009 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5010 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 5011 break;
5012 case 0x056: /* VIS I fpsub32 */
64a88d5d 5013 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5014 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 5015 break;
5016 case 0x057: /* VIS I fpsub32s */
64a88d5d 5017 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5018 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 5019 break;
3299908c 5020 case 0x060: /* VIS I fzero */
64a88d5d 5021 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5022 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5023 tcg_gen_movi_i64(cpu_dst_64, 0);
5024 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5025 break;
5026 case 0x061: /* VIS I fzeros */
64a88d5d 5027 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5028 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5029 tcg_gen_movi_i32(cpu_dst_32, 0);
5030 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5031 break;
e9ebed4d 5032 case 0x062: /* VIS I fnor */
64a88d5d 5033 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5034 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 5035 break;
5036 case 0x063: /* VIS I fnors */
64a88d5d 5037 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5038 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 5039 break;
5040 case 0x064: /* VIS I fandnot2 */
64a88d5d 5041 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5042 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 5043 break;
5044 case 0x065: /* VIS I fandnot2s */
64a88d5d 5045 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5046 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 5047 break;
5048 case 0x066: /* VIS I fnot2 */
64a88d5d 5049 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5050 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 5051 break;
5052 case 0x067: /* VIS I fnot2s */
64a88d5d 5053 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5054 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 5055 break;
5056 case 0x068: /* VIS I fandnot1 */
64a88d5d 5057 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5058 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 5059 break;
5060 case 0x069: /* VIS I fandnot1s */
64a88d5d 5061 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5062 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 5063 break;
5064 case 0x06a: /* VIS I fnot1 */
64a88d5d 5065 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5066 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 5067 break;
5068 case 0x06b: /* VIS I fnot1s */
64a88d5d 5069 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5070 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 5071 break;
5072 case 0x06c: /* VIS I fxor */
64a88d5d 5073 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5074 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 5075 break;
5076 case 0x06d: /* VIS I fxors */
64a88d5d 5077 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5078 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 5079 break;
5080 case 0x06e: /* VIS I fnand */
64a88d5d 5081 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5082 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 5083 break;
5084 case 0x06f: /* VIS I fnands */
64a88d5d 5085 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5086 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 5087 break;
5088 case 0x070: /* VIS I fand */
64a88d5d 5089 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5090 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 5091 break;
5092 case 0x071: /* VIS I fands */
64a88d5d 5093 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5094 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 5095 break;
5096 case 0x072: /* VIS I fxnor */
64a88d5d 5097 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5098 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 5099 break;
5100 case 0x073: /* VIS I fxnors */
64a88d5d 5101 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5102 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 5103 break;
3299908c 5104 case 0x074: /* VIS I fsrc1 */
64a88d5d 5105 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5106 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5107 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5108 break;
5109 case 0x075: /* VIS I fsrc1s */
64a88d5d 5110 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5111 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5112 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5113 break;
e9ebed4d 5114 case 0x076: /* VIS I fornot2 */
64a88d5d 5115 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5116 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 5117 break;
5118 case 0x077: /* VIS I fornot2s */
64a88d5d 5119 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5120 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 5121 break;
3299908c 5122 case 0x078: /* VIS I fsrc2 */
64a88d5d 5123 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5124 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5125 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5126 break;
5127 case 0x079: /* VIS I fsrc2s */
64a88d5d 5128 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5129 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5130 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5131 break;
e9ebed4d 5132 case 0x07a: /* VIS I fornot1 */
64a88d5d 5133 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5134 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 5135 break;
5136 case 0x07b: /* VIS I fornot1s */
64a88d5d 5137 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5138 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 5139 break;
5140 case 0x07c: /* VIS I for */
64a88d5d 5141 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5142 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 5143 break;
5144 case 0x07d: /* VIS I fors */
64a88d5d 5145 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5146 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 5147 break;
3299908c 5148 case 0x07e: /* VIS I fone */
64a88d5d 5149 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5150 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5151 tcg_gen_movi_i64(cpu_dst_64, -1);
5152 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5153 break;
5154 case 0x07f: /* VIS I fones */
64a88d5d 5155 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5156 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5157 tcg_gen_movi_i32(cpu_dst_32, -1);
5158 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5159 break;
e9ebed4d
BS		 5160 case 0x080: /* VIS I shutdown */
5161 case 0x081: /* VIS II siam */
5162 // XXX
5163 goto illegal_insn;
3299908c
BS		 5164 default:
5165 goto illegal_insn;
5166 }
5167#else
0f8a249a 5168 goto ncp_insn;
3299908c
BS		 5169#endif
5170 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 5171#ifdef TARGET_SPARC64
0f8a249a 5172 goto illegal_insn;
fcc72045 5173#else
0f8a249a 5174 goto ncp_insn;
fcc72045 5175#endif
3475187d 5176#ifdef TARGET_SPARC64
0f8a249a 5177 } else if (xop == 0x39) { /* V9 return */
66442b07 5178 save_state(dc);
9d1d4e34 5179 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5180 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5181 if (IS_IMM) { /* immediate */
67526b20 5182 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5183 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5184 } else { /* register */
3475187d 5185 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5186 if (rs2) {
97ea2859 5187 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5188 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5189 } else {
7b04bd5c 5190 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5191 }
3475187d 5192 }
063c3675 5193 gen_helper_restore(cpu_env);
13a6dd00 5194 gen_mov_pc_npc(dc);
35e94905 5195 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5196 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5197 dc->npc = DYNAMIC_PC;
5198 goto jmp_insn;
3475187d 5199#endif
0f8a249a 5200 } else {
9d1d4e34 5201 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5202 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5203 if (IS_IMM) { /* immediate */
67526b20 5204 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5205 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5206 } else { /* register */
e80cfcfc 5207 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5208 if (rs2) {
97ea2859 5209 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5210 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5211 } else {
7b04bd5c 5212 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5213 }
cf495bcf 5214 }
0f8a249a
BS		 5215 switch (xop) {
5216 case 0x38: /* jmpl */
5217 {
35e94905 5218 TCGv t = gen_dest_gpr(dc, rd);
97ea2859
RH		 5219 tcg_gen_movi_tl(t, dc->pc);
5220 gen_store_gpr(dc, rd, t);
35e94905 5221
13a6dd00 5222 gen_mov_pc_npc(dc);
35e94905 5223 gen_check_align(cpu_tmp0, 3);
7b04bd5c
RH		 5224 gen_address_mask(dc, cpu_tmp0);
5225 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5226 dc->npc = DYNAMIC_PC;
5227 }
5228 goto jmp_insn;
3475187d 5229#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 5230 case 0x39: /* rett, V9 return */
5231 {
5232 if (!supervisor(dc))
5233 goto priv_insn;
13a6dd00 5234 gen_mov_pc_npc(dc);
35e94905 5235 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5236 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 5237 dc->npc = DYNAMIC_PC;
063c3675 5238 gen_helper_rett(cpu_env);
0f8a249a
BS		 5239 }
5240 goto jmp_insn;
5241#endif
5242 case 0x3b: /* flush */
5578ceab 5243 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 5244 goto unimp_flush;
dcfd14b3 5245 /* nop */
0f8a249a
BS		 5246 break;
5247 case 0x3c: /* save */
063c3675 5248 gen_helper_save(cpu_env);
7b04bd5c 5249 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 5250 break;
5251 case 0x3d: /* restore */
063c3675 5252 gen_helper_restore(cpu_env);
7b04bd5c 5253 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 5254 break;
3475187d 5255#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 5256 case 0x3e: /* V9 done/retry */
5257 {
5258 switch (rd) {
5259 case 0:
5260 if (!supervisor(dc))
5261 goto priv_insn;
5262 dc->npc = DYNAMIC_PC;
5263 dc->pc = DYNAMIC_PC;
063c3675 5264 gen_helper_done(cpu_env);
0f8a249a
BS		 5265 goto jmp_insn;
5266 case 1:
5267 if (!supervisor(dc))
5268 goto priv_insn;
5269 dc->npc = DYNAMIC_PC;
5270 dc->pc = DYNAMIC_PC;
063c3675 5271 gen_helper_retry(cpu_env);
0f8a249a
BS		 5272 goto jmp_insn;
5273 default:
5274 goto illegal_insn;
5275 }
5276 }
5277 break;
5278#endif
5279 default:
5280 goto illegal_insn;
5281 }
cf495bcf 5282 }
0f8a249a
BS		 5283 break;
5284 }
5285 break;
5286 case 3: /* load/store instructions */
5287 {
5288 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 5289 /* ??? gen_address_mask prevents us from using a source
5290 register directly. Always generate a temporary. */
5291 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 5292
5e6ed439
RH		 5293 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5294 if (xop == 0x3c || xop == 0x3e) {
5295 /* V9 casa/casxa : no offset */
71817e48 5296 } else if (IS_IMM) { /* immediate */
67526b20 5297 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 5298 if (simm != 0) {
5299 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5300 }
0f8a249a
BS		 5301 } else { /* register */
5302 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5303 if (rs2 != 0) {
5e6ed439 5304 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 5305 }
0f8a249a 5306 }
2f2ecb83
BS		 5307 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5308 (xop > 0x17 && xop <= 0x1d ) ||
5309 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 5310 TCGv cpu_val = gen_dest_gpr(dc, rd);
5311
0f8a249a 5312 switch (xop) {
b89e94af 5313 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 5314 gen_address_mask(dc, cpu_addr);
6ae20372 5315 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5316 break;
b89e94af 5317 case 0x1: /* ldub, load unsigned byte */
2cade6a3 5318 gen_address_mask(dc, cpu_addr);
6ae20372 5319 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5320 break;
b89e94af 5321 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 5322 gen_address_mask(dc, cpu_addr);
6ae20372 5323 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5324 break;
b89e94af 5325 case 0x3: /* ldd, load double word */
0f8a249a 5326 if (rd & 1)
d4218d99 5327 goto illegal_insn;
1a2fb1c0 5328 else {
abcc7191 5329 TCGv_i64 t64;
2ea815ca 5330
2cade6a3 5331 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 5332 t64 = tcg_temp_new_i64();
5333 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 5334 tcg_gen_trunc_i64_tl(cpu_val, t64);
5335 tcg_gen_ext32u_tl(cpu_val, cpu_val);
5336 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 5337 tcg_gen_shri_i64(t64, t64, 32);
5338 tcg_gen_trunc_i64_tl(cpu_val, t64);
5339 tcg_temp_free_i64(t64);
de9e9d9f 5340 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 5341 }
0f8a249a 5342 break;
b89e94af 5343 case 0x9: /* ldsb, load signed byte */
2cade6a3 5344 gen_address_mask(dc, cpu_addr);
6ae20372 5345 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5346 break;
b89e94af 5347 case 0xa: /* ldsh, load signed halfword */
2cade6a3 5348 gen_address_mask(dc, cpu_addr);
6ae20372 5349 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5350 break;
fbb4bbb6
RH		 5351 case 0xd: /* ldstub */
5352 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5353 break;
de9e9d9f
RH		 5354 case 0x0f:
5355 /* swap, swap register with memory. Also atomically */
4fb554bc
RH		 5356 CHECK_IU_FEATURE(dc, SWAP);
5357 cpu_src1 = gen_load_gpr(dc, rd);
5358 gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5359 dc->mem_idx, MO_TEUL);
0f8a249a 5360 break;
3475187d 5361#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5362 case 0x10: /* lda, V9 lduwa, load word alternate */
1d65b0f5 5363 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
0f8a249a 5364 break;
b89e94af 5365 case 0x11: /* lduba, load unsigned byte alternate */
1d65b0f5 5366 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
0f8a249a 5367 break;
b89e94af 5368 case 0x12: /* lduha, load unsigned halfword alternate */
1d65b0f5 5369 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
0f8a249a 5370 break;
b89e94af 5371 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 5372 if (rd & 1) {
d4218d99 5373 goto illegal_insn;
7ec1e5ea 5374 }
e4dc0052 5375 gen_ldda_asi(dc, cpu_addr, insn, rd);
db166940 5376 goto skip_move;
b89e94af 5377 case 0x19: /* ldsba, load signed byte alternate */
1d65b0f5 5378 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
0f8a249a 5379 break;
b89e94af 5380 case 0x1a: /* ldsha, load signed halfword alternate */
1d65b0f5 5381 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
0f8a249a
BS		 5382 break;
5383 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 5384 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 5385 break;
b89e94af 5386 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 5387 atomically */
64a88d5d 5388 CHECK_IU_FEATURE(dc, SWAP);
06828032 5389 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 5390 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 5391 break;
3475187d
FB		 5392
5393#ifndef TARGET_SPARC64
0f8a249a
BS		 5394 case 0x30: /* ldc */
5395 case 0x31: /* ldcsr */
5396 case 0x33: /* lddc */
5397 goto ncp_insn;
3475187d
FB		 5398#endif
5399#endif
5400#ifdef TARGET_SPARC64
0f8a249a 5401 case 0x08: /* V9 ldsw */
2cade6a3 5402 gen_address_mask(dc, cpu_addr);
6ae20372 5403 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5404 break;
5405 case 0x0b: /* V9 ldx */
2cade6a3 5406 gen_address_mask(dc, cpu_addr);
6ae20372 5407 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5408 break;
5409 case 0x18: /* V9 ldswa */
1d65b0f5 5410 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
0f8a249a
BS		 5411 break;
5412 case 0x1b: /* V9 ldxa */
1d65b0f5 5413 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a
BS		 5414 break;
5415 case 0x2d: /* V9 prefetch, no effect */
5416 goto skip_move;
5417 case 0x30: /* V9 ldfa */
5b12f1e8 5418 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5419 goto jmp_insn;
5420 }
22e70060 5421 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
f9c816c0 5422 gen_update_fprs_dirty(dc, rd);
81ad8ba2 5423 goto skip_move;
0f8a249a 5424 case 0x33: /* V9 lddfa */
5b12f1e8 5425 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5426 goto jmp_insn;
5427 }
22e70060 5428 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
f9c816c0 5429 gen_update_fprs_dirty(dc, DFPREG(rd));
81ad8ba2 5430 goto skip_move;
0f8a249a
BS		 5431 case 0x3d: /* V9 prefetcha, no effect */
5432 goto skip_move;
5433 case 0x32: /* V9 ldqfa */
64a88d5d 5434 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5435 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5436 goto jmp_insn;
5437 }
22e70060 5438 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
f9c816c0 5439 gen_update_fprs_dirty(dc, QFPREG(rd));
1f587329 5440 goto skip_move;
0f8a249a
BS		 5441#endif
5442 default:
5443 goto illegal_insn;
5444 }
97ea2859 5445 gen_store_gpr(dc, rd, cpu_val);
db166940 5446#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 5447 skip_move: ;
3475187d 5448#endif
0f8a249a 5449 } else if (xop >= 0x20 && xop < 0x24) {
5b12f1e8 5450 if (gen_trap_ifnofpu(dc)) {
a80dde08 5451 goto jmp_insn;
5b12f1e8 5452 }
0f8a249a 5453 switch (xop) {
b89e94af 5454 case 0x20: /* ldf, load fpreg */
2cade6a3 5455 gen_address_mask(dc, cpu_addr);
ba5f5179 5456 cpu_dst_32 = gen_dest_fpr_F(dc);
cb21b4da
RH		 5457 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5458 dc->mem_idx, MO_TEUL);
208ae657 5459 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 5460 break;
3a3b925d
BS		 5461 case 0x21: /* ldfsr, V9 ldxfsr */
5462#ifdef TARGET_SPARC64
2cade6a3 5463 gen_address_mask(dc, cpu_addr);
3a3b925d 5464 if (rd == 1) {
abcc7191 5465 TCGv_i64 t64 = tcg_temp_new_i64();
cb21b4da
RH		 5466 tcg_gen_qemu_ld_i64(t64, cpu_addr,
5467 dc->mem_idx, MO_TEQ);
7385aed2 5468 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
abcc7191 5469 tcg_temp_free_i64(t64);
f8641947 5470 break;
fe987e23 5471 }
f8641947 5472#endif
de9e9d9f 5473 cpu_dst_32 = get_temp_i32(dc);
cb21b4da
RH		 5474 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5475 dc->mem_idx, MO_TEUL);
7385aed2 5476 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
0f8a249a 5477 break;
b89e94af 5478 case 0x22: /* ldqf, load quad fpreg */
f939ffe5
RH		 5479 CHECK_FPU_FEATURE(dc, FLOAT128);
5480 gen_address_mask(dc, cpu_addr);
5481 cpu_src1_64 = tcg_temp_new_i64();
cb21b4da
RH		 5482 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5483 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5484 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5485 cpu_src2_64 = tcg_temp_new_i64();
cb21b4da
RH		 5486 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
5487 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5488 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
5489 tcg_temp_free_i64(cpu_src1_64);
5490 tcg_temp_free_i64(cpu_src2_64);
1f587329 5491 break;
b89e94af 5492 case 0x23: /* lddf, load double fpreg */
03fb8cfc 5493 gen_address_mask(dc, cpu_addr);
3886b8a3 5494 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
cb21b4da
RH		 5495 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
5496 MO_TEQ | MO_ALIGN_4);
03fb8cfc 5497 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 5498 break;
5499 default:
5500 goto illegal_insn;
5501 }
dc1a6971 5502 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 5503 xop == 0xe || xop == 0x1e) {
81634eea
RH		 5504 TCGv cpu_val = gen_load_gpr(dc, rd);
5505
0f8a249a 5506 switch (xop) {
b89e94af 5507 case 0x4: /* st, store word */
2cade6a3 5508 gen_address_mask(dc, cpu_addr);
6ae20372 5509 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5510 break;
b89e94af 5511 case 0x5: /* stb, store byte */
2cade6a3 5512 gen_address_mask(dc, cpu_addr);
6ae20372 5513 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5514 break;
b89e94af 5515 case 0x6: /* sth, store halfword */
2cade6a3 5516 gen_address_mask(dc, cpu_addr);
6ae20372 5517 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5518 break;
b89e94af 5519 case 0x7: /* std, store double word */
0f8a249a 5520 if (rd & 1)
d4218d99 5521 goto illegal_insn;
1a2fb1c0 5522 else {
abcc7191 5523 TCGv_i64 t64;
81634eea 5524 TCGv lo;
1a2fb1c0 5525
2cade6a3 5526 gen_address_mask(dc, cpu_addr);
81634eea 5527 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5528 t64 = tcg_temp_new_i64();
5529 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
5530 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
5531 tcg_temp_free_i64(t64);
7fa76c0b 5532 }
0f8a249a 5533 break;
3475187d 5534#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5535 case 0x14: /* sta, V9 stwa, store word alternate */
1d65b0f5 5536 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
d39c0b99 5537 break;
b89e94af 5538 case 0x15: /* stba, store byte alternate */
1d65b0f5 5539 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
d39c0b99 5540 break;
b89e94af 5541 case 0x16: /* stha, store halfword alternate */
1d65b0f5 5542 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
d39c0b99 5543 break;
b89e94af 5544 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5545 if (rd & 1) {
0f8a249a 5546 goto illegal_insn;
1a2fb1c0 5547 }
7ec1e5ea 5548 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5549 break;
e80cfcfc 5550#endif
3475187d 5551#ifdef TARGET_SPARC64
0f8a249a 5552 case 0x0e: /* V9 stx */
2cade6a3 5553 gen_address_mask(dc, cpu_addr);
6ae20372 5554 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5555 break;
5556 case 0x1e: /* V9 stxa */
1d65b0f5 5557 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a 5558 break;
3475187d 5559#endif
0f8a249a
BS		 5560 default:
5561 goto illegal_insn;
5562 }
5563 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5564 if (gen_trap_ifnofpu(dc)) {
a80dde08 5565 goto jmp_insn;
5b12f1e8 5566 }
0f8a249a 5567 switch (xop) {
b89e94af 5568 case 0x24: /* stf, store fpreg */
cb21b4da
RH		 5569 gen_address_mask(dc, cpu_addr);
5570 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5571 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
5572 dc->mem_idx, MO_TEUL);
0f8a249a
BS		 5573 break;
5574 case 0x25: /* stfsr, V9 stxfsr */
f8641947 5575 {
3a3b925d 5576#ifdef TARGET_SPARC64
f8641947
RH		 5577 gen_address_mask(dc, cpu_addr);
5578 if (rd == 1) {
ba2397d1 5579 tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947
RH		 5580 break;
5581 }
3a3b925d 5582#endif
ba2397d1 5583 tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947 5584 }
0f8a249a 5585 break;
1f587329
BS		 5586 case 0x26:
5587#ifdef TARGET_SPARC64
1f587329 5588 /* V9 stqf, store quad fpreg */
f939ffe5
RH		 5589 CHECK_FPU_FEATURE(dc, FLOAT128);
5590 gen_address_mask(dc, cpu_addr);
5591 /* ??? While stqf only requires 4-byte alignment, it is
5592 legal for the cpu to signal the unaligned exception.
5593 The OS trap handler is then required to fix it up.
5594 For qemu, this avoids having to probe the second page
5595 before performing the first write. */
5596 cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5597 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5598 dc->mem_idx, MO_TEQ | MO_ALIGN_16);
5599 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5600 cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5601 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5602 dc->mem_idx, MO_TEQ);
1f587329 5603 break;
1f587329
BS		 5604#else /* !TARGET_SPARC64 */
5605 /* stdfq, store floating point queue */
5606#if defined(CONFIG_USER_ONLY)
5607 goto illegal_insn;
5608#else
0f8a249a
BS		 5609 if (!supervisor(dc))
5610 goto priv_insn;
5b12f1e8 5611 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5612 goto jmp_insn;
5b12f1e8 5613 }
0f8a249a 5614 goto nfq_insn;
1f587329 5615#endif
0f8a249a 5616#endif
b89e94af 5617 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5618 gen_address_mask(dc, cpu_addr);
5619 cpu_src1_64 = gen_load_fpr_D(dc, rd);
cb21b4da
RH		 5620 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5621 MO_TEQ | MO_ALIGN_4);
0f8a249a
BS		 5622 break;
5623 default:
5624 goto illegal_insn;
5625 }
5626 } else if (xop > 0x33 && xop < 0x3f) {
5627 switch (xop) {
a4d17f19 5628#ifdef TARGET_SPARC64
0f8a249a 5629 case 0x34: /* V9 stfa */
5b12f1e8 5630 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5631 goto jmp_insn;
5632 }
22e70060 5633 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5634 break;
1f587329 5635 case 0x36: /* V9 stqfa */
2ea815ca 5636 {
2ea815ca 5637 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5638 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5639 goto jmp_insn;
5640 }
22e70060 5641 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5642 }
1f587329 5643 break;
0f8a249a 5644 case 0x37: /* V9 stdfa */
5b12f1e8 5645 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5646 goto jmp_insn;
5647 }
22e70060 5648 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5649 break;
0f8a249a 5650 case 0x3e: /* V9 casxa */
a4273524
RH		 5651 rs2 = GET_FIELD(insn, 27, 31);
5652 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5653 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5654 break;
a4d17f19 5655#else
0f8a249a
BS		 5656 case 0x34: /* stc */
5657 case 0x35: /* stcsr */
5658 case 0x36: /* stdcq */
5659 case 0x37: /* stdc */
5660 goto ncp_insn;
16c358e9
SH		 5661#endif
5662#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5663 case 0x3c: /* V9 or LEON3 casa */
5664#ifndef TARGET_SPARC64
5665 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5666#endif
5667 rs2 = GET_FIELD(insn, 27, 31);
5668 cpu_src2 = gen_load_gpr(dc, rs2);
5669 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5670 break;
0f8a249a
BS		 5671#endif
5672 default:
5673 goto illegal_insn;
5674 }
a4273524 5675 } else {
0f8a249a 5676 goto illegal_insn;
a4273524 5677 }
0f8a249a
BS		 5678 }
5679 break;
cf495bcf
FB		 5680 }
5681 /* default case for non jump instructions */
72cbca10 5682 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5683 dc->pc = DYNAMIC_PC;
5684 gen_op_next_insn();
72cbca10
FB		 5685 } else if (dc->npc == JUMP_PC) {
5686 /* we can do a static jump */
6ae20372 5687 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5688 dc->is_br = 1;
5689 } else {
0f8a249a
BS		 5690 dc->pc = dc->npc;
5691 dc->npc = dc->npc + 4;
cf495bcf 5692 }
e80cfcfc 5693 jmp_insn:
42a8aa83 5694 goto egress;
cf495bcf 5695 illegal_insn:
4fbe0067 5696 gen_exception(dc, TT_ILL_INSN);
42a8aa83 5697 goto egress;
64a88d5d 5698 unimp_flush:
4fbe0067 5699 gen_exception(dc, TT_UNIMP_FLUSH);
42a8aa83 5700 goto egress;
e80cfcfc 5701#if !defined(CONFIG_USER_ONLY)
e8af50a3 5702 priv_insn:
4fbe0067 5703 gen_exception(dc, TT_PRIV_INSN);
42a8aa83 5704 goto egress;
64a88d5d 5705#endif
e80cfcfc 5706 nfpu_insn:
4fbe0067 5707 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
42a8aa83 5708 goto egress;
64a88d5d 5709#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5710 nfq_insn:
4fbe0067 5711 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
42a8aa83 5712 goto egress;
9143e598 5713#endif
fcc72045
BS		 5714#ifndef TARGET_SPARC64
5715 ncp_insn:
4fbe0067 5716 gen_exception(dc, TT_NCP_INSN);
42a8aa83 5717 goto egress;
fcc72045 5718#endif
42a8aa83 5719 egress:
30038fd8
RH		 5720 if (dc->n_t32 != 0) {
5721 int i;
5722 for (i = dc->n_t32 - 1; i >= 0; --i) {
5723 tcg_temp_free_i32(dc->t32[i]);
5724 }
5725 dc->n_t32 = 0;
5726 }
88023616
RH		 5727 if (dc->n_ttl != 0) {
5728 int i;
5729 for (i = dc->n_ttl - 1; i >= 0; --i) {
5730 tcg_temp_free(dc->ttl[i]);
5731 }
5732 dc->n_ttl = 0;
5733 }
7a3f1944
FB		 5734}
5735
9c489ea6 5736void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
7a3f1944 5737{
9c489ea6 5738 CPUSPARCState *env = cs->env_ptr;
72cbca10 5739 target_ulong pc_start, last_pc;
cf495bcf 5740 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5741 int num_insns;
5742 int max_insns;
0184e266 5743 unsigned int insn;
cf495bcf
FB		 5744
5745 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5746 dc->tb = tb;
72cbca10 5747 pc_start = tb->pc;
cf495bcf 5748 dc->pc = pc_start;
e80cfcfc 5749 last_pc = dc->pc;
72cbca10 5750 dc->npc = (target_ulong) tb->cs_base;
8393617c 5751 dc->cc_op = CC_OP_DYNAMIC;
99a23063 5752 dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
576e1c4c 5753 dc->def = &env->def;
f838e2c5
BS		 5754 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5755 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5756 dc->singlestep = (cs->singlestep_enabled || singlestep);
c9b459aa
AT		 5757#ifndef CONFIG_USER_ONLY
5758 dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
5759#endif
a6d567e5 5760#ifdef TARGET_SPARC64
f9c816c0 5761 dc->fprs_dirty = 0;
a6d567e5 5762 dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
c9b459aa
AT		 5763#ifndef CONFIG_USER_ONLY
5764 dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
5765#endif
a6d567e5 5766#endif
cf495bcf 5767
2e70f6ef 5768 num_insns = 0;
c5a49c63 5769 max_insns = tb_cflags(tb) & CF_COUNT_MASK;
190ce7fb 5770 if (max_insns == 0) {
2e70f6ef 5771 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5772 }
5773 if (max_insns > TCG_MAX_INSNS) {
5774 max_insns = TCG_MAX_INSNS;
5775 }
5776
cd42d5b2 5777 gen_tb_start(tb);
cf495bcf 5778 do {
a3d5ad76
RH		 5779 if (dc->npc & JUMP_PC) {
5780 assert(dc->jump_pc[1] == dc->pc + 4);
5781 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5782 } else {
5783 tcg_gen_insn_start(dc->pc, dc->npc);
5784 }
959082fc 5785 num_insns++;
522a0d4e 5786 last_pc = dc->pc;
667b8e29 5787
b933066a
RH		 5788 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5789 if (dc->pc != pc_start) {
5790 save_state(dc);
5791 }
5792 gen_helper_debug(cpu_env);
5793 tcg_gen_exit_tb(0);
5794 dc->is_br = 1;
5795 goto exit_gen_loop;
5796 }
5797
c5a49c63 5798 if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
2e70f6ef 5799 gen_io_start();
667b8e29
RH		 5800 }
5801
0184e266 5802 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5803
0184e266 5804 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5805
5806 if (dc->is_br)
5807 break;
5808 /* if the next PC is different, we abort now */
5809 if (dc->pc != (last_pc + 4))
5810 break;
d39c0b99
FB		 5811 /* if we reach a page boundary, we stop generation so that the
5812 PC of a TT_TFAULT exception is always in the right page */
5813 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5814 break;
e80cfcfc
FB		 5815 /* if single step mode, we generate only one instruction and
5816 generate an exception */
060718c1 5817 if (dc->singlestep) {
e80cfcfc
FB		 5818 break;
5819 }
fe700adb 5820 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5821 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5822 num_insns < max_insns);
e80cfcfc
FB		 5823
5824 exit_gen_loop:
c5a49c63 5825 if (tb_cflags(tb) & CF_LAST_IO) {
2e70f6ef 5826 gen_io_end();
b09b2fd3 5827 }
72cbca10 5828 if (!dc->is_br) {
5fafdf24 5829 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5830 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5831 /* static PC and NPC: we can use direct chaining */
2f5680ee 5832 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5833 } else {
b09b2fd3 5834 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5835 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5836 }
934da7ee 5837 save_npc(dc);
57fec1fe 5838 tcg_gen_exit_tb(0);
72cbca10
FB		 5839 }
5840 }
806f352d 5841 gen_tb_end(tb, num_insns);
0a7df5da 5842
4e5e1215
RH		 5843 tb->size = last_pc + 4 - pc_start;
5844 tb->icount = num_insns;
5845
7a3f1944 5846#ifdef DEBUG_DISAS
4910e6e4
RH		 5847 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5848 && qemu_log_in_addr_range(pc_start)) {
1ee73216 5849 qemu_log_lock();
93fcfe39
AL		 5850 qemu_log("--------------\n");
5851 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5852 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5853 qemu_log("\n");
1ee73216 5854 qemu_log_unlock();
cf495bcf 5855 }
7a3f1944 5856#endif
7a3f1944
FB		 5857}
5858
55c3ceef 5859void sparc_tcg_init(void)
e80cfcfc 5860{
d2dc4069 5861 static const char gregnames[32][4] = {
0ea63844 5862 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5863 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5864 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5865 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5866 };
0ea63844 5867 static const char fregnames[32][4] = {
30038fd8
RH		 5868 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5869 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5870 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5871 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5872 };
aaed909a 5873
0ea63844 5874 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5875#ifdef TARGET_SPARC64
0ea63844 5876 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5877 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
255e1fcb 5878#else
0ea63844
RH		 5879 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5880#endif
5881 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5882 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5883 };
5884
5885 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5886#ifdef TARGET_SPARC64
5887 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5888 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5889 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5890 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5891 "hstick_cmpr" },
5892 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5893 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5894 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5895 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5896 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5897#endif
0ea63844
RH		 5898 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5899 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5900 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5901 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5902 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5903 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5904 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5905 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 5906#ifndef CONFIG_USER_ONLY
0ea63844 5907 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 5908#endif
0ea63844
RH		 5909 };
5910
5911 unsigned int i;
5912
0ea63844
RH		 5913 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5914 offsetof(CPUSPARCState, regwptr),
5915 "regwptr");
5916
5917 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5918 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5919 }
5920
5921 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5922 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5923 }
5924
d2dc4069 5925 TCGV_UNUSED(cpu_regs[0]);
0ea63844 5926 for (i = 1; i < 8; ++i) {
d2dc4069
RH		 5927 cpu_regs[i] = tcg_global_mem_new(cpu_env,
5928 offsetof(CPUSPARCState, gregs[i]),
5929 gregnames[i]);
5930 }
5931
5932 for (i = 8; i < 32; ++i) {
5933 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5934 (i - 8) * sizeof(target_ulong),
5935 gregnames[i]);
0ea63844
RH		 5936 }
5937
5938 for (i = 0; i < TARGET_DPREGS; i++) {
5939 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5940 offsetof(CPUSPARCState, fpr[i]),
5941 fregnames[i]);
1a2fb1c0 5942 }
658138bc 5943}
d2856f1a 5944
bad729e2
RH		 5945void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5946 target_ulong *data)
d2856f1a 5947{
bad729e2
RH		 5948 target_ulong pc = data[0];
5949 target_ulong npc = data[1];
5950
5951 env->pc = pc;
6c42444f 5952 if (npc == DYNAMIC_PC) {
d2856f1a 5953 /* dynamic NPC: already stored */
6c42444f 5954 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5955 /* jump PC: use 'cond' and the jump targets of the translation */
5956 if (env->cond) {
6c42444f 5957 env->npc = npc & ~3;
d7da2a10 5958 } else {
6c42444f 5959 env->npc = pc + 4;
d7da2a10 5960 }
d2856f1a
AJ		 5961 } else {
5962 env->npc = npc;
5963 }
5964}
Empty description
This page took 2.140599 seconds and 4 git commands to generate.