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target-sparc: Introduce get_asi
[qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <[email protected]>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
57fec1fe 27#include "tcg-op.h"
f08b6170 28#include "exec/cpu_ldst.h"
7a3f1944 29
2ef6175a 30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
a7e30d84
LV		 34
35
7a3f1944
FB		 36#define DEBUG_DISAS
37
72cbca10
FB		 38#define DYNAMIC_PC 1 /* dynamic pc value */
39#define JUMP_PC 2 /* dynamic pc value which takes only two values
40 according to jump_pc[T2] */
41
1a2fb1c0 42/* global register indexes */
1bcea73e
LV		 43static TCGv_env cpu_env;
44static TCGv_ptr cpu_regwptr;
25517f99
PB		 45static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
46static TCGv_i32 cpu_cc_op;
a7812ae4 47static TCGv_i32 cpu_psr;
d2dc4069
RH		 48static TCGv cpu_fsr, cpu_pc, cpu_npc;
49static TCGv cpu_regs[32];
255e1fcb
BS		 50static TCGv cpu_y;
51#ifndef CONFIG_USER_ONLY
52static TCGv cpu_tbr;
53#endif
5793f2a4 54static TCGv cpu_cond;
dc99a3f2 55#ifdef TARGET_SPARC64
a6d567e5 56static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 57static TCGv cpu_gsr;
255e1fcb 58static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4 59static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
255e1fcb
BS		 60#else
61static TCGv cpu_wim;
dc99a3f2 62#endif
714547bb 63/* Floating point registers */
30038fd8 64static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 65
022c62cb 66#include "exec/gen-icount.h"
2e70f6ef 67
7a3f1944 68typedef struct DisasContext {
0f8a249a
BS		 69 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
70 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 71 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 72 int is_br;
e8af50a3 73 int mem_idx;
a80dde08 74 int fpu_enabled;
2cade6a3 75 int address_mask_32bit;
060718c1 76 int singlestep;
8393617c 77 uint32_t cc_op; /* current CC operation */
cf495bcf 78 struct TranslationBlock *tb;
5578ceab 79 sparc_def_t *def;
30038fd8 80 TCGv_i32 t32[3];
88023616 81 TCGv ttl[5];
30038fd8 82 int n_t32;
88023616 83 int n_ttl;
a6d567e5
RH		 84#ifdef TARGET_SPARC64
85 int asi;
86#endif
7a3f1944
FB		 87} DisasContext;
88
416fcaea
RH		 89typedef struct {
90 TCGCond cond;
91 bool is_bool;
92 bool g1, g2;
93 TCGv c1, c2;
94} DisasCompare;
95
3475187d 96// This function uses non-native bit order
dc1a6971
BS		 97#define GET_FIELD(X, FROM, TO) \
98 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 99
3475187d 100// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 101#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 102 GET_FIELD(X, 31 - (TO), 31 - (FROM))
103
104#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 105#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 106
107#ifdef TARGET_SPARC64
0387d928 108#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 109#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 110#else
c185970a 111#define DFPREG(r) (r & 0x1e)
1f587329 112#define QFPREG(r) (r & 0x1c)
3475187d
FB		 113#endif
114
b158a785
BS		 115#define UA2005_HTRAP_MASK 0xff
116#define V8_TRAP_MASK 0x7f
117
3475187d
FB		 118static int sign_extend(int x, int len)
119{
120 len = 32 - len;
121 return (x << len) >> len;
122}
123
7a3f1944
FB		 124#define IS_IMM (insn & (1<<13))
125
2ae23e17
RH		 126static inline TCGv_i32 get_temp_i32(DisasContext *dc)
127{
128 TCGv_i32 t;
129 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
130 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
131 return t;
132}
133
134static inline TCGv get_temp_tl(DisasContext *dc)
135{
136 TCGv t;
137 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
138 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
139 return t;
140}
141
141ae5c1
RH		 142static inline void gen_update_fprs_dirty(int rd)
143{
144#if defined(TARGET_SPARC64)
145 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
146#endif
147}
148
ff07ec83 149/* floating point registers moves */
208ae657
RH		 150static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
151{
30038fd8
RH		 152#if TCG_TARGET_REG_BITS == 32
153 if (src & 1) {
154 return TCGV_LOW(cpu_fpr[src / 2]);
155 } else {
156 return TCGV_HIGH(cpu_fpr[src / 2]);
157 }
158#else
159 if (src & 1) {
160 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
161 } else {
2ae23e17 162 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 163 TCGv_i64 t = tcg_temp_new_i64();
164
165 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 166 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 167 tcg_temp_free_i64(t);
168
30038fd8
RH		 169 return ret;
170 }
171#endif
208ae657
RH		 172}
173
174static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
175{
30038fd8
RH		 176#if TCG_TARGET_REG_BITS == 32
177 if (dst & 1) {
178 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
179 } else {
180 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
181 }
182#else
183 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
184 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
185 (dst & 1 ? 0 : 32), 32);
186#endif
141ae5c1 187 gen_update_fprs_dirty(dst);
208ae657
RH		 188}
189
ba5f5179 190static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 191{
ba5f5179 192 return get_temp_i32(dc);
208ae657
RH		 193}
194
96eda024
RH		 195static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
196{
96eda024 197 src = DFPREG(src);
30038fd8 198 return cpu_fpr[src / 2];
96eda024
RH		 199}
200
201static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
202{
203 dst = DFPREG(dst);
30038fd8 204 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 205 gen_update_fprs_dirty(dst);
206}
207
3886b8a3 208static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 209{
3886b8a3 210 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 211}
212
ff07ec83
BS		 213static void gen_op_load_fpr_QT0(unsigned int src)
214{
30038fd8
RH		 215 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
216 offsetof(CPU_QuadU, ll.upper));
217 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
218 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 219}
220
221static void gen_op_load_fpr_QT1(unsigned int src)
222{
30038fd8
RH		 223 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
224 offsetof(CPU_QuadU, ll.upper));
225 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
226 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 227}
228
229static void gen_op_store_QT0_fpr(unsigned int dst)
230{
30038fd8
RH		 231 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
232 offsetof(CPU_QuadU, ll.upper));
233 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
234 offsetof(CPU_QuadU, ll.lower));
ff07ec83 235}
1f587329 236
ac11f776 237#ifdef TARGET_SPARC64
30038fd8 238static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 239{
240 rd = QFPREG(rd);
241 rs = QFPREG(rs);
242
30038fd8
RH		 243 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
244 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 245 gen_update_fprs_dirty(rd);
246}
247#endif
248
81ad8ba2
BS		 249/* moves */
250#ifdef CONFIG_USER_ONLY
3475187d 251#define supervisor(dc) 0
81ad8ba2 252#ifdef TARGET_SPARC64
e9ebed4d 253#define hypervisor(dc) 0
81ad8ba2 254#endif
3475187d 255#else
2aae2b8e 256#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 257#ifdef TARGET_SPARC64
2aae2b8e 258#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 259#else
3475187d 260#endif
81ad8ba2
BS		 261#endif
262
2cade6a3
BS		 263#ifdef TARGET_SPARC64
264#ifndef TARGET_ABI32
265#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 266#else
2cade6a3
BS		 267#define AM_CHECK(dc) (1)
268#endif
1a2fb1c0 269#endif
3391c818 270
2cade6a3
BS		 271static inline void gen_address_mask(DisasContext *dc, TCGv addr)
272{
273#ifdef TARGET_SPARC64
274 if (AM_CHECK(dc))
275 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
276#endif
277}
278
88023616
RH		 279static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
280{
d2dc4069
RH		 281 if (reg > 0) {
282 assert(reg < 32);
283 return cpu_regs[reg];
284 } else {
88023616 285 TCGv t = get_temp_tl(dc);
d2dc4069 286 tcg_gen_movi_tl(t, 0);
88023616 287 return t;
88023616
RH		 288 }
289}
290
291static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
292{
293 if (reg > 0) {
d2dc4069
RH		 294 assert(reg < 32);
295 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 296 }
297}
298
299static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
300{
d2dc4069
RH		 301 if (reg > 0) {
302 assert(reg < 32);
303 return cpu_regs[reg];
88023616 304 } else {
d2dc4069 305 return get_temp_tl(dc);
88023616
RH		 306 }
307}
308
90aa39a1
SF		 309static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
310 target_ulong npc)
311{
312 if (unlikely(s->singlestep)) {
313 return false;
314 }
315
316#ifndef CONFIG_USER_ONLY
317 return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
318 (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
319#else
320 return true;
321#endif
322}
323
5fafdf24 324static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 325 target_ulong pc, target_ulong npc)
326{
90aa39a1 327 if (use_goto_tb(s, pc, npc)) {
6e256c93 328 /* jump to same page: we can use a direct jump */
57fec1fe 329 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 330 tcg_gen_movi_tl(cpu_pc, pc);
331 tcg_gen_movi_tl(cpu_npc, npc);
90aa39a1 332 tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
6e256c93
FB		 333 } else {
334 /* jump to another page: currently not optimized */
2f5680ee
BS		 335 tcg_gen_movi_tl(cpu_pc, pc);
336 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 337 tcg_gen_exit_tb(0);
6e256c93
FB		 338 }
339}
340
19f329ad 341// XXX suboptimal
a7812ae4 342static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 343{
8911f501 344 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 345 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 346 tcg_gen_andi_tl(reg, reg, 0x1);
347}
348
a7812ae4 349static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 350{
8911f501 351 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 352 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 353 tcg_gen_andi_tl(reg, reg, 0x1);
354}
355
a7812ae4 356static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 357{
8911f501 358 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 359 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 360 tcg_gen_andi_tl(reg, reg, 0x1);
361}
362
a7812ae4 363static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 364{
8911f501 365 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 366 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 367 tcg_gen_andi_tl(reg, reg, 0x1);
368}
369
4af984a7 370static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 371{
4af984a7 372 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 373 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 374 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 375 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 376}
377
70c48285 378static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 379{
70c48285
RH		 380 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
381
382 /* Carry is computed from a previous add: (dst < src) */
383#if TARGET_LONG_BITS == 64
384 cc_src1_32 = tcg_temp_new_i32();
385 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 386 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
387 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 388#else
389 cc_src1_32 = cpu_cc_dst;
390 cc_src2_32 = cpu_cc_src;
391#endif
392
393 carry_32 = tcg_temp_new_i32();
394 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
395
396#if TARGET_LONG_BITS == 64
397 tcg_temp_free_i32(cc_src1_32);
398 tcg_temp_free_i32(cc_src2_32);
399#endif
400
401 return carry_32;
41d72852
BS		 402}
403
70c48285 404static TCGv_i32 gen_sub32_carry32(void)
41d72852 405{
70c48285
RH		 406 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
407
408 /* Carry is computed from a previous borrow: (src1 < src2) */
409#if TARGET_LONG_BITS == 64
410 cc_src1_32 = tcg_temp_new_i32();
411 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 412 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
413 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 414#else
415 cc_src1_32 = cpu_cc_src;
416 cc_src2_32 = cpu_cc_src2;
417#endif
418
419 carry_32 = tcg_temp_new_i32();
420 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
421
422#if TARGET_LONG_BITS == 64
423 tcg_temp_free_i32(cc_src1_32);
424 tcg_temp_free_i32(cc_src2_32);
425#endif
426
427 return carry_32;
428}
429
430static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
431 TCGv src2, int update_cc)
432{
433 TCGv_i32 carry_32;
434 TCGv carry;
435
436 switch (dc->cc_op) {
437 case CC_OP_DIV:
438 case CC_OP_LOGIC:
439 /* Carry is known to be zero. Fall back to plain ADD. */
440 if (update_cc) {
441 gen_op_add_cc(dst, src1, src2);
442 } else {
443 tcg_gen_add_tl(dst, src1, src2);
444 }
445 return;
446
447 case CC_OP_ADD:
448 case CC_OP_TADD:
449 case CC_OP_TADDTV:
15fe216f
RH		 450 if (TARGET_LONG_BITS == 32) {
451 /* We can re-use the host's hardware carry generation by using
452 an ADD2 opcode. We discard the low part of the output.
453 Ideally we'd combine this operation with the add that
454 generated the carry in the first place. */
455 carry = tcg_temp_new();
456 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
457 tcg_temp_free(carry);
70c48285
RH		 458 goto add_done;
459 }
70c48285
RH		 460 carry_32 = gen_add32_carry32();
461 break;
462
463 case CC_OP_SUB:
464 case CC_OP_TSUB:
465 case CC_OP_TSUBTV:
466 carry_32 = gen_sub32_carry32();
467 break;
468
469 default:
470 /* We need external help to produce the carry. */
471 carry_32 = tcg_temp_new_i32();
2ffd9176 472 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 473 break;
474 }
475
476#if TARGET_LONG_BITS == 64
477 carry = tcg_temp_new();
478 tcg_gen_extu_i32_i64(carry, carry_32);
479#else
480 carry = carry_32;
481#endif
482
483 tcg_gen_add_tl(dst, src1, src2);
484 tcg_gen_add_tl(dst, dst, carry);
485
486 tcg_temp_free_i32(carry_32);
487#if TARGET_LONG_BITS == 64
488 tcg_temp_free(carry);
489#endif
490
70c48285 491 add_done:
70c48285
RH		 492 if (update_cc) {
493 tcg_gen_mov_tl(cpu_cc_src, src1);
494 tcg_gen_mov_tl(cpu_cc_src2, src2);
495 tcg_gen_mov_tl(cpu_cc_dst, dst);
496 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
497 dc->cc_op = CC_OP_ADDX;
498 }
dc99a3f2
BS		 499}
500
41d72852 501static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 502{
4af984a7 503 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 504 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 505 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 506 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 507}
508
70c48285
RH		 509static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
510 TCGv src2, int update_cc)
41d72852 511{
70c48285
RH		 512 TCGv_i32 carry_32;
513 TCGv carry;
41d72852 514
70c48285
RH		 515 switch (dc->cc_op) {
516 case CC_OP_DIV:
517 case CC_OP_LOGIC:
518 /* Carry is known to be zero. Fall back to plain SUB. */
519 if (update_cc) {
520 gen_op_sub_cc(dst, src1, src2);
521 } else {
522 tcg_gen_sub_tl(dst, src1, src2);
523 }
524 return;
525
526 case CC_OP_ADD:
527 case CC_OP_TADD:
528 case CC_OP_TADDTV:
529 carry_32 = gen_add32_carry32();
530 break;
531
532 case CC_OP_SUB:
533 case CC_OP_TSUB:
534 case CC_OP_TSUBTV:
15fe216f
RH		 535 if (TARGET_LONG_BITS == 32) {
536 /* We can re-use the host's hardware carry generation by using
537 a SUB2 opcode. We discard the low part of the output.
538 Ideally we'd combine this operation with the add that
539 generated the carry in the first place. */
540 carry = tcg_temp_new();
541 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
542 tcg_temp_free(carry);
70c48285
RH		 543 goto sub_done;
544 }
70c48285
RH		 545 carry_32 = gen_sub32_carry32();
546 break;
547
548 default:
549 /* We need external help to produce the carry. */
550 carry_32 = tcg_temp_new_i32();
2ffd9176 551 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 552 break;
553 }
554
555#if TARGET_LONG_BITS == 64
556 carry = tcg_temp_new();
557 tcg_gen_extu_i32_i64(carry, carry_32);
558#else
559 carry = carry_32;
560#endif
561
562 tcg_gen_sub_tl(dst, src1, src2);
563 tcg_gen_sub_tl(dst, dst, carry);
564
565 tcg_temp_free_i32(carry_32);
566#if TARGET_LONG_BITS == 64
567 tcg_temp_free(carry);
568#endif
569
70c48285 570 sub_done:
70c48285
RH		 571 if (update_cc) {
572 tcg_gen_mov_tl(cpu_cc_src, src1);
573 tcg_gen_mov_tl(cpu_cc_src2, src2);
574 tcg_gen_mov_tl(cpu_cc_dst, dst);
575 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
576 dc->cc_op = CC_OP_SUBX;
577 }
dc99a3f2
BS		 578}
579
4af984a7 580static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 581{
de9e9d9f 582 TCGv r_temp, zero, t0;
d9bdab86 583
a7812ae4 584 r_temp = tcg_temp_new();
de9e9d9f 585 t0 = tcg_temp_new();
d9bdab86
BS		 586
587 /* old op:
588 if (!(env->y & 1))
589 T1 = 0;
590 */
6cb675b0 591 zero = tcg_const_tl(0);
72ccba79 592 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 593 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 594 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 595 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
596 zero, cpu_cc_src2);
597 tcg_temp_free(zero);
d9bdab86
BS		 598
599 // b2 = T0 & 1;
600 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 601 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
602 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 603 tcg_gen_shri_tl(t0, cpu_y, 1);
604 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
605 tcg_gen_or_tl(t0, t0, r_temp);
606 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 607
608 // b1 = N ^ V;
de9e9d9f 609 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 610 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 611 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 612 tcg_temp_free(r_temp);
d9bdab86
BS		 613
614 // T0 = (b1 << 31) | (T0 >> 1);
615 // src1 = T0;
de9e9d9f 616 tcg_gen_shli_tl(t0, t0, 31);
6f551262 617 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 618 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
619 tcg_temp_free(t0);
d9bdab86 620
5c6a0628 621 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 622
5c6a0628 623 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 624}
625
fb170183 626static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 627{
528692a8 628#if TARGET_LONG_BITS == 32
fb170183 629 if (sign_ext) {
528692a8 630 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 631 } else {
528692a8 632 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 633 }
528692a8
RH		 634#else
635 TCGv t0 = tcg_temp_new_i64();
636 TCGv t1 = tcg_temp_new_i64();
fb170183 637
528692a8
RH		 638 if (sign_ext) {
639 tcg_gen_ext32s_i64(t0, src1);
640 tcg_gen_ext32s_i64(t1, src2);
641 } else {
642 tcg_gen_ext32u_i64(t0, src1);
643 tcg_gen_ext32u_i64(t1, src2);
644 }
fb170183 645
528692a8
RH		 646 tcg_gen_mul_i64(dst, t0, t1);
647 tcg_temp_free(t0);
648 tcg_temp_free(t1);
fb170183 649
528692a8
RH		 650 tcg_gen_shri_i64(cpu_y, dst, 32);
651#endif
8879d139
BS		 652}
653
fb170183 654static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 655{
fb170183
IK		 656 /* zero-extend truncated operands before multiplication */
657 gen_op_multiply(dst, src1, src2, 0);
658}
8879d139 659
fb170183
IK		 660static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
661{
662 /* sign-extend truncated operands before multiplication */
663 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 664}
665
19f329ad
BS		 666// 1
667static inline void gen_op_eval_ba(TCGv dst)
668{
669 tcg_gen_movi_tl(dst, 1);
670}
671
672// Z
a7812ae4 673static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 674{
675 gen_mov_reg_Z(dst, src);
676}
677
678// Z | (N ^ V)
a7812ae4 679static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 680{
de9e9d9f
RH		 681 TCGv t0 = tcg_temp_new();
682 gen_mov_reg_N(t0, src);
19f329ad 683 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 684 tcg_gen_xor_tl(dst, dst, t0);
685 gen_mov_reg_Z(t0, src);
686 tcg_gen_or_tl(dst, dst, t0);
687 tcg_temp_free(t0);
19f329ad
BS		 688}
689
690// N ^ V
a7812ae4 691static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 692{
de9e9d9f
RH		 693 TCGv t0 = tcg_temp_new();
694 gen_mov_reg_V(t0, src);
19f329ad 695 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 696 tcg_gen_xor_tl(dst, dst, t0);
697 tcg_temp_free(t0);
19f329ad
BS		 698}
699
700// C | Z
a7812ae4 701static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 702{
de9e9d9f
RH		 703 TCGv t0 = tcg_temp_new();
704 gen_mov_reg_Z(t0, src);
19f329ad 705 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 706 tcg_gen_or_tl(dst, dst, t0);
707 tcg_temp_free(t0);
19f329ad
BS		 708}
709
710// C
a7812ae4 711static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 712{
713 gen_mov_reg_C(dst, src);
714}
715
716// V
a7812ae4 717static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 718{
719 gen_mov_reg_V(dst, src);
720}
721
722// 0
723static inline void gen_op_eval_bn(TCGv dst)
724{
725 tcg_gen_movi_tl(dst, 0);
726}
727
728// N
a7812ae4 729static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 730{
731 gen_mov_reg_N(dst, src);
732}
733
734// !Z
a7812ae4 735static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 736{
737 gen_mov_reg_Z(dst, src);
738 tcg_gen_xori_tl(dst, dst, 0x1);
739}
740
741// !(Z | (N ^ V))
a7812ae4 742static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 743{
de9e9d9f 744 gen_op_eval_ble(dst, src);
19f329ad
BS		 745 tcg_gen_xori_tl(dst, dst, 0x1);
746}
747
748// !(N ^ V)
a7812ae4 749static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 750{
de9e9d9f 751 gen_op_eval_bl(dst, src);
19f329ad
BS		 752 tcg_gen_xori_tl(dst, dst, 0x1);
753}
754
755// !(C | Z)
a7812ae4 756static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 757{
de9e9d9f 758 gen_op_eval_bleu(dst, src);
19f329ad
BS		 759 tcg_gen_xori_tl(dst, dst, 0x1);
760}
761
762// !C
a7812ae4 763static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 764{
765 gen_mov_reg_C(dst, src);
766 tcg_gen_xori_tl(dst, dst, 0x1);
767}
768
769// !N
a7812ae4 770static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 771{
772 gen_mov_reg_N(dst, src);
773 tcg_gen_xori_tl(dst, dst, 0x1);
774}
775
776// !V
a7812ae4 777static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 778{
779 gen_mov_reg_V(dst, src);
780 tcg_gen_xori_tl(dst, dst, 0x1);
781}
782
783/*
784 FPSR bit field FCC1 | FCC0:
785 0 =
786 1 <
787 2 >
788 3 unordered
789*/
790static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
791 unsigned int fcc_offset)
792{
ba6a9d8c 793 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 794 tcg_gen_andi_tl(reg, reg, 0x1);
795}
796
797static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
798 unsigned int fcc_offset)
799{
ba6a9d8c 800 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 801 tcg_gen_andi_tl(reg, reg, 0x1);
802}
803
804// !0: FCC0 | FCC1
805static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
806 unsigned int fcc_offset)
807{
de9e9d9f 808 TCGv t0 = tcg_temp_new();
19f329ad 809 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 810 gen_mov_reg_FCC1(t0, src, fcc_offset);
811 tcg_gen_or_tl(dst, dst, t0);
812 tcg_temp_free(t0);
19f329ad
BS		 813}
814
815// 1 or 2: FCC0 ^ FCC1
816static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
817 unsigned int fcc_offset)
818{
de9e9d9f 819 TCGv t0 = tcg_temp_new();
19f329ad 820 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 821 gen_mov_reg_FCC1(t0, src, fcc_offset);
822 tcg_gen_xor_tl(dst, dst, t0);
823 tcg_temp_free(t0);
19f329ad
BS		 824}
825
826// 1 or 3: FCC0
827static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
828 unsigned int fcc_offset)
829{
830 gen_mov_reg_FCC0(dst, src, fcc_offset);
831}
832
833// 1: FCC0 & !FCC1
834static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
835 unsigned int fcc_offset)
836{
de9e9d9f 837 TCGv t0 = tcg_temp_new();
19f329ad 838 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 839 gen_mov_reg_FCC1(t0, src, fcc_offset);
840 tcg_gen_andc_tl(dst, dst, t0);
841 tcg_temp_free(t0);
19f329ad
BS		 842}
843
844// 2 or 3: FCC1
845static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
846 unsigned int fcc_offset)
847{
848 gen_mov_reg_FCC1(dst, src, fcc_offset);
849}
850
851// 2: !FCC0 & FCC1
852static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
853 unsigned int fcc_offset)
854{
de9e9d9f 855 TCGv t0 = tcg_temp_new();
19f329ad 856 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 857 gen_mov_reg_FCC1(t0, src, fcc_offset);
858 tcg_gen_andc_tl(dst, t0, dst);
859 tcg_temp_free(t0);
19f329ad
BS		 860}
861
862// 3: FCC0 & FCC1
863static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
864 unsigned int fcc_offset)
865{
de9e9d9f 866 TCGv t0 = tcg_temp_new();
19f329ad 867 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 868 gen_mov_reg_FCC1(t0, src, fcc_offset);
869 tcg_gen_and_tl(dst, dst, t0);
870 tcg_temp_free(t0);
19f329ad
BS		 871}
872
873// 0: !(FCC0 | FCC1)
874static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
875 unsigned int fcc_offset)
876{
de9e9d9f 877 TCGv t0 = tcg_temp_new();
19f329ad 878 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 879 gen_mov_reg_FCC1(t0, src, fcc_offset);
880 tcg_gen_or_tl(dst, dst, t0);
19f329ad 881 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 882 tcg_temp_free(t0);
19f329ad
BS		 883}
884
885// 0 or 3: !(FCC0 ^ FCC1)
886static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
887 unsigned int fcc_offset)
888{
de9e9d9f 889 TCGv t0 = tcg_temp_new();
19f329ad 890 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 891 gen_mov_reg_FCC1(t0, src, fcc_offset);
892 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 893 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 894 tcg_temp_free(t0);
19f329ad
BS		 895}
896
897// 0 or 2: !FCC0
898static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
899 unsigned int fcc_offset)
900{
901 gen_mov_reg_FCC0(dst, src, fcc_offset);
902 tcg_gen_xori_tl(dst, dst, 0x1);
903}
904
905// !1: !(FCC0 & !FCC1)
906static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
907 unsigned int fcc_offset)
908{
de9e9d9f 909 TCGv t0 = tcg_temp_new();
19f329ad 910 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 911 gen_mov_reg_FCC1(t0, src, fcc_offset);
912 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 913 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 914 tcg_temp_free(t0);
19f329ad
BS		 915}
916
917// 0 or 1: !FCC1
918static inline void gen_op_eval_fble(TCGv dst, TCGv src,
919 unsigned int fcc_offset)
920{
921 gen_mov_reg_FCC1(dst, src, fcc_offset);
922 tcg_gen_xori_tl(dst, dst, 0x1);
923}
924
925// !2: !(!FCC0 & FCC1)
926static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
927 unsigned int fcc_offset)
928{
de9e9d9f 929 TCGv t0 = tcg_temp_new();
19f329ad 930 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 931 gen_mov_reg_FCC1(t0, src, fcc_offset);
932 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 933 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 934 tcg_temp_free(t0);
19f329ad
BS		 935}
936
937// !3: !(FCC0 & FCC1)
938static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
939 unsigned int fcc_offset)
940{
de9e9d9f 941 TCGv t0 = tcg_temp_new();
19f329ad 942 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 943 gen_mov_reg_FCC1(t0, src, fcc_offset);
944 tcg_gen_and_tl(dst, dst, t0);
19f329ad 945 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 946 tcg_temp_free(t0);
19f329ad
BS		 947}
948
46525e1f 949static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 950 target_ulong pc2, TCGv r_cond)
83469015 951{
42a268c2 952 TCGLabel *l1 = gen_new_label();
83469015 953
cb63669a 954 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 955
6e256c93 956 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 957
958 gen_set_label(l1);
6e256c93 959 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 960}
961
bfa31b76 962static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 963{
42a268c2 964 TCGLabel *l1 = gen_new_label();
bfa31b76 965 target_ulong npc = dc->npc;
83469015 966
bfa31b76 967 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 968
bfa31b76 969 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 970
971 gen_set_label(l1);
bfa31b76
RH		 972 gen_goto_tb(dc, 1, npc + 4, npc + 8);
973
974 dc->is_br = 1;
83469015
FB		 975}
976
2bf2e019
RH		 977static void gen_branch_n(DisasContext *dc, target_ulong pc1)
978{
979 target_ulong npc = dc->npc;
980
981 if (likely(npc != DYNAMIC_PC)) {
982 dc->pc = npc;
983 dc->jump_pc[0] = pc1;
984 dc->jump_pc[1] = npc + 4;
985 dc->npc = JUMP_PC;
986 } else {
987 TCGv t, z;
988
989 tcg_gen_mov_tl(cpu_pc, cpu_npc);
990
991 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
992 t = tcg_const_tl(pc1);
993 z = tcg_const_tl(0);
994 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
995 tcg_temp_free(t);
996 tcg_temp_free(z);
997
998 dc->pc = DYNAMIC_PC;
999 }
1000}
1001
2e655fe7 1002static inline void gen_generic_branch(DisasContext *dc)
83469015 1003{
61316742
RH		 1004 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1005 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1006 TCGv zero = tcg_const_tl(0);
19f329ad 1007
61316742 1008 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1009
61316742
RH		 1010 tcg_temp_free(npc0);
1011 tcg_temp_free(npc1);
1012 tcg_temp_free(zero);
83469015
FB		 1013}
1014
4af984a7
BS		 1015/* call this function before using the condition register as it may
1016 have been set for a jump */
dee8913c 1017static inline void flush_cond(DisasContext *dc)
83469015
FB		 1018{
1019 if (dc->npc == JUMP_PC) {
2e655fe7 1020 gen_generic_branch(dc);
83469015
FB		 1021 dc->npc = DYNAMIC_PC;
1022 }
1023}
1024
934da7ee 1025static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1026{
1027 if (dc->npc == JUMP_PC) {
2e655fe7 1028 gen_generic_branch(dc);
72cbca10
FB		 1029 dc->npc = DYNAMIC_PC;
1030 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1031 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1032 }
1033}
1034
20132b96 1035static inline void update_psr(DisasContext *dc)
72cbca10 1036{
cfa90513
BS		 1037 if (dc->cc_op != CC_OP_FLAGS) {
1038 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1039 gen_helper_compute_psr(cpu_env);
cfa90513 1040 }
20132b96
RH		 1041}
1042
1043static inline void save_state(DisasContext *dc)
1044{
1045 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1046 save_npc(dc);
72cbca10
FB		 1047}
1048
4fbe0067
RH		 1049static void gen_exception(DisasContext *dc, int which)
1050{
1051 TCGv_i32 t;
1052
1053 save_state(dc);
1054 t = tcg_const_i32(which);
1055 gen_helper_raise_exception(cpu_env, t);
1056 tcg_temp_free_i32(t);
1057 dc->is_br = 1;
1058}
1059
13a6dd00 1060static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1061{
1062 if (dc->npc == JUMP_PC) {
2e655fe7 1063 gen_generic_branch(dc);
48d5c82b 1064 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1065 dc->pc = DYNAMIC_PC;
1066 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1067 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1068 dc->pc = DYNAMIC_PC;
1069 } else {
1070 dc->pc = dc->npc;
1071 }
1072}
1073
38bc628b
BS		 1074static inline void gen_op_next_insn(void)
1075{
48d5c82b
BS		 1076 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1077 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1078}
1079
416fcaea
RH		 1080static void free_compare(DisasCompare *cmp)
1081{
1082 if (!cmp->g1) {
1083 tcg_temp_free(cmp->c1);
1084 }
1085 if (!cmp->g2) {
1086 tcg_temp_free(cmp->c2);
1087 }
1088}
1089
2a484ecf 1090static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1091 DisasContext *dc)
19f329ad 1092{
2a484ecf 1093 static int subcc_cond[16] = {
96b5a3d3 1094 TCG_COND_NEVER,
2a484ecf
RH		 1095 TCG_COND_EQ,
1096 TCG_COND_LE,
1097 TCG_COND_LT,
1098 TCG_COND_LEU,
1099 TCG_COND_LTU,
1100 -1, /* neg */
1101 -1, /* overflow */
96b5a3d3 1102 TCG_COND_ALWAYS,
2a484ecf
RH		 1103 TCG_COND_NE,
1104 TCG_COND_GT,
1105 TCG_COND_GE,
1106 TCG_COND_GTU,
1107 TCG_COND_GEU,
1108 -1, /* pos */
1109 -1, /* no overflow */
1110 };
1111
96b5a3d3
RH		 1112 static int logic_cond[16] = {
1113 TCG_COND_NEVER,
1114 TCG_COND_EQ, /* eq: Z */
1115 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1116 TCG_COND_LT, /* lt: N ^ V -> N */
1117 TCG_COND_EQ, /* leu: C | Z -> Z */
1118 TCG_COND_NEVER, /* ltu: C -> 0 */
1119 TCG_COND_LT, /* neg: N */
1120 TCG_COND_NEVER, /* vs: V -> 0 */
1121 TCG_COND_ALWAYS,
1122 TCG_COND_NE, /* ne: !Z */
1123 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1124 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1125 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1126 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1127 TCG_COND_GE, /* pos: !N */
1128 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1129 };
1130
a7812ae4 1131 TCGv_i32 r_src;
416fcaea
RH		 1132 TCGv r_dst;
1133
3475187d 1134#ifdef TARGET_SPARC64
2a484ecf 1135 if (xcc) {
dc99a3f2 1136 r_src = cpu_xcc;
2a484ecf 1137 } else {
dc99a3f2 1138 r_src = cpu_psr;
2a484ecf 1139 }
3475187d 1140#else
dc99a3f2 1141 r_src = cpu_psr;
3475187d 1142#endif
2a484ecf 1143
8393617c 1144 switch (dc->cc_op) {
96b5a3d3
RH		 1145 case CC_OP_LOGIC:
1146 cmp->cond = logic_cond[cond];
1147 do_compare_dst_0:
1148 cmp->is_bool = false;
1149 cmp->g2 = false;
1150 cmp->c2 = tcg_const_tl(0);
1151#ifdef TARGET_SPARC64
1152 if (!xcc) {
1153 cmp->g1 = false;
1154 cmp->c1 = tcg_temp_new();
1155 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1156 break;
1157 }
1158#endif
1159 cmp->g1 = true;
1160 cmp->c1 = cpu_cc_dst;
1161 break;
1162
2a484ecf
RH		 1163 case CC_OP_SUB:
1164 switch (cond) {
1165 case 6: /* neg */
1166 case 14: /* pos */
1167 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1168 goto do_compare_dst_0;
2a484ecf 1169
2a484ecf
RH		 1170 case 7: /* overflow */
1171 case 15: /* !overflow */
1172 goto do_dynamic;
1173
1174 default:
1175 cmp->cond = subcc_cond[cond];
1176 cmp->is_bool = false;
1177#ifdef TARGET_SPARC64
1178 if (!xcc) {
1179 /* Note that sign-extension works for unsigned compares as
1180 long as both operands are sign-extended. */
1181 cmp->g1 = cmp->g2 = false;
1182 cmp->c1 = tcg_temp_new();
1183 cmp->c2 = tcg_temp_new();
1184 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1185 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1186 break;
2a484ecf
RH		 1187 }
1188#endif
1189 cmp->g1 = cmp->g2 = true;
1190 cmp->c1 = cpu_cc_src;
1191 cmp->c2 = cpu_cc_src2;
1192 break;
1193 }
8393617c 1194 break;
2a484ecf 1195
8393617c 1196 default:
2a484ecf 1197 do_dynamic:
2ffd9176 1198 gen_helper_compute_psr(cpu_env);
8393617c 1199 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1200 /* FALLTHRU */
1201
1202 case CC_OP_FLAGS:
1203 /* We're going to generate a boolean result. */
1204 cmp->cond = TCG_COND_NE;
1205 cmp->is_bool = true;
1206 cmp->g1 = cmp->g2 = false;
1207 cmp->c1 = r_dst = tcg_temp_new();
1208 cmp->c2 = tcg_const_tl(0);
1209
1210 switch (cond) {
1211 case 0x0:
1212 gen_op_eval_bn(r_dst);
1213 break;
1214 case 0x1:
1215 gen_op_eval_be(r_dst, r_src);
1216 break;
1217 case 0x2:
1218 gen_op_eval_ble(r_dst, r_src);
1219 break;
1220 case 0x3:
1221 gen_op_eval_bl(r_dst, r_src);
1222 break;
1223 case 0x4:
1224 gen_op_eval_bleu(r_dst, r_src);
1225 break;
1226 case 0x5:
1227 gen_op_eval_bcs(r_dst, r_src);
1228 break;
1229 case 0x6:
1230 gen_op_eval_bneg(r_dst, r_src);
1231 break;
1232 case 0x7:
1233 gen_op_eval_bvs(r_dst, r_src);
1234 break;
1235 case 0x8:
1236 gen_op_eval_ba(r_dst);
1237 break;
1238 case 0x9:
1239 gen_op_eval_bne(r_dst, r_src);
1240 break;
1241 case 0xa:
1242 gen_op_eval_bg(r_dst, r_src);
1243 break;
1244 case 0xb:
1245 gen_op_eval_bge(r_dst, r_src);
1246 break;
1247 case 0xc:
1248 gen_op_eval_bgu(r_dst, r_src);
1249 break;
1250 case 0xd:
1251 gen_op_eval_bcc(r_dst, r_src);
1252 break;
1253 case 0xe:
1254 gen_op_eval_bpos(r_dst, r_src);
1255 break;
1256 case 0xf:
1257 gen_op_eval_bvc(r_dst, r_src);
1258 break;
1259 }
19f329ad
BS		 1260 break;
1261 }
1262}
7a3f1944 1263
416fcaea 1264static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1265{
19f329ad 1266 unsigned int offset;
416fcaea
RH		 1267 TCGv r_dst;
1268
1269 /* For now we still generate a straight boolean result. */
1270 cmp->cond = TCG_COND_NE;
1271 cmp->is_bool = true;
1272 cmp->g1 = cmp->g2 = false;
1273 cmp->c1 = r_dst = tcg_temp_new();
1274 cmp->c2 = tcg_const_tl(0);
19f329ad 1275
19f329ad
BS		 1276 switch (cc) {
1277 default:
1278 case 0x0:
1279 offset = 0;
1280 break;
1281 case 0x1:
1282 offset = 32 - 10;
1283 break;
1284 case 0x2:
1285 offset = 34 - 10;
1286 break;
1287 case 0x3:
1288 offset = 36 - 10;
1289 break;
1290 }
1291
1292 switch (cond) {
1293 case 0x0:
1294 gen_op_eval_bn(r_dst);
1295 break;
1296 case 0x1:
87e92502 1297 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1298 break;
1299 case 0x2:
87e92502 1300 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1301 break;
1302 case 0x3:
87e92502 1303 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1304 break;
1305 case 0x4:
87e92502 1306 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1307 break;
1308 case 0x5:
87e92502 1309 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1310 break;
1311 case 0x6:
87e92502 1312 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1313 break;
1314 case 0x7:
87e92502 1315 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1316 break;
1317 case 0x8:
1318 gen_op_eval_ba(r_dst);
1319 break;
1320 case 0x9:
87e92502 1321 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1322 break;
1323 case 0xa:
87e92502 1324 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1325 break;
1326 case 0xb:
87e92502 1327 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1328 break;
1329 case 0xc:
87e92502 1330 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1331 break;
1332 case 0xd:
87e92502 1333 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1334 break;
1335 case 0xe:
87e92502 1336 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1337 break;
1338 case 0xf:
87e92502 1339 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1340 break;
1341 }
e8af50a3 1342}
00f219bf 1343
416fcaea
RH		 1344static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1345 DisasContext *dc)
1346{
1347 DisasCompare cmp;
1348 gen_compare(&cmp, cc, cond, dc);
1349
1350 /* The interface is to return a boolean in r_dst. */
1351 if (cmp.is_bool) {
1352 tcg_gen_mov_tl(r_dst, cmp.c1);
1353 } else {
1354 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1355 }
1356
1357 free_compare(&cmp);
1358}
1359
1360static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1361{
1362 DisasCompare cmp;
1363 gen_fcompare(&cmp, cc, cond);
1364
1365 /* The interface is to return a boolean in r_dst. */
1366 if (cmp.is_bool) {
1367 tcg_gen_mov_tl(r_dst, cmp.c1);
1368 } else {
1369 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1370 }
1371
1372 free_compare(&cmp);
1373}
1374
19f329ad 1375#ifdef TARGET_SPARC64
00f219bf
BS		 1376// Inverted logic
1377static const int gen_tcg_cond_reg[8] = {
1378 -1,
1379 TCG_COND_NE,
1380 TCG_COND_GT,
1381 TCG_COND_GE,
1382 -1,
1383 TCG_COND_EQ,
1384 TCG_COND_LE,
1385 TCG_COND_LT,
1386};
19f329ad 1387
416fcaea
RH		 1388static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1389{
1390 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1391 cmp->is_bool = false;
1392 cmp->g1 = true;
1393 cmp->g2 = false;
1394 cmp->c1 = r_src;
1395 cmp->c2 = tcg_const_tl(0);
1396}
1397
4af984a7 1398static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1399{
416fcaea
RH		 1400 DisasCompare cmp;
1401 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1402
416fcaea
RH		 1403 /* The interface is to return a boolean in r_dst. */
1404 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1405
1406 free_compare(&cmp);
19f329ad 1407}
3475187d 1408#endif
cf495bcf 1409
d4a288ef 1410static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1411{
cf495bcf 1412 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1413 target_ulong target = dc->pc + offset;
5fafdf24 1414
22036a49
AT		 1415#ifdef TARGET_SPARC64
1416 if (unlikely(AM_CHECK(dc))) {
1417 target &= 0xffffffffULL;
1418 }
1419#endif
cf495bcf 1420 if (cond == 0x0) {
0f8a249a
BS		 1421 /* unconditional not taken */
1422 if (a) {
1423 dc->pc = dc->npc + 4;
1424 dc->npc = dc->pc + 4;
1425 } else {
1426 dc->pc = dc->npc;
1427 dc->npc = dc->pc + 4;
1428 }
cf495bcf 1429 } else if (cond == 0x8) {
0f8a249a
BS		 1430 /* unconditional taken */
1431 if (a) {
1432 dc->pc = target;
1433 dc->npc = dc->pc + 4;
1434 } else {
1435 dc->pc = dc->npc;
1436 dc->npc = target;
c27e2752 1437 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1438 }
cf495bcf 1439 } else {
dee8913c 1440 flush_cond(dc);
d4a288ef 1441 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1442 if (a) {
bfa31b76 1443 gen_branch_a(dc, target);
0f8a249a 1444 } else {
2bf2e019 1445 gen_branch_n(dc, target);
0f8a249a 1446 }
cf495bcf 1447 }
7a3f1944
FB		 1448}
1449
d4a288ef 1450static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1451{
1452 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1453 target_ulong target = dc->pc + offset;
1454
22036a49
AT		 1455#ifdef TARGET_SPARC64
1456 if (unlikely(AM_CHECK(dc))) {
1457 target &= 0xffffffffULL;
1458 }
1459#endif
e8af50a3 1460 if (cond == 0x0) {
0f8a249a
BS		 1461 /* unconditional not taken */
1462 if (a) {
1463 dc->pc = dc->npc + 4;
1464 dc->npc = dc->pc + 4;
1465 } else {
1466 dc->pc = dc->npc;
1467 dc->npc = dc->pc + 4;
1468 }
e8af50a3 1469 } else if (cond == 0x8) {
0f8a249a
BS		 1470 /* unconditional taken */
1471 if (a) {
1472 dc->pc = target;
1473 dc->npc = dc->pc + 4;
1474 } else {
1475 dc->pc = dc->npc;
1476 dc->npc = target;
c27e2752 1477 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1478 }
e8af50a3 1479 } else {
dee8913c 1480 flush_cond(dc);
d4a288ef 1481 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1482 if (a) {
bfa31b76 1483 gen_branch_a(dc, target);
0f8a249a 1484 } else {
2bf2e019 1485 gen_branch_n(dc, target);
0f8a249a 1486 }
e8af50a3
FB		 1487 }
1488}
1489
3475187d 1490#ifdef TARGET_SPARC64
4af984a7 1491static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1492 TCGv r_reg)
7a3f1944 1493{
3475187d
FB		 1494 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1495 target_ulong target = dc->pc + offset;
1496
22036a49
AT		 1497 if (unlikely(AM_CHECK(dc))) {
1498 target &= 0xffffffffULL;
1499 }
dee8913c 1500 flush_cond(dc);
d4a288ef 1501 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1502 if (a) {
bfa31b76 1503 gen_branch_a(dc, target);
3475187d 1504 } else {
2bf2e019 1505 gen_branch_n(dc, target);
3475187d 1506 }
7a3f1944
FB		 1507}
1508
a7812ae4 1509static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1510{
714547bb
BS		 1511 switch (fccno) {
1512 case 0:
2e2f4ade 1513 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1514 break;
1515 case 1:
2e2f4ade 1516 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1517 break;
1518 case 2:
2e2f4ade 1519 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1520 break;
1521 case 3:
2e2f4ade 1522 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1523 break;
1524 }
7e8c2b6c
BS		 1525}
1526
03fb8cfc 1527static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1528{
a7812ae4
PB		 1529 switch (fccno) {
1530 case 0:
03fb8cfc 1531 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1532 break;
1533 case 1:
03fb8cfc 1534 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1535 break;
1536 case 2:
03fb8cfc 1537 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1538 break;
1539 case 3:
03fb8cfc 1540 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1541 break;
1542 }
7e8c2b6c
BS		 1543}
1544
7e8c2b6c
BS		 1545static inline void gen_op_fcmpq(int fccno)
1546{
a7812ae4
PB		 1547 switch (fccno) {
1548 case 0:
2e2f4ade 1549 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1550 break;
1551 case 1:
2e2f4ade 1552 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1553 break;
1554 case 2:
2e2f4ade 1555 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1556 break;
1557 case 3:
2e2f4ade 1558 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1559 break;
1560 }
7e8c2b6c 1561}
7e8c2b6c 1562
a7812ae4 1563static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1564{
714547bb
BS		 1565 switch (fccno) {
1566 case 0:
2e2f4ade 1567 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1568 break;
1569 case 1:
2e2f4ade 1570 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1571 break;
1572 case 2:
2e2f4ade 1573 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1574 break;
1575 case 3:
2e2f4ade 1576 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1577 break;
1578 }
7e8c2b6c
BS		 1579}
1580
03fb8cfc 1581static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1582{
a7812ae4
PB		 1583 switch (fccno) {
1584 case 0:
03fb8cfc 1585 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1586 break;
1587 case 1:
03fb8cfc 1588 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1589 break;
1590 case 2:
03fb8cfc 1591 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1592 break;
1593 case 3:
03fb8cfc 1594 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1595 break;
1596 }
7e8c2b6c
BS		 1597}
1598
7e8c2b6c
BS		 1599static inline void gen_op_fcmpeq(int fccno)
1600{
a7812ae4
PB		 1601 switch (fccno) {
1602 case 0:
2e2f4ade 1603 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1604 break;
1605 case 1:
2e2f4ade 1606 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1607 break;
1608 case 2:
2e2f4ade 1609 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1610 break;
1611 case 3:
2e2f4ade 1612 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1613 break;
1614 }
7e8c2b6c 1615}
7e8c2b6c
BS		 1616
1617#else
1618
714547bb 1619static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1620{
2e2f4ade 1621 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1622}
1623
03fb8cfc 1624static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1625{
03fb8cfc 1626 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1627}
1628
7e8c2b6c
BS		 1629static inline void gen_op_fcmpq(int fccno)
1630{
2e2f4ade 1631 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1632}
7e8c2b6c 1633
714547bb 1634static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1635{
2e2f4ade 1636 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1637}
1638
03fb8cfc 1639static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1640{
03fb8cfc 1641 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1642}
1643
7e8c2b6c
BS		 1644static inline void gen_op_fcmpeq(int fccno)
1645{
2e2f4ade 1646 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1647}
1648#endif
1649
4fbe0067 1650static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1651{
47ad35f1 1652 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1653 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1654 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1655}
1656
5b12f1e8 1657static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1658{
1659#if !defined(CONFIG_USER_ONLY)
1660 if (!dc->fpu_enabled) {
4fbe0067 1661 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1662 return 1;
1663 }
1664#endif
1665 return 0;
1666}
1667
7e8c2b6c
BS		 1668static inline void gen_op_clear_ieee_excp_and_FTT(void)
1669{
47ad35f1 1670 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1671}
1672
61f17f6e
RH		 1673static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1674 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1675{
1676 TCGv_i32 dst, src;
1677
61f17f6e 1678 src = gen_load_fpr_F(dc, rs);
ba5f5179 1679 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1680
1681 gen(dst, cpu_env, src);
1682
61f17f6e
RH		 1683 gen_store_fpr_F(dc, rd, dst);
1684}
1685
1686static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1687 void (*gen)(TCGv_i32, TCGv_i32))
1688{
1689 TCGv_i32 dst, src;
1690
1691 src = gen_load_fpr_F(dc, rs);
ba5f5179 1692 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1693
1694 gen(dst, src);
1695
1696 gen_store_fpr_F(dc, rd, dst);
1697}
1698
1699static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1700 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1701{
1702 TCGv_i32 dst, src1, src2;
1703
61f17f6e
RH		 1704 src1 = gen_load_fpr_F(dc, rs1);
1705 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1706 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1707
1708 gen(dst, cpu_env, src1, src2);
1709
61f17f6e
RH		 1710 gen_store_fpr_F(dc, rd, dst);
1711}
1712
1713#ifdef TARGET_SPARC64
1714static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1715 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1716{
1717 TCGv_i32 dst, src1, src2;
1718
1719 src1 = gen_load_fpr_F(dc, rs1);
1720 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1721 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1722
1723 gen(dst, src1, src2);
1724
1725 gen_store_fpr_F(dc, rd, dst);
1726}
1727#endif
1728
1729static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1730 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1731{
1732 TCGv_i64 dst, src;
1733
61f17f6e 1734 src = gen_load_fpr_D(dc, rs);
3886b8a3 1735 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1736
1737 gen(dst, cpu_env, src);
1738
61f17f6e
RH		 1739 gen_store_fpr_D(dc, rd, dst);
1740}
1741
1742#ifdef TARGET_SPARC64
1743static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1744 void (*gen)(TCGv_i64, TCGv_i64))
1745{
1746 TCGv_i64 dst, src;
1747
1748 src = gen_load_fpr_D(dc, rs);
3886b8a3 1749 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1750
1751 gen(dst, src);
1752
1753 gen_store_fpr_D(dc, rd, dst);
1754}
1755#endif
1756
1757static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1758 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1759{
1760 TCGv_i64 dst, src1, src2;
1761
61f17f6e
RH		 1762 src1 = gen_load_fpr_D(dc, rs1);
1763 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1764 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1765
1766 gen(dst, cpu_env, src1, src2);
1767
61f17f6e
RH		 1768 gen_store_fpr_D(dc, rd, dst);
1769}
1770
1771#ifdef TARGET_SPARC64
1772static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1773 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1774{
1775 TCGv_i64 dst, src1, src2;
1776
1777 src1 = gen_load_fpr_D(dc, rs1);
1778 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1779 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1780
1781 gen(dst, src1, src2);
1782
1783 gen_store_fpr_D(dc, rd, dst);
1784}
f888300b 1785
2dedf314
RH		 1786static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1787 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1788{
1789 TCGv_i64 dst, src1, src2;
1790
1791 src1 = gen_load_fpr_D(dc, rs1);
1792 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1793 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1794
1795 gen(dst, cpu_gsr, src1, src2);
1796
1797 gen_store_fpr_D(dc, rd, dst);
1798}
1799
f888300b
RH		 1800static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1801 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1802{
1803 TCGv_i64 dst, src0, src1, src2;
1804
1805 src1 = gen_load_fpr_D(dc, rs1);
1806 src2 = gen_load_fpr_D(dc, rs2);
1807 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1808 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1809
1810 gen(dst, src0, src1, src2);
1811
1812 gen_store_fpr_D(dc, rd, dst);
1813}
61f17f6e
RH		 1814#endif
1815
1816static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1817 void (*gen)(TCGv_ptr))
1818{
61f17f6e
RH		 1819 gen_op_load_fpr_QT1(QFPREG(rs));
1820
1821 gen(cpu_env);
1822
61f17f6e
RH		 1823 gen_op_store_QT0_fpr(QFPREG(rd));
1824 gen_update_fprs_dirty(QFPREG(rd));
1825}
1826
1827#ifdef TARGET_SPARC64
1828static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1829 void (*gen)(TCGv_ptr))
1830{
1831 gen_op_load_fpr_QT1(QFPREG(rs));
1832
1833 gen(cpu_env);
1834
1835 gen_op_store_QT0_fpr(QFPREG(rd));
1836 gen_update_fprs_dirty(QFPREG(rd));
1837}
1838#endif
1839
1840static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1841 void (*gen)(TCGv_ptr))
1842{
61f17f6e
RH		 1843 gen_op_load_fpr_QT0(QFPREG(rs1));
1844 gen_op_load_fpr_QT1(QFPREG(rs2));
1845
1846 gen(cpu_env);
1847
61f17f6e
RH		 1848 gen_op_store_QT0_fpr(QFPREG(rd));
1849 gen_update_fprs_dirty(QFPREG(rd));
1850}
1851
1852static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1853 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1854{
1855 TCGv_i64 dst;
1856 TCGv_i32 src1, src2;
1857
61f17f6e
RH		 1858 src1 = gen_load_fpr_F(dc, rs1);
1859 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1860 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1861
1862 gen(dst, cpu_env, src1, src2);
1863
61f17f6e
RH		 1864 gen_store_fpr_D(dc, rd, dst);
1865}
1866
1867static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1868 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1869{
1870 TCGv_i64 src1, src2;
1871
61f17f6e
RH		 1872 src1 = gen_load_fpr_D(dc, rs1);
1873 src2 = gen_load_fpr_D(dc, rs2);
1874
1875 gen(cpu_env, src1, src2);
1876
61f17f6e
RH		 1877 gen_op_store_QT0_fpr(QFPREG(rd));
1878 gen_update_fprs_dirty(QFPREG(rd));
1879}
1880
1881#ifdef TARGET_SPARC64
1882static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1883 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1884{
1885 TCGv_i64 dst;
1886 TCGv_i32 src;
1887
61f17f6e 1888 src = gen_load_fpr_F(dc, rs);
3886b8a3 1889 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1890
1891 gen(dst, cpu_env, src);
1892
61f17f6e
RH		 1893 gen_store_fpr_D(dc, rd, dst);
1894}
1895#endif
1896
1897static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1898 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1899{
1900 TCGv_i64 dst;
1901 TCGv_i32 src;
1902
1903 src = gen_load_fpr_F(dc, rs);
3886b8a3 1904 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1905
1906 gen(dst, cpu_env, src);
1907
1908 gen_store_fpr_D(dc, rd, dst);
1909}
1910
1911static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1912 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1913{
1914 TCGv_i32 dst;
1915 TCGv_i64 src;
1916
61f17f6e 1917 src = gen_load_fpr_D(dc, rs);
ba5f5179 1918 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1919
1920 gen(dst, cpu_env, src);
1921
61f17f6e
RH		 1922 gen_store_fpr_F(dc, rd, dst);
1923}
1924
1925static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1926 void (*gen)(TCGv_i32, TCGv_ptr))
1927{
1928 TCGv_i32 dst;
1929
61f17f6e 1930 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1931 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1932
1933 gen(dst, cpu_env);
1934
61f17f6e
RH		 1935 gen_store_fpr_F(dc, rd, dst);
1936}
1937
1938static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1939 void (*gen)(TCGv_i64, TCGv_ptr))
1940{
1941 TCGv_i64 dst;
1942
61f17f6e 1943 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1944 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1945
1946 gen(dst, cpu_env);
1947
61f17f6e
RH		 1948 gen_store_fpr_D(dc, rd, dst);
1949}
1950
1951static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1952 void (*gen)(TCGv_ptr, TCGv_i32))
1953{
1954 TCGv_i32 src;
1955
1956 src = gen_load_fpr_F(dc, rs);
1957
1958 gen(cpu_env, src);
1959
1960 gen_op_store_QT0_fpr(QFPREG(rd));
1961 gen_update_fprs_dirty(QFPREG(rd));
1962}
1963
1964static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1965 void (*gen)(TCGv_ptr, TCGv_i64))
1966{
1967 TCGv_i64 src;
1968
1969 src = gen_load_fpr_D(dc, rs);
1970
1971 gen(cpu_env, src);
1972
1973 gen_op_store_QT0_fpr(QFPREG(rd));
1974 gen_update_fprs_dirty(QFPREG(rd));
1975}
1976
1a2fb1c0 1977/* asi moves */
22e70060 1978#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
7ec1e5ea
RH		 1979typedef enum {
1980 GET_ASI_HELPER,
1981 GET_ASI_EXCP,
1982} ASIType;
1983
1984typedef struct {
1985 ASIType type;
a6d567e5 1986 int asi;
7ec1e5ea 1987} DisasASI;
1a2fb1c0 1988
7ec1e5ea
RH		 1989static DisasASI get_asi(DisasContext *dc, int insn)
1990{
1991 int asi = GET_FIELD(insn, 19, 26);
1992 ASIType type = GET_ASI_HELPER;
1993
1994#ifndef TARGET_SPARC64
1995 /* Before v9, all asis are immediate and privileged. */
1a2fb1c0 1996 if (IS_IMM) {
22e70060 1997 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 1998 type = GET_ASI_EXCP;
1999 } else if (supervisor(dc)
2000 /* Note that LEON accepts ASI_USERDATA in user mode, for
2001 use with CASA. Also note that previous versions of
2002 QEMU allowed ASI_P for LEON, which is incorrect. */
2003 || (asi == 0xa
2004 && (dc->def->features & CPU_FEATURE_CASA))) {
1a2fb1c0 2005 } else {
7ec1e5ea
RH		 2006 gen_exception(dc, TT_PRIV_INSN);
2007 type = GET_ASI_EXCP;
2008 }
2009#else
2010 if (IS_IMM) {
2011 asi = dc->asi;
1a2fb1c0 2012 }
7ec1e5ea
RH		 2013#endif
2014
2015 return (DisasASI){ type, asi };
0425bee5
BS		 2016}
2017
22e70060
RH		 2018static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
2019 int insn, int size, int sign)
0425bee5 2020{
7ec1e5ea 2021 DisasASI da = get_asi(dc, insn);
0425bee5 2022
7ec1e5ea
RH		 2023 switch (da.type) {
2024 case GET_ASI_EXCP:
2025 break;
2026 default:
2027 {
2028 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2029 TCGv_i32 r_size = tcg_const_i32(size);
2030 TCGv_i32 r_sign = tcg_const_i32(sign);
2031
2032 save_state(dc);
22e70060 2033#ifdef TARGET_SPARC64
7ec1e5ea 2034 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
22e70060 2035#else
7ec1e5ea
RH		 2036 {
2037 TCGv_i64 t64 = tcg_temp_new_i64();
2038 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2039 tcg_gen_trunc_i64_tl(dst, t64);
2040 tcg_temp_free_i64(t64);
2041 }
22e70060 2042#endif
7ec1e5ea
RH		 2043 tcg_temp_free_i32(r_sign);
2044 tcg_temp_free_i32(r_size);
2045 tcg_temp_free_i32(r_asi);
2046 }
2047 break;
2048 }
1a2fb1c0
BS		 2049}
2050
22e70060
RH		 2051static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
2052 int insn, int size)
1a2fb1c0 2053{
7ec1e5ea 2054 DisasASI da = get_asi(dc, insn);
1a2fb1c0 2055
7ec1e5ea
RH		 2056 switch (da.type) {
2057 case GET_ASI_EXCP:
2058 break;
2059 default:
2060 {
2061 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2062 TCGv_i32 r_size = tcg_const_i32(size);
2063
2064 save_state(dc);
22e70060 2065#ifdef TARGET_SPARC64
7ec1e5ea 2066 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
22e70060 2067#else
7ec1e5ea
RH		 2068 {
2069 TCGv_i64 t64 = tcg_temp_new_i64();
2070 tcg_gen_extu_tl_i64(t64, src);
2071 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2072 tcg_temp_free_i64(t64);
2073 }
22e70060 2074#endif
7ec1e5ea
RH		 2075 tcg_temp_free_i32(r_size);
2076 tcg_temp_free_i32(r_asi);
2077
2078 /* A write to a TLB register may alter page maps. End the TB. */
2079 dc->npc = DYNAMIC_PC;
2080 }
2081 break;
2082 }
1a2fb1c0
BS		 2083}
2084
22e70060
RH		 2085static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2086 TCGv addr, int insn)
1a2fb1c0 2087{
7ec1e5ea 2088 DisasASI da = get_asi(dc, insn);
22e70060 2089
7ec1e5ea
RH		 2090 switch (da.type) {
2091 case GET_ASI_EXCP:
2092 break;
2093 default:
2094 {
2095 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2096 TCGv_i32 r_size = tcg_const_i32(4);
2097 TCGv_i32 r_sign = tcg_const_i32(0);
2098 TCGv_i64 s64, t64;
2099
2100 save_state(dc);
2101 t64 = tcg_temp_new_i64();
2102 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2103 tcg_temp_free_i32(r_sign);
2104
2105 s64 = tcg_temp_new_i64();
2106 tcg_gen_extu_tl_i64(s64, src);
2107 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
2108 tcg_temp_free_i64(s64);
2109 tcg_temp_free_i32(r_size);
2110 tcg_temp_free_i32(r_asi);
2111
2112 tcg_gen_trunc_i64_tl(dst, t64);
2113 tcg_temp_free_i64(t64);
2114 }
2115 break;
2116 }
1a2fb1c0
BS		 2117}
2118
22e70060
RH		 2119static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv val2,
2120 int insn, int rd)
2121{
7ec1e5ea
RH		 2122 DisasASI da = get_asi(dc, insn);
2123 TCGv val1, dst;
2124 TCGv_i32 r_asi;
22e70060 2125
7ec1e5ea
RH		 2126 if (da.type == GET_ASI_EXCP) {
2127 return;
2128 }
2129
2130 save_state(dc);
2131 val1 = gen_load_gpr(dc, rd);
2132 dst = gen_dest_gpr(dc, rd);
2133 r_asi = tcg_const_i32(da.asi);
22e70060
RH		 2134 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2135 tcg_temp_free_i32(r_asi);
2136 gen_store_gpr(dc, rd, dst);
2137}
2138
2139static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2140{
7ec1e5ea 2141 DisasASI da = get_asi(dc, insn);
22e70060 2142
7ec1e5ea
RH		 2143 switch (da.type) {
2144 case GET_ASI_EXCP:
2145 break;
2146 default:
2147 {
2148 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2149 TCGv_i32 r_size = tcg_const_i32(1);
2150 TCGv_i32 r_sign = tcg_const_i32(0);
2151 TCGv_i64 s64, t64;
2152
2153 save_state(dc);
2154 t64 = tcg_temp_new_i64();
2155 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2156 tcg_temp_free_i32(r_sign);
2157
2158 s64 = tcg_const_i64(0xff);
2159 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_size);
2160 tcg_temp_free_i64(s64);
2161 tcg_temp_free_i32(r_size);
2162 tcg_temp_free_i32(r_asi);
2163
2164 tcg_gen_trunc_i64_tl(dst, t64);
2165 tcg_temp_free_i64(t64);
2166 }
2167 break;
2168 }
22e70060
RH		 2169}
2170#endif
2171
2172#ifdef TARGET_SPARC64
2173static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2174 int insn, int size, int rd)
1a2fb1c0 2175{
7ec1e5ea 2176 DisasASI da = get_asi(dc, insn);
1a2fb1c0 2177
7ec1e5ea
RH		 2178 switch (da.type) {
2179 case GET_ASI_EXCP:
2180 break;
2181 default:
2182 {
2183 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2184 TCGv_i32 r_size = tcg_const_i32(size);
2185 TCGv_i32 r_rd = tcg_const_i32(rd);
2186
2187 save_state(dc);
2188 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
2189 tcg_temp_free_i32(r_rd);
2190 tcg_temp_free_i32(r_size);
2191 tcg_temp_free_i32(r_asi);
2192 }
2193 break;
2194 }
1a2fb1c0
BS		 2195}
2196
22e70060
RH		 2197static void gen_stf_asi(DisasContext *dc, TCGv addr,
2198 int insn, int size, int rd)
1a2fb1c0 2199{
7ec1e5ea 2200 DisasASI da = get_asi(dc, insn);
1a2fb1c0 2201
7ec1e5ea
RH		 2202 switch (da.type) {
2203 case GET_ASI_EXCP:
2204 break;
2205 default:
2206 {
2207 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2208 TCGv_i32 r_size = tcg_const_i32(size);
2209 TCGv_i32 r_rd = tcg_const_i32(rd);
2210
2211 save_state(dc);
2212 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
2213 tcg_temp_free_i32(r_rd);
2214 tcg_temp_free_i32(r_size);
2215 tcg_temp_free_i32(r_asi);
2216 }
2217 break;
2218 }
1a2fb1c0
BS		 2219}
2220
22e70060
RH		 2221static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2222 int insn, int rd)
1a2fb1c0 2223{
7ec1e5ea 2224 DisasASI da = get_asi(dc, insn);
1a2fb1c0 2225
7ec1e5ea
RH		 2226 switch (da.type) {
2227 case GET_ASI_EXCP:
2228 break;
2229 default:
2230 {
2231 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2232 TCGv_i32 r_rd = tcg_const_i32(rd);
2233
2234 save_state(dc);
2235 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
2236 tcg_temp_free_i32(r_rd);
2237 tcg_temp_free_i32(r_asi);
2238 }
2239 break;
2240 }
0425bee5
BS		 2241}
2242
22e70060
RH		 2243static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2244 int insn, int rd)
0425bee5 2245{
7ec1e5ea 2246 DisasASI da = get_asi(dc, insn);
c7785e16 2247 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2248
7ec1e5ea
RH		 2249 switch (da.type) {
2250 case GET_ASI_EXCP:
2251 break;
2252 default:
2253 {
2254 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2255 TCGv_i32 r_size = tcg_const_i32(8);
2256 TCGv_i64 t64;
2257
2258 save_state(dc);
2259
2260 t64 = tcg_temp_new_i64();
2261 tcg_gen_concat_tl_i64(t64, lo, hi);
2262 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2263 tcg_temp_free_i32(r_size);
2264 tcg_temp_free_i32(r_asi);
2265 tcg_temp_free_i64(t64);
2266 }
2267 break;
2268 }
1a2fb1c0
BS		 2269}
2270
22e70060
RH		 2271static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv val2,
2272 int insn, int rd)
1a2fb1c0 2273{
7ec1e5ea 2274 DisasASI da = get_asi(dc, insn);
81634eea
RH		 2275 TCGv val1 = gen_load_gpr(dc, rd);
2276 TCGv dst = gen_dest_gpr(dc, rd);
7ec1e5ea 2277 TCGv_i32 r_asi;
1a2fb1c0 2278
7ec1e5ea
RH		 2279 if (da.type == GET_ASI_EXCP) {
2280 return;
2281 }
2282
2283 save_state(dc);
2284 r_asi = tcg_const_i32(da.asi);
81634eea 2285 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
a7812ae4 2286 tcg_temp_free_i32(r_asi);
81634eea 2287 gen_store_gpr(dc, rd, dst);
1a2fb1c0
BS		 2288}
2289
2290#elif !defined(CONFIG_USER_ONLY)
22e70060
RH		 2291static void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2292 int insn, int rd)
1a2fb1c0 2293{
d2dc4069
RH		 2294 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2295 whereby "rd + 1" elicits "error: array subscript is above array".
2296 Since we have already asserted that rd is even, the semantics
2297 are unchanged. */
7ec1e5ea
RH		 2298 DisasASI da = get_asi(dc, insn);
2299 TCGv lo = gen_dest_gpr(dc, rd | 1);
2300 TCGv_i64 t64 = tcg_temp_new_i64();
2301
2302 switch (da.type) {
2303 case GET_ASI_EXCP:
2304 tcg_temp_free_i64(t64);
2305 return;
2306 default:
2307 {
2308 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2309 TCGv_i32 r_size = tcg_const_i32(8);
2310 TCGv_i32 r_sign = tcg_const_i32(0);
2311
2312 save_state(dc);
2313 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2314 tcg_temp_free_i32(r_sign);
2315 tcg_temp_free_i32(r_size);
2316 tcg_temp_free_i32(r_asi);
2317 }
2318 break;
2319 }
c7785e16 2320
7ec1e5ea 2321 tcg_gen_extr_i64_i32(lo, hi, t64);
1ec789ab 2322 tcg_temp_free_i64(t64);
7ec1e5ea 2323 gen_store_gpr(dc, rd | 1, lo);
c7785e16 2324 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2325}
2326
22e70060
RH		 2327static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2328 int insn, int rd)
0425bee5 2329{
7ec1e5ea 2330 DisasASI da = get_asi(dc, insn);
c7785e16 2331 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2332 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2333
1ec789ab 2334 tcg_gen_concat_tl_i64(t64, lo, hi);
7ec1e5ea
RH		 2335
2336 switch (da.type) {
2337 case GET_ASI_EXCP:
2338 break;
2339 default:
2340 {
2341 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2342 TCGv_i32 r_size = tcg_const_i32(8);
2343
2344 save_state(dc);
2345 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2346 tcg_temp_free_i32(r_size);
2347 tcg_temp_free_i32(r_asi);
2348 }
2349 break;
2350 }
2351
1ec789ab 2352 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2353}
2354#endif
2355
9d1d4e34 2356static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2357{
9d1d4e34
RH		 2358 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2359 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2360}
2361
9d1d4e34 2362static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2363{
a49d9390 2364 if (IS_IMM) { /* immediate */
42a8aa83 2365 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2366 TCGv t = get_temp_tl(dc);
2367 tcg_gen_movi_tl(t, simm);
2368 return t;
2369 } else { /* register */
42a8aa83 2370 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2371 return gen_load_gpr(dc, rs2);
a49d9390 2372 }
a49d9390
BS		 2373}
2374
8194f35a 2375#ifdef TARGET_SPARC64
7e480893
RH		 2376static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2377{
2378 TCGv_i32 c32, zero, dst, s1, s2;
2379
2380 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2381 or fold the comparison down to 32 bits and use movcond_i32. Choose
2382 the later. */
2383 c32 = tcg_temp_new_i32();
2384 if (cmp->is_bool) {
ecc7b3aa 2385 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2386 } else {
2387 TCGv_i64 c64 = tcg_temp_new_i64();
2388 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2389 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2390 tcg_temp_free_i64(c64);
2391 }
2392
2393 s1 = gen_load_fpr_F(dc, rs);
2394 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2395 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2396 zero = tcg_const_i32(0);
2397
2398 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2399
2400 tcg_temp_free_i32(c32);
2401 tcg_temp_free_i32(zero);
2402 gen_store_fpr_F(dc, rd, dst);
2403}
2404
2405static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2406{
3886b8a3 2407 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2408 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2409 gen_load_fpr_D(dc, rs),
2410 gen_load_fpr_D(dc, rd));
2411 gen_store_fpr_D(dc, rd, dst);
2412}
2413
2414static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2415{
2416 int qd = QFPREG(rd);
2417 int qs = QFPREG(rs);
2418
2419 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2420 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2421 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2422 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2423
2424 gen_update_fprs_dirty(qd);
2425}
2426
a2035e83 2427#ifndef CONFIG_USER_ONLY
1bcea73e 2428static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
8194f35a 2429{
b551ec04 2430 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2431
2432 /* load env->tl into r_tl */
b551ec04 2433 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2434
2435 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2436 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2437
2438 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2439 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2440 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2441
2442 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2443 {
2444 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2445 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2446 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2447 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2448 }
8194f35a 2449
b551ec04 2450 tcg_temp_free_i32(r_tl);
8194f35a 2451}
a2035e83 2452#endif
6c073553
RH		 2453
2454static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2455 int width, bool cc, bool left)
2456{
2457 TCGv lo1, lo2, t1, t2;
2458 uint64_t amask, tabl, tabr;
2459 int shift, imask, omask;
2460
2461 if (cc) {
2462 tcg_gen_mov_tl(cpu_cc_src, s1);
2463 tcg_gen_mov_tl(cpu_cc_src2, s2);
2464 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2465 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2466 dc->cc_op = CC_OP_SUB;
2467 }
2468
2469 /* Theory of operation: there are two tables, left and right (not to
2470 be confused with the left and right versions of the opcode). These
2471 are indexed by the low 3 bits of the inputs. To make things "easy",
2472 these tables are loaded into two constants, TABL and TABR below.
2473 The operation index = (input & imask) << shift calculates the index
2474 into the constant, while val = (table >> index) & omask calculates
2475 the value we're looking for. */
2476 switch (width) {
2477 case 8:
2478 imask = 0x7;
2479 shift = 3;
2480 omask = 0xff;
2481 if (left) {
2482 tabl = 0x80c0e0f0f8fcfeffULL;
2483 tabr = 0xff7f3f1f0f070301ULL;
2484 } else {
2485 tabl = 0x0103070f1f3f7fffULL;
2486 tabr = 0xfffefcf8f0e0c080ULL;
2487 }
2488 break;
2489 case 16:
2490 imask = 0x6;
2491 shift = 1;
2492 omask = 0xf;
2493 if (left) {
2494 tabl = 0x8cef;
2495 tabr = 0xf731;
2496 } else {
2497 tabl = 0x137f;
2498 tabr = 0xfec8;
2499 }
2500 break;
2501 case 32:
2502 imask = 0x4;
2503 shift = 0;
2504 omask = 0x3;
2505 if (left) {
2506 tabl = (2 << 2) | 3;
2507 tabr = (3 << 2) | 1;
2508 } else {
2509 tabl = (1 << 2) | 3;
2510 tabr = (3 << 2) | 2;
2511 }
2512 break;
2513 default:
2514 abort();
2515 }
2516
2517 lo1 = tcg_temp_new();
2518 lo2 = tcg_temp_new();
2519 tcg_gen_andi_tl(lo1, s1, imask);
2520 tcg_gen_andi_tl(lo2, s2, imask);
2521 tcg_gen_shli_tl(lo1, lo1, shift);
2522 tcg_gen_shli_tl(lo2, lo2, shift);
2523
2524 t1 = tcg_const_tl(tabl);
2525 t2 = tcg_const_tl(tabr);
2526 tcg_gen_shr_tl(lo1, t1, lo1);
2527 tcg_gen_shr_tl(lo2, t2, lo2);
2528 tcg_gen_andi_tl(dst, lo1, omask);
2529 tcg_gen_andi_tl(lo2, lo2, omask);
2530
2531 amask = -8;
2532 if (AM_CHECK(dc)) {
2533 amask &= 0xffffffffULL;
2534 }
2535 tcg_gen_andi_tl(s1, s1, amask);
2536 tcg_gen_andi_tl(s2, s2, amask);
2537
2538 /* We want to compute
2539 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2540 We've already done dst = lo1, so this reduces to
2541 dst &= (s1 == s2 ? -1 : lo2)
2542 Which we perform by
2543 lo2 |= -(s1 == s2)
2544 dst &= lo2
2545 */
2546 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2547 tcg_gen_neg_tl(t1, t1);
2548 tcg_gen_or_tl(lo2, lo2, t1);
2549 tcg_gen_and_tl(dst, dst, lo2);
2550
2551 tcg_temp_free(lo1);
2552 tcg_temp_free(lo2);
2553 tcg_temp_free(t1);
2554 tcg_temp_free(t2);
2555}
add545ab
RH		 2556
2557static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2558{
2559 TCGv tmp = tcg_temp_new();
2560
2561 tcg_gen_add_tl(tmp, s1, s2);
2562 tcg_gen_andi_tl(dst, tmp, -8);
2563 if (left) {
2564 tcg_gen_neg_tl(tmp, tmp);
2565 }
2566 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2567
2568 tcg_temp_free(tmp);
2569}
50c796f9
RH		 2570
2571static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2572{
2573 TCGv t1, t2, shift;
2574
2575 t1 = tcg_temp_new();
2576 t2 = tcg_temp_new();
2577 shift = tcg_temp_new();
2578
2579 tcg_gen_andi_tl(shift, gsr, 7);
2580 tcg_gen_shli_tl(shift, shift, 3);
2581 tcg_gen_shl_tl(t1, s1, shift);
2582
2583 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2584 shift of (up to 63) followed by a constant shift of 1. */
2585 tcg_gen_xori_tl(shift, shift, 63);
2586 tcg_gen_shr_tl(t2, s2, shift);
2587 tcg_gen_shri_tl(t2, t2, 1);
2588
2589 tcg_gen_or_tl(dst, t1, t2);
2590
2591 tcg_temp_free(t1);
2592 tcg_temp_free(t2);
2593 tcg_temp_free(shift);
2594}
8194f35a
IK		 2595#endif
2596
64a88d5d 2597#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2598 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2599 goto illegal_insn;
2600#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2601 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2602 goto nfpu_insn;
2603
0bee699e 2604/* before an instruction, dc->pc must be static */
0184e266 2605static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 2606{
0184e266 2607 unsigned int opc, rs1, rs2, rd;
a4273524 2608 TCGv cpu_src1, cpu_src2;
208ae657 2609 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2610 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2611 target_long simm;
7a3f1944 2612
cf495bcf 2613 opc = GET_FIELD(insn, 0, 1);
cf495bcf 2614 rd = GET_FIELD(insn, 2, 6);
6ae20372 2615
cf495bcf 2616 switch (opc) {
0f8a249a
BS		 2617 case 0: /* branches/sethi */
2618 {
2619 unsigned int xop = GET_FIELD(insn, 7, 9);
2620 int32_t target;
2621 switch (xop) {
3475187d 2622#ifdef TARGET_SPARC64
0f8a249a
BS		 2623 case 0x1: /* V9 BPcc */
2624 {
2625 int cc;
2626
2627 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2628 target = sign_extend(target, 19);
0f8a249a
BS		 2629 target <<= 2;
2630 cc = GET_FIELD_SP(insn, 20, 21);
2631 if (cc == 0)
d4a288ef 2632 do_branch(dc, target, insn, 0);
0f8a249a 2633 else if (cc == 2)
d4a288ef 2634 do_branch(dc, target, insn, 1);
0f8a249a
BS		 2635 else
2636 goto illegal_insn;
2637 goto jmp_insn;
2638 }
2639 case 0x3: /* V9 BPr */
2640 {
2641 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2642 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2643 target = sign_extend(target, 16);
2644 target <<= 2;
9d1d4e34 2645 cpu_src1 = get_src1(dc, insn);
d4a288ef 2646 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 2647 goto jmp_insn;
2648 }
2649 case 0x5: /* V9 FBPcc */
2650 {
2651 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 2652 if (gen_trap_ifnofpu(dc)) {
a80dde08 2653 goto jmp_insn;
5b12f1e8 2654 }
0f8a249a
BS		 2655 target = GET_FIELD_SP(insn, 0, 18);
2656 target = sign_extend(target, 19);
2657 target <<= 2;
d4a288ef 2658 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 2659 goto jmp_insn;
2660 }
a4d17f19 2661#else
0f8a249a
BS		 2662 case 0x7: /* CBN+x */
2663 {
2664 goto ncp_insn;
2665 }
2666#endif
2667 case 0x2: /* BN+x */
2668 {
2669 target = GET_FIELD(insn, 10, 31);
2670 target = sign_extend(target, 22);
2671 target <<= 2;
d4a288ef 2672 do_branch(dc, target, insn, 0);
0f8a249a
BS		 2673 goto jmp_insn;
2674 }
2675 case 0x6: /* FBN+x */
2676 {
5b12f1e8 2677 if (gen_trap_ifnofpu(dc)) {
a80dde08 2678 goto jmp_insn;
5b12f1e8 2679 }
0f8a249a
BS		 2680 target = GET_FIELD(insn, 10, 31);
2681 target = sign_extend(target, 22);
2682 target <<= 2;
d4a288ef 2683 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 2684 goto jmp_insn;
2685 }
2686 case 0x4: /* SETHI */
97ea2859
RH		 2687 /* Special-case %g0 because that's the canonical nop. */
2688 if (rd) {
0f8a249a 2689 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 2690 TCGv t = gen_dest_gpr(dc, rd);
2691 tcg_gen_movi_tl(t, value << 10);
2692 gen_store_gpr(dc, rd, t);
0f8a249a 2693 }
0f8a249a
BS		 2694 break;
2695 case 0x0: /* UNIMPL */
2696 default:
3475187d 2697 goto illegal_insn;
0f8a249a
BS		 2698 }
2699 break;
2700 }
2701 break;
dc1a6971
BS		 2702 case 1: /*CALL*/
2703 {
0f8a249a 2704 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 2705 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 2706
97ea2859
RH		 2707 tcg_gen_movi_tl(o7, dc->pc);
2708 gen_store_gpr(dc, 15, o7);
0f8a249a 2709 target += dc->pc;
13a6dd00 2710 gen_mov_pc_npc(dc);
22036a49
AT		 2711#ifdef TARGET_SPARC64
2712 if (unlikely(AM_CHECK(dc))) {
2713 target &= 0xffffffffULL;
2714 }
2715#endif
0f8a249a
BS		 2716 dc->npc = target;
2717 }
2718 goto jmp_insn;
2719 case 2: /* FPU & Logical Operations */
2720 {
2721 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 2722 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 2723 TCGv cpu_tmp0;
5793f2a4 2724
0f8a249a 2725 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 2726 int cond = GET_FIELD(insn, 3, 6);
2727 TCGv_i32 trap;
42a268c2
RH		 2728 TCGLabel *l1 = NULL;
2729 int mask;
3475187d 2730
bd49ed41
RH		 2731 if (cond == 0) {
2732 /* Trap never. */
2733 break;
cf495bcf 2734 }
b04d9890 2735
bd49ed41 2736 save_state(dc);
b04d9890 2737
bd49ed41
RH		 2738 if (cond != 8) {
2739 /* Conditional trap. */
3a49e759 2740 DisasCompare cmp;
3475187d 2741#ifdef TARGET_SPARC64
0f8a249a
BS		 2742 /* V9 icc/xcc */
2743 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 2744 if (cc == 0) {
2745 gen_compare(&cmp, 0, cond, dc);
2746 } else if (cc == 2) {
2747 gen_compare(&cmp, 1, cond, dc);
2748 } else {
0f8a249a 2749 goto illegal_insn;
3a49e759 2750 }
3475187d 2751#else
3a49e759 2752 gen_compare(&cmp, 0, cond, dc);
3475187d 2753#endif
b158a785 2754 l1 = gen_new_label();
3a49e759
RH		 2755 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2756 cmp.c1, cmp.c2, l1);
2757 free_compare(&cmp);
bd49ed41 2758 }
b158a785 2759
bd49ed41
RH		 2760 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2761 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2762
2763 /* Don't use the normal temporaries, as they may well have
2764 gone out of scope with the branch above. While we're
2765 doing that we might as well pre-truncate to 32-bit. */
2766 trap = tcg_temp_new_i32();
2767
2768 rs1 = GET_FIELD_SP(insn, 14, 18);
2769 if (IS_IMM) {
2770 rs2 = GET_FIELD_SP(insn, 0, 6);
2771 if (rs1 == 0) {
2772 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2773 /* Signal that the trap value is fully constant. */
2774 mask = 0;
2775 } else {
97ea2859 2776 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 2777 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2778 tcg_gen_addi_i32(trap, trap, rs2);
2779 }
2780 } else {
97ea2859 2781 TCGv t1, t2;
bd49ed41 2782 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 2783 t1 = gen_load_gpr(dc, rs1);
2784 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 2785 tcg_gen_add_tl(t1, t1, t2);
2786 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2787 }
2788 if (mask != 0) {
2789 tcg_gen_andi_i32(trap, trap, mask);
2790 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2791 }
2792
2793 gen_helper_raise_exception(cpu_env, trap);
2794 tcg_temp_free_i32(trap);
b158a785 2795
fe1755cb
RH		 2796 if (cond == 8) {
2797 /* An unconditional trap ends the TB. */
2798 dc->is_br = 1;
2799 goto jmp_insn;
2800 } else {
2801 /* A conditional trap falls through to the next insn. */
b158a785 2802 gen_set_label(l1);
fe1755cb 2803 break;
cf495bcf
FB		 2804 }
2805 } else if (xop == 0x28) {
2806 rs1 = GET_FIELD(insn, 13, 17);
2807 switch(rs1) {
2808 case 0: /* rdy */
65fe7b09
BS		 2809#ifndef TARGET_SPARC64
2810 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2811 manual, rdy on the microSPARC
2812 II */
2813 case 0x0f: /* stbar in the SPARCv8 manual,
2814 rdy on the microSPARC II */
2815 case 0x10 ... 0x1f: /* implementation-dependent in the
2816 SPARCv8 manual, rdy on the
2817 microSPARC II */
4a2ba232
FC		 2818 /* Read Asr17 */
2819 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 2820 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 2821 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 2822 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2823 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 2824 break;
2825 }
65fe7b09 2826#endif
97ea2859 2827 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 2828 break;
3475187d 2829#ifdef TARGET_SPARC64
0f8a249a 2830 case 0x2: /* V9 rdccr */
20132b96 2831 update_psr(dc);
063c3675 2832 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 2833 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2834 break;
0f8a249a 2835 case 0x3: /* V9 rdasi */
a6d567e5 2836 tcg_gen_movi_tl(cpu_dst, dc->asi);
97ea2859 2837 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2838 break;
0f8a249a 2839 case 0x4: /* V9 rdtick */
ccd4a219 2840 {
a7812ae4 2841 TCGv_ptr r_tickptr;
c9a46442 2842 TCGv_i32 r_const;
ccd4a219 2843
a7812ae4 2844 r_tickptr = tcg_temp_new_ptr();
c9a46442 2845 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2846 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2847 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 2848 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2849 r_const);
a7812ae4 2850 tcg_temp_free_ptr(r_tickptr);
c9a46442 2851 tcg_temp_free_i32(r_const);
97ea2859 2852 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2853 }
3475187d 2854 break;
0f8a249a 2855 case 0x5: /* V9 rdpc */
2ea815ca 2856 {
97ea2859 2857 TCGv t = gen_dest_gpr(dc, rd);
22036a49 2858 if (unlikely(AM_CHECK(dc))) {
97ea2859 2859 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 2860 } else {
97ea2859 2861 tcg_gen_movi_tl(t, dc->pc);
22036a49 2862 }
97ea2859 2863 gen_store_gpr(dc, rd, t);
2ea815ca 2864 }
0f8a249a
BS		 2865 break;
2866 case 0x6: /* V9 rdfprs */
255e1fcb 2867 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 2868 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2869 break;
65fe7b09
BS		 2870 case 0xf: /* V9 membar */
2871 break; /* no effect */
0f8a249a 2872 case 0x13: /* Graphics Status */
5b12f1e8 2873 if (gen_trap_ifnofpu(dc)) {
725cb90b 2874 goto jmp_insn;
5b12f1e8 2875 }
97ea2859 2876 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 2877 break;
9d926598 2878 case 0x16: /* Softint */
e86ceb0d
RH		 2879 tcg_gen_ld32s_tl(cpu_dst, cpu_env,
2880 offsetof(CPUSPARCState, softint));
97ea2859 2881 gen_store_gpr(dc, rd, cpu_dst);
9d926598 2882 break;
0f8a249a 2883 case 0x17: /* Tick compare */
97ea2859 2884 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 2885 break;
0f8a249a 2886 case 0x18: /* System tick */
ccd4a219 2887 {
a7812ae4 2888 TCGv_ptr r_tickptr;
c9a46442 2889 TCGv_i32 r_const;
ccd4a219 2890
a7812ae4 2891 r_tickptr = tcg_temp_new_ptr();
c9a46442 2892 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2893 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2894 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 2895 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2896 r_const);
a7812ae4 2897 tcg_temp_free_ptr(r_tickptr);
c9a46442 2898 tcg_temp_free_i32(r_const);
97ea2859 2899 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2900 }
83469015 2901 break;
0f8a249a 2902 case 0x19: /* System tick compare */
97ea2859 2903 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 2904 break;
0f8a249a
BS		 2905 case 0x10: /* Performance Control */
2906 case 0x11: /* Performance Instrumentation Counter */
2907 case 0x12: /* Dispatch Control */
2908 case 0x14: /* Softint set, WO */
2909 case 0x15: /* Softint clear, WO */
3475187d
FB		 2910#endif
2911 default:
cf495bcf
FB		 2912 goto illegal_insn;
2913 }
e8af50a3 2914#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2915 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2916#ifndef TARGET_SPARC64
20132b96 2917 if (!supervisor(dc)) {
0f8a249a 2918 goto priv_insn;
20132b96
RH		 2919 }
2920 update_psr(dc);
063c3675 2921 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2922#else
fb79ceb9 2923 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2924 if (!hypervisor(dc))
2925 goto priv_insn;
2926 rs1 = GET_FIELD(insn, 13, 17);
2927 switch (rs1) {
2928 case 0: // hpstate
2929 // gen_op_rdhpstate();
2930 break;
2931 case 1: // htstate
2932 // gen_op_rdhtstate();
2933 break;
2934 case 3: // hintp
255e1fcb 2935 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2936 break;
2937 case 5: // htba
255e1fcb 2938 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2939 break;
2940 case 6: // hver
255e1fcb 2941 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2942 break;
2943 case 31: // hstick_cmpr
255e1fcb 2944 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2945 break;
2946 default:
2947 goto illegal_insn;
2948 }
2949#endif
97ea2859 2950 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 2951 break;
3475187d 2952 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 2953 if (!supervisor(dc)) {
0f8a249a 2954 goto priv_insn;
de9e9d9f
RH		 2955 }
2956 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 2957#ifdef TARGET_SPARC64
2958 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2959 switch (rs1) {
2960 case 0: // tpc
375ee38b 2961 {
a7812ae4 2962 TCGv_ptr r_tsptr;
375ee38b 2963
a7812ae4 2964 r_tsptr = tcg_temp_new_ptr();
8194f35a 2965 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2966 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2967 offsetof(trap_state, tpc));
a7812ae4 2968 tcg_temp_free_ptr(r_tsptr);
375ee38b 2969 }
0f8a249a
BS		 2970 break;
2971 case 1: // tnpc
375ee38b 2972 {
a7812ae4 2973 TCGv_ptr r_tsptr;
375ee38b 2974
a7812ae4 2975 r_tsptr = tcg_temp_new_ptr();
8194f35a 2976 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2977 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2978 offsetof(trap_state, tnpc));
a7812ae4 2979 tcg_temp_free_ptr(r_tsptr);
375ee38b 2980 }
0f8a249a
BS		 2981 break;
2982 case 2: // tstate
375ee38b 2983 {
a7812ae4 2984 TCGv_ptr r_tsptr;
375ee38b 2985
a7812ae4 2986 r_tsptr = tcg_temp_new_ptr();
8194f35a 2987 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2988 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2989 offsetof(trap_state, tstate));
a7812ae4 2990 tcg_temp_free_ptr(r_tsptr);
375ee38b 2991 }
0f8a249a
BS		 2992 break;
2993 case 3: // tt
375ee38b 2994 {
45778f99 2995 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 2996
8194f35a 2997 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 2998 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2999 offsetof(trap_state, tt));
a7812ae4 3000 tcg_temp_free_ptr(r_tsptr);
375ee38b 3001 }
0f8a249a
BS		 3002 break;
3003 case 4: // tick
ccd4a219 3004 {
a7812ae4 3005 TCGv_ptr r_tickptr;
c9a46442 3006 TCGv_i32 r_const;
ccd4a219 3007
a7812ae4 3008 r_tickptr = tcg_temp_new_ptr();
c9a46442 3009 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3010 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3011 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3012 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
3013 r_tickptr, r_const);
a7812ae4 3014 tcg_temp_free_ptr(r_tickptr);
c9a46442 3015 tcg_temp_free_i32(r_const);
ccd4a219 3016 }
0f8a249a
BS		 3017 break;
3018 case 5: // tba
255e1fcb 3019 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 3020 break;
3021 case 6: // pstate
45778f99
RH		 3022 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3023 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 3024 break;
3025 case 7: // tl
45778f99
RH		 3026 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3027 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3028 break;
3029 case 8: // pil
45778f99
RH		 3030 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3031 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3032 break;
3033 case 9: // cwp
063c3675 3034 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 3035 break;
3036 case 10: // cansave
45778f99
RH		 3037 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3038 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3039 break;
3040 case 11: // canrestore
45778f99
RH		 3041 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3042 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3043 break;
3044 case 12: // cleanwin
45778f99
RH		 3045 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3046 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3047 break;
3048 case 13: // otherwin
45778f99
RH		 3049 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3050 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3051 break;
3052 case 14: // wstate
45778f99
RH		 3053 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3054 offsetof(CPUSPARCState, wstate));
0f8a249a 3055 break;
e9ebed4d 3056 case 16: // UA2005 gl
fb79ceb9 3057 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 3058 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3059 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3060 break;
3061 case 26: // UA2005 strand status
fb79ceb9 3062 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3063 if (!hypervisor(dc))
3064 goto priv_insn;
527067d8 3065 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 3066 break;
0f8a249a 3067 case 31: // ver
255e1fcb 3068 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 3069 break;
3070 case 15: // fq
3071 default:
3072 goto illegal_insn;
3073 }
3475187d 3074#else
255e1fcb 3075 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 3076#endif
97ea2859 3077 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 3078 break;
3475187d
FB		 3079 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
3080#ifdef TARGET_SPARC64
66442b07 3081 save_state(dc);
063c3675 3082 gen_helper_flushw(cpu_env);
3475187d 3083#else
0f8a249a
BS		 3084 if (!supervisor(dc))
3085 goto priv_insn;
97ea2859 3086 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 3087#endif
e8af50a3
FB		 3088 break;
3089#endif
0f8a249a 3090 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 3091 if (gen_trap_ifnofpu(dc)) {
a80dde08 3092 goto jmp_insn;
5b12f1e8 3093 }
0f8a249a 3094 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 3095 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3096 rs2 = GET_FIELD(insn, 27, 31);
3097 xop = GET_FIELD(insn, 18, 26);
66442b07 3098 save_state(dc);
0f8a249a 3099 switch (xop) {
dc1a6971 3100 case 0x1: /* fmovs */
208ae657
RH		 3101 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3102 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 3103 break;
3104 case 0x5: /* fnegs */
61f17f6e 3105 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 3106 break;
3107 case 0x9: /* fabss */
61f17f6e 3108 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 3109 break;
3110 case 0x29: /* fsqrts */
3111 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3112 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 3113 break;
3114 case 0x2a: /* fsqrtd */
3115 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3116 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 3117 break;
3118 case 0x2b: /* fsqrtq */
3119 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3120 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 3121 break;
3122 case 0x41: /* fadds */
61f17f6e 3123 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 3124 break;
3125 case 0x42: /* faddd */
61f17f6e 3126 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 3127 break;
3128 case 0x43: /* faddq */
3129 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3130 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 3131 break;
3132 case 0x45: /* fsubs */
61f17f6e 3133 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 3134 break;
3135 case 0x46: /* fsubd */
61f17f6e 3136 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3137 break;
3138 case 0x47: /* fsubq */
3139 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3140 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3141 break;
3142 case 0x49: /* fmuls */
3143 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3144 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3145 break;
3146 case 0x4a: /* fmuld */
3147 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3148 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3149 break;
3150 case 0x4b: /* fmulq */
3151 CHECK_FPU_FEATURE(dc, FLOAT128);
3152 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3153 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3154 break;
3155 case 0x4d: /* fdivs */
61f17f6e 3156 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3157 break;
3158 case 0x4e: /* fdivd */
61f17f6e 3159 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3160 break;
3161 case 0x4f: /* fdivq */
3162 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3163 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3164 break;
3165 case 0x69: /* fsmuld */
3166 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3167 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3168 break;
3169 case 0x6e: /* fdmulq */
3170 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3171 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3172 break;
3173 case 0xc4: /* fitos */
61f17f6e 3174 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3175 break;
3176 case 0xc6: /* fdtos */
61f17f6e 3177 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3178 break;
3179 case 0xc7: /* fqtos */
3180 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3181 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3182 break;
3183 case 0xc8: /* fitod */
61f17f6e 3184 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3185 break;
3186 case 0xc9: /* fstod */
61f17f6e 3187 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3188 break;
3189 case 0xcb: /* fqtod */
3190 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3191 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3192 break;
3193 case 0xcc: /* fitoq */
3194 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3195 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3196 break;
3197 case 0xcd: /* fstoq */
3198 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3199 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3200 break;
3201 case 0xce: /* fdtoq */
3202 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3203 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3204 break;
3205 case 0xd1: /* fstoi */
61f17f6e 3206 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3207 break;
3208 case 0xd2: /* fdtoi */
61f17f6e 3209 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3210 break;
3211 case 0xd3: /* fqtoi */
3212 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3213 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3214 break;
3475187d 3215#ifdef TARGET_SPARC64
dc1a6971 3216 case 0x2: /* V9 fmovd */
96eda024
RH		 3217 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3218 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3219 break;
3220 case 0x3: /* V9 fmovq */
3221 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 3222 gen_move_Q(rd, rs2);
dc1a6971
BS		 3223 break;
3224 case 0x6: /* V9 fnegd */
61f17f6e 3225 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3226 break;
3227 case 0x7: /* V9 fnegq */
3228 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3229 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3230 break;
3231 case 0xa: /* V9 fabsd */
61f17f6e 3232 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3233 break;
3234 case 0xb: /* V9 fabsq */
3235 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3236 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3237 break;
3238 case 0x81: /* V9 fstox */
61f17f6e 3239 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3240 break;
3241 case 0x82: /* V9 fdtox */
61f17f6e 3242 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3243 break;
3244 case 0x83: /* V9 fqtox */
3245 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3246 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3247 break;
3248 case 0x84: /* V9 fxtos */
61f17f6e 3249 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3250 break;
3251 case 0x88: /* V9 fxtod */
61f17f6e 3252 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3253 break;
3254 case 0x8c: /* V9 fxtoq */
3255 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3256 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3257 break;
0f8a249a 3258#endif
dc1a6971
BS		 3259 default:
3260 goto illegal_insn;
0f8a249a
BS		 3261 }
3262 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3263#ifdef TARGET_SPARC64
0f8a249a 3264 int cond;
3475187d 3265#endif
5b12f1e8 3266 if (gen_trap_ifnofpu(dc)) {
a80dde08 3267 goto jmp_insn;
5b12f1e8 3268 }
0f8a249a 3269 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3270 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3271 rs2 = GET_FIELD(insn, 27, 31);
3272 xop = GET_FIELD(insn, 18, 26);
66442b07 3273 save_state(dc);
dcf24905 3274
690995a6
RH		 3275#ifdef TARGET_SPARC64
3276#define FMOVR(sz) \
3277 do { \
3278 DisasCompare cmp; \
e7c8afb9 3279 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3280 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3281 gen_compare_reg(&cmp, cond, cpu_src1); \
3282 gen_fmov##sz(dc, &cmp, rd, rs2); \
3283 free_compare(&cmp); \
3284 } while (0)
3285
3286 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3287 FMOVR(s);
0f8a249a
BS		 3288 break;
3289 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3290 FMOVR(d);
0f8a249a
BS		 3291 break;
3292 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3293 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3294 FMOVR(q);
1f587329 3295 break;
0f8a249a 3296 }
690995a6 3297#undef FMOVR
0f8a249a
BS		 3298#endif
3299 switch (xop) {
3475187d 3300#ifdef TARGET_SPARC64
7e480893
RH		 3301#define FMOVCC(fcc, sz) \
3302 do { \
3303 DisasCompare cmp; \
714547bb 3304 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3305 gen_fcompare(&cmp, fcc, cond); \
3306 gen_fmov##sz(dc, &cmp, rd, rs2); \
3307 free_compare(&cmp); \
3308 } while (0)
3309
0f8a249a 3310 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3311 FMOVCC(0, s);
0f8a249a
BS		 3312 break;
3313 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3314 FMOVCC(0, d);
0f8a249a
BS		 3315 break;
3316 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3317 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3318 FMOVCC(0, q);
1f587329 3319 break;
0f8a249a 3320 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3321 FMOVCC(1, s);
0f8a249a
BS		 3322 break;
3323 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3324 FMOVCC(1, d);
0f8a249a
BS		 3325 break;
3326 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3327 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3328 FMOVCC(1, q);
1f587329 3329 break;
0f8a249a 3330 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3331 FMOVCC(2, s);
0f8a249a
BS		 3332 break;
3333 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3334 FMOVCC(2, d);
0f8a249a
BS		 3335 break;
3336 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3337 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3338 FMOVCC(2, q);
1f587329 3339 break;
0f8a249a 3340 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3341 FMOVCC(3, s);
0f8a249a
BS		 3342 break;
3343 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3344 FMOVCC(3, d);
0f8a249a
BS		 3345 break;
3346 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3347 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3348 FMOVCC(3, q);
1f587329 3349 break;
7e480893
RH		 3350#undef FMOVCC
3351#define FMOVCC(xcc, sz) \
3352 do { \
3353 DisasCompare cmp; \
714547bb 3354 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3355 gen_compare(&cmp, xcc, cond, dc); \
3356 gen_fmov##sz(dc, &cmp, rd, rs2); \
3357 free_compare(&cmp); \
3358 } while (0)
19f329ad 3359
0f8a249a 3360 case 0x101: /* V9 fmovscc %icc */
7e480893 3361 FMOVCC(0, s);
0f8a249a
BS		 3362 break;
3363 case 0x102: /* V9 fmovdcc %icc */
7e480893 3364 FMOVCC(0, d);
b7d69dc2 3365 break;
0f8a249a 3366 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3367 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3368 FMOVCC(0, q);
1f587329 3369 break;
0f8a249a 3370 case 0x181: /* V9 fmovscc %xcc */
7e480893 3371 FMOVCC(1, s);
0f8a249a
BS		 3372 break;
3373 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3374 FMOVCC(1, d);
0f8a249a
BS		 3375 break;
3376 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3377 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3378 FMOVCC(1, q);
1f587329 3379 break;
7e480893 3380#undef FMOVCC
1f587329
BS		 3381#endif
3382 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3383 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3384 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3385 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3386 break;
1f587329 3387 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3388 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3389 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3390 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3391 break;
1f587329 3392 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3393 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3394 gen_op_load_fpr_QT0(QFPREG(rs1));
3395 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3396 gen_op_fcmpq(rd & 3);
1f587329 3397 break;
0f8a249a 3398 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3399 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3400 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3401 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3402 break;
3403 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3404 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3405 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3406 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3407 break;
1f587329 3408 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3409 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3410 gen_op_load_fpr_QT0(QFPREG(rs1));
3411 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3412 gen_op_fcmpeq(rd & 3);
1f587329 3413 break;
0f8a249a
BS		 3414 default:
3415 goto illegal_insn;
3416 }
0f8a249a 3417 } else if (xop == 0x2) {
97ea2859 3418 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3419 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3420 if (rs1 == 0) {
97ea2859 3421 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3422 if (IS_IMM) { /* immediate */
67526b20 3423 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3424 tcg_gen_movi_tl(dst, simm);
3425 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3426 } else { /* register */
3427 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3428 if (rs2 == 0) {
3429 tcg_gen_movi_tl(dst, 0);
3430 gen_store_gpr(dc, rd, dst);
3431 } else {
3432 cpu_src2 = gen_load_gpr(dc, rs2);
3433 gen_store_gpr(dc, rd, cpu_src2);
3434 }
0f8a249a 3435 }
0f8a249a 3436 } else {
9d1d4e34 3437 cpu_src1 = get_src1(dc, insn);
0f8a249a 3438 if (IS_IMM) { /* immediate */
67526b20 3439 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3440 tcg_gen_ori_tl(dst, cpu_src1, simm);
3441 gen_store_gpr(dc, rd, dst);
0f8a249a 3442 } else { /* register */
0f8a249a 3443 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3444 if (rs2 == 0) {
3445 /* mov shortcut: or x, %g0, y -> mov x, y */
3446 gen_store_gpr(dc, rd, cpu_src1);
3447 } else {
3448 cpu_src2 = gen_load_gpr(dc, rs2);
3449 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3450 gen_store_gpr(dc, rd, dst);
3451 }
0f8a249a 3452 }
0f8a249a 3453 }
83469015 3454#ifdef TARGET_SPARC64
0f8a249a 3455 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3456 cpu_src1 = get_src1(dc, insn);
0f8a249a 3457 if (IS_IMM) { /* immediate */
67526b20 3458 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3459 if (insn & (1 << 12)) {
67526b20 3460 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3461 } else {
67526b20 3462 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3463 }
0f8a249a 3464 } else { /* register */
83469015 3465 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3466 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3467 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3468 if (insn & (1 << 12)) {
6ae20372 3469 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3470 } else {
6ae20372 3471 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3472 }
01b1fa6d 3473 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3474 }
97ea2859 3475 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3476 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 3477 cpu_src1 = get_src1(dc, insn);
0f8a249a 3478 if (IS_IMM) { /* immediate */
67526b20 3479 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3480 if (insn & (1 << 12)) {
67526b20 3481 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3482 } else {
6ae20372 3483 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3484 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3485 }
0f8a249a 3486 } else { /* register */
83469015 3487 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3488 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3489 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3490 if (insn & (1 << 12)) {
6ae20372
BS		 3491 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3492 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3493 } else {
6ae20372
BS		 3494 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3495 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3496 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3497 }
83469015 3498 }
97ea2859 3499 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3500 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 3501 cpu_src1 = get_src1(dc, insn);
0f8a249a 3502 if (IS_IMM) { /* immediate */
67526b20 3503 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3504 if (insn & (1 << 12)) {
67526b20 3505 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3506 } else {
97ea2859 3507 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 3508 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3509 }
0f8a249a 3510 } else { /* register */
83469015 3511 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3512 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3513 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3514 if (insn & (1 << 12)) {
6ae20372
BS		 3515 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3516 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3517 } else {
6ae20372 3518 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 3519 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 3520 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3521 }
83469015 3522 }
97ea2859 3523 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 3524#endif
fcc72045 3525 } else if (xop < 0x36) {
cf495bcf 3526 if (xop < 0x20) {
9d1d4e34
RH		 3527 cpu_src1 = get_src1(dc, insn);
3528 cpu_src2 = get_src2(dc, insn);
cf495bcf 3529 switch (xop & ~0x10) {
b89e94af 3530 case 0x0: /* add */
97ea2859
RH		 3531 if (xop & 0x10) {
3532 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3533 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3534 dc->cc_op = CC_OP_ADD;
41d72852 3535 } else {
97ea2859 3536 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3537 }
cf495bcf 3538 break;
b89e94af 3539 case 0x1: /* and */
97ea2859 3540 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3541 if (xop & 0x10) {
38482a77
BS		 3542 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3543 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3544 dc->cc_op = CC_OP_LOGIC;
41d72852 3545 }
cf495bcf 3546 break;
b89e94af 3547 case 0x2: /* or */
97ea2859 3548 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3549 if (xop & 0x10) {
38482a77
BS		 3550 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3551 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3552 dc->cc_op = CC_OP_LOGIC;
8393617c 3553 }
0f8a249a 3554 break;
b89e94af 3555 case 0x3: /* xor */
97ea2859 3556 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3557 if (xop & 0x10) {
38482a77
BS		 3558 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3559 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3560 dc->cc_op = CC_OP_LOGIC;
8393617c 3561 }
cf495bcf 3562 break;
b89e94af 3563 case 0x4: /* sub */
97ea2859
RH		 3564 if (xop & 0x10) {
3565 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3566 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3567 dc->cc_op = CC_OP_SUB;
41d72852 3568 } else {
97ea2859 3569 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3570 }
cf495bcf 3571 break;
b89e94af 3572 case 0x5: /* andn */
97ea2859 3573 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3574 if (xop & 0x10) {
38482a77
BS		 3575 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3576 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3577 dc->cc_op = CC_OP_LOGIC;
8393617c 3578 }
cf495bcf 3579 break;
b89e94af 3580 case 0x6: /* orn */
97ea2859 3581 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3582 if (xop & 0x10) {
38482a77
BS		 3583 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3584 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3585 dc->cc_op = CC_OP_LOGIC;
8393617c 3586 }
cf495bcf 3587 break;
b89e94af 3588 case 0x7: /* xorn */
97ea2859 3589 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3590 if (xop & 0x10) {
38482a77
BS		 3591 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3592 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3593 dc->cc_op = CC_OP_LOGIC;
8393617c 3594 }
cf495bcf 3595 break;
b89e94af 3596 case 0x8: /* addx, V9 addc */
70c48285
RH		 3597 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3598 (xop & 0x10));
cf495bcf 3599 break;
ded3ab80 3600#ifdef TARGET_SPARC64
0f8a249a 3601 case 0x9: /* V9 mulx */
97ea2859 3602 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3603 break;
3604#endif
b89e94af 3605 case 0xa: /* umul */
64a88d5d 3606 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3607 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3608 if (xop & 0x10) {
38482a77
BS		 3609 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3610 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3611 dc->cc_op = CC_OP_LOGIC;
8393617c 3612 }
cf495bcf 3613 break;
b89e94af 3614 case 0xb: /* smul */
64a88d5d 3615 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3616 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3617 if (xop & 0x10) {
38482a77
BS		 3618 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3619 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3620 dc->cc_op = CC_OP_LOGIC;
8393617c 3621 }
cf495bcf 3622 break;
b89e94af 3623 case 0xc: /* subx, V9 subc */
70c48285
RH		 3624 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3625 (xop & 0x10));
cf495bcf 3626 break;
ded3ab80 3627#ifdef TARGET_SPARC64
0f8a249a 3628 case 0xd: /* V9 udivx */
c28ae41e 3629 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 3630 break;
3631#endif
b89e94af 3632 case 0xe: /* udiv */
64a88d5d 3633 CHECK_IU_FEATURE(dc, DIV);
8393617c 3634 if (xop & 0x10) {
7a5e4488
BS		 3635 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3636 cpu_src2);
6c78ea32 3637 dc->cc_op = CC_OP_DIV;
0fcec41e 3638 } else {
7a5e4488
BS		 3639 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3640 cpu_src2);
8393617c 3641 }
cf495bcf 3642 break;
b89e94af 3643 case 0xf: /* sdiv */
64a88d5d 3644 CHECK_IU_FEATURE(dc, DIV);
8393617c 3645 if (xop & 0x10) {
7a5e4488
BS		 3646 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3647 cpu_src2);
6c78ea32 3648 dc->cc_op = CC_OP_DIV;
0fcec41e 3649 } else {
7a5e4488
BS		 3650 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3651 cpu_src2);
8393617c 3652 }
cf495bcf
FB		 3653 break;
3654 default:
3655 goto illegal_insn;
3656 }
97ea2859 3657 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3658 } else {
9d1d4e34
RH		 3659 cpu_src1 = get_src1(dc, insn);
3660 cpu_src2 = get_src2(dc, insn);
cf495bcf 3661 switch (xop) {
0f8a249a 3662 case 0x20: /* taddcc */
a2ea4aa9 3663 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3664 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3665 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3666 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3667 break;
3668 case 0x21: /* tsubcc */
a2ea4aa9 3669 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3670 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3671 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3672 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3673 break;
3674 case 0x22: /* taddcctv */
a2ea4aa9
RH		 3675 gen_helper_taddcctv(cpu_dst, cpu_env,
3676 cpu_src1, cpu_src2);
97ea2859 3677 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3678 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3679 break;
3680 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 3681 gen_helper_tsubcctv(cpu_dst, cpu_env,
3682 cpu_src1, cpu_src2);
97ea2859 3683 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3684 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3685 break;
cf495bcf 3686 case 0x24: /* mulscc */
20132b96 3687 update_psr(dc);
6ae20372 3688 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3689 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 3690 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3691 dc->cc_op = CC_OP_ADD;
cf495bcf 3692 break;
83469015 3693#ifndef TARGET_SPARC64
0f8a249a 3694 case 0x25: /* sll */
e35298cd 3695 if (IS_IMM) { /* immediate */
67526b20
BS		 3696 simm = GET_FIELDs(insn, 20, 31);
3697 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3698 } else { /* register */
de9e9d9f 3699 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3700 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3701 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3702 }
97ea2859 3703 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3704 break;
83469015 3705 case 0x26: /* srl */
e35298cd 3706 if (IS_IMM) { /* immediate */
67526b20
BS		 3707 simm = GET_FIELDs(insn, 20, 31);
3708 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3709 } else { /* register */
de9e9d9f 3710 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3711 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3712 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3713 }
97ea2859 3714 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3715 break;
83469015 3716 case 0x27: /* sra */
e35298cd 3717 if (IS_IMM) { /* immediate */
67526b20
BS		 3718 simm = GET_FIELDs(insn, 20, 31);
3719 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3720 } else { /* register */
de9e9d9f 3721 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3722 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3723 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3724 }
97ea2859 3725 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3726 break;
83469015 3727#endif
cf495bcf
FB		 3728 case 0x30:
3729 {
de9e9d9f 3730 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 3731 switch(rd) {
3475187d 3732 case 0: /* wry */
5068cbd9
BS		 3733 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3734 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3735 break;
65fe7b09
BS		 3736#ifndef TARGET_SPARC64
3737 case 0x01 ... 0x0f: /* undefined in the
3738 SPARCv8 manual, nop
3739 on the microSPARC
3740 II */
3741 case 0x10 ... 0x1f: /* implementation-dependent
3742 in the SPARCv8
3743 manual, nop on the
3744 microSPARC II */
d1c36ba7
RH		 3745 if ((rd == 0x13) && (dc->def->features &
3746 CPU_FEATURE_POWERDOWN)) {
3747 /* LEON3 power-down */
1cf892ca 3748 save_state(dc);
d1c36ba7
RH		 3749 gen_helper_power_down(cpu_env);
3750 }
65fe7b09
BS		 3751 break;
3752#else
0f8a249a 3753 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 3754 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3755 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 3756 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3757 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3758 break;
3759 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 3760 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3761 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
a6d567e5
RH		 3762 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3763 offsetof(CPUSPARCState, asi));
3764 /* End TB to notice changed ASI. */
3765 save_state(dc);
3766 gen_op_next_insn();
3767 tcg_gen_exit_tb(0);
3768 dc->is_br = 1;
0f8a249a
BS		 3769 break;
3770 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 3771 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3772 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
66442b07 3773 save_state(dc);
3299908c 3774 gen_op_next_insn();
57fec1fe 3775 tcg_gen_exit_tb(0);
3299908c 3776 dc->is_br = 1;
0f8a249a
BS		 3777 break;
3778 case 0xf: /* V9 sir, nop if user */
3475187d 3779#if !defined(CONFIG_USER_ONLY)
6ad6135d 3780 if (supervisor(dc)) {
1a2fb1c0 3781 ; // XXX
6ad6135d 3782 }
3475187d 3783#endif
0f8a249a
BS		 3784 break;
3785 case 0x13: /* Graphics Status */
5b12f1e8 3786 if (gen_trap_ifnofpu(dc)) {
725cb90b 3787 goto jmp_insn;
5b12f1e8 3788 }
255e1fcb 3789 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3790 break;
9d926598
BS		 3791 case 0x14: /* Softint set */
3792 if (!supervisor(dc))
3793 goto illegal_insn;
aeff993c
RH		 3794 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3795 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3796 break;
3797 case 0x15: /* Softint clear */
3798 if (!supervisor(dc))
3799 goto illegal_insn;
aeff993c
RH		 3800 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3801 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3802 break;
3803 case 0x16: /* Softint write */
3804 if (!supervisor(dc))
3805 goto illegal_insn;
aeff993c
RH		 3806 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3807 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 3808 break;
0f8a249a 3809 case 0x17: /* Tick compare */
83469015 3810#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3811 if (!supervisor(dc))
3812 goto illegal_insn;
83469015 3813#endif
ccd4a219 3814 {
a7812ae4 3815 TCGv_ptr r_tickptr;
ccd4a219 3816
255e1fcb 3817 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3818 cpu_src2);
a7812ae4 3819 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3820 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3821 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3822 gen_helper_tick_set_limit(r_tickptr,
3823 cpu_tick_cmpr);
3824 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3825 }
0f8a249a
BS		 3826 break;
3827 case 0x18: /* System tick */
83469015 3828#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3829 if (!supervisor(dc))
3830 goto illegal_insn;
83469015 3831#endif
ccd4a219 3832 {
a7812ae4 3833 TCGv_ptr r_tickptr;
ccd4a219 3834
7b04bd5c 3835 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3836 cpu_src2);
a7812ae4 3837 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3838 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3839 offsetof(CPUSPARCState, stick));
a7812ae4 3840 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 3841 cpu_tmp0);
a7812ae4 3842 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3843 }
0f8a249a
BS		 3844 break;
3845 case 0x19: /* System tick compare */
83469015 3846#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3847 if (!supervisor(dc))
3848 goto illegal_insn;
3475187d 3849#endif
ccd4a219 3850 {
a7812ae4 3851 TCGv_ptr r_tickptr;
ccd4a219 3852
255e1fcb 3853 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3854 cpu_src2);
a7812ae4 3855 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3856 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3857 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 3858 gen_helper_tick_set_limit(r_tickptr,
3859 cpu_stick_cmpr);
3860 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3861 }
0f8a249a 3862 break;
83469015 3863
0f8a249a 3864 case 0x10: /* Performance Control */
77f193da
BS		 3865 case 0x11: /* Performance Instrumentation
3866 Counter */
0f8a249a 3867 case 0x12: /* Dispatch Control */
83469015 3868#endif
3475187d 3869 default:
cf495bcf
FB		 3870 goto illegal_insn;
3871 }
3872 }
3873 break;
e8af50a3 3874#if !defined(CONFIG_USER_ONLY)
af7bf89b 3875 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3876 {
0f8a249a
BS		 3877 if (!supervisor(dc))
3878 goto priv_insn;
3475187d 3879#ifdef TARGET_SPARC64
0f8a249a
BS		 3880 switch (rd) {
3881 case 0:
063c3675 3882 gen_helper_saved(cpu_env);
0f8a249a
BS		 3883 break;
3884 case 1:
063c3675 3885 gen_helper_restored(cpu_env);
0f8a249a 3886 break;
e9ebed4d
BS		 3887 case 2: /* UA2005 allclean */
3888 case 3: /* UA2005 otherw */
3889 case 4: /* UA2005 normalw */
3890 case 5: /* UA2005 invalw */
3891 // XXX
0f8a249a 3892 default:
3475187d
FB		 3893 goto illegal_insn;
3894 }
3895#else
de9e9d9f 3896 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 3897 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3898 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 3899 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3900 dc->cc_op = CC_OP_FLAGS;
66442b07 3901 save_state(dc);
9e61bde5 3902 gen_op_next_insn();
57fec1fe 3903 tcg_gen_exit_tb(0);
0f8a249a 3904 dc->is_br = 1;
3475187d 3905#endif
e8af50a3
FB		 3906 }
3907 break;
af7bf89b 3908 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3909 {
0f8a249a
BS		 3910 if (!supervisor(dc))
3911 goto priv_insn;
de9e9d9f 3912 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3913 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3914#ifdef TARGET_SPARC64
0f8a249a
BS		 3915 switch (rd) {
3916 case 0: // tpc
375ee38b 3917 {
a7812ae4 3918 TCGv_ptr r_tsptr;
375ee38b 3919
a7812ae4 3920 r_tsptr = tcg_temp_new_ptr();
8194f35a 3921 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3922 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3923 offsetof(trap_state, tpc));
a7812ae4 3924 tcg_temp_free_ptr(r_tsptr);
375ee38b 3925 }
0f8a249a
BS		 3926 break;
3927 case 1: // tnpc
375ee38b 3928 {
a7812ae4 3929 TCGv_ptr r_tsptr;
375ee38b 3930
a7812ae4 3931 r_tsptr = tcg_temp_new_ptr();
8194f35a 3932 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3933 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3934 offsetof(trap_state, tnpc));
a7812ae4 3935 tcg_temp_free_ptr(r_tsptr);
375ee38b 3936 }
0f8a249a
BS		 3937 break;
3938 case 2: // tstate
375ee38b 3939 {
a7812ae4 3940 TCGv_ptr r_tsptr;
375ee38b 3941
a7812ae4 3942 r_tsptr = tcg_temp_new_ptr();
8194f35a 3943 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3944 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3945 offsetof(trap_state,
3946 tstate));
a7812ae4 3947 tcg_temp_free_ptr(r_tsptr);
375ee38b 3948 }
0f8a249a
BS		 3949 break;
3950 case 3: // tt
375ee38b 3951 {
a7812ae4 3952 TCGv_ptr r_tsptr;
375ee38b 3953
a7812ae4 3954 r_tsptr = tcg_temp_new_ptr();
8194f35a 3955 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 3956 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3957 offsetof(trap_state, tt));
a7812ae4 3958 tcg_temp_free_ptr(r_tsptr);
375ee38b 3959 }
0f8a249a
BS		 3960 break;
3961 case 4: // tick
ccd4a219 3962 {
a7812ae4 3963 TCGv_ptr r_tickptr;
ccd4a219 3964
a7812ae4 3965 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3966 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3967 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3968 gen_helper_tick_set_count(r_tickptr,
3969 cpu_tmp0);
3970 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3971 }
0f8a249a
BS		 3972 break;
3973 case 5: // tba
255e1fcb 3974 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3975 break;
3976 case 6: // pstate
6234ac09
RH		 3977 save_state(dc);
3978 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3979 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3980 break;
3981 case 7: // tl
6234ac09 3982 save_state(dc);
7b9e066b 3983 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 3984 offsetof(CPUSPARCState, tl));
3985 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3986 break;
3987 case 8: // pil
063c3675 3988 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3989 break;
3990 case 9: // cwp
063c3675 3991 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3992 break;
3993 case 10: // cansave
7b9e066b
RH		 3994 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3995 offsetof(CPUSPARCState,
3996 cansave));
0f8a249a
BS		 3997 break;
3998 case 11: // canrestore
7b9e066b
RH		 3999 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4000 offsetof(CPUSPARCState,
4001 canrestore));
0f8a249a
BS		 4002 break;
4003 case 12: // cleanwin
7b9e066b
RH		 4004 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4005 offsetof(CPUSPARCState,
4006 cleanwin));
0f8a249a
BS		 4007 break;
4008 case 13: // otherwin
7b9e066b
RH		 4009 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4010 offsetof(CPUSPARCState,
4011 otherwin));
0f8a249a
BS		 4012 break;
4013 case 14: // wstate
7b9e066b
RH		 4014 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4015 offsetof(CPUSPARCState,
4016 wstate));
0f8a249a 4017 break;
e9ebed4d 4018 case 16: // UA2005 gl
fb79ceb9 4019 CHECK_IU_FEATURE(dc, GL);
7b9e066b
RH		 4020 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4021 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 4022 break;
4023 case 26: // UA2005 strand status
fb79ceb9 4024 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4025 if (!hypervisor(dc))
4026 goto priv_insn;
527067d8 4027 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 4028 break;
0f8a249a
BS		 4029 default:
4030 goto illegal_insn;
4031 }
3475187d 4032#else
7b9e066b
RH		 4033 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
4034 if (dc->def->nwindows != 32) {
4035 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 4036 (1 << dc->def->nwindows) - 1);
7b9e066b 4037 }
3475187d 4038#endif
e8af50a3
FB		 4039 }
4040 break;
e9ebed4d 4041 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 4042 {
e9ebed4d 4043#ifndef TARGET_SPARC64
0f8a249a
BS		 4044 if (!supervisor(dc))
4045 goto priv_insn;
255e1fcb 4046 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 4047#else
fb79ceb9 4048 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4049 if (!hypervisor(dc))
4050 goto priv_insn;
de9e9d9f 4051 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4052 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 4053 switch (rd) {
4054 case 0: // hpstate
4055 // XXX gen_op_wrhpstate();
66442b07 4056 save_state(dc);
e9ebed4d 4057 gen_op_next_insn();
57fec1fe 4058 tcg_gen_exit_tb(0);
e9ebed4d
BS		 4059 dc->is_br = 1;
4060 break;
4061 case 1: // htstate
4062 // XXX gen_op_wrhtstate();
4063 break;
4064 case 3: // hintp
255e1fcb 4065 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 4066 break;
4067 case 5: // htba
255e1fcb 4068 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 4069 break;
4070 case 31: // hstick_cmpr
ccd4a219 4071 {
a7812ae4 4072 TCGv_ptr r_tickptr;
ccd4a219 4073
255e1fcb 4074 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 4075 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4076 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4077 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 4078 gen_helper_tick_set_limit(r_tickptr,
4079 cpu_hstick_cmpr);
4080 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4081 }
e9ebed4d
BS		 4082 break;
4083 case 6: // hver readonly
4084 default:
4085 goto illegal_insn;
4086 }
4087#endif
e8af50a3
FB		 4088 }
4089 break;
4090#endif
3475187d 4091#ifdef TARGET_SPARC64
0f8a249a
BS		 4092 case 0x2c: /* V9 movcc */
4093 {
4094 int cc = GET_FIELD_SP(insn, 11, 12);
4095 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 4096 DisasCompare cmp;
97ea2859 4097 TCGv dst;
00f219bf 4098
0f8a249a 4099 if (insn & (1 << 18)) {
f52879b4
RH		 4100 if (cc == 0) {
4101 gen_compare(&cmp, 0, cond, dc);
4102 } else if (cc == 2) {
4103 gen_compare(&cmp, 1, cond, dc);
4104 } else {
0f8a249a 4105 goto illegal_insn;
f52879b4 4106 }
0f8a249a 4107 } else {
f52879b4 4108 gen_fcompare(&cmp, cc, cond);
0f8a249a 4109 }
00f219bf 4110
f52879b4
RH		 4111 /* The get_src2 above loaded the normal 13-bit
4112 immediate field, not the 11-bit field we have
4113 in movcc. But it did handle the reg case. */
4114 if (IS_IMM) {
67526b20 4115 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 4116 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 4117 }
f52879b4 4118
97ea2859
RH		 4119 dst = gen_load_gpr(dc, rd);
4120 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 4121 cmp.c1, cmp.c2,
97ea2859 4122 cpu_src2, dst);
f52879b4 4123 free_compare(&cmp);
97ea2859 4124 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4125 break;
4126 }
4127 case 0x2d: /* V9 sdivx */
c28ae41e 4128 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 4129 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 4130 break;
4131 case 0x2e: /* V9 popc */
97ea2859
RH		 4132 gen_helper_popc(cpu_dst, cpu_src2);
4133 gen_store_gpr(dc, rd, cpu_dst);
4134 break;
0f8a249a
BS		 4135 case 0x2f: /* V9 movr */
4136 {
4137 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 4138 DisasCompare cmp;
97ea2859 4139 TCGv dst;
00f219bf 4140
c33f80f5 4141 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4142
c33f80f5
RH		 4143 /* The get_src2 above loaded the normal 13-bit
4144 immediate field, not the 10-bit field we have
4145 in movr. But it did handle the reg case. */
4146 if (IS_IMM) {
67526b20 4147 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4148 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4149 }
c33f80f5 4150
97ea2859
RH		 4151 dst = gen_load_gpr(dc, rd);
4152 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4153 cmp.c1, cmp.c2,
97ea2859 4154 cpu_src2, dst);
c33f80f5 4155 free_compare(&cmp);
97ea2859 4156 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4157 break;
4158 }
4159#endif
4160 default:
4161 goto illegal_insn;
4162 }
4163 }
3299908c
BS		 4164 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4165#ifdef TARGET_SPARC64
4166 int opf = GET_FIELD_SP(insn, 5, 13);
4167 rs1 = GET_FIELD(insn, 13, 17);
4168 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4169 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4170 goto jmp_insn;
5b12f1e8 4171 }
3299908c
BS		 4172
4173 switch (opf) {
e9ebed4d 4174 case 0x000: /* VIS I edge8cc */
6c073553 4175 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4176 cpu_src1 = gen_load_gpr(dc, rs1);
4177 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4178 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4179 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4180 break;
e9ebed4d 4181 case 0x001: /* VIS II edge8n */
6c073553 4182 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4183 cpu_src1 = gen_load_gpr(dc, rs1);
4184 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4185 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4186 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4187 break;
e9ebed4d 4188 case 0x002: /* VIS I edge8lcc */
6c073553 4189 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4190 cpu_src1 = gen_load_gpr(dc, rs1);
4191 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4192 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4193 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4194 break;
e9ebed4d 4195 case 0x003: /* VIS II edge8ln */
6c073553 4196 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4197 cpu_src1 = gen_load_gpr(dc, rs1);
4198 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4199 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4200 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4201 break;
e9ebed4d 4202 case 0x004: /* VIS I edge16cc */
6c073553 4203 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4204 cpu_src1 = gen_load_gpr(dc, rs1);
4205 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4206 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4207 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4208 break;
e9ebed4d 4209 case 0x005: /* VIS II edge16n */
6c073553 4210 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4211 cpu_src1 = gen_load_gpr(dc, rs1);
4212 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4213 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4214 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4215 break;
e9ebed4d 4216 case 0x006: /* VIS I edge16lcc */
6c073553 4217 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4218 cpu_src1 = gen_load_gpr(dc, rs1);
4219 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4220 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4221 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4222 break;
e9ebed4d 4223 case 0x007: /* VIS II edge16ln */
6c073553 4224 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4225 cpu_src1 = gen_load_gpr(dc, rs1);
4226 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4227 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4228 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4229 break;
e9ebed4d 4230 case 0x008: /* VIS I edge32cc */
6c073553 4231 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4232 cpu_src1 = gen_load_gpr(dc, rs1);
4233 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4234 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4235 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4236 break;
e9ebed4d 4237 case 0x009: /* VIS II edge32n */
6c073553 4238 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4239 cpu_src1 = gen_load_gpr(dc, rs1);
4240 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4241 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4242 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4243 break;
e9ebed4d 4244 case 0x00a: /* VIS I edge32lcc */
6c073553 4245 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4246 cpu_src1 = gen_load_gpr(dc, rs1);
4247 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4248 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4249 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4250 break;
e9ebed4d 4251 case 0x00b: /* VIS II edge32ln */
6c073553 4252 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4253 cpu_src1 = gen_load_gpr(dc, rs1);
4254 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4255 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4256 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4257 break;
e9ebed4d 4258 case 0x010: /* VIS I array8 */
64a88d5d 4259 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4260 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4261 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4262 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4263 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4264 break;
4265 case 0x012: /* VIS I array16 */
64a88d5d 4266 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4267 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4268 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4269 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4270 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4271 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4272 break;
4273 case 0x014: /* VIS I array32 */
64a88d5d 4274 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4275 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4276 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4277 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4278 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4279 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4280 break;
3299908c 4281 case 0x018: /* VIS I alignaddr */
64a88d5d 4282 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4283 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4284 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4285 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4286 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4287 break;
4288 case 0x01a: /* VIS I alignaddrl */
add545ab 4289 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4290 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4291 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4292 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4293 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4294 break;
4295 case 0x019: /* VIS II bmask */
793a137a 4296 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4297 cpu_src1 = gen_load_gpr(dc, rs1);
4298 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4299 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4300 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4301 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4302 break;
e9ebed4d 4303 case 0x020: /* VIS I fcmple16 */
64a88d5d 4304 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4305 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4306 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4307 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4308 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4309 break;
4310 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4311 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4312 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4313 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4314 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4315 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4316 break;
e9ebed4d 4317 case 0x024: /* VIS I fcmple32 */
64a88d5d 4318 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4319 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4320 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4321 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4322 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4323 break;
4324 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4325 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4326 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4327 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4328 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4329 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4330 break;
4331 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4332 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4333 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4334 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4335 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4336 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4337 break;
4338 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4339 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4340 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4341 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4342 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4343 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4344 break;
4345 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4346 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4347 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4348 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4349 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4350 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4351 break;
4352 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4353 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4354 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4355 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4356 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4357 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4358 break;
4359 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4360 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4361 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4362 break;
4363 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4364 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4365 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4366 break;
4367 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4368 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4369 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4370 break;
4371 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4372 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4373 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4374 break;
4375 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4376 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4377 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4378 break;
4379 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4380 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4381 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4382 break;
4383 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4384 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4385 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4386 break;
4387 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4388 CHECK_FPU_FEATURE(dc, VIS1);
4389 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4390 break;
e9ebed4d 4391 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4392 CHECK_FPU_FEATURE(dc, VIS1);
4393 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4394 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4395 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4396 gen_store_fpr_F(dc, rd, cpu_dst_32);
4397 break;
e9ebed4d 4398 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4399 CHECK_FPU_FEATURE(dc, VIS1);
4400 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4401 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4402 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4403 gen_store_fpr_F(dc, rd, cpu_dst_32);
4404 break;
f888300b
RH		 4405 case 0x03e: /* VIS I pdist */
4406 CHECK_FPU_FEATURE(dc, VIS1);
4407 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4408 break;
3299908c 4409 case 0x048: /* VIS I faligndata */
64a88d5d 4410 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4411 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4412 break;
e9ebed4d 4413 case 0x04b: /* VIS I fpmerge */
64a88d5d 4414 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4415 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4416 break;
4417 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4418 CHECK_FPU_FEATURE(dc, VIS2);
4419 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4420 break;
e9ebed4d 4421 case 0x04d: /* VIS I fexpand */
64a88d5d 4422 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4423 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4424 break;
4425 case 0x050: /* VIS I fpadd16 */
64a88d5d 4426 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4427 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4428 break;
4429 case 0x051: /* VIS I fpadd16s */
64a88d5d 4430 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4431 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4432 break;
4433 case 0x052: /* VIS I fpadd32 */
64a88d5d 4434 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4435 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4436 break;
4437 case 0x053: /* VIS I fpadd32s */
64a88d5d 4438 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4439 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4440 break;
4441 case 0x054: /* VIS I fpsub16 */
64a88d5d 4442 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4443 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4444 break;
4445 case 0x055: /* VIS I fpsub16s */
64a88d5d 4446 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4447 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4448 break;
4449 case 0x056: /* VIS I fpsub32 */
64a88d5d 4450 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4451 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4452 break;
4453 case 0x057: /* VIS I fpsub32s */
64a88d5d 4454 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4455 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4456 break;
3299908c 4457 case 0x060: /* VIS I fzero */
64a88d5d 4458 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4459 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4460 tcg_gen_movi_i64(cpu_dst_64, 0);
4461 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4462 break;
4463 case 0x061: /* VIS I fzeros */
64a88d5d 4464 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4465 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4466 tcg_gen_movi_i32(cpu_dst_32, 0);
4467 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4468 break;
e9ebed4d 4469 case 0x062: /* VIS I fnor */
64a88d5d 4470 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4471 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4472 break;
4473 case 0x063: /* VIS I fnors */
64a88d5d 4474 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4475 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4476 break;
4477 case 0x064: /* VIS I fandnot2 */
64a88d5d 4478 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4479 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4480 break;
4481 case 0x065: /* VIS I fandnot2s */
64a88d5d 4482 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4483 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4484 break;
4485 case 0x066: /* VIS I fnot2 */
64a88d5d 4486 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4487 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4488 break;
4489 case 0x067: /* VIS I fnot2s */
64a88d5d 4490 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4491 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4492 break;
4493 case 0x068: /* VIS I fandnot1 */
64a88d5d 4494 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4495 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4496 break;
4497 case 0x069: /* VIS I fandnot1s */
64a88d5d 4498 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4499 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4500 break;
4501 case 0x06a: /* VIS I fnot1 */
64a88d5d 4502 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4503 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4504 break;
4505 case 0x06b: /* VIS I fnot1s */
64a88d5d 4506 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4507 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4508 break;
4509 case 0x06c: /* VIS I fxor */
64a88d5d 4510 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4511 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4512 break;
4513 case 0x06d: /* VIS I fxors */
64a88d5d 4514 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4515 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4516 break;
4517 case 0x06e: /* VIS I fnand */
64a88d5d 4518 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4519 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4520 break;
4521 case 0x06f: /* VIS I fnands */
64a88d5d 4522 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4523 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4524 break;
4525 case 0x070: /* VIS I fand */
64a88d5d 4526 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4527 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4528 break;
4529 case 0x071: /* VIS I fands */
64a88d5d 4530 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4531 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4532 break;
4533 case 0x072: /* VIS I fxnor */
64a88d5d 4534 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4535 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4536 break;
4537 case 0x073: /* VIS I fxnors */
64a88d5d 4538 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4539 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4540 break;
3299908c 4541 case 0x074: /* VIS I fsrc1 */
64a88d5d 4542 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4543 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4544 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4545 break;
4546 case 0x075: /* VIS I fsrc1s */
64a88d5d 4547 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4548 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4549 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4550 break;
e9ebed4d 4551 case 0x076: /* VIS I fornot2 */
64a88d5d 4552 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4553 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4554 break;
4555 case 0x077: /* VIS I fornot2s */
64a88d5d 4556 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4557 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4558 break;
3299908c 4559 case 0x078: /* VIS I fsrc2 */
64a88d5d 4560 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4561 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4562 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4563 break;
4564 case 0x079: /* VIS I fsrc2s */
64a88d5d 4565 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4566 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4567 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4568 break;
e9ebed4d 4569 case 0x07a: /* VIS I fornot1 */
64a88d5d 4570 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4571 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4572 break;
4573 case 0x07b: /* VIS I fornot1s */
64a88d5d 4574 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4575 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4576 break;
4577 case 0x07c: /* VIS I for */
64a88d5d 4578 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4579 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4580 break;
4581 case 0x07d: /* VIS I fors */
64a88d5d 4582 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4583 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4584 break;
3299908c 4585 case 0x07e: /* VIS I fone */
64a88d5d 4586 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4587 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4588 tcg_gen_movi_i64(cpu_dst_64, -1);
4589 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4590 break;
4591 case 0x07f: /* VIS I fones */
64a88d5d 4592 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4593 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4594 tcg_gen_movi_i32(cpu_dst_32, -1);
4595 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4596 break;
e9ebed4d
BS		 4597 case 0x080: /* VIS I shutdown */
4598 case 0x081: /* VIS II siam */
4599 // XXX
4600 goto illegal_insn;
3299908c
BS		 4601 default:
4602 goto illegal_insn;
4603 }
4604#else
0f8a249a 4605 goto ncp_insn;
3299908c
BS		 4606#endif
4607 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4608#ifdef TARGET_SPARC64
0f8a249a 4609 goto illegal_insn;
fcc72045 4610#else
0f8a249a 4611 goto ncp_insn;
fcc72045 4612#endif
3475187d 4613#ifdef TARGET_SPARC64
0f8a249a 4614 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4615 TCGv_i32 r_const;
2ea815ca 4616
66442b07 4617 save_state(dc);
9d1d4e34 4618 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4619 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4620 if (IS_IMM) { /* immediate */
67526b20 4621 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4622 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4623 } else { /* register */
3475187d 4624 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4625 if (rs2) {
97ea2859 4626 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4627 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4628 } else {
7b04bd5c 4629 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4630 }
3475187d 4631 }
063c3675 4632 gen_helper_restore(cpu_env);
13a6dd00 4633 gen_mov_pc_npc(dc);
2ea815ca 4634 r_const = tcg_const_i32(3);
7b04bd5c 4635 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4636 tcg_temp_free_i32(r_const);
7b04bd5c 4637 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4638 dc->npc = DYNAMIC_PC;
4639 goto jmp_insn;
3475187d 4640#endif
0f8a249a 4641 } else {
9d1d4e34 4642 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4643 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4644 if (IS_IMM) { /* immediate */
67526b20 4645 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4646 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4647 } else { /* register */
e80cfcfc 4648 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4649 if (rs2) {
97ea2859 4650 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4651 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4652 } else {
7b04bd5c 4653 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4654 }
cf495bcf 4655 }
0f8a249a
BS		 4656 switch (xop) {
4657 case 0x38: /* jmpl */
4658 {
97ea2859 4659 TCGv t;
a7812ae4 4660 TCGv_i32 r_const;
2ea815ca 4661
97ea2859
RH		 4662 t = gen_dest_gpr(dc, rd);
4663 tcg_gen_movi_tl(t, dc->pc);
4664 gen_store_gpr(dc, rd, t);
13a6dd00 4665 gen_mov_pc_npc(dc);
2ea815ca 4666 r_const = tcg_const_i32(3);
7b04bd5c 4667 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4668 tcg_temp_free_i32(r_const);
7b04bd5c
RH		 4669 gen_address_mask(dc, cpu_tmp0);
4670 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4671 dc->npc = DYNAMIC_PC;
4672 }
4673 goto jmp_insn;
3475187d 4674#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4675 case 0x39: /* rett, V9 return */
4676 {
a7812ae4 4677 TCGv_i32 r_const;
2ea815ca 4678
0f8a249a
BS		 4679 if (!supervisor(dc))
4680 goto priv_insn;
13a6dd00 4681 gen_mov_pc_npc(dc);
2ea815ca 4682 r_const = tcg_const_i32(3);
7b04bd5c 4683 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4684 tcg_temp_free_i32(r_const);
7b04bd5c 4685 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 4686 dc->npc = DYNAMIC_PC;
063c3675 4687 gen_helper_rett(cpu_env);
0f8a249a
BS		 4688 }
4689 goto jmp_insn;
4690#endif
4691 case 0x3b: /* flush */
5578ceab 4692 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4693 goto unimp_flush;
dcfd14b3 4694 /* nop */
0f8a249a
BS		 4695 break;
4696 case 0x3c: /* save */
66442b07 4697 save_state(dc);
063c3675 4698 gen_helper_save(cpu_env);
7b04bd5c 4699 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 4700 break;
4701 case 0x3d: /* restore */
66442b07 4702 save_state(dc);
063c3675 4703 gen_helper_restore(cpu_env);
7b04bd5c 4704 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 4705 break;
3475187d 4706#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4707 case 0x3e: /* V9 done/retry */
4708 {
4709 switch (rd) {
4710 case 0:
4711 if (!supervisor(dc))
4712 goto priv_insn;
4713 dc->npc = DYNAMIC_PC;
4714 dc->pc = DYNAMIC_PC;
063c3675 4715 gen_helper_done(cpu_env);
0f8a249a
BS		 4716 goto jmp_insn;
4717 case 1:
4718 if (!supervisor(dc))
4719 goto priv_insn;
4720 dc->npc = DYNAMIC_PC;
4721 dc->pc = DYNAMIC_PC;
063c3675 4722 gen_helper_retry(cpu_env);
0f8a249a
BS		 4723 goto jmp_insn;
4724 default:
4725 goto illegal_insn;
4726 }
4727 }
4728 break;
4729#endif
4730 default:
4731 goto illegal_insn;
4732 }
cf495bcf 4733 }
0f8a249a
BS		 4734 break;
4735 }
4736 break;
4737 case 3: /* load/store instructions */
4738 {
4739 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 4740 /* ??? gen_address_mask prevents us from using a source
4741 register directly. Always generate a temporary. */
4742 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 4743
5e6ed439
RH		 4744 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4745 if (xop == 0x3c || xop == 0x3e) {
4746 /* V9 casa/casxa : no offset */
71817e48 4747 } else if (IS_IMM) { /* immediate */
67526b20 4748 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 4749 if (simm != 0) {
4750 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4751 }
0f8a249a
BS		 4752 } else { /* register */
4753 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4754 if (rs2 != 0) {
5e6ed439 4755 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 4756 }
0f8a249a 4757 }
2f2ecb83
BS		 4758 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4759 (xop > 0x17 && xop <= 0x1d ) ||
4760 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 4761 TCGv cpu_val = gen_dest_gpr(dc, rd);
4762
0f8a249a 4763 switch (xop) {
b89e94af 4764 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4765 gen_address_mask(dc, cpu_addr);
6ae20372 4766 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4767 break;
b89e94af 4768 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4769 gen_address_mask(dc, cpu_addr);
6ae20372 4770 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4771 break;
b89e94af 4772 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4773 gen_address_mask(dc, cpu_addr);
6ae20372 4774 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4775 break;
b89e94af 4776 case 0x3: /* ldd, load double word */
0f8a249a 4777 if (rd & 1)
d4218d99 4778 goto illegal_insn;
1a2fb1c0 4779 else {
a7812ae4 4780 TCGv_i32 r_const;
abcc7191 4781 TCGv_i64 t64;
2ea815ca 4782
66442b07 4783 save_state(dc);
2ea815ca 4784 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4785 /* XXX remove alignment check */
4786 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4787 tcg_temp_free_i32(r_const);
2cade6a3 4788 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 4789 t64 = tcg_temp_new_i64();
4790 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 4791 tcg_gen_trunc_i64_tl(cpu_val, t64);
4792 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4793 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 4794 tcg_gen_shri_i64(t64, t64, 32);
4795 tcg_gen_trunc_i64_tl(cpu_val, t64);
4796 tcg_temp_free_i64(t64);
de9e9d9f 4797 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 4798 }
0f8a249a 4799 break;
b89e94af 4800 case 0x9: /* ldsb, load signed byte */
2cade6a3 4801 gen_address_mask(dc, cpu_addr);
6ae20372 4802 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4803 break;
b89e94af 4804 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4805 gen_address_mask(dc, cpu_addr);
6ae20372 4806 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4807 break;
4808 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4809 {
4810 TCGv r_const;
b64d2e57 4811 TCGv tmp = tcg_temp_new();
2ea815ca 4812
2cade6a3 4813 gen_address_mask(dc, cpu_addr);
b64d2e57 4814 tcg_gen_qemu_ld8u(tmp, cpu_addr, dc->mem_idx);
2ea815ca
BS		 4815 r_const = tcg_const_tl(0xff);
4816 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
b64d2e57 4817 tcg_gen_mov_tl(cpu_val, tmp);
2ea815ca 4818 tcg_temp_free(r_const);
b64d2e57 4819 tcg_temp_free(tmp);
2ea815ca 4820 }
0f8a249a 4821 break;
de9e9d9f
RH		 4822 case 0x0f:
4823 /* swap, swap register with memory. Also atomically */
4824 {
4825 TCGv t0 = get_temp_tl(dc);
4826 CHECK_IU_FEATURE(dc, SWAP);
4827 cpu_src1 = gen_load_gpr(dc, rd);
4828 gen_address_mask(dc, cpu_addr);
4829 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4830 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4831 tcg_gen_mov_tl(cpu_val, t0);
4832 }
0f8a249a 4833 break;
3475187d 4834#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4835 case 0x10: /* lda, V9 lduwa, load word alternate */
22e70060 4836 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4837 break;
b89e94af 4838 case 0x11: /* lduba, load unsigned byte alternate */
22e70060 4839 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4840 break;
b89e94af 4841 case 0x12: /* lduha, load unsigned halfword alternate */
22e70060 4842 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4843 break;
b89e94af 4844 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 4845 if (rd & 1) {
d4218d99 4846 goto illegal_insn;
7ec1e5ea 4847 }
c7785e16 4848 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
db166940 4849 goto skip_move;
b89e94af 4850 case 0x19: /* ldsba, load signed byte alternate */
22e70060 4851 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4852 break;
b89e94af 4853 case 0x1a: /* ldsha, load signed halfword alternate */
22e70060 4854 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4855 break;
4856 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 4857 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 4858 break;
b89e94af 4859 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4860 atomically */
64a88d5d 4861 CHECK_IU_FEATURE(dc, SWAP);
06828032 4862 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 4863 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 4864 break;
3475187d
FB		 4865
4866#ifndef TARGET_SPARC64
0f8a249a
BS		 4867 case 0x30: /* ldc */
4868 case 0x31: /* ldcsr */
4869 case 0x33: /* lddc */
4870 goto ncp_insn;
3475187d
FB		 4871#endif
4872#endif
4873#ifdef TARGET_SPARC64
0f8a249a 4874 case 0x08: /* V9 ldsw */
2cade6a3 4875 gen_address_mask(dc, cpu_addr);
6ae20372 4876 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4877 break;
4878 case 0x0b: /* V9 ldx */
2cade6a3 4879 gen_address_mask(dc, cpu_addr);
6ae20372 4880 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4881 break;
4882 case 0x18: /* V9 ldswa */
22e70060 4883 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4884 break;
4885 case 0x1b: /* V9 ldxa */
22e70060 4886 gen_ld_asi(dc, cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4887 break;
4888 case 0x2d: /* V9 prefetch, no effect */
4889 goto skip_move;
4890 case 0x30: /* V9 ldfa */
5b12f1e8 4891 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4892 goto jmp_insn;
4893 }
22e70060 4894 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
638737ad 4895 gen_update_fprs_dirty(rd);
81ad8ba2 4896 goto skip_move;
0f8a249a 4897 case 0x33: /* V9 lddfa */
5b12f1e8 4898 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4899 goto jmp_insn;
4900 }
22e70060 4901 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
638737ad 4902 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4903 goto skip_move;
0f8a249a
BS		 4904 case 0x3d: /* V9 prefetcha, no effect */
4905 goto skip_move;
4906 case 0x32: /* V9 ldqfa */
64a88d5d 4907 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 4908 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4909 goto jmp_insn;
4910 }
22e70060 4911 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
638737ad 4912 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4913 goto skip_move;
0f8a249a
BS		 4914#endif
4915 default:
4916 goto illegal_insn;
4917 }
97ea2859 4918 gen_store_gpr(dc, rd, cpu_val);
db166940 4919#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4920 skip_move: ;
3475187d 4921#endif
0f8a249a 4922 } else if (xop >= 0x20 && xop < 0x24) {
de9e9d9f
RH		 4923 TCGv t0;
4924
5b12f1e8 4925 if (gen_trap_ifnofpu(dc)) {
a80dde08 4926 goto jmp_insn;
5b12f1e8 4927 }
66442b07 4928 save_state(dc);
0f8a249a 4929 switch (xop) {
b89e94af 4930 case 0x20: /* ldf, load fpreg */
2cade6a3 4931 gen_address_mask(dc, cpu_addr);
de9e9d9f
RH		 4932 t0 = get_temp_tl(dc);
4933 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
ba5f5179 4934 cpu_dst_32 = gen_dest_fpr_F(dc);
de9e9d9f 4935 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
208ae657 4936 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4937 break;
3a3b925d
BS		 4938 case 0x21: /* ldfsr, V9 ldxfsr */
4939#ifdef TARGET_SPARC64
2cade6a3 4940 gen_address_mask(dc, cpu_addr);
3a3b925d 4941 if (rd == 1) {
abcc7191
RH		 4942 TCGv_i64 t64 = tcg_temp_new_i64();
4943 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4944 gen_helper_ldxfsr(cpu_env, t64);
4945 tcg_temp_free_i64(t64);
f8641947 4946 break;
fe987e23 4947 }
f8641947 4948#endif
de9e9d9f
RH		 4949 cpu_dst_32 = get_temp_i32(dc);
4950 t0 = get_temp_tl(dc);
4951 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4952 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4953 gen_helper_ldfsr(cpu_env, cpu_dst_32);
0f8a249a 4954 break;
b89e94af 4955 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4956 {
a7812ae4 4957 TCGv_i32 r_const;
2ea815ca
BS		 4958
4959 CHECK_FPU_FEATURE(dc, FLOAT128);
4960 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4961 gen_address_mask(dc, cpu_addr);
fe8d8f0f 4962 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
a7812ae4 4963 tcg_temp_free_i32(r_const);
2ea815ca 4964 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4965 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4966 }
1f587329 4967 break;
b89e94af 4968 case 0x23: /* lddf, load double fpreg */
03fb8cfc 4969 gen_address_mask(dc, cpu_addr);
3886b8a3 4970 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
03fb8cfc
RH		 4971 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4972 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4973 break;
4974 default:
4975 goto illegal_insn;
4976 }
dc1a6971 4977 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4978 xop == 0xe || xop == 0x1e) {
81634eea
RH		 4979 TCGv cpu_val = gen_load_gpr(dc, rd);
4980
0f8a249a 4981 switch (xop) {
b89e94af 4982 case 0x4: /* st, store word */
2cade6a3 4983 gen_address_mask(dc, cpu_addr);
6ae20372 4984 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4985 break;
b89e94af 4986 case 0x5: /* stb, store byte */
2cade6a3 4987 gen_address_mask(dc, cpu_addr);
6ae20372 4988 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4989 break;
b89e94af 4990 case 0x6: /* sth, store halfword */
2cade6a3 4991 gen_address_mask(dc, cpu_addr);
6ae20372 4992 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4993 break;
b89e94af 4994 case 0x7: /* std, store double word */
0f8a249a 4995 if (rd & 1)
d4218d99 4996 goto illegal_insn;
1a2fb1c0 4997 else {
a7812ae4 4998 TCGv_i32 r_const;
abcc7191 4999 TCGv_i64 t64;
81634eea 5000 TCGv lo;
1a2fb1c0 5001
66442b07 5002 save_state(dc);
2cade6a3 5003 gen_address_mask(dc, cpu_addr);
2ea815ca 5004 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 5005 /* XXX remove alignment check */
5006 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5007 tcg_temp_free_i32(r_const);
81634eea 5008 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5009
5010 t64 = tcg_temp_new_i64();
5011 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
5012 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
5013 tcg_temp_free_i64(t64);
7fa76c0b 5014 }
0f8a249a 5015 break;
3475187d 5016#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5017 case 0x14: /* sta, V9 stwa, store word alternate */
22e70060 5018 gen_st_asi(dc, cpu_val, cpu_addr, insn, 4);
d39c0b99 5019 break;
b89e94af 5020 case 0x15: /* stba, store byte alternate */
22e70060 5021 gen_st_asi(dc, cpu_val, cpu_addr, insn, 1);
d39c0b99 5022 break;
b89e94af 5023 case 0x16: /* stha, store halfword alternate */
22e70060 5024 gen_st_asi(dc, cpu_val, cpu_addr, insn, 2);
d39c0b99 5025 break;
b89e94af 5026 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5027 if (rd & 1) {
0f8a249a 5028 goto illegal_insn;
1a2fb1c0 5029 }
7ec1e5ea 5030 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5031 break;
e80cfcfc 5032#endif
3475187d 5033#ifdef TARGET_SPARC64
0f8a249a 5034 case 0x0e: /* V9 stx */
2cade6a3 5035 gen_address_mask(dc, cpu_addr);
6ae20372 5036 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5037 break;
5038 case 0x1e: /* V9 stxa */
22e70060 5039 gen_st_asi(dc, cpu_val, cpu_addr, insn, 8);
0f8a249a 5040 break;
3475187d 5041#endif
0f8a249a
BS		 5042 default:
5043 goto illegal_insn;
5044 }
5045 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5046 if (gen_trap_ifnofpu(dc)) {
a80dde08 5047 goto jmp_insn;
5b12f1e8 5048 }
66442b07 5049 save_state(dc);
0f8a249a 5050 switch (xop) {
b89e94af 5051 case 0x24: /* stf, store fpreg */
de9e9d9f
RH		 5052 {
5053 TCGv t = get_temp_tl(dc);
5054 gen_address_mask(dc, cpu_addr);
5055 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5056 tcg_gen_ext_i32_tl(t, cpu_src1_32);
5057 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5058 }
0f8a249a
BS		 5059 break;
5060 case 0x25: /* stfsr, V9 stxfsr */
f8641947
RH		 5061 {
5062 TCGv t = get_temp_tl(dc);
5063
5064 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
3a3b925d 5065#ifdef TARGET_SPARC64
f8641947
RH		 5066 gen_address_mask(dc, cpu_addr);
5067 if (rd == 1) {
5068 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5069 break;
5070 }
3a3b925d 5071#endif
f8641947
RH		 5072 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5073 }
0f8a249a 5074 break;
1f587329
BS		 5075 case 0x26:
5076#ifdef TARGET_SPARC64
1f587329 5077 /* V9 stqf, store quad fpreg */
2ea815ca 5078 {
a7812ae4 5079 TCGv_i32 r_const;
2ea815ca
BS		 5080
5081 CHECK_FPU_FEATURE(dc, FLOAT128);
5082 gen_op_load_fpr_QT0(QFPREG(rd));
5083 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5084 gen_address_mask(dc, cpu_addr);
fe8d8f0f 5085 gen_helper_stqf(cpu_env, cpu_addr, r_const);
a7812ae4 5086 tcg_temp_free_i32(r_const);
2ea815ca 5087 }
1f587329 5088 break;
1f587329
BS		 5089#else /* !TARGET_SPARC64 */
5090 /* stdfq, store floating point queue */
5091#if defined(CONFIG_USER_ONLY)
5092 goto illegal_insn;
5093#else
0f8a249a
BS		 5094 if (!supervisor(dc))
5095 goto priv_insn;
5b12f1e8 5096 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5097 goto jmp_insn;
5b12f1e8 5098 }
0f8a249a 5099 goto nfq_insn;
1f587329 5100#endif
0f8a249a 5101#endif
b89e94af 5102 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5103 gen_address_mask(dc, cpu_addr);
5104 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5105 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5106 break;
5107 default:
5108 goto illegal_insn;
5109 }
5110 } else if (xop > 0x33 && xop < 0x3f) {
66442b07 5111 save_state(dc);
0f8a249a 5112 switch (xop) {
a4d17f19 5113#ifdef TARGET_SPARC64
0f8a249a 5114 case 0x34: /* V9 stfa */
5b12f1e8 5115 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5116 goto jmp_insn;
5117 }
22e70060 5118 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5119 break;
1f587329 5120 case 0x36: /* V9 stqfa */
2ea815ca 5121 {
a7812ae4 5122 TCGv_i32 r_const;
2ea815ca
BS		 5123
5124 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5125 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5126 goto jmp_insn;
5127 }
2ea815ca 5128 r_const = tcg_const_i32(7);
fe8d8f0f 5129 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5130 tcg_temp_free_i32(r_const);
22e70060 5131 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5132 }
1f587329 5133 break;
0f8a249a 5134 case 0x37: /* V9 stdfa */
5b12f1e8 5135 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5136 goto jmp_insn;
5137 }
22e70060 5138 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5139 break;
0f8a249a 5140 case 0x3e: /* V9 casxa */
a4273524
RH		 5141 rs2 = GET_FIELD(insn, 27, 31);
5142 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5143 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5144 break;
a4d17f19 5145#else
0f8a249a
BS		 5146 case 0x34: /* stc */
5147 case 0x35: /* stcsr */
5148 case 0x36: /* stdcq */
5149 case 0x37: /* stdc */
5150 goto ncp_insn;
16c358e9
SH		 5151#endif
5152#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5153 case 0x3c: /* V9 or LEON3 casa */
5154#ifndef TARGET_SPARC64
5155 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5156#endif
5157 rs2 = GET_FIELD(insn, 27, 31);
5158 cpu_src2 = gen_load_gpr(dc, rs2);
5159 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5160 break;
0f8a249a
BS		 5161#endif
5162 default:
5163 goto illegal_insn;
5164 }
a4273524 5165 } else {
0f8a249a 5166 goto illegal_insn;
a4273524 5167 }
0f8a249a
BS		 5168 }
5169 break;
cf495bcf
FB		 5170 }
5171 /* default case for non jump instructions */
72cbca10 5172 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5173 dc->pc = DYNAMIC_PC;
5174 gen_op_next_insn();
72cbca10
FB		 5175 } else if (dc->npc == JUMP_PC) {
5176 /* we can do a static jump */
6ae20372 5177 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5178 dc->is_br = 1;
5179 } else {
0f8a249a
BS		 5180 dc->pc = dc->npc;
5181 dc->npc = dc->npc + 4;
cf495bcf 5182 }
e80cfcfc 5183 jmp_insn:
42a8aa83 5184 goto egress;
cf495bcf 5185 illegal_insn:
4fbe0067 5186 gen_exception(dc, TT_ILL_INSN);
42a8aa83 5187 goto egress;
64a88d5d 5188 unimp_flush:
4fbe0067 5189 gen_exception(dc, TT_UNIMP_FLUSH);
42a8aa83 5190 goto egress;
e80cfcfc 5191#if !defined(CONFIG_USER_ONLY)
e8af50a3 5192 priv_insn:
4fbe0067 5193 gen_exception(dc, TT_PRIV_INSN);
42a8aa83 5194 goto egress;
64a88d5d 5195#endif
e80cfcfc 5196 nfpu_insn:
4fbe0067 5197 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
42a8aa83 5198 goto egress;
64a88d5d 5199#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5200 nfq_insn:
4fbe0067 5201 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
42a8aa83 5202 goto egress;
9143e598 5203#endif
fcc72045
BS		 5204#ifndef TARGET_SPARC64
5205 ncp_insn:
4fbe0067 5206 gen_exception(dc, TT_NCP_INSN);
42a8aa83 5207 goto egress;
fcc72045 5208#endif
42a8aa83 5209 egress:
30038fd8
RH		 5210 if (dc->n_t32 != 0) {
5211 int i;
5212 for (i = dc->n_t32 - 1; i >= 0; --i) {
5213 tcg_temp_free_i32(dc->t32[i]);
5214 }
5215 dc->n_t32 = 0;
5216 }
88023616
RH		 5217 if (dc->n_ttl != 0) {
5218 int i;
5219 for (i = dc->n_ttl - 1; i >= 0; --i) {
5220 tcg_temp_free(dc->ttl[i]);
5221 }
5222 dc->n_ttl = 0;
5223 }
7a3f1944
FB		 5224}
5225
4e5e1215 5226void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5227{
4e5e1215 5228 SPARCCPU *cpu = sparc_env_get_cpu(env);
ed2803da 5229 CPUState *cs = CPU(cpu);
72cbca10 5230 target_ulong pc_start, last_pc;
cf495bcf 5231 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5232 int num_insns;
5233 int max_insns;
0184e266 5234 unsigned int insn;
cf495bcf
FB		 5235
5236 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5237 dc->tb = tb;
72cbca10 5238 pc_start = tb->pc;
cf495bcf 5239 dc->pc = pc_start;
e80cfcfc 5240 last_pc = dc->pc;
72cbca10 5241 dc->npc = (target_ulong) tb->cs_base;
8393617c 5242 dc->cc_op = CC_OP_DYNAMIC;
99a23063 5243 dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
5578ceab 5244 dc->def = env->def;
f838e2c5
BS		 5245 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5246 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5247 dc->singlestep = (cs->singlestep_enabled || singlestep);
a6d567e5
RH		 5248#ifdef TARGET_SPARC64
5249 dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
5250#endif
cf495bcf 5251
2e70f6ef
PB		 5252 num_insns = 0;
5253 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5254 if (max_insns == 0) {
2e70f6ef 5255 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5256 }
5257 if (max_insns > TCG_MAX_INSNS) {
5258 max_insns = TCG_MAX_INSNS;
5259 }
5260
cd42d5b2 5261 gen_tb_start(tb);
cf495bcf 5262 do {
a3d5ad76
RH		 5263 if (dc->npc & JUMP_PC) {
5264 assert(dc->jump_pc[1] == dc->pc + 4);
5265 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5266 } else {
5267 tcg_gen_insn_start(dc->pc, dc->npc);
5268 }
959082fc 5269 num_insns++;
522a0d4e 5270 last_pc = dc->pc;
667b8e29 5271
b933066a
RH		 5272 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5273 if (dc->pc != pc_start) {
5274 save_state(dc);
5275 }
5276 gen_helper_debug(cpu_env);
5277 tcg_gen_exit_tb(0);
5278 dc->is_br = 1;
5279 goto exit_gen_loop;
5280 }
5281
959082fc 5282 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5283 gen_io_start();
667b8e29
RH		 5284 }
5285
0184e266 5286 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5287
0184e266 5288 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5289
5290 if (dc->is_br)
5291 break;
5292 /* if the next PC is different, we abort now */
5293 if (dc->pc != (last_pc + 4))
5294 break;
d39c0b99
FB		 5295 /* if we reach a page boundary, we stop generation so that the
5296 PC of a TT_TFAULT exception is always in the right page */
5297 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5298 break;
e80cfcfc
FB		 5299 /* if single step mode, we generate only one instruction and
5300 generate an exception */
060718c1 5301 if (dc->singlestep) {
e80cfcfc
FB		 5302 break;
5303 }
fe700adb 5304 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5305 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5306 num_insns < max_insns);
e80cfcfc
FB		 5307
5308 exit_gen_loop:
b09b2fd3 5309 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5310 gen_io_end();
b09b2fd3 5311 }
72cbca10 5312 if (!dc->is_br) {
5fafdf24 5313 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5314 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5315 /* static PC and NPC: we can use direct chaining */
2f5680ee 5316 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5317 } else {
b09b2fd3 5318 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5319 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5320 }
934da7ee 5321 save_npc(dc);
57fec1fe 5322 tcg_gen_exit_tb(0);
72cbca10
FB		 5323 }
5324 }
806f352d 5325 gen_tb_end(tb, num_insns);
0a7df5da 5326
4e5e1215
RH		 5327 tb->size = last_pc + 4 - pc_start;
5328 tb->icount = num_insns;
5329
7a3f1944 5330#ifdef DEBUG_DISAS
4910e6e4
RH		 5331 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5332 && qemu_log_in_addr_range(pc_start)) {
93fcfe39
AL		 5333 qemu_log("--------------\n");
5334 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5335 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5336 qemu_log("\n");
cf495bcf 5337 }
7a3f1944 5338#endif
7a3f1944
FB		 5339}
5340
c48fcb47 5341void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5342{
c48fcb47 5343 static int inited;
d2dc4069 5344 static const char gregnames[32][4] = {
0ea63844 5345 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5346 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5347 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5348 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5349 };
0ea63844 5350 static const char fregnames[32][4] = {
30038fd8
RH		 5351 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5352 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5353 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5354 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5355 };
aaed909a 5356
0ea63844 5357 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5358#ifdef TARGET_SPARC64
0ea63844 5359 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5360 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
255e1fcb 5361#else
0ea63844
RH		 5362 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5363#endif
5364 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5365 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5366 };
5367
5368 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5369#ifdef TARGET_SPARC64
5370 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5371 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5372 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5373 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5374 "hstick_cmpr" },
5375 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5376 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5377 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5378 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5379 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5380#endif
0ea63844
RH		 5381 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5382 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5383 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5384 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5385 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5386 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5387 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5388 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 5389#ifndef CONFIG_USER_ONLY
0ea63844 5390 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 5391#endif
0ea63844
RH		 5392 };
5393
5394 unsigned int i;
5395
5396 /* init various static tables */
5397 if (inited) {
5398 return;
5399 }
5400 inited = 1;
5401
5402 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 5403 tcg_ctx.tcg_env = cpu_env;
0ea63844
RH		 5404
5405 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5406 offsetof(CPUSPARCState, regwptr),
5407 "regwptr");
5408
5409 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5410 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5411 }
5412
5413 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5414 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5415 }
5416
d2dc4069 5417 TCGV_UNUSED(cpu_regs[0]);
0ea63844 5418 for (i = 1; i < 8; ++i) {
d2dc4069
RH		 5419 cpu_regs[i] = tcg_global_mem_new(cpu_env,
5420 offsetof(CPUSPARCState, gregs[i]),
5421 gregnames[i]);
5422 }
5423
5424 for (i = 8; i < 32; ++i) {
5425 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5426 (i - 8) * sizeof(target_ulong),
5427 gregnames[i]);
0ea63844
RH		 5428 }
5429
5430 for (i = 0; i < TARGET_DPREGS; i++) {
5431 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5432 offsetof(CPUSPARCState, fpr[i]),
5433 fregnames[i]);
1a2fb1c0 5434 }
658138bc 5435}
d2856f1a 5436
bad729e2
RH		 5437void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5438 target_ulong *data)
d2856f1a 5439{
bad729e2
RH		 5440 target_ulong pc = data[0];
5441 target_ulong npc = data[1];
5442
5443 env->pc = pc;
6c42444f 5444 if (npc == DYNAMIC_PC) {
d2856f1a 5445 /* dynamic NPC: already stored */
6c42444f 5446 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5447 /* jump PC: use 'cond' and the jump targets of the translation */
5448 if (env->cond) {
6c42444f 5449 env->npc = npc & ~3;
d7da2a10 5450 } else {
6c42444f 5451 env->npc = pc + 4;
d7da2a10 5452 }
d2856f1a
AJ		 5453 } else {
5454 env->npc = npc;
5455 }
5456}
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