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target-sparc: Tidy global register initialization
[qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <[email protected]>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
57fec1fe 26#include "tcg-op.h"
f08b6170 27#include "exec/cpu_ldst.h"
7a3f1944 28
2ef6175a 29#include "exec/helper-gen.h"
a7812ae4 30
a7e30d84 31#include "trace-tcg.h"
508127e2 32#include "exec/log.h"
a7e30d84
LV		 33
34
7a3f1944
FB		 35#define DEBUG_DISAS
36
72cbca10
FB		 37#define DYNAMIC_PC 1 /* dynamic pc value */
38#define JUMP_PC 2 /* dynamic pc value which takes only two values
39 according to jump_pc[T2] */
40
1a2fb1c0 41/* global register indexes */
a7812ae4 42static TCGv_ptr cpu_env, cpu_regwptr;
25517f99
PB		 43static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
44static TCGv_i32 cpu_cc_op;
a7812ae4
PB		 45static TCGv_i32 cpu_psr;
46static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
255e1fcb
BS		 47static TCGv cpu_y;
48#ifndef CONFIG_USER_ONLY
49static TCGv cpu_tbr;
50#endif
5793f2a4 51static TCGv cpu_cond;
dc99a3f2 52#ifdef TARGET_SPARC64
a7812ae4
PB		 53static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
54static TCGv cpu_gsr;
255e1fcb 55static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4
PB		 56static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
57static TCGv_i32 cpu_softint;
255e1fcb
BS		 58#else
59static TCGv cpu_wim;
dc99a3f2 60#endif
714547bb 61/* Floating point registers */
30038fd8 62static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 63
022c62cb 64#include "exec/gen-icount.h"
2e70f6ef 65
7a3f1944 66typedef struct DisasContext {
0f8a249a
BS		 67 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
68 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 69 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 70 int is_br;
e8af50a3 71 int mem_idx;
a80dde08 72 int fpu_enabled;
2cade6a3 73 int address_mask_32bit;
060718c1 74 int singlestep;
8393617c 75 uint32_t cc_op; /* current CC operation */
cf495bcf 76 struct TranslationBlock *tb;
5578ceab 77 sparc_def_t *def;
30038fd8 78 TCGv_i32 t32[3];
88023616 79 TCGv ttl[5];
30038fd8 80 int n_t32;
88023616 81 int n_ttl;
7a3f1944
FB		 82} DisasContext;
83
416fcaea
RH		 84typedef struct {
85 TCGCond cond;
86 bool is_bool;
87 bool g1, g2;
88 TCGv c1, c2;
89} DisasCompare;
90
3475187d 91// This function uses non-native bit order
dc1a6971
BS		 92#define GET_FIELD(X, FROM, TO) \
93 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 94
3475187d 95// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 96#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 97 GET_FIELD(X, 31 - (TO), 31 - (FROM))
98
99#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 100#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 101
102#ifdef TARGET_SPARC64
0387d928 103#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 104#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 105#else
c185970a 106#define DFPREG(r) (r & 0x1e)
1f587329 107#define QFPREG(r) (r & 0x1c)
3475187d
FB		 108#endif
109
b158a785
BS		 110#define UA2005_HTRAP_MASK 0xff
111#define V8_TRAP_MASK 0x7f
112
3475187d
FB		 113static int sign_extend(int x, int len)
114{
115 len = 32 - len;
116 return (x << len) >> len;
117}
118
7a3f1944
FB		 119#define IS_IMM (insn & (1<<13))
120
2ae23e17
RH		 121static inline TCGv_i32 get_temp_i32(DisasContext *dc)
122{
123 TCGv_i32 t;
124 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
125 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
126 return t;
127}
128
129static inline TCGv get_temp_tl(DisasContext *dc)
130{
131 TCGv t;
132 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
133 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
134 return t;
135}
136
141ae5c1
RH		 137static inline void gen_update_fprs_dirty(int rd)
138{
139#if defined(TARGET_SPARC64)
140 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
141#endif
142}
143
ff07ec83 144/* floating point registers moves */
208ae657
RH		 145static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
146{
30038fd8
RH		 147#if TCG_TARGET_REG_BITS == 32
148 if (src & 1) {
149 return TCGV_LOW(cpu_fpr[src / 2]);
150 } else {
151 return TCGV_HIGH(cpu_fpr[src / 2]);
152 }
153#else
154 if (src & 1) {
155 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
156 } else {
2ae23e17 157 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 158 TCGv_i64 t = tcg_temp_new_i64();
159
160 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 161 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 162 tcg_temp_free_i64(t);
163
30038fd8
RH		 164 return ret;
165 }
166#endif
208ae657
RH		 167}
168
169static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
170{
30038fd8
RH		 171#if TCG_TARGET_REG_BITS == 32
172 if (dst & 1) {
173 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
174 } else {
175 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
176 }
177#else
178 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
179 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
180 (dst & 1 ? 0 : 32), 32);
181#endif
141ae5c1 182 gen_update_fprs_dirty(dst);
208ae657
RH		 183}
184
ba5f5179 185static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 186{
ba5f5179 187 return get_temp_i32(dc);
208ae657
RH		 188}
189
96eda024
RH		 190static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
191{
96eda024 192 src = DFPREG(src);
30038fd8 193 return cpu_fpr[src / 2];
96eda024
RH		 194}
195
196static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
197{
198 dst = DFPREG(dst);
30038fd8 199 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
96eda024
RH		 200 gen_update_fprs_dirty(dst);
201}
202
3886b8a3 203static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 204{
3886b8a3 205 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 206}
207
ff07ec83
BS		 208static void gen_op_load_fpr_QT0(unsigned int src)
209{
30038fd8
RH		 210 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
211 offsetof(CPU_QuadU, ll.upper));
212 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
213 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 214}
215
216static void gen_op_load_fpr_QT1(unsigned int src)
217{
30038fd8
RH		 218 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
219 offsetof(CPU_QuadU, ll.upper));
220 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
221 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 222}
223
224static void gen_op_store_QT0_fpr(unsigned int dst)
225{
30038fd8
RH		 226 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
227 offsetof(CPU_QuadU, ll.upper));
228 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
229 offsetof(CPU_QuadU, ll.lower));
ff07ec83 230}
1f587329 231
ac11f776 232#ifdef TARGET_SPARC64
30038fd8 233static void gen_move_Q(unsigned int rd, unsigned int rs)
ac11f776
RH		 234{
235 rd = QFPREG(rd);
236 rs = QFPREG(rs);
237
30038fd8
RH		 238 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
239 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
ac11f776
RH		 240 gen_update_fprs_dirty(rd);
241}
242#endif
243
81ad8ba2
BS		 244/* moves */
245#ifdef CONFIG_USER_ONLY
3475187d 246#define supervisor(dc) 0
81ad8ba2 247#ifdef TARGET_SPARC64
e9ebed4d 248#define hypervisor(dc) 0
81ad8ba2 249#endif
3475187d 250#else
2aae2b8e 251#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
81ad8ba2 252#ifdef TARGET_SPARC64
2aae2b8e 253#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
6f27aba6 254#else
3475187d 255#endif
81ad8ba2
BS		 256#endif
257
2cade6a3
BS		 258#ifdef TARGET_SPARC64
259#ifndef TARGET_ABI32
260#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 261#else
2cade6a3
BS		 262#define AM_CHECK(dc) (1)
263#endif
1a2fb1c0 264#endif
3391c818 265
2cade6a3
BS		 266static inline void gen_address_mask(DisasContext *dc, TCGv addr)
267{
268#ifdef TARGET_SPARC64
269 if (AM_CHECK(dc))
270 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
271#endif
272}
273
88023616
RH		 274static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
275{
276 if (reg == 0 || reg >= 8) {
277 TCGv t = get_temp_tl(dc);
278 if (reg == 0) {
279 tcg_gen_movi_tl(t, 0);
280 } else {
281 tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
282 }
283 return t;
284 } else {
285 return cpu_gregs[reg];
286 }
287}
288
289static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
290{
291 if (reg > 0) {
292 if (reg < 8) {
293 tcg_gen_mov_tl(cpu_gregs[reg], v);
294 } else {
295 tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
296 }
297 }
298}
299
300static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
301{
302 if (reg == 0 || reg >= 8) {
303 return get_temp_tl(dc);
304 } else {
305 return cpu_gregs[reg];
306 }
307}
308
5fafdf24 309static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 310 target_ulong pc, target_ulong npc)
311{
312 TranslationBlock *tb;
313
314 tb = s->tb;
315 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
060718c1
RH		 316 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
317 !s->singlestep) {
6e256c93 318 /* jump to same page: we can use a direct jump */
57fec1fe 319 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 320 tcg_gen_movi_tl(cpu_pc, pc);
321 tcg_gen_movi_tl(cpu_npc, npc);
8cfd0495 322 tcg_gen_exit_tb((uintptr_t)tb + tb_num);
6e256c93
FB		 323 } else {
324 /* jump to another page: currently not optimized */
2f5680ee
BS		 325 tcg_gen_movi_tl(cpu_pc, pc);
326 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 327 tcg_gen_exit_tb(0);
6e256c93
FB		 328 }
329}
330
19f329ad 331// XXX suboptimal
a7812ae4 332static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 333{
8911f501 334 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 335 tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
19f329ad
BS		 336 tcg_gen_andi_tl(reg, reg, 0x1);
337}
338
a7812ae4 339static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 340{
8911f501 341 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 342 tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
19f329ad
BS		 343 tcg_gen_andi_tl(reg, reg, 0x1);
344}
345
a7812ae4 346static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 347{
8911f501 348 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 349 tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
19f329ad
BS		 350 tcg_gen_andi_tl(reg, reg, 0x1);
351}
352
a7812ae4 353static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 354{
8911f501 355 tcg_gen_extu_i32_tl(reg, src);
4b8b8b76 356 tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
19f329ad
BS		 357 tcg_gen_andi_tl(reg, reg, 0x1);
358}
359
4af984a7 360static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 361{
4af984a7 362 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 363 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 364 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 365 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 366}
367
70c48285 368static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 369{
70c48285
RH		 370 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
371
372 /* Carry is computed from a previous add: (dst < src) */
373#if TARGET_LONG_BITS == 64
374 cc_src1_32 = tcg_temp_new_i32();
375 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 376 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
377 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 378#else
379 cc_src1_32 = cpu_cc_dst;
380 cc_src2_32 = cpu_cc_src;
381#endif
382
383 carry_32 = tcg_temp_new_i32();
384 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
385
386#if TARGET_LONG_BITS == 64
387 tcg_temp_free_i32(cc_src1_32);
388 tcg_temp_free_i32(cc_src2_32);
389#endif
390
391 return carry_32;
41d72852
BS		 392}
393
70c48285 394static TCGv_i32 gen_sub32_carry32(void)
41d72852 395{
70c48285
RH		 396 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
397
398 /* Carry is computed from a previous borrow: (src1 < src2) */
399#if TARGET_LONG_BITS == 64
400 cc_src1_32 = tcg_temp_new_i32();
401 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 402 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
403 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 404#else
405 cc_src1_32 = cpu_cc_src;
406 cc_src2_32 = cpu_cc_src2;
407#endif
408
409 carry_32 = tcg_temp_new_i32();
410 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
411
412#if TARGET_LONG_BITS == 64
413 tcg_temp_free_i32(cc_src1_32);
414 tcg_temp_free_i32(cc_src2_32);
415#endif
416
417 return carry_32;
418}
419
420static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
421 TCGv src2, int update_cc)
422{
423 TCGv_i32 carry_32;
424 TCGv carry;
425
426 switch (dc->cc_op) {
427 case CC_OP_DIV:
428 case CC_OP_LOGIC:
429 /* Carry is known to be zero. Fall back to plain ADD. */
430 if (update_cc) {
431 gen_op_add_cc(dst, src1, src2);
432 } else {
433 tcg_gen_add_tl(dst, src1, src2);
434 }
435 return;
436
437 case CC_OP_ADD:
438 case CC_OP_TADD:
439 case CC_OP_TADDTV:
15fe216f
RH		 440 if (TARGET_LONG_BITS == 32) {
441 /* We can re-use the host's hardware carry generation by using
442 an ADD2 opcode. We discard the low part of the output.
443 Ideally we'd combine this operation with the add that
444 generated the carry in the first place. */
445 carry = tcg_temp_new();
446 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
447 tcg_temp_free(carry);
70c48285
RH		 448 goto add_done;
449 }
70c48285
RH		 450 carry_32 = gen_add32_carry32();
451 break;
452
453 case CC_OP_SUB:
454 case CC_OP_TSUB:
455 case CC_OP_TSUBTV:
456 carry_32 = gen_sub32_carry32();
457 break;
458
459 default:
460 /* We need external help to produce the carry. */
461 carry_32 = tcg_temp_new_i32();
2ffd9176 462 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 463 break;
464 }
465
466#if TARGET_LONG_BITS == 64
467 carry = tcg_temp_new();
468 tcg_gen_extu_i32_i64(carry, carry_32);
469#else
470 carry = carry_32;
471#endif
472
473 tcg_gen_add_tl(dst, src1, src2);
474 tcg_gen_add_tl(dst, dst, carry);
475
476 tcg_temp_free_i32(carry_32);
477#if TARGET_LONG_BITS == 64
478 tcg_temp_free(carry);
479#endif
480
70c48285 481 add_done:
70c48285
RH		 482 if (update_cc) {
483 tcg_gen_mov_tl(cpu_cc_src, src1);
484 tcg_gen_mov_tl(cpu_cc_src2, src2);
485 tcg_gen_mov_tl(cpu_cc_dst, dst);
486 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
487 dc->cc_op = CC_OP_ADDX;
488 }
dc99a3f2
BS		 489}
490
41d72852 491static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 492{
4af984a7 493 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 494 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 495 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 496 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 497}
498
70c48285
RH		 499static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
500 TCGv src2, int update_cc)
41d72852 501{
70c48285
RH		 502 TCGv_i32 carry_32;
503 TCGv carry;
41d72852 504
70c48285
RH		 505 switch (dc->cc_op) {
506 case CC_OP_DIV:
507 case CC_OP_LOGIC:
508 /* Carry is known to be zero. Fall back to plain SUB. */
509 if (update_cc) {
510 gen_op_sub_cc(dst, src1, src2);
511 } else {
512 tcg_gen_sub_tl(dst, src1, src2);
513 }
514 return;
515
516 case CC_OP_ADD:
517 case CC_OP_TADD:
518 case CC_OP_TADDTV:
519 carry_32 = gen_add32_carry32();
520 break;
521
522 case CC_OP_SUB:
523 case CC_OP_TSUB:
524 case CC_OP_TSUBTV:
15fe216f
RH		 525 if (TARGET_LONG_BITS == 32) {
526 /* We can re-use the host's hardware carry generation by using
527 a SUB2 opcode. We discard the low part of the output.
528 Ideally we'd combine this operation with the add that
529 generated the carry in the first place. */
530 carry = tcg_temp_new();
531 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
532 tcg_temp_free(carry);
70c48285
RH		 533 goto sub_done;
534 }
70c48285
RH		 535 carry_32 = gen_sub32_carry32();
536 break;
537
538 default:
539 /* We need external help to produce the carry. */
540 carry_32 = tcg_temp_new_i32();
2ffd9176 541 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 542 break;
543 }
544
545#if TARGET_LONG_BITS == 64
546 carry = tcg_temp_new();
547 tcg_gen_extu_i32_i64(carry, carry_32);
548#else
549 carry = carry_32;
550#endif
551
552 tcg_gen_sub_tl(dst, src1, src2);
553 tcg_gen_sub_tl(dst, dst, carry);
554
555 tcg_temp_free_i32(carry_32);
556#if TARGET_LONG_BITS == 64
557 tcg_temp_free(carry);
558#endif
559
70c48285 560 sub_done:
70c48285
RH		 561 if (update_cc) {
562 tcg_gen_mov_tl(cpu_cc_src, src1);
563 tcg_gen_mov_tl(cpu_cc_src2, src2);
564 tcg_gen_mov_tl(cpu_cc_dst, dst);
565 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
566 dc->cc_op = CC_OP_SUBX;
567 }
dc99a3f2
BS		 568}
569
4af984a7 570static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 571{
de9e9d9f 572 TCGv r_temp, zero, t0;
d9bdab86 573
a7812ae4 574 r_temp = tcg_temp_new();
de9e9d9f 575 t0 = tcg_temp_new();
d9bdab86
BS		 576
577 /* old op:
578 if (!(env->y & 1))
579 T1 = 0;
580 */
6cb675b0 581 zero = tcg_const_tl(0);
72ccba79 582 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 583 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 584 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 585 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
586 zero, cpu_cc_src2);
587 tcg_temp_free(zero);
d9bdab86
BS		 588
589 // b2 = T0 & 1;
590 // env->y = (b2 << 31) | (env->y >> 1);
105a1f04
BS		 591 tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
592 tcg_gen_shli_tl(r_temp, r_temp, 31);
de9e9d9f
RH		 593 tcg_gen_shri_tl(t0, cpu_y, 1);
594 tcg_gen_andi_tl(t0, t0, 0x7fffffff);
595 tcg_gen_or_tl(t0, t0, r_temp);
596 tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
d9bdab86
BS		 597
598 // b1 = N ^ V;
de9e9d9f 599 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 600 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 601 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 602 tcg_temp_free(r_temp);
d9bdab86
BS		 603
604 // T0 = (b1 << 31) | (T0 >> 1);
605 // src1 = T0;
de9e9d9f 606 tcg_gen_shli_tl(t0, t0, 31);
6f551262 607 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 608 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
609 tcg_temp_free(t0);
d9bdab86 610
5c6a0628 611 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 612
5c6a0628 613 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 614}
615
fb170183 616static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 617{
528692a8 618#if TARGET_LONG_BITS == 32
fb170183 619 if (sign_ext) {
528692a8 620 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 621 } else {
528692a8 622 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 623 }
528692a8
RH		 624#else
625 TCGv t0 = tcg_temp_new_i64();
626 TCGv t1 = tcg_temp_new_i64();
fb170183 627
528692a8
RH		 628 if (sign_ext) {
629 tcg_gen_ext32s_i64(t0, src1);
630 tcg_gen_ext32s_i64(t1, src2);
631 } else {
632 tcg_gen_ext32u_i64(t0, src1);
633 tcg_gen_ext32u_i64(t1, src2);
634 }
fb170183 635
528692a8
RH		 636 tcg_gen_mul_i64(dst, t0, t1);
637 tcg_temp_free(t0);
638 tcg_temp_free(t1);
fb170183 639
528692a8
RH		 640 tcg_gen_shri_i64(cpu_y, dst, 32);
641#endif
8879d139
BS		 642}
643
fb170183 644static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 645{
fb170183
IK		 646 /* zero-extend truncated operands before multiplication */
647 gen_op_multiply(dst, src1, src2, 0);
648}
8879d139 649
fb170183
IK		 650static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
651{
652 /* sign-extend truncated operands before multiplication */
653 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 654}
655
19f329ad
BS		 656// 1
657static inline void gen_op_eval_ba(TCGv dst)
658{
659 tcg_gen_movi_tl(dst, 1);
660}
661
662// Z
a7812ae4 663static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 664{
665 gen_mov_reg_Z(dst, src);
666}
667
668// Z | (N ^ V)
a7812ae4 669static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 670{
de9e9d9f
RH		 671 TCGv t0 = tcg_temp_new();
672 gen_mov_reg_N(t0, src);
19f329ad 673 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 674 tcg_gen_xor_tl(dst, dst, t0);
675 gen_mov_reg_Z(t0, src);
676 tcg_gen_or_tl(dst, dst, t0);
677 tcg_temp_free(t0);
19f329ad
BS		 678}
679
680// N ^ V
a7812ae4 681static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 682{
de9e9d9f
RH		 683 TCGv t0 = tcg_temp_new();
684 gen_mov_reg_V(t0, src);
19f329ad 685 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 686 tcg_gen_xor_tl(dst, dst, t0);
687 tcg_temp_free(t0);
19f329ad
BS		 688}
689
690// C | Z
a7812ae4 691static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 692{
de9e9d9f
RH		 693 TCGv t0 = tcg_temp_new();
694 gen_mov_reg_Z(t0, src);
19f329ad 695 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 696 tcg_gen_or_tl(dst, dst, t0);
697 tcg_temp_free(t0);
19f329ad
BS		 698}
699
700// C
a7812ae4 701static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 702{
703 gen_mov_reg_C(dst, src);
704}
705
706// V
a7812ae4 707static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 708{
709 gen_mov_reg_V(dst, src);
710}
711
712// 0
713static inline void gen_op_eval_bn(TCGv dst)
714{
715 tcg_gen_movi_tl(dst, 0);
716}
717
718// N
a7812ae4 719static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 720{
721 gen_mov_reg_N(dst, src);
722}
723
724// !Z
a7812ae4 725static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 726{
727 gen_mov_reg_Z(dst, src);
728 tcg_gen_xori_tl(dst, dst, 0x1);
729}
730
731// !(Z | (N ^ V))
a7812ae4 732static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 733{
de9e9d9f 734 gen_op_eval_ble(dst, src);
19f329ad
BS		 735 tcg_gen_xori_tl(dst, dst, 0x1);
736}
737
738// !(N ^ V)
a7812ae4 739static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 740{
de9e9d9f 741 gen_op_eval_bl(dst, src);
19f329ad
BS		 742 tcg_gen_xori_tl(dst, dst, 0x1);
743}
744
745// !(C | Z)
a7812ae4 746static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 747{
de9e9d9f 748 gen_op_eval_bleu(dst, src);
19f329ad
BS		 749 tcg_gen_xori_tl(dst, dst, 0x1);
750}
751
752// !C
a7812ae4 753static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 754{
755 gen_mov_reg_C(dst, src);
756 tcg_gen_xori_tl(dst, dst, 0x1);
757}
758
759// !N
a7812ae4 760static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 761{
762 gen_mov_reg_N(dst, src);
763 tcg_gen_xori_tl(dst, dst, 0x1);
764}
765
766// !V
a7812ae4 767static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 768{
769 gen_mov_reg_V(dst, src);
770 tcg_gen_xori_tl(dst, dst, 0x1);
771}
772
773/*
774 FPSR bit field FCC1 | FCC0:
775 0 =
776 1 <
777 2 >
778 3 unordered
779*/
780static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
781 unsigned int fcc_offset)
782{
ba6a9d8c 783 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 784 tcg_gen_andi_tl(reg, reg, 0x1);
785}
786
787static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
788 unsigned int fcc_offset)
789{
ba6a9d8c 790 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 791 tcg_gen_andi_tl(reg, reg, 0x1);
792}
793
794// !0: FCC0 | FCC1
795static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
796 unsigned int fcc_offset)
797{
de9e9d9f 798 TCGv t0 = tcg_temp_new();
19f329ad 799 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 800 gen_mov_reg_FCC1(t0, src, fcc_offset);
801 tcg_gen_or_tl(dst, dst, t0);
802 tcg_temp_free(t0);
19f329ad
BS		 803}
804
805// 1 or 2: FCC0 ^ FCC1
806static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
807 unsigned int fcc_offset)
808{
de9e9d9f 809 TCGv t0 = tcg_temp_new();
19f329ad 810 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 811 gen_mov_reg_FCC1(t0, src, fcc_offset);
812 tcg_gen_xor_tl(dst, dst, t0);
813 tcg_temp_free(t0);
19f329ad
BS		 814}
815
816// 1 or 3: FCC0
817static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
818 unsigned int fcc_offset)
819{
820 gen_mov_reg_FCC0(dst, src, fcc_offset);
821}
822
823// 1: FCC0 & !FCC1
824static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
825 unsigned int fcc_offset)
826{
de9e9d9f 827 TCGv t0 = tcg_temp_new();
19f329ad 828 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 829 gen_mov_reg_FCC1(t0, src, fcc_offset);
830 tcg_gen_andc_tl(dst, dst, t0);
831 tcg_temp_free(t0);
19f329ad
BS		 832}
833
834// 2 or 3: FCC1
835static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
836 unsigned int fcc_offset)
837{
838 gen_mov_reg_FCC1(dst, src, fcc_offset);
839}
840
841// 2: !FCC0 & FCC1
842static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
843 unsigned int fcc_offset)
844{
de9e9d9f 845 TCGv t0 = tcg_temp_new();
19f329ad 846 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 847 gen_mov_reg_FCC1(t0, src, fcc_offset);
848 tcg_gen_andc_tl(dst, t0, dst);
849 tcg_temp_free(t0);
19f329ad
BS		 850}
851
852// 3: FCC0 & FCC1
853static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
854 unsigned int fcc_offset)
855{
de9e9d9f 856 TCGv t0 = tcg_temp_new();
19f329ad 857 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 858 gen_mov_reg_FCC1(t0, src, fcc_offset);
859 tcg_gen_and_tl(dst, dst, t0);
860 tcg_temp_free(t0);
19f329ad
BS		 861}
862
863// 0: !(FCC0 | FCC1)
864static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
865 unsigned int fcc_offset)
866{
de9e9d9f 867 TCGv t0 = tcg_temp_new();
19f329ad 868 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 869 gen_mov_reg_FCC1(t0, src, fcc_offset);
870 tcg_gen_or_tl(dst, dst, t0);
19f329ad 871 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 872 tcg_temp_free(t0);
19f329ad
BS		 873}
874
875// 0 or 3: !(FCC0 ^ FCC1)
876static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
877 unsigned int fcc_offset)
878{
de9e9d9f 879 TCGv t0 = tcg_temp_new();
19f329ad 880 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 881 gen_mov_reg_FCC1(t0, src, fcc_offset);
882 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 883 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 884 tcg_temp_free(t0);
19f329ad
BS		 885}
886
887// 0 or 2: !FCC0
888static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
889 unsigned int fcc_offset)
890{
891 gen_mov_reg_FCC0(dst, src, fcc_offset);
892 tcg_gen_xori_tl(dst, dst, 0x1);
893}
894
895// !1: !(FCC0 & !FCC1)
896static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
897 unsigned int fcc_offset)
898{
de9e9d9f 899 TCGv t0 = tcg_temp_new();
19f329ad 900 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 901 gen_mov_reg_FCC1(t0, src, fcc_offset);
902 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 903 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 904 tcg_temp_free(t0);
19f329ad
BS		 905}
906
907// 0 or 1: !FCC1
908static inline void gen_op_eval_fble(TCGv dst, TCGv src,
909 unsigned int fcc_offset)
910{
911 gen_mov_reg_FCC1(dst, src, fcc_offset);
912 tcg_gen_xori_tl(dst, dst, 0x1);
913}
914
915// !2: !(!FCC0 & FCC1)
916static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
917 unsigned int fcc_offset)
918{
de9e9d9f 919 TCGv t0 = tcg_temp_new();
19f329ad 920 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 921 gen_mov_reg_FCC1(t0, src, fcc_offset);
922 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 923 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 924 tcg_temp_free(t0);
19f329ad
BS		 925}
926
927// !3: !(FCC0 & FCC1)
928static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
929 unsigned int fcc_offset)
930{
de9e9d9f 931 TCGv t0 = tcg_temp_new();
19f329ad 932 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 933 gen_mov_reg_FCC1(t0, src, fcc_offset);
934 tcg_gen_and_tl(dst, dst, t0);
19f329ad 935 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 936 tcg_temp_free(t0);
19f329ad
BS		 937}
938
46525e1f 939static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 940 target_ulong pc2, TCGv r_cond)
83469015 941{
42a268c2 942 TCGLabel *l1 = gen_new_label();
83469015 943
cb63669a 944 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 945
6e256c93 946 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 947
948 gen_set_label(l1);
6e256c93 949 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 950}
951
bfa31b76 952static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 953{
42a268c2 954 TCGLabel *l1 = gen_new_label();
bfa31b76 955 target_ulong npc = dc->npc;
83469015 956
bfa31b76 957 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 958
bfa31b76 959 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 960
961 gen_set_label(l1);
bfa31b76
RH		 962 gen_goto_tb(dc, 1, npc + 4, npc + 8);
963
964 dc->is_br = 1;
83469015
FB		 965}
966
2bf2e019
RH		 967static void gen_branch_n(DisasContext *dc, target_ulong pc1)
968{
969 target_ulong npc = dc->npc;
970
971 if (likely(npc != DYNAMIC_PC)) {
972 dc->pc = npc;
973 dc->jump_pc[0] = pc1;
974 dc->jump_pc[1] = npc + 4;
975 dc->npc = JUMP_PC;
976 } else {
977 TCGv t, z;
978
979 tcg_gen_mov_tl(cpu_pc, cpu_npc);
980
981 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
982 t = tcg_const_tl(pc1);
983 z = tcg_const_tl(0);
984 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
985 tcg_temp_free(t);
986 tcg_temp_free(z);
987
988 dc->pc = DYNAMIC_PC;
989 }
990}
991
2e655fe7 992static inline void gen_generic_branch(DisasContext *dc)
83469015 993{
61316742
RH		 994 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
995 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
996 TCGv zero = tcg_const_tl(0);
19f329ad 997
61316742 998 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 999
61316742
RH		 1000 tcg_temp_free(npc0);
1001 tcg_temp_free(npc1);
1002 tcg_temp_free(zero);
83469015
FB		 1003}
1004
4af984a7
BS		 1005/* call this function before using the condition register as it may
1006 have been set for a jump */
dee8913c 1007static inline void flush_cond(DisasContext *dc)
83469015
FB		 1008{
1009 if (dc->npc == JUMP_PC) {
2e655fe7 1010 gen_generic_branch(dc);
83469015
FB		 1011 dc->npc = DYNAMIC_PC;
1012 }
1013}
1014
934da7ee 1015static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1016{
1017 if (dc->npc == JUMP_PC) {
2e655fe7 1018 gen_generic_branch(dc);
72cbca10
FB		 1019 dc->npc = DYNAMIC_PC;
1020 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1021 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1022 }
1023}
1024
20132b96 1025static inline void update_psr(DisasContext *dc)
72cbca10 1026{
cfa90513
BS		 1027 if (dc->cc_op != CC_OP_FLAGS) {
1028 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1029 gen_helper_compute_psr(cpu_env);
cfa90513 1030 }
20132b96
RH		 1031}
1032
1033static inline void save_state(DisasContext *dc)
1034{
1035 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1036 save_npc(dc);
72cbca10
FB		 1037}
1038
13a6dd00 1039static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1040{
1041 if (dc->npc == JUMP_PC) {
2e655fe7 1042 gen_generic_branch(dc);
48d5c82b 1043 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1044 dc->pc = DYNAMIC_PC;
1045 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1046 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1047 dc->pc = DYNAMIC_PC;
1048 } else {
1049 dc->pc = dc->npc;
1050 }
1051}
1052
38bc628b
BS		 1053static inline void gen_op_next_insn(void)
1054{
48d5c82b
BS		 1055 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1056 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1057}
1058
416fcaea
RH		 1059static void free_compare(DisasCompare *cmp)
1060{
1061 if (!cmp->g1) {
1062 tcg_temp_free(cmp->c1);
1063 }
1064 if (!cmp->g2) {
1065 tcg_temp_free(cmp->c2);
1066 }
1067}
1068
2a484ecf 1069static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1070 DisasContext *dc)
19f329ad 1071{
2a484ecf 1072 static int subcc_cond[16] = {
96b5a3d3 1073 TCG_COND_NEVER,
2a484ecf
RH		 1074 TCG_COND_EQ,
1075 TCG_COND_LE,
1076 TCG_COND_LT,
1077 TCG_COND_LEU,
1078 TCG_COND_LTU,
1079 -1, /* neg */
1080 -1, /* overflow */
96b5a3d3 1081 TCG_COND_ALWAYS,
2a484ecf
RH		 1082 TCG_COND_NE,
1083 TCG_COND_GT,
1084 TCG_COND_GE,
1085 TCG_COND_GTU,
1086 TCG_COND_GEU,
1087 -1, /* pos */
1088 -1, /* no overflow */
1089 };
1090
96b5a3d3
RH		 1091 static int logic_cond[16] = {
1092 TCG_COND_NEVER,
1093 TCG_COND_EQ, /* eq: Z */
1094 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1095 TCG_COND_LT, /* lt: N ^ V -> N */
1096 TCG_COND_EQ, /* leu: C | Z -> Z */
1097 TCG_COND_NEVER, /* ltu: C -> 0 */
1098 TCG_COND_LT, /* neg: N */
1099 TCG_COND_NEVER, /* vs: V -> 0 */
1100 TCG_COND_ALWAYS,
1101 TCG_COND_NE, /* ne: !Z */
1102 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1103 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1104 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1105 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1106 TCG_COND_GE, /* pos: !N */
1107 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1108 };
1109
a7812ae4 1110 TCGv_i32 r_src;
416fcaea
RH		 1111 TCGv r_dst;
1112
3475187d 1113#ifdef TARGET_SPARC64
2a484ecf 1114 if (xcc) {
dc99a3f2 1115 r_src = cpu_xcc;
2a484ecf 1116 } else {
dc99a3f2 1117 r_src = cpu_psr;
2a484ecf 1118 }
3475187d 1119#else
dc99a3f2 1120 r_src = cpu_psr;
3475187d 1121#endif
2a484ecf 1122
8393617c 1123 switch (dc->cc_op) {
96b5a3d3
RH		 1124 case CC_OP_LOGIC:
1125 cmp->cond = logic_cond[cond];
1126 do_compare_dst_0:
1127 cmp->is_bool = false;
1128 cmp->g2 = false;
1129 cmp->c2 = tcg_const_tl(0);
1130#ifdef TARGET_SPARC64
1131 if (!xcc) {
1132 cmp->g1 = false;
1133 cmp->c1 = tcg_temp_new();
1134 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1135 break;
1136 }
1137#endif
1138 cmp->g1 = true;
1139 cmp->c1 = cpu_cc_dst;
1140 break;
1141
2a484ecf
RH		 1142 case CC_OP_SUB:
1143 switch (cond) {
1144 case 6: /* neg */
1145 case 14: /* pos */
1146 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1147 goto do_compare_dst_0;
2a484ecf 1148
2a484ecf
RH		 1149 case 7: /* overflow */
1150 case 15: /* !overflow */
1151 goto do_dynamic;
1152
1153 default:
1154 cmp->cond = subcc_cond[cond];
1155 cmp->is_bool = false;
1156#ifdef TARGET_SPARC64
1157 if (!xcc) {
1158 /* Note that sign-extension works for unsigned compares as
1159 long as both operands are sign-extended. */
1160 cmp->g1 = cmp->g2 = false;
1161 cmp->c1 = tcg_temp_new();
1162 cmp->c2 = tcg_temp_new();
1163 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1164 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1165 break;
2a484ecf
RH		 1166 }
1167#endif
1168 cmp->g1 = cmp->g2 = true;
1169 cmp->c1 = cpu_cc_src;
1170 cmp->c2 = cpu_cc_src2;
1171 break;
1172 }
8393617c 1173 break;
2a484ecf 1174
8393617c 1175 default:
2a484ecf 1176 do_dynamic:
2ffd9176 1177 gen_helper_compute_psr(cpu_env);
8393617c 1178 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1179 /* FALLTHRU */
1180
1181 case CC_OP_FLAGS:
1182 /* We're going to generate a boolean result. */
1183 cmp->cond = TCG_COND_NE;
1184 cmp->is_bool = true;
1185 cmp->g1 = cmp->g2 = false;
1186 cmp->c1 = r_dst = tcg_temp_new();
1187 cmp->c2 = tcg_const_tl(0);
1188
1189 switch (cond) {
1190 case 0x0:
1191 gen_op_eval_bn(r_dst);
1192 break;
1193 case 0x1:
1194 gen_op_eval_be(r_dst, r_src);
1195 break;
1196 case 0x2:
1197 gen_op_eval_ble(r_dst, r_src);
1198 break;
1199 case 0x3:
1200 gen_op_eval_bl(r_dst, r_src);
1201 break;
1202 case 0x4:
1203 gen_op_eval_bleu(r_dst, r_src);
1204 break;
1205 case 0x5:
1206 gen_op_eval_bcs(r_dst, r_src);
1207 break;
1208 case 0x6:
1209 gen_op_eval_bneg(r_dst, r_src);
1210 break;
1211 case 0x7:
1212 gen_op_eval_bvs(r_dst, r_src);
1213 break;
1214 case 0x8:
1215 gen_op_eval_ba(r_dst);
1216 break;
1217 case 0x9:
1218 gen_op_eval_bne(r_dst, r_src);
1219 break;
1220 case 0xa:
1221 gen_op_eval_bg(r_dst, r_src);
1222 break;
1223 case 0xb:
1224 gen_op_eval_bge(r_dst, r_src);
1225 break;
1226 case 0xc:
1227 gen_op_eval_bgu(r_dst, r_src);
1228 break;
1229 case 0xd:
1230 gen_op_eval_bcc(r_dst, r_src);
1231 break;
1232 case 0xe:
1233 gen_op_eval_bpos(r_dst, r_src);
1234 break;
1235 case 0xf:
1236 gen_op_eval_bvc(r_dst, r_src);
1237 break;
1238 }
19f329ad
BS		 1239 break;
1240 }
1241}
7a3f1944 1242
416fcaea 1243static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1244{
19f329ad 1245 unsigned int offset;
416fcaea
RH		 1246 TCGv r_dst;
1247
1248 /* For now we still generate a straight boolean result. */
1249 cmp->cond = TCG_COND_NE;
1250 cmp->is_bool = true;
1251 cmp->g1 = cmp->g2 = false;
1252 cmp->c1 = r_dst = tcg_temp_new();
1253 cmp->c2 = tcg_const_tl(0);
19f329ad 1254
19f329ad
BS		 1255 switch (cc) {
1256 default:
1257 case 0x0:
1258 offset = 0;
1259 break;
1260 case 0x1:
1261 offset = 32 - 10;
1262 break;
1263 case 0x2:
1264 offset = 34 - 10;
1265 break;
1266 case 0x3:
1267 offset = 36 - 10;
1268 break;
1269 }
1270
1271 switch (cond) {
1272 case 0x0:
1273 gen_op_eval_bn(r_dst);
1274 break;
1275 case 0x1:
87e92502 1276 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1277 break;
1278 case 0x2:
87e92502 1279 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1280 break;
1281 case 0x3:
87e92502 1282 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1283 break;
1284 case 0x4:
87e92502 1285 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1286 break;
1287 case 0x5:
87e92502 1288 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1289 break;
1290 case 0x6:
87e92502 1291 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1292 break;
1293 case 0x7:
87e92502 1294 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1295 break;
1296 case 0x8:
1297 gen_op_eval_ba(r_dst);
1298 break;
1299 case 0x9:
87e92502 1300 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1301 break;
1302 case 0xa:
87e92502 1303 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1304 break;
1305 case 0xb:
87e92502 1306 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1307 break;
1308 case 0xc:
87e92502 1309 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1310 break;
1311 case 0xd:
87e92502 1312 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1313 break;
1314 case 0xe:
87e92502 1315 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1316 break;
1317 case 0xf:
87e92502 1318 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1319 break;
1320 }
e8af50a3 1321}
00f219bf 1322
416fcaea
RH		 1323static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1324 DisasContext *dc)
1325{
1326 DisasCompare cmp;
1327 gen_compare(&cmp, cc, cond, dc);
1328
1329 /* The interface is to return a boolean in r_dst. */
1330 if (cmp.is_bool) {
1331 tcg_gen_mov_tl(r_dst, cmp.c1);
1332 } else {
1333 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1334 }
1335
1336 free_compare(&cmp);
1337}
1338
1339static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1340{
1341 DisasCompare cmp;
1342 gen_fcompare(&cmp, cc, cond);
1343
1344 /* The interface is to return a boolean in r_dst. */
1345 if (cmp.is_bool) {
1346 tcg_gen_mov_tl(r_dst, cmp.c1);
1347 } else {
1348 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1349 }
1350
1351 free_compare(&cmp);
1352}
1353
19f329ad 1354#ifdef TARGET_SPARC64
00f219bf
BS		 1355// Inverted logic
1356static const int gen_tcg_cond_reg[8] = {
1357 -1,
1358 TCG_COND_NE,
1359 TCG_COND_GT,
1360 TCG_COND_GE,
1361 -1,
1362 TCG_COND_EQ,
1363 TCG_COND_LE,
1364 TCG_COND_LT,
1365};
19f329ad 1366
416fcaea
RH		 1367static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1368{
1369 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1370 cmp->is_bool = false;
1371 cmp->g1 = true;
1372 cmp->g2 = false;
1373 cmp->c1 = r_src;
1374 cmp->c2 = tcg_const_tl(0);
1375}
1376
4af984a7 1377static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1378{
416fcaea
RH		 1379 DisasCompare cmp;
1380 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1381
416fcaea
RH		 1382 /* The interface is to return a boolean in r_dst. */
1383 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1384
1385 free_compare(&cmp);
19f329ad 1386}
3475187d 1387#endif
cf495bcf 1388
d4a288ef 1389static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1390{
cf495bcf 1391 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1392 target_ulong target = dc->pc + offset;
5fafdf24 1393
22036a49
AT		 1394#ifdef TARGET_SPARC64
1395 if (unlikely(AM_CHECK(dc))) {
1396 target &= 0xffffffffULL;
1397 }
1398#endif
cf495bcf 1399 if (cond == 0x0) {
0f8a249a
BS		 1400 /* unconditional not taken */
1401 if (a) {
1402 dc->pc = dc->npc + 4;
1403 dc->npc = dc->pc + 4;
1404 } else {
1405 dc->pc = dc->npc;
1406 dc->npc = dc->pc + 4;
1407 }
cf495bcf 1408 } else if (cond == 0x8) {
0f8a249a
BS		 1409 /* unconditional taken */
1410 if (a) {
1411 dc->pc = target;
1412 dc->npc = dc->pc + 4;
1413 } else {
1414 dc->pc = dc->npc;
1415 dc->npc = target;
c27e2752 1416 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1417 }
cf495bcf 1418 } else {
dee8913c 1419 flush_cond(dc);
d4a288ef 1420 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1421 if (a) {
bfa31b76 1422 gen_branch_a(dc, target);
0f8a249a 1423 } else {
2bf2e019 1424 gen_branch_n(dc, target);
0f8a249a 1425 }
cf495bcf 1426 }
7a3f1944
FB		 1427}
1428
d4a288ef 1429static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1430{
1431 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1432 target_ulong target = dc->pc + offset;
1433
22036a49
AT		 1434#ifdef TARGET_SPARC64
1435 if (unlikely(AM_CHECK(dc))) {
1436 target &= 0xffffffffULL;
1437 }
1438#endif
e8af50a3 1439 if (cond == 0x0) {
0f8a249a
BS		 1440 /* unconditional not taken */
1441 if (a) {
1442 dc->pc = dc->npc + 4;
1443 dc->npc = dc->pc + 4;
1444 } else {
1445 dc->pc = dc->npc;
1446 dc->npc = dc->pc + 4;
1447 }
e8af50a3 1448 } else if (cond == 0x8) {
0f8a249a
BS		 1449 /* unconditional taken */
1450 if (a) {
1451 dc->pc = target;
1452 dc->npc = dc->pc + 4;
1453 } else {
1454 dc->pc = dc->npc;
1455 dc->npc = target;
c27e2752 1456 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1457 }
e8af50a3 1458 } else {
dee8913c 1459 flush_cond(dc);
d4a288ef 1460 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1461 if (a) {
bfa31b76 1462 gen_branch_a(dc, target);
0f8a249a 1463 } else {
2bf2e019 1464 gen_branch_n(dc, target);
0f8a249a 1465 }
e8af50a3
FB		 1466 }
1467}
1468
3475187d 1469#ifdef TARGET_SPARC64
4af984a7 1470static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1471 TCGv r_reg)
7a3f1944 1472{
3475187d
FB		 1473 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1474 target_ulong target = dc->pc + offset;
1475
22036a49
AT		 1476 if (unlikely(AM_CHECK(dc))) {
1477 target &= 0xffffffffULL;
1478 }
dee8913c 1479 flush_cond(dc);
d4a288ef 1480 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1481 if (a) {
bfa31b76 1482 gen_branch_a(dc, target);
3475187d 1483 } else {
2bf2e019 1484 gen_branch_n(dc, target);
3475187d 1485 }
7a3f1944
FB		 1486}
1487
a7812ae4 1488static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1489{
714547bb
BS		 1490 switch (fccno) {
1491 case 0:
2e2f4ade 1492 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1493 break;
1494 case 1:
2e2f4ade 1495 gen_helper_fcmps_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1496 break;
1497 case 2:
2e2f4ade 1498 gen_helper_fcmps_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1499 break;
1500 case 3:
2e2f4ade 1501 gen_helper_fcmps_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1502 break;
1503 }
7e8c2b6c
BS		 1504}
1505
03fb8cfc 1506static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1507{
a7812ae4
PB		 1508 switch (fccno) {
1509 case 0:
03fb8cfc 1510 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1511 break;
1512 case 1:
03fb8cfc 1513 gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1514 break;
1515 case 2:
03fb8cfc 1516 gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1517 break;
1518 case 3:
03fb8cfc 1519 gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1520 break;
1521 }
7e8c2b6c
BS		 1522}
1523
7e8c2b6c
BS		 1524static inline void gen_op_fcmpq(int fccno)
1525{
a7812ae4
PB		 1526 switch (fccno) {
1527 case 0:
2e2f4ade 1528 gen_helper_fcmpq(cpu_env);
a7812ae4
PB		 1529 break;
1530 case 1:
2e2f4ade 1531 gen_helper_fcmpq_fcc1(cpu_env);
a7812ae4
PB		 1532 break;
1533 case 2:
2e2f4ade 1534 gen_helper_fcmpq_fcc2(cpu_env);
a7812ae4
PB		 1535 break;
1536 case 3:
2e2f4ade 1537 gen_helper_fcmpq_fcc3(cpu_env);
a7812ae4
PB		 1538 break;
1539 }
7e8c2b6c 1540}
7e8c2b6c 1541
a7812ae4 1542static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1543{
714547bb
BS		 1544 switch (fccno) {
1545 case 0:
2e2f4ade 1546 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1547 break;
1548 case 1:
2e2f4ade 1549 gen_helper_fcmpes_fcc1(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1550 break;
1551 case 2:
2e2f4ade 1552 gen_helper_fcmpes_fcc2(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1553 break;
1554 case 3:
2e2f4ade 1555 gen_helper_fcmpes_fcc3(cpu_env, r_rs1, r_rs2);
714547bb
BS		 1556 break;
1557 }
7e8c2b6c
BS		 1558}
1559
03fb8cfc 1560static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1561{
a7812ae4
PB		 1562 switch (fccno) {
1563 case 0:
03fb8cfc 1564 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1565 break;
1566 case 1:
03fb8cfc 1567 gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1568 break;
1569 case 2:
03fb8cfc 1570 gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1571 break;
1572 case 3:
03fb8cfc 1573 gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1574 break;
1575 }
7e8c2b6c
BS		 1576}
1577
7e8c2b6c
BS		 1578static inline void gen_op_fcmpeq(int fccno)
1579{
a7812ae4
PB		 1580 switch (fccno) {
1581 case 0:
2e2f4ade 1582 gen_helper_fcmpeq(cpu_env);
a7812ae4
PB		 1583 break;
1584 case 1:
2e2f4ade 1585 gen_helper_fcmpeq_fcc1(cpu_env);
a7812ae4
PB		 1586 break;
1587 case 2:
2e2f4ade 1588 gen_helper_fcmpeq_fcc2(cpu_env);
a7812ae4
PB		 1589 break;
1590 case 3:
2e2f4ade 1591 gen_helper_fcmpeq_fcc3(cpu_env);
a7812ae4
PB		 1592 break;
1593 }
7e8c2b6c 1594}
7e8c2b6c
BS		 1595
1596#else
1597
714547bb 1598static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1599{
2e2f4ade 1600 gen_helper_fcmps(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1601}
1602
03fb8cfc 1603static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1604{
03fb8cfc 1605 gen_helper_fcmpd(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1606}
1607
7e8c2b6c
BS		 1608static inline void gen_op_fcmpq(int fccno)
1609{
2e2f4ade 1610 gen_helper_fcmpq(cpu_env);
7e8c2b6c 1611}
7e8c2b6c 1612
714547bb 1613static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1614{
2e2f4ade 1615 gen_helper_fcmpes(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1616}
1617
03fb8cfc 1618static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1619{
03fb8cfc 1620 gen_helper_fcmped(cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1621}
1622
7e8c2b6c
BS		 1623static inline void gen_op_fcmpeq(int fccno)
1624{
2e2f4ade 1625 gen_helper_fcmpeq(cpu_env);
7e8c2b6c
BS		 1626}
1627#endif
1628
134d77a1
BS		 1629static inline void gen_op_fpexception_im(int fsr_flags)
1630{
a7812ae4 1631 TCGv_i32 r_const;
2ea815ca 1632
47ad35f1 1633 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1634 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
2ea815ca 1635 r_const = tcg_const_i32(TT_FP_EXCP);
bc265319 1636 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1637 tcg_temp_free_i32(r_const);
134d77a1
BS		 1638}
1639
5b12f1e8 1640static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1641{
1642#if !defined(CONFIG_USER_ONLY)
1643 if (!dc->fpu_enabled) {
a7812ae4 1644 TCGv_i32 r_const;
2ea815ca 1645
66442b07 1646 save_state(dc);
2ea815ca 1647 r_const = tcg_const_i32(TT_NFPU_INSN);
bc265319 1648 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 1649 tcg_temp_free_i32(r_const);
a80dde08
FB		 1650 dc->is_br = 1;
1651 return 1;
1652 }
1653#endif
1654 return 0;
1655}
1656
7e8c2b6c
BS		 1657static inline void gen_op_clear_ieee_excp_and_FTT(void)
1658{
47ad35f1 1659 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1660}
1661
61f17f6e
RH		 1662static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1663 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1664{
1665 TCGv_i32 dst, src;
1666
61f17f6e 1667 src = gen_load_fpr_F(dc, rs);
ba5f5179 1668 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1669
1670 gen(dst, cpu_env, src);
1671
61f17f6e
RH		 1672 gen_store_fpr_F(dc, rd, dst);
1673}
1674
1675static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1676 void (*gen)(TCGv_i32, TCGv_i32))
1677{
1678 TCGv_i32 dst, src;
1679
1680 src = gen_load_fpr_F(dc, rs);
ba5f5179 1681 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1682
1683 gen(dst, src);
1684
1685 gen_store_fpr_F(dc, rd, dst);
1686}
1687
1688static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1689 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1690{
1691 TCGv_i32 dst, src1, src2;
1692
61f17f6e
RH		 1693 src1 = gen_load_fpr_F(dc, rs1);
1694 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1695 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1696
1697 gen(dst, cpu_env, src1, src2);
1698
61f17f6e
RH		 1699 gen_store_fpr_F(dc, rd, dst);
1700}
1701
1702#ifdef TARGET_SPARC64
1703static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1704 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1705{
1706 TCGv_i32 dst, src1, src2;
1707
1708 src1 = gen_load_fpr_F(dc, rs1);
1709 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1710 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1711
1712 gen(dst, src1, src2);
1713
1714 gen_store_fpr_F(dc, rd, dst);
1715}
1716#endif
1717
1718static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1719 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1720{
1721 TCGv_i64 dst, src;
1722
61f17f6e 1723 src = gen_load_fpr_D(dc, rs);
3886b8a3 1724 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1725
1726 gen(dst, cpu_env, src);
1727
61f17f6e
RH		 1728 gen_store_fpr_D(dc, rd, dst);
1729}
1730
1731#ifdef TARGET_SPARC64
1732static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1733 void (*gen)(TCGv_i64, TCGv_i64))
1734{
1735 TCGv_i64 dst, src;
1736
1737 src = gen_load_fpr_D(dc, rs);
3886b8a3 1738 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1739
1740 gen(dst, src);
1741
1742 gen_store_fpr_D(dc, rd, dst);
1743}
1744#endif
1745
1746static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1747 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1748{
1749 TCGv_i64 dst, src1, src2;
1750
61f17f6e
RH		 1751 src1 = gen_load_fpr_D(dc, rs1);
1752 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1753 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1754
1755 gen(dst, cpu_env, src1, src2);
1756
61f17f6e
RH		 1757 gen_store_fpr_D(dc, rd, dst);
1758}
1759
1760#ifdef TARGET_SPARC64
1761static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1762 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1763{
1764 TCGv_i64 dst, src1, src2;
1765
1766 src1 = gen_load_fpr_D(dc, rs1);
1767 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1768 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1769
1770 gen(dst, src1, src2);
1771
1772 gen_store_fpr_D(dc, rd, dst);
1773}
f888300b 1774
2dedf314
RH		 1775static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1776 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1777{
1778 TCGv_i64 dst, src1, src2;
1779
1780 src1 = gen_load_fpr_D(dc, rs1);
1781 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1782 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1783
1784 gen(dst, cpu_gsr, src1, src2);
1785
1786 gen_store_fpr_D(dc, rd, dst);
1787}
1788
f888300b
RH		 1789static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1790 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1791{
1792 TCGv_i64 dst, src0, src1, src2;
1793
1794 src1 = gen_load_fpr_D(dc, rs1);
1795 src2 = gen_load_fpr_D(dc, rs2);
1796 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1797 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1798
1799 gen(dst, src0, src1, src2);
1800
1801 gen_store_fpr_D(dc, rd, dst);
1802}
61f17f6e
RH		 1803#endif
1804
1805static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1806 void (*gen)(TCGv_ptr))
1807{
61f17f6e
RH		 1808 gen_op_load_fpr_QT1(QFPREG(rs));
1809
1810 gen(cpu_env);
1811
61f17f6e
RH		 1812 gen_op_store_QT0_fpr(QFPREG(rd));
1813 gen_update_fprs_dirty(QFPREG(rd));
1814}
1815
1816#ifdef TARGET_SPARC64
1817static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1818 void (*gen)(TCGv_ptr))
1819{
1820 gen_op_load_fpr_QT1(QFPREG(rs));
1821
1822 gen(cpu_env);
1823
1824 gen_op_store_QT0_fpr(QFPREG(rd));
1825 gen_update_fprs_dirty(QFPREG(rd));
1826}
1827#endif
1828
1829static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1830 void (*gen)(TCGv_ptr))
1831{
61f17f6e
RH		 1832 gen_op_load_fpr_QT0(QFPREG(rs1));
1833 gen_op_load_fpr_QT1(QFPREG(rs2));
1834
1835 gen(cpu_env);
1836
61f17f6e
RH		 1837 gen_op_store_QT0_fpr(QFPREG(rd));
1838 gen_update_fprs_dirty(QFPREG(rd));
1839}
1840
1841static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1842 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1843{
1844 TCGv_i64 dst;
1845 TCGv_i32 src1, src2;
1846
61f17f6e
RH		 1847 src1 = gen_load_fpr_F(dc, rs1);
1848 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1849 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1850
1851 gen(dst, cpu_env, src1, src2);
1852
61f17f6e
RH		 1853 gen_store_fpr_D(dc, rd, dst);
1854}
1855
1856static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1857 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1858{
1859 TCGv_i64 src1, src2;
1860
61f17f6e
RH		 1861 src1 = gen_load_fpr_D(dc, rs1);
1862 src2 = gen_load_fpr_D(dc, rs2);
1863
1864 gen(cpu_env, src1, src2);
1865
61f17f6e
RH		 1866 gen_op_store_QT0_fpr(QFPREG(rd));
1867 gen_update_fprs_dirty(QFPREG(rd));
1868}
1869
1870#ifdef TARGET_SPARC64
1871static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1872 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1873{
1874 TCGv_i64 dst;
1875 TCGv_i32 src;
1876
61f17f6e 1877 src = gen_load_fpr_F(dc, rs);
3886b8a3 1878 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1879
1880 gen(dst, cpu_env, src);
1881
61f17f6e
RH		 1882 gen_store_fpr_D(dc, rd, dst);
1883}
1884#endif
1885
1886static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1887 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1888{
1889 TCGv_i64 dst;
1890 TCGv_i32 src;
1891
1892 src = gen_load_fpr_F(dc, rs);
3886b8a3 1893 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1894
1895 gen(dst, cpu_env, src);
1896
1897 gen_store_fpr_D(dc, rd, dst);
1898}
1899
1900static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1901 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1902{
1903 TCGv_i32 dst;
1904 TCGv_i64 src;
1905
61f17f6e 1906 src = gen_load_fpr_D(dc, rs);
ba5f5179 1907 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1908
1909 gen(dst, cpu_env, src);
1910
61f17f6e
RH		 1911 gen_store_fpr_F(dc, rd, dst);
1912}
1913
1914static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1915 void (*gen)(TCGv_i32, TCGv_ptr))
1916{
1917 TCGv_i32 dst;
1918
61f17f6e 1919 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1920 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1921
1922 gen(dst, cpu_env);
1923
61f17f6e
RH		 1924 gen_store_fpr_F(dc, rd, dst);
1925}
1926
1927static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1928 void (*gen)(TCGv_i64, TCGv_ptr))
1929{
1930 TCGv_i64 dst;
1931
61f17f6e 1932 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1933 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1934
1935 gen(dst, cpu_env);
1936
61f17f6e
RH		 1937 gen_store_fpr_D(dc, rd, dst);
1938}
1939
1940static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
1941 void (*gen)(TCGv_ptr, TCGv_i32))
1942{
1943 TCGv_i32 src;
1944
1945 src = gen_load_fpr_F(dc, rs);
1946
1947 gen(cpu_env, src);
1948
1949 gen_op_store_QT0_fpr(QFPREG(rd));
1950 gen_update_fprs_dirty(QFPREG(rd));
1951}
1952
1953static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
1954 void (*gen)(TCGv_ptr, TCGv_i64))
1955{
1956 TCGv_i64 src;
1957
1958 src = gen_load_fpr_D(dc, rs);
1959
1960 gen(cpu_env, src);
1961
1962 gen_op_store_QT0_fpr(QFPREG(rd));
1963 gen_update_fprs_dirty(QFPREG(rd));
1964}
1965
1a2fb1c0
BS		 1966/* asi moves */
1967#ifdef TARGET_SPARC64
a7812ae4 1968static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1a2fb1c0 1969{
95f9397c 1970 int asi;
a7812ae4 1971 TCGv_i32 r_asi;
1a2fb1c0 1972
1a2fb1c0 1973 if (IS_IMM) {
a7812ae4 1974 r_asi = tcg_temp_new_i32();
255e1fcb 1975 tcg_gen_mov_i32(r_asi, cpu_asi);
1a2fb1c0
BS		 1976 } else {
1977 asi = GET_FIELD(insn, 19, 26);
0425bee5 1978 r_asi = tcg_const_i32(asi);
1a2fb1c0 1979 }
0425bee5
BS		 1980 return r_asi;
1981}
1982
77f193da
BS		 1983static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1984 int sign)
0425bee5 1985{
a7812ae4 1986 TCGv_i32 r_asi, r_size, r_sign;
0425bee5 1987
4af984a7 1988 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 1989 r_size = tcg_const_i32(size);
1990 r_sign = tcg_const_i32(sign);
fe8d8f0f 1991 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4
PB		 1992 tcg_temp_free_i32(r_sign);
1993 tcg_temp_free_i32(r_size);
1994 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 1995}
1996
4af984a7 1997static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 1998{
a7812ae4 1999 TCGv_i32 r_asi, r_size;
1a2fb1c0 2000
4af984a7 2001 r_asi = gen_get_asi(insn, addr);
2ea815ca 2002 r_size = tcg_const_i32(size);
fe8d8f0f 2003 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2004 tcg_temp_free_i32(r_size);
2005 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2006}
2007
4af984a7 2008static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2009{
a7812ae4 2010 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2011
4af984a7 2012 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2013 r_size = tcg_const_i32(size);
2014 r_rd = tcg_const_i32(rd);
fe8d8f0f 2015 gen_helper_ldf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2016 tcg_temp_free_i32(r_rd);
2017 tcg_temp_free_i32(r_size);
2018 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2019}
2020
4af984a7 2021static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1a2fb1c0 2022{
a7812ae4 2023 TCGv_i32 r_asi, r_size, r_rd;
1a2fb1c0 2024
31741a27 2025 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2026 r_size = tcg_const_i32(size);
2027 r_rd = tcg_const_i32(rd);
fe8d8f0f 2028 gen_helper_stf_asi(cpu_env, addr, r_asi, r_size, r_rd);
a7812ae4
PB		 2029 tcg_temp_free_i32(r_rd);
2030 tcg_temp_free_i32(r_size);
2031 tcg_temp_free_i32(r_asi);
1a2fb1c0
BS		 2032}
2033
06828032 2034static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2035{
a7812ae4 2036 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2037 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2038
4af984a7 2039 r_asi = gen_get_asi(insn, addr);
2ea815ca
BS		 2040 r_size = tcg_const_i32(4);
2041 r_sign = tcg_const_i32(0);
1ec789ab 2042 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
a7812ae4 2043 tcg_temp_free_i32(r_sign);
06828032 2044 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_size);
a7812ae4
PB		 2045 tcg_temp_free_i32(r_size);
2046 tcg_temp_free_i32(r_asi);
1ec789ab
RH		 2047 tcg_gen_trunc_i64_tl(dst, t64);
2048 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2049}
2050
c7785e16
RH		 2051static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2052 int insn, int rd)
1a2fb1c0 2053{
a7812ae4 2054 TCGv_i32 r_asi, r_rd;
1a2fb1c0 2055
4af984a7 2056 r_asi = gen_get_asi(insn, addr);
db166940 2057 r_rd = tcg_const_i32(rd);
fe8d8f0f 2058 gen_helper_ldda_asi(cpu_env, addr, r_asi, r_rd);
a7812ae4
PB		 2059 tcg_temp_free_i32(r_rd);
2060 tcg_temp_free_i32(r_asi);
0425bee5
BS		 2061}
2062
c7785e16
RH		 2063static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2064 int insn, int rd)
0425bee5 2065{
a7812ae4 2066 TCGv_i32 r_asi, r_size;
c7785e16 2067 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2068 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2069
1ec789ab 2070 tcg_gen_concat_tl_i64(t64, lo, hi);
4af984a7 2071 r_asi = gen_get_asi(insn, addr);
2ea815ca 2072 r_size = tcg_const_i32(8);
1ec789ab 2073 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
a7812ae4
PB		 2074 tcg_temp_free_i32(r_size);
2075 tcg_temp_free_i32(r_asi);
1ec789ab 2076 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2077}
2078
81634eea 2079static inline void gen_casx_asi(DisasContext *dc, TCGv addr,
c7785e16 2080 TCGv val2, int insn, int rd)
1a2fb1c0 2081{
81634eea
RH		 2082 TCGv val1 = gen_load_gpr(dc, rd);
2083 TCGv dst = gen_dest_gpr(dc, rd);
c7785e16 2084 TCGv_i32 r_asi = gen_get_asi(insn, addr);
1a2fb1c0 2085
81634eea 2086 gen_helper_casx_asi(dst, cpu_env, addr, val1, val2, r_asi);
a7812ae4 2087 tcg_temp_free_i32(r_asi);
81634eea 2088 gen_store_gpr(dc, rd, dst);
1a2fb1c0
BS		 2089}
2090
2091#elif !defined(CONFIG_USER_ONLY)
2092
77f193da
BS		 2093static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
2094 int sign)
1a2fb1c0 2095{
a7812ae4 2096 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2097 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2098
2ea815ca
BS		 2099 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2100 r_size = tcg_const_i32(size);
2101 r_sign = tcg_const_i32(sign);
1ec789ab
RH		 2102 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2103 tcg_temp_free_i32(r_sign);
2104 tcg_temp_free_i32(r_size);
2105 tcg_temp_free_i32(r_asi);
2106 tcg_gen_trunc_i64_tl(dst, t64);
2107 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2108}
2109
4af984a7 2110static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1a2fb1c0 2111{
a7812ae4 2112 TCGv_i32 r_asi, r_size;
1ec789ab 2113 TCGv_i64 t64 = tcg_temp_new_i64();
1a2fb1c0 2114
1ec789ab 2115 tcg_gen_extu_tl_i64(t64, src);
2ea815ca
BS		 2116 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2117 r_size = tcg_const_i32(size);
1ec789ab
RH		 2118 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2119 tcg_temp_free_i32(r_size);
2120 tcg_temp_free_i32(r_asi);
2121 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2122}
2123
06828032 2124static inline void gen_swap_asi(TCGv dst, TCGv src, TCGv addr, int insn)
1a2fb1c0 2125{
a7812ae4 2126 TCGv_i32 r_asi, r_size, r_sign;
1ec789ab 2127 TCGv_i64 r_val, t64;
1a2fb1c0 2128
2ea815ca
BS		 2129 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2130 r_size = tcg_const_i32(4);
2131 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2132 t64 = tcg_temp_new_i64();
2133 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2ea815ca 2134 tcg_temp_free(r_sign);
a7812ae4 2135 r_val = tcg_temp_new_i64();
06828032 2136 tcg_gen_extu_tl_i64(r_val, src);
fe8d8f0f 2137 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4 2138 tcg_temp_free_i64(r_val);
1ec789ab
RH		 2139 tcg_temp_free_i32(r_size);
2140 tcg_temp_free_i32(r_asi);
2141 tcg_gen_trunc_i64_tl(dst, t64);
2142 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2143}
2144
c7785e16
RH		 2145static inline void gen_ldda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2146 int insn, int rd)
1a2fb1c0 2147{
a7812ae4 2148 TCGv_i32 r_asi, r_size, r_sign;
c7785e16 2149 TCGv t;
1ec789ab 2150 TCGv_i64 t64;
1a2fb1c0 2151
2ea815ca
BS		 2152 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2153 r_size = tcg_const_i32(8);
2154 r_sign = tcg_const_i32(0);
1ec789ab
RH		 2155 t64 = tcg_temp_new_i64();
2156 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_size, r_sign);
2157 tcg_temp_free_i32(r_sign);
2158 tcg_temp_free_i32(r_size);
2159 tcg_temp_free_i32(r_asi);
c7785e16
RH		 2160
2161 t = gen_dest_gpr(dc, rd + 1);
1ec789ab 2162 tcg_gen_trunc_i64_tl(t, t64);
c7785e16
RH		 2163 gen_store_gpr(dc, rd + 1, t);
2164
1ec789ab
RH		 2165 tcg_gen_shri_i64(t64, t64, 32);
2166 tcg_gen_trunc_i64_tl(hi, t64);
2167 tcg_temp_free_i64(t64);
c7785e16 2168 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2169}
2170
c7785e16
RH		 2171static inline void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2172 int insn, int rd)
0425bee5 2173{
a7812ae4 2174 TCGv_i32 r_asi, r_size;
c7785e16 2175 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2176 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2177
1ec789ab 2178 tcg_gen_concat_tl_i64(t64, lo, hi);
2ea815ca
BS		 2179 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2180 r_size = tcg_const_i32(8);
1ec789ab
RH		 2181 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_size);
2182 tcg_temp_free_i32(r_size);
2183 tcg_temp_free_i32(r_asi);
2184 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2185}
2186#endif
2187
2188#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
16c358e9
SH		 2189static inline void gen_cas_asi(DisasContext *dc, TCGv addr,
2190 TCGv val2, int insn, int rd)
2191{
2192 TCGv val1 = gen_load_gpr(dc, rd);
2193 TCGv dst = gen_dest_gpr(dc, rd);
2194#ifdef TARGET_SPARC64
2195 TCGv_i32 r_asi = gen_get_asi(insn, addr);
2196#else
2197 TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2198#endif
2199
2200 gen_helper_cas_asi(dst, cpu_env, addr, val1, val2, r_asi);
2201 tcg_temp_free_i32(r_asi);
2202 gen_store_gpr(dc, rd, dst);
2203}
2204
4af984a7 2205static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1a2fb1c0 2206{
a7812ae4
PB		 2207 TCGv_i64 r_val;
2208 TCGv_i32 r_asi, r_size;
1a2fb1c0 2209
4af984a7 2210 gen_ld_asi(dst, addr, insn, 1, 0);
1a2fb1c0 2211
2ea815ca
BS		 2212 r_val = tcg_const_i64(0xffULL);
2213 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
2214 r_size = tcg_const_i32(1);
fe8d8f0f 2215 gen_helper_st_asi(cpu_env, addr, r_val, r_asi, r_size);
a7812ae4
PB		 2216 tcg_temp_free_i32(r_size);
2217 tcg_temp_free_i32(r_asi);
2218 tcg_temp_free_i64(r_val);
1a2fb1c0
BS		 2219}
2220#endif
2221
9d1d4e34 2222static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2223{
9d1d4e34
RH		 2224 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2225 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2226}
2227
9d1d4e34 2228static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2229{
a49d9390 2230 if (IS_IMM) { /* immediate */
42a8aa83 2231 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2232 TCGv t = get_temp_tl(dc);
2233 tcg_gen_movi_tl(t, simm);
2234 return t;
2235 } else { /* register */
42a8aa83 2236 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2237 return gen_load_gpr(dc, rs2);
a49d9390 2238 }
a49d9390
BS		 2239}
2240
8194f35a 2241#ifdef TARGET_SPARC64
7e480893
RH		 2242static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2243{
2244 TCGv_i32 c32, zero, dst, s1, s2;
2245
2246 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2247 or fold the comparison down to 32 bits and use movcond_i32. Choose
2248 the later. */
2249 c32 = tcg_temp_new_i32();
2250 if (cmp->is_bool) {
ecc7b3aa 2251 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2252 } else {
2253 TCGv_i64 c64 = tcg_temp_new_i64();
2254 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2255 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2256 tcg_temp_free_i64(c64);
2257 }
2258
2259 s1 = gen_load_fpr_F(dc, rs);
2260 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2261 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2262 zero = tcg_const_i32(0);
2263
2264 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2265
2266 tcg_temp_free_i32(c32);
2267 tcg_temp_free_i32(zero);
2268 gen_store_fpr_F(dc, rd, dst);
2269}
2270
2271static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2272{
3886b8a3 2273 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2274 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2275 gen_load_fpr_D(dc, rs),
2276 gen_load_fpr_D(dc, rd));
2277 gen_store_fpr_D(dc, rd, dst);
2278}
2279
2280static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2281{
2282 int qd = QFPREG(rd);
2283 int qs = QFPREG(rs);
2284
2285 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2286 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2287 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2288 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2289
2290 gen_update_fprs_dirty(qd);
2291}
2292
a2035e83 2293#ifndef CONFIG_USER_ONLY
8194f35a
IK		 2294static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
2295{
b551ec04 2296 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2297
2298 /* load env->tl into r_tl */
b551ec04 2299 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2300
2301 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2302 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2303
2304 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2305 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2306 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2307
2308 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 2309 {
2310 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
2311 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
2312 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 2313 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 2314 }
8194f35a 2315
b551ec04 2316 tcg_temp_free_i32(r_tl);
8194f35a 2317}
a2035e83 2318#endif
6c073553
RH		 2319
2320static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
2321 int width, bool cc, bool left)
2322{
2323 TCGv lo1, lo2, t1, t2;
2324 uint64_t amask, tabl, tabr;
2325 int shift, imask, omask;
2326
2327 if (cc) {
2328 tcg_gen_mov_tl(cpu_cc_src, s1);
2329 tcg_gen_mov_tl(cpu_cc_src2, s2);
2330 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
2331 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
2332 dc->cc_op = CC_OP_SUB;
2333 }
2334
2335 /* Theory of operation: there are two tables, left and right (not to
2336 be confused with the left and right versions of the opcode). These
2337 are indexed by the low 3 bits of the inputs. To make things "easy",
2338 these tables are loaded into two constants, TABL and TABR below.
2339 The operation index = (input & imask) << shift calculates the index
2340 into the constant, while val = (table >> index) & omask calculates
2341 the value we're looking for. */
2342 switch (width) {
2343 case 8:
2344 imask = 0x7;
2345 shift = 3;
2346 omask = 0xff;
2347 if (left) {
2348 tabl = 0x80c0e0f0f8fcfeffULL;
2349 tabr = 0xff7f3f1f0f070301ULL;
2350 } else {
2351 tabl = 0x0103070f1f3f7fffULL;
2352 tabr = 0xfffefcf8f0e0c080ULL;
2353 }
2354 break;
2355 case 16:
2356 imask = 0x6;
2357 shift = 1;
2358 omask = 0xf;
2359 if (left) {
2360 tabl = 0x8cef;
2361 tabr = 0xf731;
2362 } else {
2363 tabl = 0x137f;
2364 tabr = 0xfec8;
2365 }
2366 break;
2367 case 32:
2368 imask = 0x4;
2369 shift = 0;
2370 omask = 0x3;
2371 if (left) {
2372 tabl = (2 << 2) | 3;
2373 tabr = (3 << 2) | 1;
2374 } else {
2375 tabl = (1 << 2) | 3;
2376 tabr = (3 << 2) | 2;
2377 }
2378 break;
2379 default:
2380 abort();
2381 }
2382
2383 lo1 = tcg_temp_new();
2384 lo2 = tcg_temp_new();
2385 tcg_gen_andi_tl(lo1, s1, imask);
2386 tcg_gen_andi_tl(lo2, s2, imask);
2387 tcg_gen_shli_tl(lo1, lo1, shift);
2388 tcg_gen_shli_tl(lo2, lo2, shift);
2389
2390 t1 = tcg_const_tl(tabl);
2391 t2 = tcg_const_tl(tabr);
2392 tcg_gen_shr_tl(lo1, t1, lo1);
2393 tcg_gen_shr_tl(lo2, t2, lo2);
2394 tcg_gen_andi_tl(dst, lo1, omask);
2395 tcg_gen_andi_tl(lo2, lo2, omask);
2396
2397 amask = -8;
2398 if (AM_CHECK(dc)) {
2399 amask &= 0xffffffffULL;
2400 }
2401 tcg_gen_andi_tl(s1, s1, amask);
2402 tcg_gen_andi_tl(s2, s2, amask);
2403
2404 /* We want to compute
2405 dst = (s1 == s2 ? lo1 : lo1 & lo2).
2406 We've already done dst = lo1, so this reduces to
2407 dst &= (s1 == s2 ? -1 : lo2)
2408 Which we perform by
2409 lo2 |= -(s1 == s2)
2410 dst &= lo2
2411 */
2412 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
2413 tcg_gen_neg_tl(t1, t1);
2414 tcg_gen_or_tl(lo2, lo2, t1);
2415 tcg_gen_and_tl(dst, dst, lo2);
2416
2417 tcg_temp_free(lo1);
2418 tcg_temp_free(lo2);
2419 tcg_temp_free(t1);
2420 tcg_temp_free(t2);
2421}
add545ab
RH		 2422
2423static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
2424{
2425 TCGv tmp = tcg_temp_new();
2426
2427 tcg_gen_add_tl(tmp, s1, s2);
2428 tcg_gen_andi_tl(dst, tmp, -8);
2429 if (left) {
2430 tcg_gen_neg_tl(tmp, tmp);
2431 }
2432 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
2433
2434 tcg_temp_free(tmp);
2435}
50c796f9
RH		 2436
2437static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
2438{
2439 TCGv t1, t2, shift;
2440
2441 t1 = tcg_temp_new();
2442 t2 = tcg_temp_new();
2443 shift = tcg_temp_new();
2444
2445 tcg_gen_andi_tl(shift, gsr, 7);
2446 tcg_gen_shli_tl(shift, shift, 3);
2447 tcg_gen_shl_tl(t1, s1, shift);
2448
2449 /* A shift of 64 does not produce 0 in TCG. Divide this into a
2450 shift of (up to 63) followed by a constant shift of 1. */
2451 tcg_gen_xori_tl(shift, shift, 63);
2452 tcg_gen_shr_tl(t2, s2, shift);
2453 tcg_gen_shri_tl(t2, t2, 1);
2454
2455 tcg_gen_or_tl(dst, t1, t2);
2456
2457 tcg_temp_free(t1);
2458 tcg_temp_free(t2);
2459 tcg_temp_free(shift);
2460}
8194f35a
IK		 2461#endif
2462
64a88d5d 2463#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 2464 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2465 goto illegal_insn;
2466#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 2467 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 2468 goto nfpu_insn;
2469
0bee699e 2470/* before an instruction, dc->pc must be static */
0184e266 2471static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 2472{
0184e266 2473 unsigned int opc, rs1, rs2, rd;
a4273524 2474 TCGv cpu_src1, cpu_src2;
208ae657 2475 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 2476 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 2477 target_long simm;
7a3f1944 2478
cf495bcf 2479 opc = GET_FIELD(insn, 0, 1);
cf495bcf 2480 rd = GET_FIELD(insn, 2, 6);
6ae20372 2481
cf495bcf 2482 switch (opc) {
0f8a249a
BS		 2483 case 0: /* branches/sethi */
2484 {
2485 unsigned int xop = GET_FIELD(insn, 7, 9);
2486 int32_t target;
2487 switch (xop) {
3475187d 2488#ifdef TARGET_SPARC64
0f8a249a
BS		 2489 case 0x1: /* V9 BPcc */
2490 {
2491 int cc;
2492
2493 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 2494 target = sign_extend(target, 19);
0f8a249a
BS		 2495 target <<= 2;
2496 cc = GET_FIELD_SP(insn, 20, 21);
2497 if (cc == 0)
d4a288ef 2498 do_branch(dc, target, insn, 0);
0f8a249a 2499 else if (cc == 2)
d4a288ef 2500 do_branch(dc, target, insn, 1);
0f8a249a
BS		 2501 else
2502 goto illegal_insn;
2503 goto jmp_insn;
2504 }
2505 case 0x3: /* V9 BPr */
2506 {
2507 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 2508 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 2509 target = sign_extend(target, 16);
2510 target <<= 2;
9d1d4e34 2511 cpu_src1 = get_src1(dc, insn);
d4a288ef 2512 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 2513 goto jmp_insn;
2514 }
2515 case 0x5: /* V9 FBPcc */
2516 {
2517 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 2518 if (gen_trap_ifnofpu(dc)) {
a80dde08 2519 goto jmp_insn;
5b12f1e8 2520 }
0f8a249a
BS		 2521 target = GET_FIELD_SP(insn, 0, 18);
2522 target = sign_extend(target, 19);
2523 target <<= 2;
d4a288ef 2524 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 2525 goto jmp_insn;
2526 }
a4d17f19 2527#else
0f8a249a
BS		 2528 case 0x7: /* CBN+x */
2529 {
2530 goto ncp_insn;
2531 }
2532#endif
2533 case 0x2: /* BN+x */
2534 {
2535 target = GET_FIELD(insn, 10, 31);
2536 target = sign_extend(target, 22);
2537 target <<= 2;
d4a288ef 2538 do_branch(dc, target, insn, 0);
0f8a249a
BS		 2539 goto jmp_insn;
2540 }
2541 case 0x6: /* FBN+x */
2542 {
5b12f1e8 2543 if (gen_trap_ifnofpu(dc)) {
a80dde08 2544 goto jmp_insn;
5b12f1e8 2545 }
0f8a249a
BS		 2546 target = GET_FIELD(insn, 10, 31);
2547 target = sign_extend(target, 22);
2548 target <<= 2;
d4a288ef 2549 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 2550 goto jmp_insn;
2551 }
2552 case 0x4: /* SETHI */
97ea2859
RH		 2553 /* Special-case %g0 because that's the canonical nop. */
2554 if (rd) {
0f8a249a 2555 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 2556 TCGv t = gen_dest_gpr(dc, rd);
2557 tcg_gen_movi_tl(t, value << 10);
2558 gen_store_gpr(dc, rd, t);
0f8a249a 2559 }
0f8a249a
BS		 2560 break;
2561 case 0x0: /* UNIMPL */
2562 default:
3475187d 2563 goto illegal_insn;
0f8a249a
BS		 2564 }
2565 break;
2566 }
2567 break;
dc1a6971
BS		 2568 case 1: /*CALL*/
2569 {
0f8a249a 2570 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 2571 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 2572
97ea2859
RH		 2573 tcg_gen_movi_tl(o7, dc->pc);
2574 gen_store_gpr(dc, 15, o7);
0f8a249a 2575 target += dc->pc;
13a6dd00 2576 gen_mov_pc_npc(dc);
22036a49
AT		 2577#ifdef TARGET_SPARC64
2578 if (unlikely(AM_CHECK(dc))) {
2579 target &= 0xffffffffULL;
2580 }
2581#endif
0f8a249a
BS		 2582 dc->npc = target;
2583 }
2584 goto jmp_insn;
2585 case 2: /* FPU & Logical Operations */
2586 {
2587 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 2588 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 2589 TCGv cpu_tmp0;
5793f2a4 2590
0f8a249a 2591 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 2592 int cond = GET_FIELD(insn, 3, 6);
2593 TCGv_i32 trap;
42a268c2
RH		 2594 TCGLabel *l1 = NULL;
2595 int mask;
3475187d 2596
bd49ed41
RH		 2597 if (cond == 0) {
2598 /* Trap never. */
2599 break;
cf495bcf 2600 }
b04d9890 2601
bd49ed41 2602 save_state(dc);
b04d9890 2603
bd49ed41
RH		 2604 if (cond != 8) {
2605 /* Conditional trap. */
3a49e759 2606 DisasCompare cmp;
3475187d 2607#ifdef TARGET_SPARC64
0f8a249a
BS		 2608 /* V9 icc/xcc */
2609 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 2610 if (cc == 0) {
2611 gen_compare(&cmp, 0, cond, dc);
2612 } else if (cc == 2) {
2613 gen_compare(&cmp, 1, cond, dc);
2614 } else {
0f8a249a 2615 goto illegal_insn;
3a49e759 2616 }
3475187d 2617#else
3a49e759 2618 gen_compare(&cmp, 0, cond, dc);
3475187d 2619#endif
b158a785 2620 l1 = gen_new_label();
3a49e759
RH		 2621 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
2622 cmp.c1, cmp.c2, l1);
2623 free_compare(&cmp);
bd49ed41 2624 }
b158a785 2625
bd49ed41
RH		 2626 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
2627 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
2628
2629 /* Don't use the normal temporaries, as they may well have
2630 gone out of scope with the branch above. While we're
2631 doing that we might as well pre-truncate to 32-bit. */
2632 trap = tcg_temp_new_i32();
2633
2634 rs1 = GET_FIELD_SP(insn, 14, 18);
2635 if (IS_IMM) {
2636 rs2 = GET_FIELD_SP(insn, 0, 6);
2637 if (rs1 == 0) {
2638 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
2639 /* Signal that the trap value is fully constant. */
2640 mask = 0;
2641 } else {
97ea2859 2642 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 2643 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2644 tcg_gen_addi_i32(trap, trap, rs2);
2645 }
2646 } else {
97ea2859 2647 TCGv t1, t2;
bd49ed41 2648 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 2649 t1 = gen_load_gpr(dc, rs1);
2650 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 2651 tcg_gen_add_tl(t1, t1, t2);
2652 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 2653 }
2654 if (mask != 0) {
2655 tcg_gen_andi_i32(trap, trap, mask);
2656 tcg_gen_addi_i32(trap, trap, TT_TRAP);
2657 }
2658
2659 gen_helper_raise_exception(cpu_env, trap);
2660 tcg_temp_free_i32(trap);
b158a785 2661
fe1755cb
RH		 2662 if (cond == 8) {
2663 /* An unconditional trap ends the TB. */
2664 dc->is_br = 1;
2665 goto jmp_insn;
2666 } else {
2667 /* A conditional trap falls through to the next insn. */
b158a785 2668 gen_set_label(l1);
fe1755cb 2669 break;
cf495bcf
FB		 2670 }
2671 } else if (xop == 0x28) {
2672 rs1 = GET_FIELD(insn, 13, 17);
2673 switch(rs1) {
2674 case 0: /* rdy */
65fe7b09
BS		 2675#ifndef TARGET_SPARC64
2676 case 0x01 ... 0x0e: /* undefined in the SPARCv8
2677 manual, rdy on the microSPARC
2678 II */
2679 case 0x0f: /* stbar in the SPARCv8 manual,
2680 rdy on the microSPARC II */
2681 case 0x10 ... 0x1f: /* implementation-dependent in the
2682 SPARCv8 manual, rdy on the
2683 microSPARC II */
4a2ba232
FC		 2684 /* Read Asr17 */
2685 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 2686 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 2687 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 2688 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
2689 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 2690 break;
2691 }
65fe7b09 2692#endif
97ea2859 2693 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 2694 break;
3475187d 2695#ifdef TARGET_SPARC64
0f8a249a 2696 case 0x2: /* V9 rdccr */
20132b96 2697 update_psr(dc);
063c3675 2698 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 2699 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2700 break;
0f8a249a 2701 case 0x3: /* V9 rdasi */
255e1fcb 2702 tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
97ea2859 2703 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2704 break;
0f8a249a 2705 case 0x4: /* V9 rdtick */
ccd4a219 2706 {
a7812ae4 2707 TCGv_ptr r_tickptr;
c9a46442 2708 TCGv_i32 r_const;
ccd4a219 2709
a7812ae4 2710 r_tickptr = tcg_temp_new_ptr();
c9a46442 2711 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2712 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2713 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 2714 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2715 r_const);
a7812ae4 2716 tcg_temp_free_ptr(r_tickptr);
c9a46442 2717 tcg_temp_free_i32(r_const);
97ea2859 2718 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2719 }
3475187d 2720 break;
0f8a249a 2721 case 0x5: /* V9 rdpc */
2ea815ca 2722 {
97ea2859 2723 TCGv t = gen_dest_gpr(dc, rd);
22036a49 2724 if (unlikely(AM_CHECK(dc))) {
97ea2859 2725 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 2726 } else {
97ea2859 2727 tcg_gen_movi_tl(t, dc->pc);
22036a49 2728 }
97ea2859 2729 gen_store_gpr(dc, rd, t);
2ea815ca 2730 }
0f8a249a
BS		 2731 break;
2732 case 0x6: /* V9 rdfprs */
255e1fcb 2733 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 2734 gen_store_gpr(dc, rd, cpu_dst);
3475187d 2735 break;
65fe7b09
BS		 2736 case 0xf: /* V9 membar */
2737 break; /* no effect */
0f8a249a 2738 case 0x13: /* Graphics Status */
5b12f1e8 2739 if (gen_trap_ifnofpu(dc)) {
725cb90b 2740 goto jmp_insn;
5b12f1e8 2741 }
97ea2859 2742 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 2743 break;
9d926598
BS		 2744 case 0x16: /* Softint */
2745 tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
97ea2859 2746 gen_store_gpr(dc, rd, cpu_dst);
9d926598 2747 break;
0f8a249a 2748 case 0x17: /* Tick compare */
97ea2859 2749 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 2750 break;
0f8a249a 2751 case 0x18: /* System tick */
ccd4a219 2752 {
a7812ae4 2753 TCGv_ptr r_tickptr;
c9a46442 2754 TCGv_i32 r_const;
ccd4a219 2755
a7812ae4 2756 r_tickptr = tcg_temp_new_ptr();
c9a46442 2757 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2758 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2759 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 2760 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
2761 r_const);
a7812ae4 2762 tcg_temp_free_ptr(r_tickptr);
c9a46442 2763 tcg_temp_free_i32(r_const);
97ea2859 2764 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 2765 }
83469015 2766 break;
0f8a249a 2767 case 0x19: /* System tick compare */
97ea2859 2768 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 2769 break;
0f8a249a
BS		 2770 case 0x10: /* Performance Control */
2771 case 0x11: /* Performance Instrumentation Counter */
2772 case 0x12: /* Dispatch Control */
2773 case 0x14: /* Softint set, WO */
2774 case 0x15: /* Softint clear, WO */
3475187d
FB		 2775#endif
2776 default:
cf495bcf
FB		 2777 goto illegal_insn;
2778 }
e8af50a3 2779#if !defined(CONFIG_USER_ONLY)
e9ebed4d 2780 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 2781#ifndef TARGET_SPARC64
20132b96 2782 if (!supervisor(dc)) {
0f8a249a 2783 goto priv_insn;
20132b96
RH		 2784 }
2785 update_psr(dc);
063c3675 2786 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 2787#else
fb79ceb9 2788 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2789 if (!hypervisor(dc))
2790 goto priv_insn;
2791 rs1 = GET_FIELD(insn, 13, 17);
2792 switch (rs1) {
2793 case 0: // hpstate
2794 // gen_op_rdhpstate();
2795 break;
2796 case 1: // htstate
2797 // gen_op_rdhtstate();
2798 break;
2799 case 3: // hintp
255e1fcb 2800 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 2801 break;
2802 case 5: // htba
255e1fcb 2803 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 2804 break;
2805 case 6: // hver
255e1fcb 2806 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 2807 break;
2808 case 31: // hstick_cmpr
255e1fcb 2809 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 2810 break;
2811 default:
2812 goto illegal_insn;
2813 }
2814#endif
97ea2859 2815 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 2816 break;
3475187d 2817 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 2818 if (!supervisor(dc)) {
0f8a249a 2819 goto priv_insn;
de9e9d9f
RH		 2820 }
2821 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 2822#ifdef TARGET_SPARC64
2823 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2824 switch (rs1) {
2825 case 0: // tpc
375ee38b 2826 {
a7812ae4 2827 TCGv_ptr r_tsptr;
375ee38b 2828
a7812ae4 2829 r_tsptr = tcg_temp_new_ptr();
8194f35a 2830 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 2831 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2832 offsetof(trap_state, tpc));
a7812ae4 2833 tcg_temp_free_ptr(r_tsptr);
375ee38b 2834 }
0f8a249a
BS		 2835 break;
2836 case 1: // tnpc
375ee38b 2837 {
a7812ae4 2838 TCGv_ptr r_tsptr;
375ee38b 2839
a7812ae4 2840 r_tsptr = tcg_temp_new_ptr();
8194f35a 2841 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2842 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2843 offsetof(trap_state, tnpc));
a7812ae4 2844 tcg_temp_free_ptr(r_tsptr);
375ee38b 2845 }
0f8a249a
BS		 2846 break;
2847 case 2: // tstate
375ee38b 2848 {
a7812ae4 2849 TCGv_ptr r_tsptr;
375ee38b 2850
a7812ae4 2851 r_tsptr = tcg_temp_new_ptr();
8194f35a 2852 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 2853 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 2854 offsetof(trap_state, tstate));
a7812ae4 2855 tcg_temp_free_ptr(r_tsptr);
375ee38b 2856 }
0f8a249a
BS		 2857 break;
2858 case 3: // tt
375ee38b 2859 {
45778f99 2860 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 2861
8194f35a 2862 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 2863 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
2864 offsetof(trap_state, tt));
a7812ae4 2865 tcg_temp_free_ptr(r_tsptr);
375ee38b 2866 }
0f8a249a
BS		 2867 break;
2868 case 4: // tick
ccd4a219 2869 {
a7812ae4 2870 TCGv_ptr r_tickptr;
c9a46442 2871 TCGv_i32 r_const;
ccd4a219 2872
a7812ae4 2873 r_tickptr = tcg_temp_new_ptr();
c9a46442 2874 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 2875 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 2876 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 2877 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
2878 r_tickptr, r_const);
a7812ae4 2879 tcg_temp_free_ptr(r_tickptr);
c9a46442 2880 tcg_temp_free_i32(r_const);
ccd4a219 2881 }
0f8a249a
BS		 2882 break;
2883 case 5: // tba
255e1fcb 2884 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 2885 break;
2886 case 6: // pstate
45778f99
RH		 2887 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2888 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 2889 break;
2890 case 7: // tl
45778f99
RH		 2891 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2892 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 2893 break;
2894 case 8: // pil
45778f99
RH		 2895 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2896 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 2897 break;
2898 case 9: // cwp
063c3675 2899 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 2900 break;
2901 case 10: // cansave
45778f99
RH		 2902 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2903 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 2904 break;
2905 case 11: // canrestore
45778f99
RH		 2906 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2907 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 2908 break;
2909 case 12: // cleanwin
45778f99
RH		 2910 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2911 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 2912 break;
2913 case 13: // otherwin
45778f99
RH		 2914 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2915 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 2916 break;
2917 case 14: // wstate
45778f99
RH		 2918 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2919 offsetof(CPUSPARCState, wstate));
0f8a249a 2920 break;
e9ebed4d 2921 case 16: // UA2005 gl
fb79ceb9 2922 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 2923 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
2924 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 2925 break;
2926 case 26: // UA2005 strand status
fb79ceb9 2927 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 2928 if (!hypervisor(dc))
2929 goto priv_insn;
527067d8 2930 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 2931 break;
0f8a249a 2932 case 31: // ver
255e1fcb 2933 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 2934 break;
2935 case 15: // fq
2936 default:
2937 goto illegal_insn;
2938 }
3475187d 2939#else
255e1fcb 2940 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 2941#endif
97ea2859 2942 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 2943 break;
3475187d
FB		 2944 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2945#ifdef TARGET_SPARC64
66442b07 2946 save_state(dc);
063c3675 2947 gen_helper_flushw(cpu_env);
3475187d 2948#else
0f8a249a
BS		 2949 if (!supervisor(dc))
2950 goto priv_insn;
97ea2859 2951 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 2952#endif
e8af50a3
FB		 2953 break;
2954#endif
0f8a249a 2955 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 2956 if (gen_trap_ifnofpu(dc)) {
a80dde08 2957 goto jmp_insn;
5b12f1e8 2958 }
0f8a249a 2959 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 2960 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 2961 rs2 = GET_FIELD(insn, 27, 31);
2962 xop = GET_FIELD(insn, 18, 26);
66442b07 2963 save_state(dc);
0f8a249a 2964 switch (xop) {
dc1a6971 2965 case 0x1: /* fmovs */
208ae657
RH		 2966 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
2967 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 2968 break;
2969 case 0x5: /* fnegs */
61f17f6e 2970 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 2971 break;
2972 case 0x9: /* fabss */
61f17f6e 2973 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 2974 break;
2975 case 0x29: /* fsqrts */
2976 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2977 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 2978 break;
2979 case 0x2a: /* fsqrtd */
2980 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 2981 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 2982 break;
2983 case 0x2b: /* fsqrtq */
2984 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2985 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 2986 break;
2987 case 0x41: /* fadds */
61f17f6e 2988 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 2989 break;
2990 case 0x42: /* faddd */
61f17f6e 2991 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 2992 break;
2993 case 0x43: /* faddq */
2994 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 2995 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 2996 break;
2997 case 0x45: /* fsubs */
61f17f6e 2998 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 2999 break;
3000 case 0x46: /* fsubd */
61f17f6e 3001 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3002 break;
3003 case 0x47: /* fsubq */
3004 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3005 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3006 break;
3007 case 0x49: /* fmuls */
3008 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3009 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3010 break;
3011 case 0x4a: /* fmuld */
3012 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3013 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3014 break;
3015 case 0x4b: /* fmulq */
3016 CHECK_FPU_FEATURE(dc, FLOAT128);
3017 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3018 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3019 break;
3020 case 0x4d: /* fdivs */
61f17f6e 3021 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3022 break;
3023 case 0x4e: /* fdivd */
61f17f6e 3024 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3025 break;
3026 case 0x4f: /* fdivq */
3027 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3028 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3029 break;
3030 case 0x69: /* fsmuld */
3031 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3032 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3033 break;
3034 case 0x6e: /* fdmulq */
3035 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3036 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3037 break;
3038 case 0xc4: /* fitos */
61f17f6e 3039 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3040 break;
3041 case 0xc6: /* fdtos */
61f17f6e 3042 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3043 break;
3044 case 0xc7: /* fqtos */
3045 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3046 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3047 break;
3048 case 0xc8: /* fitod */
61f17f6e 3049 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3050 break;
3051 case 0xc9: /* fstod */
61f17f6e 3052 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3053 break;
3054 case 0xcb: /* fqtod */
3055 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3056 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3057 break;
3058 case 0xcc: /* fitoq */
3059 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3060 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3061 break;
3062 case 0xcd: /* fstoq */
3063 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3064 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3065 break;
3066 case 0xce: /* fdtoq */
3067 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3068 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3069 break;
3070 case 0xd1: /* fstoi */
61f17f6e 3071 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3072 break;
3073 case 0xd2: /* fdtoi */
61f17f6e 3074 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3075 break;
3076 case 0xd3: /* fqtoi */
3077 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3078 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3079 break;
3475187d 3080#ifdef TARGET_SPARC64
dc1a6971 3081 case 0x2: /* V9 fmovd */
96eda024
RH		 3082 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3083 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3084 break;
3085 case 0x3: /* V9 fmovq */
3086 CHECK_FPU_FEATURE(dc, FLOAT128);
ac11f776 3087 gen_move_Q(rd, rs2);
dc1a6971
BS		 3088 break;
3089 case 0x6: /* V9 fnegd */
61f17f6e 3090 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3091 break;
3092 case 0x7: /* V9 fnegq */
3093 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3094 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3095 break;
3096 case 0xa: /* V9 fabsd */
61f17f6e 3097 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3098 break;
3099 case 0xb: /* V9 fabsq */
3100 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3101 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3102 break;
3103 case 0x81: /* V9 fstox */
61f17f6e 3104 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3105 break;
3106 case 0x82: /* V9 fdtox */
61f17f6e 3107 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3108 break;
3109 case 0x83: /* V9 fqtox */
3110 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3111 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3112 break;
3113 case 0x84: /* V9 fxtos */
61f17f6e 3114 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3115 break;
3116 case 0x88: /* V9 fxtod */
61f17f6e 3117 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3118 break;
3119 case 0x8c: /* V9 fxtoq */
3120 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3121 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3122 break;
0f8a249a 3123#endif
dc1a6971
BS		 3124 default:
3125 goto illegal_insn;
0f8a249a
BS		 3126 }
3127 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3128#ifdef TARGET_SPARC64
0f8a249a 3129 int cond;
3475187d 3130#endif
5b12f1e8 3131 if (gen_trap_ifnofpu(dc)) {
a80dde08 3132 goto jmp_insn;
5b12f1e8 3133 }
0f8a249a 3134 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3135 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3136 rs2 = GET_FIELD(insn, 27, 31);
3137 xop = GET_FIELD(insn, 18, 26);
66442b07 3138 save_state(dc);
dcf24905 3139
690995a6
RH		 3140#ifdef TARGET_SPARC64
3141#define FMOVR(sz) \
3142 do { \
3143 DisasCompare cmp; \
e7c8afb9 3144 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3145 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3146 gen_compare_reg(&cmp, cond, cpu_src1); \
3147 gen_fmov##sz(dc, &cmp, rd, rs2); \
3148 free_compare(&cmp); \
3149 } while (0)
3150
3151 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3152 FMOVR(s);
0f8a249a
BS		 3153 break;
3154 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3155 FMOVR(d);
0f8a249a
BS		 3156 break;
3157 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3158 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3159 FMOVR(q);
1f587329 3160 break;
0f8a249a 3161 }
690995a6 3162#undef FMOVR
0f8a249a
BS		 3163#endif
3164 switch (xop) {
3475187d 3165#ifdef TARGET_SPARC64
7e480893
RH		 3166#define FMOVCC(fcc, sz) \
3167 do { \
3168 DisasCompare cmp; \
714547bb 3169 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3170 gen_fcompare(&cmp, fcc, cond); \
3171 gen_fmov##sz(dc, &cmp, rd, rs2); \
3172 free_compare(&cmp); \
3173 } while (0)
3174
0f8a249a 3175 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3176 FMOVCC(0, s);
0f8a249a
BS		 3177 break;
3178 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3179 FMOVCC(0, d);
0f8a249a
BS		 3180 break;
3181 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3182 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3183 FMOVCC(0, q);
1f587329 3184 break;
0f8a249a 3185 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3186 FMOVCC(1, s);
0f8a249a
BS		 3187 break;
3188 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3189 FMOVCC(1, d);
0f8a249a
BS		 3190 break;
3191 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3192 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3193 FMOVCC(1, q);
1f587329 3194 break;
0f8a249a 3195 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3196 FMOVCC(2, s);
0f8a249a
BS		 3197 break;
3198 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3199 FMOVCC(2, d);
0f8a249a
BS		 3200 break;
3201 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3202 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3203 FMOVCC(2, q);
1f587329 3204 break;
0f8a249a 3205 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3206 FMOVCC(3, s);
0f8a249a
BS		 3207 break;
3208 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3209 FMOVCC(3, d);
0f8a249a
BS		 3210 break;
3211 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3212 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3213 FMOVCC(3, q);
1f587329 3214 break;
7e480893
RH		 3215#undef FMOVCC
3216#define FMOVCC(xcc, sz) \
3217 do { \
3218 DisasCompare cmp; \
714547bb 3219 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3220 gen_compare(&cmp, xcc, cond, dc); \
3221 gen_fmov##sz(dc, &cmp, rd, rs2); \
3222 free_compare(&cmp); \
3223 } while (0)
19f329ad 3224
0f8a249a 3225 case 0x101: /* V9 fmovscc %icc */
7e480893 3226 FMOVCC(0, s);
0f8a249a
BS		 3227 break;
3228 case 0x102: /* V9 fmovdcc %icc */
7e480893 3229 FMOVCC(0, d);
b7d69dc2 3230 break;
0f8a249a 3231 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3232 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3233 FMOVCC(0, q);
1f587329 3234 break;
0f8a249a 3235 case 0x181: /* V9 fmovscc %xcc */
7e480893 3236 FMOVCC(1, s);
0f8a249a
BS		 3237 break;
3238 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3239 FMOVCC(1, d);
0f8a249a
BS		 3240 break;
3241 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3242 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3243 FMOVCC(1, q);
1f587329 3244 break;
7e480893 3245#undef FMOVCC
1f587329
BS		 3246#endif
3247 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3248 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3249 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3250 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3251 break;
1f587329 3252 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3253 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3254 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3255 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3256 break;
1f587329 3257 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3258 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3259 gen_op_load_fpr_QT0(QFPREG(rs1));
3260 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3261 gen_op_fcmpq(rd & 3);
1f587329 3262 break;
0f8a249a 3263 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3264 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3265 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3266 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3267 break;
3268 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3269 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3270 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3271 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3272 break;
1f587329 3273 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3274 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3275 gen_op_load_fpr_QT0(QFPREG(rs1));
3276 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3277 gen_op_fcmpeq(rd & 3);
1f587329 3278 break;
0f8a249a
BS		 3279 default:
3280 goto illegal_insn;
3281 }
0f8a249a 3282 } else if (xop == 0x2) {
97ea2859 3283 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3284 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3285 if (rs1 == 0) {
97ea2859 3286 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3287 if (IS_IMM) { /* immediate */
67526b20 3288 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3289 tcg_gen_movi_tl(dst, simm);
3290 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3291 } else { /* register */
3292 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3293 if (rs2 == 0) {
3294 tcg_gen_movi_tl(dst, 0);
3295 gen_store_gpr(dc, rd, dst);
3296 } else {
3297 cpu_src2 = gen_load_gpr(dc, rs2);
3298 gen_store_gpr(dc, rd, cpu_src2);
3299 }
0f8a249a 3300 }
0f8a249a 3301 } else {
9d1d4e34 3302 cpu_src1 = get_src1(dc, insn);
0f8a249a 3303 if (IS_IMM) { /* immediate */
67526b20 3304 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3305 tcg_gen_ori_tl(dst, cpu_src1, simm);
3306 gen_store_gpr(dc, rd, dst);
0f8a249a 3307 } else { /* register */
0f8a249a 3308 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3309 if (rs2 == 0) {
3310 /* mov shortcut: or x, %g0, y -> mov x, y */
3311 gen_store_gpr(dc, rd, cpu_src1);
3312 } else {
3313 cpu_src2 = gen_load_gpr(dc, rs2);
3314 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
3315 gen_store_gpr(dc, rd, dst);
3316 }
0f8a249a 3317 }
0f8a249a 3318 }
83469015 3319#ifdef TARGET_SPARC64
0f8a249a 3320 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 3321 cpu_src1 = get_src1(dc, insn);
0f8a249a 3322 if (IS_IMM) { /* immediate */
67526b20 3323 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3324 if (insn & (1 << 12)) {
67526b20 3325 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3326 } else {
67526b20 3327 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 3328 }
0f8a249a 3329 } else { /* register */
83469015 3330 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3331 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3332 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3333 if (insn & (1 << 12)) {
6ae20372 3334 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 3335 } else {
6ae20372 3336 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 3337 }
01b1fa6d 3338 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 3339 }
97ea2859 3340 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3341 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 3342 cpu_src1 = get_src1(dc, insn);
0f8a249a 3343 if (IS_IMM) { /* immediate */
67526b20 3344 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3345 if (insn & (1 << 12)) {
67526b20 3346 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3347 } else {
6ae20372 3348 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 3349 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3350 }
0f8a249a 3351 } else { /* register */
83469015 3352 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3353 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3354 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3355 if (insn & (1 << 12)) {
6ae20372
BS		 3356 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3357 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3358 } else {
6ae20372
BS		 3359 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3360 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3361 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3362 }
83469015 3363 }
97ea2859 3364 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 3365 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 3366 cpu_src1 = get_src1(dc, insn);
0f8a249a 3367 if (IS_IMM) { /* immediate */
67526b20 3368 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 3369 if (insn & (1 << 12)) {
67526b20 3370 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 3371 } else {
97ea2859 3372 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 3373 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 3374 }
0f8a249a 3375 } else { /* register */
83469015 3376 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 3377 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 3378 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 3379 if (insn & (1 << 12)) {
6ae20372
BS		 3380 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3381 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 3382 } else {
6ae20372 3383 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 3384 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 3385 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 3386 }
83469015 3387 }
97ea2859 3388 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 3389#endif
fcc72045 3390 } else if (xop < 0x36) {
cf495bcf 3391 if (xop < 0x20) {
9d1d4e34
RH		 3392 cpu_src1 = get_src1(dc, insn);
3393 cpu_src2 = get_src2(dc, insn);
cf495bcf 3394 switch (xop & ~0x10) {
b89e94af 3395 case 0x0: /* add */
97ea2859
RH		 3396 if (xop & 0x10) {
3397 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
3398 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3399 dc->cc_op = CC_OP_ADD;
41d72852 3400 } else {
97ea2859 3401 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3402 }
cf495bcf 3403 break;
b89e94af 3404 case 0x1: /* and */
97ea2859 3405 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3406 if (xop & 0x10) {
38482a77
BS		 3407 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3408 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3409 dc->cc_op = CC_OP_LOGIC;
41d72852 3410 }
cf495bcf 3411 break;
b89e94af 3412 case 0x2: /* or */
97ea2859 3413 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3414 if (xop & 0x10) {
38482a77
BS		 3415 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3416 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3417 dc->cc_op = CC_OP_LOGIC;
8393617c 3418 }
0f8a249a 3419 break;
b89e94af 3420 case 0x3: /* xor */
97ea2859 3421 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3422 if (xop & 0x10) {
38482a77
BS		 3423 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3424 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3425 dc->cc_op = CC_OP_LOGIC;
8393617c 3426 }
cf495bcf 3427 break;
b89e94af 3428 case 0x4: /* sub */
97ea2859
RH		 3429 if (xop & 0x10) {
3430 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3431 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3432 dc->cc_op = CC_OP_SUB;
41d72852 3433 } else {
97ea2859 3434 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 3435 }
cf495bcf 3436 break;
b89e94af 3437 case 0x5: /* andn */
97ea2859 3438 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3439 if (xop & 0x10) {
38482a77
BS		 3440 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3441 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3442 dc->cc_op = CC_OP_LOGIC;
8393617c 3443 }
cf495bcf 3444 break;
b89e94af 3445 case 0x6: /* orn */
97ea2859 3446 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3447 if (xop & 0x10) {
38482a77
BS		 3448 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3449 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3450 dc->cc_op = CC_OP_LOGIC;
8393617c 3451 }
cf495bcf 3452 break;
b89e94af 3453 case 0x7: /* xorn */
97ea2859 3454 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 3455 if (xop & 0x10) {
38482a77
BS		 3456 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3457 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3458 dc->cc_op = CC_OP_LOGIC;
8393617c 3459 }
cf495bcf 3460 break;
b89e94af 3461 case 0x8: /* addx, V9 addc */
70c48285
RH		 3462 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3463 (xop & 0x10));
cf495bcf 3464 break;
ded3ab80 3465#ifdef TARGET_SPARC64
0f8a249a 3466 case 0x9: /* V9 mulx */
97ea2859 3467 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 3468 break;
3469#endif
b89e94af 3470 case 0xa: /* umul */
64a88d5d 3471 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3472 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3473 if (xop & 0x10) {
38482a77
BS		 3474 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3475 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3476 dc->cc_op = CC_OP_LOGIC;
8393617c 3477 }
cf495bcf 3478 break;
b89e94af 3479 case 0xb: /* smul */
64a88d5d 3480 CHECK_IU_FEATURE(dc, MUL);
6ae20372 3481 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 3482 if (xop & 0x10) {
38482a77
BS		 3483 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
3484 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
3485 dc->cc_op = CC_OP_LOGIC;
8393617c 3486 }
cf495bcf 3487 break;
b89e94af 3488 case 0xc: /* subx, V9 subc */
70c48285
RH		 3489 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
3490 (xop & 0x10));
cf495bcf 3491 break;
ded3ab80 3492#ifdef TARGET_SPARC64
0f8a249a 3493 case 0xd: /* V9 udivx */
c28ae41e 3494 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 3495 break;
3496#endif
b89e94af 3497 case 0xe: /* udiv */
64a88d5d 3498 CHECK_IU_FEATURE(dc, DIV);
8393617c 3499 if (xop & 0x10) {
7a5e4488
BS		 3500 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
3501 cpu_src2);
6c78ea32 3502 dc->cc_op = CC_OP_DIV;
0fcec41e 3503 } else {
7a5e4488
BS		 3504 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
3505 cpu_src2);
8393617c 3506 }
cf495bcf 3507 break;
b89e94af 3508 case 0xf: /* sdiv */
64a88d5d 3509 CHECK_IU_FEATURE(dc, DIV);
8393617c 3510 if (xop & 0x10) {
7a5e4488
BS		 3511 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
3512 cpu_src2);
6c78ea32 3513 dc->cc_op = CC_OP_DIV;
0fcec41e 3514 } else {
7a5e4488
BS		 3515 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
3516 cpu_src2);
8393617c 3517 }
cf495bcf
FB		 3518 break;
3519 default:
3520 goto illegal_insn;
3521 }
97ea2859 3522 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3523 } else {
9d1d4e34
RH		 3524 cpu_src1 = get_src1(dc, insn);
3525 cpu_src2 = get_src2(dc, insn);
cf495bcf 3526 switch (xop) {
0f8a249a 3527 case 0x20: /* taddcc */
a2ea4aa9 3528 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3529 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3530 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
3531 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 3532 break;
3533 case 0x21: /* tsubcc */
a2ea4aa9 3534 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3535 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 3536 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
3537 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 3538 break;
3539 case 0x22: /* taddcctv */
a2ea4aa9
RH		 3540 gen_helper_taddcctv(cpu_dst, cpu_env,
3541 cpu_src1, cpu_src2);
97ea2859 3542 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3543 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 3544 break;
3545 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 3546 gen_helper_tsubcctv(cpu_dst, cpu_env,
3547 cpu_src1, cpu_src2);
97ea2859 3548 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 3549 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 3550 break;
cf495bcf 3551 case 0x24: /* mulscc */
20132b96 3552 update_psr(dc);
6ae20372 3553 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 3554 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 3555 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
3556 dc->cc_op = CC_OP_ADD;
cf495bcf 3557 break;
83469015 3558#ifndef TARGET_SPARC64
0f8a249a 3559 case 0x25: /* sll */
e35298cd 3560 if (IS_IMM) { /* immediate */
67526b20
BS		 3561 simm = GET_FIELDs(insn, 20, 31);
3562 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3563 } else { /* register */
de9e9d9f 3564 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3565 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3566 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3567 }
97ea2859 3568 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3569 break;
83469015 3570 case 0x26: /* srl */
e35298cd 3571 if (IS_IMM) { /* immediate */
67526b20
BS		 3572 simm = GET_FIELDs(insn, 20, 31);
3573 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3574 } else { /* register */
de9e9d9f 3575 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3576 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3577 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3578 }
97ea2859 3579 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3580 break;
83469015 3581 case 0x27: /* sra */
e35298cd 3582 if (IS_IMM) { /* immediate */
67526b20
BS		 3583 simm = GET_FIELDs(insn, 20, 31);
3584 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 3585 } else { /* register */
de9e9d9f 3586 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 3587 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3588 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3589 }
97ea2859 3590 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 3591 break;
83469015 3592#endif
cf495bcf
FB		 3593 case 0x30:
3594 {
de9e9d9f 3595 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 3596 switch(rd) {
3475187d 3597 case 0: /* wry */
5068cbd9
BS		 3598 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3599 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 3600 break;
65fe7b09
BS		 3601#ifndef TARGET_SPARC64
3602 case 0x01 ... 0x0f: /* undefined in the
3603 SPARCv8 manual, nop
3604 on the microSPARC
3605 II */
3606 case 0x10 ... 0x1f: /* implementation-dependent
3607 in the SPARCv8
3608 manual, nop on the
3609 microSPARC II */
d1c36ba7
RH		 3610 if ((rd == 0x13) && (dc->def->features &
3611 CPU_FEATURE_POWERDOWN)) {
3612 /* LEON3 power-down */
1cf892ca 3613 save_state(dc);
d1c36ba7
RH		 3614 gen_helper_power_down(cpu_env);
3615 }
65fe7b09
BS		 3616 break;
3617#else
0f8a249a 3618 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 3619 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3620 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 3621 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3622 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 3623 break;
3624 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 3625 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3626 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
3627 tcg_gen_trunc_tl_i32(cpu_asi, cpu_tmp0);
0f8a249a
BS		 3628 break;
3629 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 3630 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3631 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
66442b07 3632 save_state(dc);
3299908c 3633 gen_op_next_insn();
57fec1fe 3634 tcg_gen_exit_tb(0);
3299908c 3635 dc->is_br = 1;
0f8a249a
BS		 3636 break;
3637 case 0xf: /* V9 sir, nop if user */
3475187d 3638#if !defined(CONFIG_USER_ONLY)
6ad6135d 3639 if (supervisor(dc)) {
1a2fb1c0 3640 ; // XXX
6ad6135d 3641 }
3475187d 3642#endif
0f8a249a
BS		 3643 break;
3644 case 0x13: /* Graphics Status */
5b12f1e8 3645 if (gen_trap_ifnofpu(dc)) {
725cb90b 3646 goto jmp_insn;
5b12f1e8 3647 }
255e1fcb 3648 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 3649 break;
9d926598
BS		 3650 case 0x14: /* Softint set */
3651 if (!supervisor(dc))
3652 goto illegal_insn;
aeff993c
RH		 3653 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3654 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3655 break;
3656 case 0x15: /* Softint clear */
3657 if (!supervisor(dc))
3658 goto illegal_insn;
aeff993c
RH		 3659 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3660 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 3661 break;
3662 case 0x16: /* Softint write */
3663 if (!supervisor(dc))
3664 goto illegal_insn;
aeff993c
RH		 3665 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3666 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 3667 break;
0f8a249a 3668 case 0x17: /* Tick compare */
83469015 3669#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3670 if (!supervisor(dc))
3671 goto illegal_insn;
83469015 3672#endif
ccd4a219 3673 {
a7812ae4 3674 TCGv_ptr r_tickptr;
ccd4a219 3675
255e1fcb 3676 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 3677 cpu_src2);
a7812ae4 3678 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3679 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3680 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3681 gen_helper_tick_set_limit(r_tickptr,
3682 cpu_tick_cmpr);
3683 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3684 }
0f8a249a
BS		 3685 break;
3686 case 0x18: /* System tick */
83469015 3687#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3688 if (!supervisor(dc))
3689 goto illegal_insn;
83469015 3690#endif
ccd4a219 3691 {
a7812ae4 3692 TCGv_ptr r_tickptr;
ccd4a219 3693
7b04bd5c 3694 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 3695 cpu_src2);
a7812ae4 3696 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3697 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3698 offsetof(CPUSPARCState, stick));
a7812ae4 3699 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 3700 cpu_tmp0);
a7812ae4 3701 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3702 }
0f8a249a
BS		 3703 break;
3704 case 0x19: /* System tick compare */
83469015 3705#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 3706 if (!supervisor(dc))
3707 goto illegal_insn;
3475187d 3708#endif
ccd4a219 3709 {
a7812ae4 3710 TCGv_ptr r_tickptr;
ccd4a219 3711
255e1fcb 3712 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 3713 cpu_src2);
a7812ae4 3714 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3715 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3716 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 3717 gen_helper_tick_set_limit(r_tickptr,
3718 cpu_stick_cmpr);
3719 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3720 }
0f8a249a 3721 break;
83469015 3722
0f8a249a 3723 case 0x10: /* Performance Control */
77f193da
BS		 3724 case 0x11: /* Performance Instrumentation
3725 Counter */
0f8a249a 3726 case 0x12: /* Dispatch Control */
83469015 3727#endif
3475187d 3728 default:
cf495bcf
FB		 3729 goto illegal_insn;
3730 }
3731 }
3732 break;
e8af50a3 3733#if !defined(CONFIG_USER_ONLY)
af7bf89b 3734 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 3735 {
0f8a249a
BS		 3736 if (!supervisor(dc))
3737 goto priv_insn;
3475187d 3738#ifdef TARGET_SPARC64
0f8a249a
BS		 3739 switch (rd) {
3740 case 0:
063c3675 3741 gen_helper_saved(cpu_env);
0f8a249a
BS		 3742 break;
3743 case 1:
063c3675 3744 gen_helper_restored(cpu_env);
0f8a249a 3745 break;
e9ebed4d
BS		 3746 case 2: /* UA2005 allclean */
3747 case 3: /* UA2005 otherw */
3748 case 4: /* UA2005 normalw */
3749 case 5: /* UA2005 invalw */
3750 // XXX
0f8a249a 3751 default:
3475187d
FB		 3752 goto illegal_insn;
3753 }
3754#else
de9e9d9f 3755 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 3756 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3757 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 3758 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3759 dc->cc_op = CC_OP_FLAGS;
66442b07 3760 save_state(dc);
9e61bde5 3761 gen_op_next_insn();
57fec1fe 3762 tcg_gen_exit_tb(0);
0f8a249a 3763 dc->is_br = 1;
3475187d 3764#endif
e8af50a3
FB		 3765 }
3766 break;
af7bf89b 3767 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 3768 {
0f8a249a
BS		 3769 if (!supervisor(dc))
3770 goto priv_insn;
de9e9d9f 3771 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3772 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 3773#ifdef TARGET_SPARC64
0f8a249a
BS		 3774 switch (rd) {
3775 case 0: // tpc
375ee38b 3776 {
a7812ae4 3777 TCGv_ptr r_tsptr;
375ee38b 3778
a7812ae4 3779 r_tsptr = tcg_temp_new_ptr();
8194f35a 3780 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3781 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3782 offsetof(trap_state, tpc));
a7812ae4 3783 tcg_temp_free_ptr(r_tsptr);
375ee38b 3784 }
0f8a249a
BS		 3785 break;
3786 case 1: // tnpc
375ee38b 3787 {
a7812ae4 3788 TCGv_ptr r_tsptr;
375ee38b 3789
a7812ae4 3790 r_tsptr = tcg_temp_new_ptr();
8194f35a 3791 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3792 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 3793 offsetof(trap_state, tnpc));
a7812ae4 3794 tcg_temp_free_ptr(r_tsptr);
375ee38b 3795 }
0f8a249a
BS		 3796 break;
3797 case 2: // tstate
375ee38b 3798 {
a7812ae4 3799 TCGv_ptr r_tsptr;
375ee38b 3800
a7812ae4 3801 r_tsptr = tcg_temp_new_ptr();
8194f35a 3802 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3803 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 3804 offsetof(trap_state,
3805 tstate));
a7812ae4 3806 tcg_temp_free_ptr(r_tsptr);
375ee38b 3807 }
0f8a249a
BS		 3808 break;
3809 case 3: // tt
375ee38b 3810 {
a7812ae4 3811 TCGv_ptr r_tsptr;
375ee38b 3812
a7812ae4 3813 r_tsptr = tcg_temp_new_ptr();
8194f35a 3814 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 3815 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
3816 offsetof(trap_state, tt));
a7812ae4 3817 tcg_temp_free_ptr(r_tsptr);
375ee38b 3818 }
0f8a249a
BS		 3819 break;
3820 case 4: // tick
ccd4a219 3821 {
a7812ae4 3822 TCGv_ptr r_tickptr;
ccd4a219 3823
a7812ae4 3824 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3825 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3826 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 3827 gen_helper_tick_set_count(r_tickptr,
3828 cpu_tmp0);
3829 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3830 }
0f8a249a
BS		 3831 break;
3832 case 5: // tba
255e1fcb 3833 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 3834 break;
3835 case 6: // pstate
6234ac09
RH		 3836 save_state(dc);
3837 gen_helper_wrpstate(cpu_env, cpu_tmp0);
3838 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3839 break;
3840 case 7: // tl
6234ac09 3841 save_state(dc);
7b9e066b 3842 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 3843 offsetof(CPUSPARCState, tl));
3844 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 3845 break;
3846 case 8: // pil
063c3675 3847 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 3848 break;
3849 case 9: // cwp
063c3675 3850 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 3851 break;
3852 case 10: // cansave
7b9e066b
RH		 3853 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3854 offsetof(CPUSPARCState,
3855 cansave));
0f8a249a
BS		 3856 break;
3857 case 11: // canrestore
7b9e066b
RH		 3858 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3859 offsetof(CPUSPARCState,
3860 canrestore));
0f8a249a
BS		 3861 break;
3862 case 12: // cleanwin
7b9e066b
RH		 3863 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3864 offsetof(CPUSPARCState,
3865 cleanwin));
0f8a249a
BS		 3866 break;
3867 case 13: // otherwin
7b9e066b
RH		 3868 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3869 offsetof(CPUSPARCState,
3870 otherwin));
0f8a249a
BS		 3871 break;
3872 case 14: // wstate
7b9e066b
RH		 3873 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3874 offsetof(CPUSPARCState,
3875 wstate));
0f8a249a 3876 break;
e9ebed4d 3877 case 16: // UA2005 gl
fb79ceb9 3878 CHECK_IU_FEATURE(dc, GL);
7b9e066b
RH		 3879 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
3880 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3881 break;
3882 case 26: // UA2005 strand status
fb79ceb9 3883 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3884 if (!hypervisor(dc))
3885 goto priv_insn;
527067d8 3886 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 3887 break;
0f8a249a
BS		 3888 default:
3889 goto illegal_insn;
3890 }
3475187d 3891#else
7b9e066b
RH		 3892 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
3893 if (dc->def->nwindows != 32) {
3894 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 3895 (1 << dc->def->nwindows) - 1);
7b9e066b 3896 }
3475187d 3897#endif
e8af50a3
FB		 3898 }
3899 break;
e9ebed4d 3900 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 3901 {
e9ebed4d 3902#ifndef TARGET_SPARC64
0f8a249a
BS		 3903 if (!supervisor(dc))
3904 goto priv_insn;
255e1fcb 3905 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 3906#else
fb79ceb9 3907 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3908 if (!hypervisor(dc))
3909 goto priv_insn;
de9e9d9f 3910 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 3911 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 3912 switch (rd) {
3913 case 0: // hpstate
3914 // XXX gen_op_wrhpstate();
66442b07 3915 save_state(dc);
e9ebed4d 3916 gen_op_next_insn();
57fec1fe 3917 tcg_gen_exit_tb(0);
e9ebed4d
BS		 3918 dc->is_br = 1;
3919 break;
3920 case 1: // htstate
3921 // XXX gen_op_wrhtstate();
3922 break;
3923 case 3: // hintp
255e1fcb 3924 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 3925 break;
3926 case 5: // htba
255e1fcb 3927 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 3928 break;
3929 case 31: // hstick_cmpr
ccd4a219 3930 {
a7812ae4 3931 TCGv_ptr r_tickptr;
ccd4a219 3932
255e1fcb 3933 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 3934 r_tickptr = tcg_temp_new_ptr();
ccd4a219 3935 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3936 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 3937 gen_helper_tick_set_limit(r_tickptr,
3938 cpu_hstick_cmpr);
3939 tcg_temp_free_ptr(r_tickptr);
ccd4a219 3940 }
e9ebed4d
BS		 3941 break;
3942 case 6: // hver readonly
3943 default:
3944 goto illegal_insn;
3945 }
3946#endif
e8af50a3
FB		 3947 }
3948 break;
3949#endif
3475187d 3950#ifdef TARGET_SPARC64
0f8a249a
BS		 3951 case 0x2c: /* V9 movcc */
3952 {
3953 int cc = GET_FIELD_SP(insn, 11, 12);
3954 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 3955 DisasCompare cmp;
97ea2859 3956 TCGv dst;
00f219bf 3957
0f8a249a 3958 if (insn & (1 << 18)) {
f52879b4
RH		 3959 if (cc == 0) {
3960 gen_compare(&cmp, 0, cond, dc);
3961 } else if (cc == 2) {
3962 gen_compare(&cmp, 1, cond, dc);
3963 } else {
0f8a249a 3964 goto illegal_insn;
f52879b4 3965 }
0f8a249a 3966 } else {
f52879b4 3967 gen_fcompare(&cmp, cc, cond);
0f8a249a 3968 }
00f219bf 3969
f52879b4
RH		 3970 /* The get_src2 above loaded the normal 13-bit
3971 immediate field, not the 11-bit field we have
3972 in movcc. But it did handle the reg case. */
3973 if (IS_IMM) {
67526b20 3974 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 3975 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 3976 }
f52879b4 3977
97ea2859
RH		 3978 dst = gen_load_gpr(dc, rd);
3979 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 3980 cmp.c1, cmp.c2,
97ea2859 3981 cpu_src2, dst);
f52879b4 3982 free_compare(&cmp);
97ea2859 3983 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3984 break;
3985 }
3986 case 0x2d: /* V9 sdivx */
c28ae41e 3987 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 3988 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 3989 break;
3990 case 0x2e: /* V9 popc */
97ea2859
RH		 3991 gen_helper_popc(cpu_dst, cpu_src2);
3992 gen_store_gpr(dc, rd, cpu_dst);
3993 break;
0f8a249a
BS		 3994 case 0x2f: /* V9 movr */
3995 {
3996 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 3997 DisasCompare cmp;
97ea2859 3998 TCGv dst;
00f219bf 3999
c33f80f5 4000 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4001
c33f80f5
RH		 4002 /* The get_src2 above loaded the normal 13-bit
4003 immediate field, not the 10-bit field we have
4004 in movr. But it did handle the reg case. */
4005 if (IS_IMM) {
67526b20 4006 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4007 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4008 }
c33f80f5 4009
97ea2859
RH		 4010 dst = gen_load_gpr(dc, rd);
4011 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4012 cmp.c1, cmp.c2,
97ea2859 4013 cpu_src2, dst);
c33f80f5 4014 free_compare(&cmp);
97ea2859 4015 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4016 break;
4017 }
4018#endif
4019 default:
4020 goto illegal_insn;
4021 }
4022 }
3299908c
BS		 4023 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4024#ifdef TARGET_SPARC64
4025 int opf = GET_FIELD_SP(insn, 5, 13);
4026 rs1 = GET_FIELD(insn, 13, 17);
4027 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4028 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4029 goto jmp_insn;
5b12f1e8 4030 }
3299908c
BS		 4031
4032 switch (opf) {
e9ebed4d 4033 case 0x000: /* VIS I edge8cc */
6c073553 4034 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4035 cpu_src1 = gen_load_gpr(dc, rs1);
4036 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4037 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4038 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4039 break;
e9ebed4d 4040 case 0x001: /* VIS II edge8n */
6c073553 4041 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4042 cpu_src1 = gen_load_gpr(dc, rs1);
4043 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4044 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4045 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4046 break;
e9ebed4d 4047 case 0x002: /* VIS I edge8lcc */
6c073553 4048 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4049 cpu_src1 = gen_load_gpr(dc, rs1);
4050 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4051 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4052 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4053 break;
e9ebed4d 4054 case 0x003: /* VIS II edge8ln */
6c073553 4055 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4056 cpu_src1 = gen_load_gpr(dc, rs1);
4057 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4058 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4059 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4060 break;
e9ebed4d 4061 case 0x004: /* VIS I edge16cc */
6c073553 4062 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4063 cpu_src1 = gen_load_gpr(dc, rs1);
4064 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4065 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4066 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4067 break;
e9ebed4d 4068 case 0x005: /* VIS II edge16n */
6c073553 4069 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4070 cpu_src1 = gen_load_gpr(dc, rs1);
4071 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4072 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4073 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4074 break;
e9ebed4d 4075 case 0x006: /* VIS I edge16lcc */
6c073553 4076 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4077 cpu_src1 = gen_load_gpr(dc, rs1);
4078 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4079 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4080 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4081 break;
e9ebed4d 4082 case 0x007: /* VIS II edge16ln */
6c073553 4083 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4084 cpu_src1 = gen_load_gpr(dc, rs1);
4085 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4086 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4087 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4088 break;
e9ebed4d 4089 case 0x008: /* VIS I edge32cc */
6c073553 4090 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4091 cpu_src1 = gen_load_gpr(dc, rs1);
4092 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4093 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4094 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4095 break;
e9ebed4d 4096 case 0x009: /* VIS II edge32n */
6c073553 4097 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4098 cpu_src1 = gen_load_gpr(dc, rs1);
4099 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4100 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4101 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4102 break;
e9ebed4d 4103 case 0x00a: /* VIS I edge32lcc */
6c073553 4104 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4105 cpu_src1 = gen_load_gpr(dc, rs1);
4106 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4107 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4108 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4109 break;
e9ebed4d 4110 case 0x00b: /* VIS II edge32ln */
6c073553 4111 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4112 cpu_src1 = gen_load_gpr(dc, rs1);
4113 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4114 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4115 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4116 break;
e9ebed4d 4117 case 0x010: /* VIS I array8 */
64a88d5d 4118 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4119 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4120 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4121 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4122 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4123 break;
4124 case 0x012: /* VIS I array16 */
64a88d5d 4125 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4126 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4127 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4128 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4129 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4130 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4131 break;
4132 case 0x014: /* VIS I array32 */
64a88d5d 4133 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4134 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4135 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4136 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4137 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4138 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4139 break;
3299908c 4140 case 0x018: /* VIS I alignaddr */
64a88d5d 4141 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4142 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4143 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4144 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4145 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4146 break;
4147 case 0x01a: /* VIS I alignaddrl */
add545ab 4148 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4149 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4150 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4151 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4152 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4153 break;
4154 case 0x019: /* VIS II bmask */
793a137a 4155 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4156 cpu_src1 = gen_load_gpr(dc, rs1);
4157 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4158 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4159 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4160 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4161 break;
e9ebed4d 4162 case 0x020: /* VIS I fcmple16 */
64a88d5d 4163 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4164 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4165 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4166 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4167 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4168 break;
4169 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4170 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4171 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4172 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4173 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4174 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4175 break;
e9ebed4d 4176 case 0x024: /* VIS I fcmple32 */
64a88d5d 4177 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4178 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4179 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4180 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4181 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4182 break;
4183 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4184 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4185 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4186 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4187 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4188 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4189 break;
4190 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4191 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4192 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4193 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4194 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4195 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4196 break;
4197 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4198 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4199 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4200 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4201 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4202 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4203 break;
4204 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4205 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4206 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4207 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4208 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4209 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4210 break;
4211 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4212 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4213 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4214 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4215 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4216 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4217 break;
4218 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4219 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4220 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4221 break;
4222 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4223 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4224 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4225 break;
4226 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4227 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4228 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4229 break;
4230 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4231 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4232 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4233 break;
4234 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4235 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4236 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4237 break;
4238 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4239 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4240 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4241 break;
4242 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4243 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4244 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4245 break;
4246 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4247 CHECK_FPU_FEATURE(dc, VIS1);
4248 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4249 break;
e9ebed4d 4250 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4251 CHECK_FPU_FEATURE(dc, VIS1);
4252 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4253 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4254 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4255 gen_store_fpr_F(dc, rd, cpu_dst_32);
4256 break;
e9ebed4d 4257 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4258 CHECK_FPU_FEATURE(dc, VIS1);
4259 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4260 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4261 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4262 gen_store_fpr_F(dc, rd, cpu_dst_32);
4263 break;
f888300b
RH		 4264 case 0x03e: /* VIS I pdist */
4265 CHECK_FPU_FEATURE(dc, VIS1);
4266 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4267 break;
3299908c 4268 case 0x048: /* VIS I faligndata */
64a88d5d 4269 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4270 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4271 break;
e9ebed4d 4272 case 0x04b: /* VIS I fpmerge */
64a88d5d 4273 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4274 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4275 break;
4276 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4277 CHECK_FPU_FEATURE(dc, VIS2);
4278 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4279 break;
e9ebed4d 4280 case 0x04d: /* VIS I fexpand */
64a88d5d 4281 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4282 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4283 break;
4284 case 0x050: /* VIS I fpadd16 */
64a88d5d 4285 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4286 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4287 break;
4288 case 0x051: /* VIS I fpadd16s */
64a88d5d 4289 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4290 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 4291 break;
4292 case 0x052: /* VIS I fpadd32 */
64a88d5d 4293 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4294 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 4295 break;
4296 case 0x053: /* VIS I fpadd32s */
64a88d5d 4297 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4298 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 4299 break;
4300 case 0x054: /* VIS I fpsub16 */
64a88d5d 4301 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4302 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 4303 break;
4304 case 0x055: /* VIS I fpsub16s */
64a88d5d 4305 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4306 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 4307 break;
4308 case 0x056: /* VIS I fpsub32 */
64a88d5d 4309 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4310 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 4311 break;
4312 case 0x057: /* VIS I fpsub32s */
64a88d5d 4313 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4314 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 4315 break;
3299908c 4316 case 0x060: /* VIS I fzero */
64a88d5d 4317 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4318 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4319 tcg_gen_movi_i64(cpu_dst_64, 0);
4320 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4321 break;
4322 case 0x061: /* VIS I fzeros */
64a88d5d 4323 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4324 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4325 tcg_gen_movi_i32(cpu_dst_32, 0);
4326 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4327 break;
e9ebed4d 4328 case 0x062: /* VIS I fnor */
64a88d5d 4329 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4330 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 4331 break;
4332 case 0x063: /* VIS I fnors */
64a88d5d 4333 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4334 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 4335 break;
4336 case 0x064: /* VIS I fandnot2 */
64a88d5d 4337 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4338 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 4339 break;
4340 case 0x065: /* VIS I fandnot2s */
64a88d5d 4341 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4342 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 4343 break;
4344 case 0x066: /* VIS I fnot2 */
64a88d5d 4345 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4346 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 4347 break;
4348 case 0x067: /* VIS I fnot2s */
64a88d5d 4349 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4350 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 4351 break;
4352 case 0x068: /* VIS I fandnot1 */
64a88d5d 4353 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4354 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 4355 break;
4356 case 0x069: /* VIS I fandnot1s */
64a88d5d 4357 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4358 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 4359 break;
4360 case 0x06a: /* VIS I fnot1 */
64a88d5d 4361 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4362 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 4363 break;
4364 case 0x06b: /* VIS I fnot1s */
64a88d5d 4365 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4366 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 4367 break;
4368 case 0x06c: /* VIS I fxor */
64a88d5d 4369 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4370 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 4371 break;
4372 case 0x06d: /* VIS I fxors */
64a88d5d 4373 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4374 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 4375 break;
4376 case 0x06e: /* VIS I fnand */
64a88d5d 4377 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4378 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 4379 break;
4380 case 0x06f: /* VIS I fnands */
64a88d5d 4381 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4382 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 4383 break;
4384 case 0x070: /* VIS I fand */
64a88d5d 4385 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4386 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 4387 break;
4388 case 0x071: /* VIS I fands */
64a88d5d 4389 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4390 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 4391 break;
4392 case 0x072: /* VIS I fxnor */
64a88d5d 4393 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4394 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 4395 break;
4396 case 0x073: /* VIS I fxnors */
64a88d5d 4397 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4398 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 4399 break;
3299908c 4400 case 0x074: /* VIS I fsrc1 */
64a88d5d 4401 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4402 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4403 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4404 break;
4405 case 0x075: /* VIS I fsrc1s */
64a88d5d 4406 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4407 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
4408 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4409 break;
e9ebed4d 4410 case 0x076: /* VIS I fornot2 */
64a88d5d 4411 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4412 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 4413 break;
4414 case 0x077: /* VIS I fornot2s */
64a88d5d 4415 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4416 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 4417 break;
3299908c 4418 case 0x078: /* VIS I fsrc2 */
64a88d5d 4419 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 4420 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
4421 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 4422 break;
4423 case 0x079: /* VIS I fsrc2s */
64a88d5d 4424 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 4425 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
4426 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 4427 break;
e9ebed4d 4428 case 0x07a: /* VIS I fornot1 */
64a88d5d 4429 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4430 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 4431 break;
4432 case 0x07b: /* VIS I fornot1s */
64a88d5d 4433 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4434 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 4435 break;
4436 case 0x07c: /* VIS I for */
64a88d5d 4437 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4438 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 4439 break;
4440 case 0x07d: /* VIS I fors */
64a88d5d 4441 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4442 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 4443 break;
3299908c 4444 case 0x07e: /* VIS I fone */
64a88d5d 4445 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 4446 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 4447 tcg_gen_movi_i64(cpu_dst_64, -1);
4448 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 4449 break;
4450 case 0x07f: /* VIS I fones */
64a88d5d 4451 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 4452 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 4453 tcg_gen_movi_i32(cpu_dst_32, -1);
4454 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 4455 break;
e9ebed4d
BS		 4456 case 0x080: /* VIS I shutdown */
4457 case 0x081: /* VIS II siam */
4458 // XXX
4459 goto illegal_insn;
3299908c
BS		 4460 default:
4461 goto illegal_insn;
4462 }
4463#else
0f8a249a 4464 goto ncp_insn;
3299908c
BS		 4465#endif
4466 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 4467#ifdef TARGET_SPARC64
0f8a249a 4468 goto illegal_insn;
fcc72045 4469#else
0f8a249a 4470 goto ncp_insn;
fcc72045 4471#endif
3475187d 4472#ifdef TARGET_SPARC64
0f8a249a 4473 } else if (xop == 0x39) { /* V9 return */
a7812ae4 4474 TCGv_i32 r_const;
2ea815ca 4475
66442b07 4476 save_state(dc);
9d1d4e34 4477 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4478 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4479 if (IS_IMM) { /* immediate */
67526b20 4480 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4481 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4482 } else { /* register */
3475187d 4483 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4484 if (rs2) {
97ea2859 4485 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4486 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4487 } else {
7b04bd5c 4488 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4489 }
3475187d 4490 }
063c3675 4491 gen_helper_restore(cpu_env);
13a6dd00 4492 gen_mov_pc_npc(dc);
2ea815ca 4493 r_const = tcg_const_i32(3);
7b04bd5c 4494 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4495 tcg_temp_free_i32(r_const);
7b04bd5c 4496 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4497 dc->npc = DYNAMIC_PC;
4498 goto jmp_insn;
3475187d 4499#endif
0f8a249a 4500 } else {
9d1d4e34 4501 cpu_src1 = get_src1(dc, insn);
de9e9d9f 4502 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 4503 if (IS_IMM) { /* immediate */
67526b20 4504 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 4505 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 4506 } else { /* register */
e80cfcfc 4507 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4508 if (rs2) {
97ea2859 4509 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 4510 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 4511 } else {
7b04bd5c 4512 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 4513 }
cf495bcf 4514 }
0f8a249a
BS		 4515 switch (xop) {
4516 case 0x38: /* jmpl */
4517 {
97ea2859 4518 TCGv t;
a7812ae4 4519 TCGv_i32 r_const;
2ea815ca 4520
97ea2859
RH		 4521 t = gen_dest_gpr(dc, rd);
4522 tcg_gen_movi_tl(t, dc->pc);
4523 gen_store_gpr(dc, rd, t);
13a6dd00 4524 gen_mov_pc_npc(dc);
2ea815ca 4525 r_const = tcg_const_i32(3);
7b04bd5c 4526 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4527 tcg_temp_free_i32(r_const);
7b04bd5c
RH		 4528 gen_address_mask(dc, cpu_tmp0);
4529 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 4530 dc->npc = DYNAMIC_PC;
4531 }
4532 goto jmp_insn;
3475187d 4533#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 4534 case 0x39: /* rett, V9 return */
4535 {
a7812ae4 4536 TCGv_i32 r_const;
2ea815ca 4537
0f8a249a
BS		 4538 if (!supervisor(dc))
4539 goto priv_insn;
13a6dd00 4540 gen_mov_pc_npc(dc);
2ea815ca 4541 r_const = tcg_const_i32(3);
7b04bd5c 4542 gen_helper_check_align(cpu_env, cpu_tmp0, r_const);
a7812ae4 4543 tcg_temp_free_i32(r_const);
7b04bd5c 4544 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 4545 dc->npc = DYNAMIC_PC;
063c3675 4546 gen_helper_rett(cpu_env);
0f8a249a
BS		 4547 }
4548 goto jmp_insn;
4549#endif
4550 case 0x3b: /* flush */
5578ceab 4551 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 4552 goto unimp_flush;
dcfd14b3 4553 /* nop */
0f8a249a
BS		 4554 break;
4555 case 0x3c: /* save */
66442b07 4556 save_state(dc);
063c3675 4557 gen_helper_save(cpu_env);
7b04bd5c 4558 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 4559 break;
4560 case 0x3d: /* restore */
66442b07 4561 save_state(dc);
063c3675 4562 gen_helper_restore(cpu_env);
7b04bd5c 4563 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 4564 break;
3475187d 4565#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 4566 case 0x3e: /* V9 done/retry */
4567 {
4568 switch (rd) {
4569 case 0:
4570 if (!supervisor(dc))
4571 goto priv_insn;
4572 dc->npc = DYNAMIC_PC;
4573 dc->pc = DYNAMIC_PC;
063c3675 4574 gen_helper_done(cpu_env);
0f8a249a
BS		 4575 goto jmp_insn;
4576 case 1:
4577 if (!supervisor(dc))
4578 goto priv_insn;
4579 dc->npc = DYNAMIC_PC;
4580 dc->pc = DYNAMIC_PC;
063c3675 4581 gen_helper_retry(cpu_env);
0f8a249a
BS		 4582 goto jmp_insn;
4583 default:
4584 goto illegal_insn;
4585 }
4586 }
4587 break;
4588#endif
4589 default:
4590 goto illegal_insn;
4591 }
cf495bcf 4592 }
0f8a249a
BS		 4593 break;
4594 }
4595 break;
4596 case 3: /* load/store instructions */
4597 {
4598 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 4599 /* ??? gen_address_mask prevents us from using a source
4600 register directly. Always generate a temporary. */
4601 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 4602
5e6ed439
RH		 4603 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
4604 if (xop == 0x3c || xop == 0x3e) {
4605 /* V9 casa/casxa : no offset */
71817e48 4606 } else if (IS_IMM) { /* immediate */
67526b20 4607 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 4608 if (simm != 0) {
4609 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
4610 }
0f8a249a
BS		 4611 } else { /* register */
4612 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 4613 if (rs2 != 0) {
5e6ed439 4614 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 4615 }
0f8a249a 4616 }
2f2ecb83
BS		 4617 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4618 (xop > 0x17 && xop <= 0x1d ) ||
4619 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 4620 TCGv cpu_val = gen_dest_gpr(dc, rd);
4621
0f8a249a 4622 switch (xop) {
b89e94af 4623 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 4624 gen_address_mask(dc, cpu_addr);
6ae20372 4625 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4626 break;
b89e94af 4627 case 0x1: /* ldub, load unsigned byte */
2cade6a3 4628 gen_address_mask(dc, cpu_addr);
6ae20372 4629 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4630 break;
b89e94af 4631 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 4632 gen_address_mask(dc, cpu_addr);
6ae20372 4633 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4634 break;
b89e94af 4635 case 0x3: /* ldd, load double word */
0f8a249a 4636 if (rd & 1)
d4218d99 4637 goto illegal_insn;
1a2fb1c0 4638 else {
a7812ae4 4639 TCGv_i32 r_const;
abcc7191 4640 TCGv_i64 t64;
2ea815ca 4641
66442b07 4642 save_state(dc);
2ea815ca 4643 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4644 /* XXX remove alignment check */
4645 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4646 tcg_temp_free_i32(r_const);
2cade6a3 4647 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 4648 t64 = tcg_temp_new_i64();
4649 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 4650 tcg_gen_trunc_i64_tl(cpu_val, t64);
4651 tcg_gen_ext32u_tl(cpu_val, cpu_val);
4652 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 4653 tcg_gen_shri_i64(t64, t64, 32);
4654 tcg_gen_trunc_i64_tl(cpu_val, t64);
4655 tcg_temp_free_i64(t64);
de9e9d9f 4656 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 4657 }
0f8a249a 4658 break;
b89e94af 4659 case 0x9: /* ldsb, load signed byte */
2cade6a3 4660 gen_address_mask(dc, cpu_addr);
6ae20372 4661 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4662 break;
b89e94af 4663 case 0xa: /* ldsh, load signed halfword */
2cade6a3 4664 gen_address_mask(dc, cpu_addr);
6ae20372 4665 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4666 break;
4667 case 0xd: /* ldstub -- XXX: should be atomically */
2ea815ca
BS		 4668 {
4669 TCGv r_const;
4670
2cade6a3 4671 gen_address_mask(dc, cpu_addr);
2ea815ca
BS		 4672 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4673 r_const = tcg_const_tl(0xff);
4674 tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4675 tcg_temp_free(r_const);
4676 }
0f8a249a 4677 break;
de9e9d9f
RH		 4678 case 0x0f:
4679 /* swap, swap register with memory. Also atomically */
4680 {
4681 TCGv t0 = get_temp_tl(dc);
4682 CHECK_IU_FEATURE(dc, SWAP);
4683 cpu_src1 = gen_load_gpr(dc, rd);
4684 gen_address_mask(dc, cpu_addr);
4685 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4686 tcg_gen_qemu_st32(cpu_src1, cpu_addr, dc->mem_idx);
4687 tcg_gen_mov_tl(cpu_val, t0);
4688 }
0f8a249a 4689 break;
3475187d 4690#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4691 case 0x10: /* lda, V9 lduwa, load word alternate */
3475187d 4692#ifndef TARGET_SPARC64
0f8a249a
BS		 4693 if (IS_IMM)
4694 goto illegal_insn;
4695 if (!supervisor(dc))
4696 goto priv_insn;
6ea4a6c8 4697#endif
66442b07 4698 save_state(dc);
6ae20372 4699 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
0f8a249a 4700 break;
b89e94af 4701 case 0x11: /* lduba, load unsigned byte alternate */
3475187d 4702#ifndef TARGET_SPARC64
0f8a249a
BS		 4703 if (IS_IMM)
4704 goto illegal_insn;
4705 if (!supervisor(dc))
4706 goto priv_insn;
4707#endif
66442b07 4708 save_state(dc);
6ae20372 4709 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
0f8a249a 4710 break;
b89e94af 4711 case 0x12: /* lduha, load unsigned halfword alternate */
3475187d 4712#ifndef TARGET_SPARC64
0f8a249a
BS		 4713 if (IS_IMM)
4714 goto illegal_insn;
4715 if (!supervisor(dc))
4716 goto priv_insn;
3475187d 4717#endif
66442b07 4718 save_state(dc);
6ae20372 4719 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
0f8a249a 4720 break;
b89e94af 4721 case 0x13: /* ldda, load double word alternate */
3475187d 4722#ifndef TARGET_SPARC64
0f8a249a
BS		 4723 if (IS_IMM)
4724 goto illegal_insn;
4725 if (!supervisor(dc))
4726 goto priv_insn;
3475187d 4727#endif
0f8a249a 4728 if (rd & 1)
d4218d99 4729 goto illegal_insn;
66442b07 4730 save_state(dc);
c7785e16 4731 gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
db166940 4732 goto skip_move;
b89e94af 4733 case 0x19: /* ldsba, load signed byte alternate */
3475187d 4734#ifndef TARGET_SPARC64
0f8a249a
BS		 4735 if (IS_IMM)
4736 goto illegal_insn;
4737 if (!supervisor(dc))
4738 goto priv_insn;
4739#endif
66442b07 4740 save_state(dc);
6ae20372 4741 gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
0f8a249a 4742 break;
b89e94af 4743 case 0x1a: /* ldsha, load signed halfword alternate */
3475187d 4744#ifndef TARGET_SPARC64
0f8a249a
BS		 4745 if (IS_IMM)
4746 goto illegal_insn;
4747 if (!supervisor(dc))
4748 goto priv_insn;
3475187d 4749#endif
66442b07 4750 save_state(dc);
6ae20372 4751 gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
0f8a249a
BS		 4752 break;
4753 case 0x1d: /* ldstuba -- XXX: should be atomically */
3475187d 4754#ifndef TARGET_SPARC64
0f8a249a
BS		 4755 if (IS_IMM)
4756 goto illegal_insn;
4757 if (!supervisor(dc))
4758 goto priv_insn;
4759#endif
66442b07 4760 save_state(dc);
6ae20372 4761 gen_ldstub_asi(cpu_val, cpu_addr, insn);
0f8a249a 4762 break;
b89e94af 4763 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 4764 atomically */
64a88d5d 4765 CHECK_IU_FEATURE(dc, SWAP);
3475187d 4766#ifndef TARGET_SPARC64
0f8a249a
BS		 4767 if (IS_IMM)
4768 goto illegal_insn;
4769 if (!supervisor(dc))
4770 goto priv_insn;
6ea4a6c8 4771#endif
66442b07 4772 save_state(dc);
06828032
RH		 4773 cpu_src1 = gen_load_gpr(dc, rd);
4774 gen_swap_asi(cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 4775 break;
3475187d
FB		 4776
4777#ifndef TARGET_SPARC64
0f8a249a
BS		 4778 case 0x30: /* ldc */
4779 case 0x31: /* ldcsr */
4780 case 0x33: /* lddc */
4781 goto ncp_insn;
3475187d
FB		 4782#endif
4783#endif
4784#ifdef TARGET_SPARC64
0f8a249a 4785 case 0x08: /* V9 ldsw */
2cade6a3 4786 gen_address_mask(dc, cpu_addr);
6ae20372 4787 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4788 break;
4789 case 0x0b: /* V9 ldx */
2cade6a3 4790 gen_address_mask(dc, cpu_addr);
6ae20372 4791 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4792 break;
4793 case 0x18: /* V9 ldswa */
66442b07 4794 save_state(dc);
6ae20372 4795 gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
0f8a249a
BS		 4796 break;
4797 case 0x1b: /* V9 ldxa */
66442b07 4798 save_state(dc);
6ae20372 4799 gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
0f8a249a
BS		 4800 break;
4801 case 0x2d: /* V9 prefetch, no effect */
4802 goto skip_move;
4803 case 0x30: /* V9 ldfa */
5b12f1e8 4804 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4805 goto jmp_insn;
4806 }
66442b07 4807 save_state(dc);
6ae20372 4808 gen_ldf_asi(cpu_addr, insn, 4, rd);
638737ad 4809 gen_update_fprs_dirty(rd);
81ad8ba2 4810 goto skip_move;
0f8a249a 4811 case 0x33: /* V9 lddfa */
5b12f1e8 4812 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4813 goto jmp_insn;
4814 }
66442b07 4815 save_state(dc);
6ae20372 4816 gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
638737ad 4817 gen_update_fprs_dirty(DFPREG(rd));
81ad8ba2 4818 goto skip_move;
0f8a249a
BS		 4819 case 0x3d: /* V9 prefetcha, no effect */
4820 goto skip_move;
4821 case 0x32: /* V9 ldqfa */
64a88d5d 4822 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 4823 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 4824 goto jmp_insn;
4825 }
66442b07 4826 save_state(dc);
6ae20372 4827 gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
638737ad 4828 gen_update_fprs_dirty(QFPREG(rd));
1f587329 4829 goto skip_move;
0f8a249a
BS		 4830#endif
4831 default:
4832 goto illegal_insn;
4833 }
97ea2859 4834 gen_store_gpr(dc, rd, cpu_val);
db166940 4835#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 4836 skip_move: ;
3475187d 4837#endif
0f8a249a 4838 } else if (xop >= 0x20 && xop < 0x24) {
de9e9d9f
RH		 4839 TCGv t0;
4840
5b12f1e8 4841 if (gen_trap_ifnofpu(dc)) {
a80dde08 4842 goto jmp_insn;
5b12f1e8 4843 }
66442b07 4844 save_state(dc);
0f8a249a 4845 switch (xop) {
b89e94af 4846 case 0x20: /* ldf, load fpreg */
2cade6a3 4847 gen_address_mask(dc, cpu_addr);
de9e9d9f
RH		 4848 t0 = get_temp_tl(dc);
4849 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
ba5f5179 4850 cpu_dst_32 = gen_dest_fpr_F(dc);
de9e9d9f 4851 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
208ae657 4852 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 4853 break;
3a3b925d
BS		 4854 case 0x21: /* ldfsr, V9 ldxfsr */
4855#ifdef TARGET_SPARC64
2cade6a3 4856 gen_address_mask(dc, cpu_addr);
3a3b925d 4857 if (rd == 1) {
abcc7191
RH		 4858 TCGv_i64 t64 = tcg_temp_new_i64();
4859 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
4860 gen_helper_ldxfsr(cpu_env, t64);
4861 tcg_temp_free_i64(t64);
f8641947 4862 break;
fe987e23 4863 }
f8641947 4864#endif
de9e9d9f
RH		 4865 cpu_dst_32 = get_temp_i32(dc);
4866 t0 = get_temp_tl(dc);
4867 tcg_gen_qemu_ld32u(t0, cpu_addr, dc->mem_idx);
4868 tcg_gen_trunc_tl_i32(cpu_dst_32, t0);
4869 gen_helper_ldfsr(cpu_env, cpu_dst_32);
0f8a249a 4870 break;
b89e94af 4871 case 0x22: /* ldqf, load quad fpreg */
2ea815ca 4872 {
a7812ae4 4873 TCGv_i32 r_const;
2ea815ca
BS		 4874
4875 CHECK_FPU_FEATURE(dc, FLOAT128);
4876 r_const = tcg_const_i32(dc->mem_idx);
1295001c 4877 gen_address_mask(dc, cpu_addr);
fe8d8f0f 4878 gen_helper_ldqf(cpu_env, cpu_addr, r_const);
a7812ae4 4879 tcg_temp_free_i32(r_const);
2ea815ca 4880 gen_op_store_QT0_fpr(QFPREG(rd));
638737ad 4881 gen_update_fprs_dirty(QFPREG(rd));
2ea815ca 4882 }
1f587329 4883 break;
b89e94af 4884 case 0x23: /* lddf, load double fpreg */
03fb8cfc 4885 gen_address_mask(dc, cpu_addr);
3886b8a3 4886 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
03fb8cfc
RH		 4887 tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx);
4888 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 4889 break;
4890 default:
4891 goto illegal_insn;
4892 }
dc1a6971 4893 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 4894 xop == 0xe || xop == 0x1e) {
81634eea
RH		 4895 TCGv cpu_val = gen_load_gpr(dc, rd);
4896
0f8a249a 4897 switch (xop) {
b89e94af 4898 case 0x4: /* st, store word */
2cade6a3 4899 gen_address_mask(dc, cpu_addr);
6ae20372 4900 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4901 break;
b89e94af 4902 case 0x5: /* stb, store byte */
2cade6a3 4903 gen_address_mask(dc, cpu_addr);
6ae20372 4904 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4905 break;
b89e94af 4906 case 0x6: /* sth, store halfword */
2cade6a3 4907 gen_address_mask(dc, cpu_addr);
6ae20372 4908 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 4909 break;
b89e94af 4910 case 0x7: /* std, store double word */
0f8a249a 4911 if (rd & 1)
d4218d99 4912 goto illegal_insn;
1a2fb1c0 4913 else {
a7812ae4 4914 TCGv_i32 r_const;
abcc7191 4915 TCGv_i64 t64;
81634eea 4916 TCGv lo;
1a2fb1c0 4917
66442b07 4918 save_state(dc);
2cade6a3 4919 gen_address_mask(dc, cpu_addr);
2ea815ca 4920 r_const = tcg_const_i32(7);
fe8d8f0f
BS		 4921 /* XXX remove alignment check */
4922 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 4923 tcg_temp_free_i32(r_const);
81634eea 4924 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 4925
4926 t64 = tcg_temp_new_i64();
4927 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
4928 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
4929 tcg_temp_free_i64(t64);
7fa76c0b 4930 }
0f8a249a 4931 break;
3475187d 4932#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 4933 case 0x14: /* sta, V9 stwa, store word alternate */
3475187d 4934#ifndef TARGET_SPARC64
0f8a249a
BS		 4935 if (IS_IMM)
4936 goto illegal_insn;
4937 if (!supervisor(dc))
4938 goto priv_insn;
6ea4a6c8 4939#endif
66442b07 4940 save_state(dc);
6ae20372 4941 gen_st_asi(cpu_val, cpu_addr, insn, 4);
9fd1ae3a 4942 dc->npc = DYNAMIC_PC;
d39c0b99 4943 break;
b89e94af 4944 case 0x15: /* stba, store byte alternate */
3475187d 4945#ifndef TARGET_SPARC64
0f8a249a
BS		 4946 if (IS_IMM)
4947 goto illegal_insn;
4948 if (!supervisor(dc))
4949 goto priv_insn;
3475187d 4950#endif
66442b07 4951 save_state(dc);
6ae20372 4952 gen_st_asi(cpu_val, cpu_addr, insn, 1);
9fd1ae3a 4953 dc->npc = DYNAMIC_PC;
d39c0b99 4954 break;
b89e94af 4955 case 0x16: /* stha, store halfword alternate */
3475187d 4956#ifndef TARGET_SPARC64
0f8a249a
BS		 4957 if (IS_IMM)
4958 goto illegal_insn;
4959 if (!supervisor(dc))
4960 goto priv_insn;
6ea4a6c8 4961#endif
66442b07 4962 save_state(dc);
6ae20372 4963 gen_st_asi(cpu_val, cpu_addr, insn, 2);
9fd1ae3a 4964 dc->npc = DYNAMIC_PC;
d39c0b99 4965 break;
b89e94af 4966 case 0x17: /* stda, store double word alternate */
3475187d 4967#ifndef TARGET_SPARC64
0f8a249a
BS		 4968 if (IS_IMM)
4969 goto illegal_insn;
4970 if (!supervisor(dc))
4971 goto priv_insn;
3475187d 4972#endif
0f8a249a 4973 if (rd & 1)
d4218d99 4974 goto illegal_insn;
1a2fb1c0 4975 else {
66442b07 4976 save_state(dc);
c7785e16 4977 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
1a2fb1c0 4978 }
d39c0b99 4979 break;
e80cfcfc 4980#endif
3475187d 4981#ifdef TARGET_SPARC64
0f8a249a 4982 case 0x0e: /* V9 stx */
2cade6a3 4983 gen_address_mask(dc, cpu_addr);
6ae20372 4984 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 4985 break;
4986 case 0x1e: /* V9 stxa */
66442b07 4987 save_state(dc);
6ae20372 4988 gen_st_asi(cpu_val, cpu_addr, insn, 8);
9fd1ae3a 4989 dc->npc = DYNAMIC_PC;
0f8a249a 4990 break;
3475187d 4991#endif
0f8a249a
BS		 4992 default:
4993 goto illegal_insn;
4994 }
4995 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 4996 if (gen_trap_ifnofpu(dc)) {
a80dde08 4997 goto jmp_insn;
5b12f1e8 4998 }
66442b07 4999 save_state(dc);
0f8a249a 5000 switch (xop) {
b89e94af 5001 case 0x24: /* stf, store fpreg */
de9e9d9f
RH		 5002 {
5003 TCGv t = get_temp_tl(dc);
5004 gen_address_mask(dc, cpu_addr);
5005 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5006 tcg_gen_ext_i32_tl(t, cpu_src1_32);
5007 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5008 }
0f8a249a
BS		 5009 break;
5010 case 0x25: /* stfsr, V9 stxfsr */
f8641947
RH		 5011 {
5012 TCGv t = get_temp_tl(dc);
5013
5014 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUSPARCState, fsr));
3a3b925d 5015#ifdef TARGET_SPARC64
f8641947
RH		 5016 gen_address_mask(dc, cpu_addr);
5017 if (rd == 1) {
5018 tcg_gen_qemu_st64(t, cpu_addr, dc->mem_idx);
5019 break;
5020 }
3a3b925d 5021#endif
f8641947
RH		 5022 tcg_gen_qemu_st32(t, cpu_addr, dc->mem_idx);
5023 }
0f8a249a 5024 break;
1f587329
BS		 5025 case 0x26:
5026#ifdef TARGET_SPARC64
1f587329 5027 /* V9 stqf, store quad fpreg */
2ea815ca 5028 {
a7812ae4 5029 TCGv_i32 r_const;
2ea815ca
BS		 5030
5031 CHECK_FPU_FEATURE(dc, FLOAT128);
5032 gen_op_load_fpr_QT0(QFPREG(rd));
5033 r_const = tcg_const_i32(dc->mem_idx);
1295001c 5034 gen_address_mask(dc, cpu_addr);
fe8d8f0f 5035 gen_helper_stqf(cpu_env, cpu_addr, r_const);
a7812ae4 5036 tcg_temp_free_i32(r_const);
2ea815ca 5037 }
1f587329 5038 break;
1f587329
BS		 5039#else /* !TARGET_SPARC64 */
5040 /* stdfq, store floating point queue */
5041#if defined(CONFIG_USER_ONLY)
5042 goto illegal_insn;
5043#else
0f8a249a
BS		 5044 if (!supervisor(dc))
5045 goto priv_insn;
5b12f1e8 5046 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5047 goto jmp_insn;
5b12f1e8 5048 }
0f8a249a 5049 goto nfq_insn;
1f587329 5050#endif
0f8a249a 5051#endif
b89e94af 5052 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5053 gen_address_mask(dc, cpu_addr);
5054 cpu_src1_64 = gen_load_fpr_D(dc, rd);
5055 tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5056 break;
5057 default:
5058 goto illegal_insn;
5059 }
5060 } else if (xop > 0x33 && xop < 0x3f) {
66442b07 5061 save_state(dc);
0f8a249a 5062 switch (xop) {
a4d17f19 5063#ifdef TARGET_SPARC64
0f8a249a 5064 case 0x34: /* V9 stfa */
5b12f1e8 5065 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5066 goto jmp_insn;
5067 }
6ae20372 5068 gen_stf_asi(cpu_addr, insn, 4, rd);
0f8a249a 5069 break;
1f587329 5070 case 0x36: /* V9 stqfa */
2ea815ca 5071 {
a7812ae4 5072 TCGv_i32 r_const;
2ea815ca
BS		 5073
5074 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5075 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5076 goto jmp_insn;
5077 }
2ea815ca 5078 r_const = tcg_const_i32(7);
fe8d8f0f 5079 gen_helper_check_align(cpu_env, cpu_addr, r_const);
a7812ae4 5080 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5081 gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
5082 }
1f587329 5083 break;
0f8a249a 5084 case 0x37: /* V9 stdfa */
5b12f1e8 5085 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5086 goto jmp_insn;
5087 }
6ae20372 5088 gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5089 break;
0f8a249a 5090 case 0x3e: /* V9 casxa */
a4273524
RH		 5091 rs2 = GET_FIELD(insn, 27, 31);
5092 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5093 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5094 break;
a4d17f19 5095#else
0f8a249a
BS		 5096 case 0x34: /* stc */
5097 case 0x35: /* stcsr */
5098 case 0x36: /* stdcq */
5099 case 0x37: /* stdc */
5100 goto ncp_insn;
16c358e9
SH		 5101#endif
5102#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5103 case 0x3c: /* V9 or LEON3 casa */
5104#ifndef TARGET_SPARC64
5105 CHECK_IU_FEATURE(dc, CASA);
5106 if (IS_IMM) {
5107 goto illegal_insn;
5108 }
bd4e097a
AZ		 5109 /* LEON3 allows CASA from user space with ASI 0xa */
5110 if ((GET_FIELD(insn, 19, 26) != 0xa) && !supervisor(dc)) {
16c358e9
SH		 5111 goto priv_insn;
5112 }
5113#endif
5114 rs2 = GET_FIELD(insn, 27, 31);
5115 cpu_src2 = gen_load_gpr(dc, rs2);
5116 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5117 break;
0f8a249a
BS		 5118#endif
5119 default:
5120 goto illegal_insn;
5121 }
a4273524 5122 } else {
0f8a249a 5123 goto illegal_insn;
a4273524 5124 }
0f8a249a
BS		 5125 }
5126 break;
cf495bcf
FB		 5127 }
5128 /* default case for non jump instructions */
72cbca10 5129 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5130 dc->pc = DYNAMIC_PC;
5131 gen_op_next_insn();
72cbca10
FB		 5132 } else if (dc->npc == JUMP_PC) {
5133 /* we can do a static jump */
6ae20372 5134 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5135 dc->is_br = 1;
5136 } else {
0f8a249a
BS		 5137 dc->pc = dc->npc;
5138 dc->npc = dc->npc + 4;
cf495bcf 5139 }
e80cfcfc 5140 jmp_insn:
42a8aa83 5141 goto egress;
cf495bcf 5142 illegal_insn:
2ea815ca 5143 {
a7812ae4 5144 TCGv_i32 r_const;
2ea815ca 5145
66442b07 5146 save_state(dc);
2ea815ca 5147 r_const = tcg_const_i32(TT_ILL_INSN);
bc265319 5148 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5149 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5150 dc->is_br = 1;
5151 }
42a8aa83 5152 goto egress;
64a88d5d 5153 unimp_flush:
2ea815ca 5154 {
a7812ae4 5155 TCGv_i32 r_const;
2ea815ca 5156
66442b07 5157 save_state(dc);
2ea815ca 5158 r_const = tcg_const_i32(TT_UNIMP_FLUSH);
bc265319 5159 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5160 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5161 dc->is_br = 1;
5162 }
42a8aa83 5163 goto egress;
e80cfcfc 5164#if !defined(CONFIG_USER_ONLY)
e8af50a3 5165 priv_insn:
2ea815ca 5166 {
a7812ae4 5167 TCGv_i32 r_const;
2ea815ca 5168
66442b07 5169 save_state(dc);
2ea815ca 5170 r_const = tcg_const_i32(TT_PRIV_INSN);
bc265319 5171 gen_helper_raise_exception(cpu_env, r_const);
a7812ae4 5172 tcg_temp_free_i32(r_const);
2ea815ca
BS		 5173 dc->is_br = 1;
5174 }
42a8aa83 5175 goto egress;
64a88d5d 5176#endif
e80cfcfc 5177 nfpu_insn:
66442b07 5178 save_state(dc);
e80cfcfc
FB		 5179 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
5180 dc->is_br = 1;
42a8aa83 5181 goto egress;
64a88d5d 5182#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5183 nfq_insn:
66442b07 5184 save_state(dc);
9143e598
BS		 5185 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
5186 dc->is_br = 1;
42a8aa83 5187 goto egress;
9143e598 5188#endif
fcc72045
BS		 5189#ifndef TARGET_SPARC64
5190 ncp_insn:
2ea815ca
BS		 5191 {
5192 TCGv r_const;
5193
66442b07 5194 save_state(dc);
2ea815ca 5195 r_const = tcg_const_i32(TT_NCP_INSN);
bc265319 5196 gen_helper_raise_exception(cpu_env, r_const);
2ea815ca
BS		 5197 tcg_temp_free(r_const);
5198 dc->is_br = 1;
5199 }
42a8aa83 5200 goto egress;
fcc72045 5201#endif
42a8aa83 5202 egress:
30038fd8
RH		 5203 if (dc->n_t32 != 0) {
5204 int i;
5205 for (i = dc->n_t32 - 1; i >= 0; --i) {
5206 tcg_temp_free_i32(dc->t32[i]);
5207 }
5208 dc->n_t32 = 0;
5209 }
88023616
RH		 5210 if (dc->n_ttl != 0) {
5211 int i;
5212 for (i = dc->n_ttl - 1; i >= 0; --i) {
5213 tcg_temp_free(dc->ttl[i]);
5214 }
5215 dc->n_ttl = 0;
5216 }
7a3f1944
FB		 5217}
5218
4e5e1215 5219void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 5220{
4e5e1215 5221 SPARCCPU *cpu = sparc_env_get_cpu(env);
ed2803da 5222 CPUState *cs = CPU(cpu);
72cbca10 5223 target_ulong pc_start, last_pc;
cf495bcf 5224 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5225 int num_insns;
5226 int max_insns;
0184e266 5227 unsigned int insn;
cf495bcf
FB		 5228
5229 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5230 dc->tb = tb;
72cbca10 5231 pc_start = tb->pc;
cf495bcf 5232 dc->pc = pc_start;
e80cfcfc 5233 last_pc = dc->pc;
72cbca10 5234 dc->npc = (target_ulong) tb->cs_base;
8393617c 5235 dc->cc_op = CC_OP_DYNAMIC;
97ed5ccd 5236 dc->mem_idx = cpu_mmu_index(env, false);
5578ceab 5237 dc->def = env->def;
f838e2c5
BS		 5238 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5239 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5240 dc->singlestep = (cs->singlestep_enabled || singlestep);
cf495bcf 5241
2e70f6ef
PB		 5242 num_insns = 0;
5243 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5244 if (max_insns == 0) {
2e70f6ef 5245 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5246 }
5247 if (max_insns > TCG_MAX_INSNS) {
5248 max_insns = TCG_MAX_INSNS;
5249 }
5250
cd42d5b2 5251 gen_tb_start(tb);
cf495bcf 5252 do {
a3d5ad76
RH		 5253 if (dc->npc & JUMP_PC) {
5254 assert(dc->jump_pc[1] == dc->pc + 4);
5255 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5256 } else {
5257 tcg_gen_insn_start(dc->pc, dc->npc);
5258 }
959082fc 5259 num_insns++;
522a0d4e 5260 last_pc = dc->pc;
667b8e29 5261
b933066a
RH		 5262 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5263 if (dc->pc != pc_start) {
5264 save_state(dc);
5265 }
5266 gen_helper_debug(cpu_env);
5267 tcg_gen_exit_tb(0);
5268 dc->is_br = 1;
5269 goto exit_gen_loop;
5270 }
5271
959082fc 5272 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5273 gen_io_start();
667b8e29
RH		 5274 }
5275
0184e266 5276 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5277
0184e266 5278 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5279
5280 if (dc->is_br)
5281 break;
5282 /* if the next PC is different, we abort now */
5283 if (dc->pc != (last_pc + 4))
5284 break;
d39c0b99
FB		 5285 /* if we reach a page boundary, we stop generation so that the
5286 PC of a TT_TFAULT exception is always in the right page */
5287 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5288 break;
e80cfcfc
FB		 5289 /* if single step mode, we generate only one instruction and
5290 generate an exception */
060718c1 5291 if (dc->singlestep) {
e80cfcfc
FB		 5292 break;
5293 }
fe700adb 5294 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5295 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5296 num_insns < max_insns);
e80cfcfc
FB		 5297
5298 exit_gen_loop:
b09b2fd3 5299 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5300 gen_io_end();
b09b2fd3 5301 }
72cbca10 5302 if (!dc->is_br) {
5fafdf24 5303 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5304 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5305 /* static PC and NPC: we can use direct chaining */
2f5680ee 5306 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5307 } else {
b09b2fd3 5308 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5309 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5310 }
934da7ee 5311 save_npc(dc);
57fec1fe 5312 tcg_gen_exit_tb(0);
72cbca10
FB		 5313 }
5314 }
806f352d 5315 gen_tb_end(tb, num_insns);
0a7df5da 5316
4e5e1215
RH		 5317 tb->size = last_pc + 4 - pc_start;
5318 tb->icount = num_insns;
5319
7a3f1944 5320#ifdef DEBUG_DISAS
8fec2b8c 5321 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
93fcfe39
AL		 5322 qemu_log("--------------\n");
5323 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5324 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5325 qemu_log("\n");
cf495bcf 5326 }
7a3f1944 5327#endif
7a3f1944
FB		 5328}
5329
c48fcb47 5330void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5331{
c48fcb47 5332 static int inited;
0ea63844
RH		 5333 static const char gregnames[8][4] = {
5334 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
f5069b26 5335 };
0ea63844 5336 static const char fregnames[32][4] = {
30038fd8
RH		 5337 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5338 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5339 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5340 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5341 };
aaed909a 5342
0ea63844 5343 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5344#ifdef TARGET_SPARC64
0ea63844
RH		 5345 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
5346 { &cpu_asi, offsetof(CPUSPARCState, asi), "asi" },
5347 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
5348 { &cpu_softint, offsetof(CPUSPARCState, softint), "softint" },
255e1fcb 5349#else
0ea63844
RH		 5350 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5351#endif
5352 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5353 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5354 };
5355
5356 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5357#ifdef TARGET_SPARC64
5358 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5359 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5360 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5361 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5362 "hstick_cmpr" },
5363 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5364 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5365 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5366 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5367 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5368#endif
0ea63844
RH		 5369 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5370 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5371 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5372 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5373 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5374 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5375 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5376 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 5377#ifndef CONFIG_USER_ONLY
0ea63844 5378 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 5379#endif
0ea63844
RH		 5380 };
5381
5382 unsigned int i;
5383
5384 /* init various static tables */
5385 if (inited) {
5386 return;
5387 }
5388 inited = 1;
5389
5390 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
5391
5392 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5393 offsetof(CPUSPARCState, regwptr),
5394 "regwptr");
5395
5396 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5397 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5398 }
5399
5400 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5401 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5402 }
5403
5404 TCGV_UNUSED(cpu_gregs[0]);
5405 for (i = 1; i < 8; ++i) {
5406 cpu_gregs[i] = tcg_global_mem_new(cpu_env,
5407 offsetof(CPUSPARCState, gregs[i]),
5408 gregnames[i]);
5409 }
5410
5411 for (i = 0; i < TARGET_DPREGS; i++) {
5412 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5413 offsetof(CPUSPARCState, fpr[i]),
5414 fregnames[i]);
1a2fb1c0 5415 }
658138bc 5416}
d2856f1a 5417
bad729e2
RH		 5418void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5419 target_ulong *data)
d2856f1a 5420{
bad729e2
RH		 5421 target_ulong pc = data[0];
5422 target_ulong npc = data[1];
5423
5424 env->pc = pc;
6c42444f 5425 if (npc == DYNAMIC_PC) {
d2856f1a 5426 /* dynamic NPC: already stored */
6c42444f 5427 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5428 /* jump PC: use 'cond' and the jump targets of the translation */
5429 if (env->cond) {
6c42444f 5430 env->npc = npc & ~3;
d7da2a10 5431 } else {
6c42444f 5432 env->npc = pc + 4;
d7da2a10 5433 }
d2856f1a
AJ		 5434 } else {
5435 env->npc = npc;
5436 }
5437}
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