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[qemu.git] / hw / misc / ivshmem.c
CommitLineData
6cbf4c8c
CM
1/*
2 * Inter-VM Shared Memory PCI device.
3 *
4 * Author:
5 * Cam Macdonell <[email protected]>
6 *
7 * Based On: cirrus_vga.c
8 * Copyright (c) 2004 Fabrice Bellard
9 * Copyright (c) 2004 Makoto Suzuki (suzu)
10 *
11 * and rtl8139.c
12 * Copyright (c) 2006 Igor Kovalenko
13 *
14 * This code is licensed under the GNU GPL v2.
6b620ca3
PB
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
6cbf4c8c 18 */
0d1c9782 19#include "qemu/osdep.h"
da34e65c 20#include "qapi/error.h"
f348b6d1 21#include "qemu/cutils.h"
83c9f4ca 22#include "hw/hw.h"
0d09e41a 23#include "hw/i386/pc.h"
83c9f4ca 24#include "hw/pci/pci.h"
660c97ee 25#include "hw/pci/msi.h"
83c9f4ca 26#include "hw/pci/msix.h"
9c17d615 27#include "sysemu/kvm.h"
795c40b8 28#include "migration/blocker.h"
d49b6836 29#include "qemu/error-report.h"
1de7afc9 30#include "qemu/event_notifier.h"
5503e285 31#include "qom/object_interfaces.h"
4d43a603 32#include "chardev/char-fe.h"
d9453c93 33#include "sysemu/hostmem.h"
5400c02b 34#include "sysemu/qtest.h"
d9453c93 35#include "qapi/visitor.h"
6cbf4c8c 36
5105b1d8
DM
37#include "hw/misc/ivshmem.h"
38
b8ef62a9
PB
39#define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET
40#define PCI_DEVICE_ID_IVSHMEM 0x1110
41
cd9953f7 42#define IVSHMEM_MAX_PEERS UINT16_MAX
6cbf4c8c
CM
43#define IVSHMEM_IOEVENTFD 0
44#define IVSHMEM_MSI 1
45
6cbf4c8c
CM
46#define IVSHMEM_REG_BAR_SIZE 0x100
47
a4fa93bf
MA
48#define IVSHMEM_DEBUG 0
49#define IVSHMEM_DPRINTF(fmt, ...) \
50 do { \
51 if (IVSHMEM_DEBUG) { \
52 printf("IVSHMEM: " fmt, ## __VA_ARGS__); \
53 } \
54 } while (0)
6cbf4c8c 55
5400c02b
MA
56#define TYPE_IVSHMEM_COMMON "ivshmem-common"
57#define IVSHMEM_COMMON(obj) \
58 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON)
59
60#define TYPE_IVSHMEM_PLAIN "ivshmem-plain"
61#define IVSHMEM_PLAIN(obj) \
62 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN)
63
64#define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell"
65#define IVSHMEM_DOORBELL(obj) \
66 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL)
67
eb3fedf3
PC
68#define TYPE_IVSHMEM "ivshmem"
69#define IVSHMEM(obj) \
70 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
71
6cbf4c8c
CM
72typedef struct Peer {
73 int nb_eventfds;
563027cc 74 EventNotifier *eventfds;
6cbf4c8c
CM
75} Peer;
76
0f57350e 77typedef struct MSIVector {
6cbf4c8c 78 PCIDevice *pdev;
660c97ee 79 int virq;
0f57350e 80} MSIVector;
6cbf4c8c
CM
81
82typedef struct IVShmemState {
b7578eaa
AF
83 /*< private >*/
84 PCIDevice parent_obj;
85 /*< public >*/
86
ddc85284
MA
87 uint32_t features;
88
89 /* exactly one of these two may be set */
90 HostMemoryBackend *hostmem; /* with interrupts */
becdfa00 91 CharBackend server_chr; /* without interrupts */
ddc85284
MA
92
93 /* registers */
6cbf4c8c
CM
94 uint32_t intrmask;
95 uint32_t intrstatus;
ddc85284 96 int vm_id;
6cbf4c8c 97
ddc85284
MA
98 /* BARs */
99 MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */
c2d8019c
MA
100 MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */
101 MemoryRegion server_bar2; /* used with server_chr */
6cbf4c8c 102
ddc85284 103 /* interrupt support */
6cbf4c8c 104 Peer *peers;
cd9953f7 105 int nb_peers; /* space in @peers[] */
6cbf4c8c 106 uint32_t vectors;
0f57350e 107 MSIVector *msi_vectors;
ee276391
MA
108 uint64_t msg_buf; /* buffer for receiving server messages */
109 int msg_buffered_bytes; /* #bytes in @msg_buf */
6cbf4c8c 110
ddc85284 111 /* migration stuff */
2a845da7 112 OnOffAuto master;
38e0735e
AL
113 Error *migration_blocker;
114
5400c02b
MA
115 /* legacy cruft */
116 char *role;
117 char *shmobj;
118 char *sizearg;
119 size_t legacy_size;
120 uint32_t not_legacy_32bit;
6cbf4c8c
CM
121} IVShmemState;
122
123/* registers for the Inter-VM shared memory device */
124enum ivshmem_registers {
125 INTRMASK = 0,
126 INTRSTATUS = 4,
127 IVPOSITION = 8,
128 DOORBELL = 12,
129};
130
131static inline uint32_t ivshmem_has_feature(IVShmemState *ivs,
132 unsigned int feature) {
133 return (ivs->features & (1 << feature));
134}
135
2a845da7
MA
136static inline bool ivshmem_is_master(IVShmemState *s)
137{
138 assert(s->master != ON_OFF_AUTO_AUTO);
139 return s->master == ON_OFF_AUTO_ON;
140}
141
d8a5da07 142static void ivshmem_update_irq(IVShmemState *s)
6cbf4c8c 143{
b7578eaa 144 PCIDevice *d = PCI_DEVICE(s);
434ad76d 145 uint32_t isr = s->intrstatus & s->intrmask;
6cbf4c8c 146
5400c02b
MA
147 /*
148 * Do nothing unless the device actually uses INTx. Here's how
149 * the device variants signal interrupts, what they put in PCI
150 * config space:
151 * Device variant Interrupt Interrupt Pin MSI-X cap.
152 * ivshmem-plain none 0 no
153 * ivshmem-doorbell MSI-X 1 yes(1)
154 * ivshmem,msi=off INTx 1 no
155 * ivshmem,msi=on MSI-X 1(2) yes(1)
156 * (1) if guest enabled MSI-X
157 * (2) the device lies
158 * Leads to the condition for doing nothing:
159 */
160 if (ivshmem_has_feature(s, IVSHMEM_MSI)
161 || !d->config[PCI_INTERRUPT_PIN]) {
2d1d422d
MA
162 return;
163 }
164
6cbf4c8c
CM
165 /* don't print ISR resets */
166 if (isr) {
167 IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n",
dbc464d4 168 isr ? 1 : 0, s->intrstatus, s->intrmask);
6cbf4c8c
CM
169 }
170
434ad76d 171 pci_set_irq(d, isr != 0);
6cbf4c8c
CM
172}
173
174static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
175{
176 IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val);
177
178 s->intrmask = val;
d8a5da07 179 ivshmem_update_irq(s);
6cbf4c8c
CM
180}
181
182static uint32_t ivshmem_IntrMask_read(IVShmemState *s)
183{
184 uint32_t ret = s->intrmask;
185
186 IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret);
6cbf4c8c
CM
187 return ret;
188}
189
190static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val)
191{
192 IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val);
193
194 s->intrstatus = val;
d8a5da07 195 ivshmem_update_irq(s);
6cbf4c8c
CM
196}
197
198static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
199{
200 uint32_t ret = s->intrstatus;
201
202 /* reading ISR clears all interrupts */
203 s->intrstatus = 0;
d8a5da07 204 ivshmem_update_irq(s);
6cbf4c8c
CM
205 return ret;
206}
207
a8170e5e 208static void ivshmem_io_write(void *opaque, hwaddr addr,
cb06608e 209 uint64_t val, unsigned size)
6cbf4c8c
CM
210{
211 IVShmemState *s = opaque;
212
6cbf4c8c
CM
213 uint16_t dest = val >> 16;
214 uint16_t vector = val & 0xff;
215
216 addr &= 0xfc;
217
218 IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr);
219 switch (addr)
220 {
221 case INTRMASK:
222 ivshmem_IntrMask_write(s, val);
223 break;
224
225 case INTRSTATUS:
226 ivshmem_IntrStatus_write(s, val);
227 break;
228
229 case DOORBELL:
230 /* check that dest VM ID is reasonable */
95c8425c 231 if (dest >= s->nb_peers) {
6cbf4c8c
CM
232 IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest);
233 break;
234 }
235
236 /* check doorbell range */
1b27d7a1 237 if (vector < s->peers[dest].nb_eventfds) {
563027cc
PB
238 IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector);
239 event_notifier_set(&s->peers[dest].eventfds[vector]);
f59bb378
MAL
240 } else {
241 IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n",
242 vector, dest);
6cbf4c8c
CM
243 }
244 break;
245 default:
f59bb378 246 IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr);
6cbf4c8c
CM
247 }
248}
249
a8170e5e 250static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
cb06608e 251 unsigned size)
6cbf4c8c
CM
252{
253
254 IVShmemState *s = opaque;
255 uint32_t ret;
256
257 switch (addr)
258 {
259 case INTRMASK:
260 ret = ivshmem_IntrMask_read(s);
261 break;
262
263 case INTRSTATUS:
264 ret = ivshmem_IntrStatus_read(s);
265 break;
266
267 case IVPOSITION:
1309cf44 268 ret = s->vm_id;
6cbf4c8c
CM
269 break;
270
271 default:
272 IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr);
273 ret = 0;
274 }
275
276 return ret;
277}
278
cb06608e
AK
279static const MemoryRegionOps ivshmem_mmio_ops = {
280 .read = ivshmem_io_read,
281 .write = ivshmem_io_write,
282 .endianness = DEVICE_NATIVE_ENDIAN,
283 .impl = {
284 .min_access_size = 4,
285 .max_access_size = 4,
286 },
6cbf4c8c
CM
287};
288
9940c323
MAL
289static void ivshmem_vector_notify(void *opaque)
290{
0f57350e 291 MSIVector *entry = opaque;
6cbf4c8c 292 PCIDevice *pdev = entry->pdev;
5400c02b 293 IVShmemState *s = IVSHMEM_COMMON(pdev);
0f57350e 294 int vector = entry - s->msi_vectors;
9940c323
MAL
295 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
296
297 if (!event_notifier_test_and_clear(n)) {
298 return;
299 }
6cbf4c8c 300
d160f3f7 301 IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector);
9940c323 302 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8
MA
303 if (msix_enabled(pdev)) {
304 msix_notify(pdev, vector);
305 }
9940c323
MAL
306 } else {
307 ivshmem_IntrStatus_write(s, 1);
308 }
6cbf4c8c
CM
309}
310
660c97ee
MAL
311static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector,
312 MSIMessage msg)
313{
5400c02b 314 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
315 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
316 MSIVector *v = &s->msi_vectors[vector];
317 int ret;
318
319 IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector);
320
321 ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev);
322 if (ret < 0) {
323 return ret;
324 }
3f1fea0f 325 kvm_irqchip_commit_routes(kvm_state);
660c97ee
MAL
326
327 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq);
328}
329
330static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector)
331{
5400c02b 332 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
333 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
334 int ret;
335
336 IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector);
337
338 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n,
339 s->msi_vectors[vector].virq);
340 if (ret != 0) {
341 error_report("remove_irqfd_notifier_gsi failed");
342 }
343}
344
345static void ivshmem_vector_poll(PCIDevice *dev,
346 unsigned int vector_start,
347 unsigned int vector_end)
348{
5400c02b 349 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
350 unsigned int vector;
351
352 IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end);
353
354 vector_end = MIN(vector_end, s->vectors);
355
356 for (vector = vector_start; vector < vector_end; vector++) {
357 EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector];
358
359 if (!msix_is_masked(dev, vector)) {
360 continue;
361 }
362
363 if (event_notifier_test_and_clear(notifier)) {
364 msix_set_pending(dev, vector);
365 }
366 }
367}
368
9940c323
MAL
369static void watch_vector_notifier(IVShmemState *s, EventNotifier *n,
370 int vector)
6cbf4c8c 371{
563027cc 372 int eventfd = event_notifier_get_fd(n);
6cbf4c8c 373
3c27969b 374 assert(!s->msi_vectors[vector].pdev);
9940c323 375 s->msi_vectors[vector].pdev = PCI_DEVICE(s);
6cbf4c8c 376
9940c323
MAL
377 qemu_set_fd_handler(eventfd, ivshmem_vector_notify,
378 NULL, &s->msi_vectors[vector]);
6cbf4c8c
CM
379}
380
563027cc
PB
381static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i)
382{
383 memory_region_add_eventfd(&s->ivshmem_mmio,
384 DOORBELL,
385 4,
386 true,
387 (posn << 16) | i,
753d5e14 388 &s->peers[posn].eventfds[i]);
563027cc
PB
389}
390
391static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i)
392{
393 memory_region_del_eventfd(&s->ivshmem_mmio,
394 DOORBELL,
395 4,
396 true,
397 (posn << 16) | i,
753d5e14 398 &s->peers[posn].eventfds[i]);
563027cc
PB
399}
400
f456179f 401static void close_peer_eventfds(IVShmemState *s, int posn)
6cbf4c8c 402{
f456179f 403 int i, n;
6cbf4c8c 404
9db51b4d 405 assert(posn >= 0 && posn < s->nb_peers);
f456179f 406 n = s->peers[posn].nb_eventfds;
6cbf4c8c 407
9db51b4d
MA
408 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
409 memory_region_transaction_begin();
410 for (i = 0; i < n; i++) {
411 ivshmem_del_eventfd(s, posn, i);
412 }
413 memory_region_transaction_commit();
b6a1f3a5 414 }
9db51b4d 415
f456179f 416 for (i = 0; i < n; i++) {
563027cc 417 event_notifier_cleanup(&s->peers[posn].eventfds[i]);
6cbf4c8c
CM
418 }
419
7267c094 420 g_free(s->peers[posn].eventfds);
6cbf4c8c
CM
421 s->peers[posn].nb_eventfds = 0;
422}
423
cd9953f7 424static void resize_peers(IVShmemState *s, int nb_peers)
34bc07c5 425{
cd9953f7
MA
426 int old_nb_peers = s->nb_peers;
427 int i;
6cbf4c8c 428
cd9953f7
MA
429 assert(nb_peers > old_nb_peers);
430 IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers);
6cbf4c8c 431
cd9953f7
MA
432 s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer));
433 s->nb_peers = nb_peers;
1300b273 434
cd9953f7
MA
435 for (i = old_nb_peers; i < nb_peers; i++) {
436 s->peers[i].eventfds = g_new0(EventNotifier, s->vectors);
437 s->peers[i].nb_eventfds = 0;
6cbf4c8c
CM
438 }
439}
440
1309cf44
MA
441static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector,
442 Error **errp)
660c97ee
MAL
443{
444 PCIDevice *pdev = PCI_DEVICE(s);
660c97ee
MAL
445 int ret;
446
447 IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector);
3c27969b 448 assert(!s->msi_vectors[vector].pdev);
660c97ee 449
d1f6af6a 450 ret = kvm_irqchip_add_msi_route(kvm_state, vector, pdev);
660c97ee 451 if (ret < 0) {
1309cf44
MA
452 error_setg(errp, "kvm_irqchip_add_msi_route failed");
453 return;
660c97ee
MAL
454 }
455
456 s->msi_vectors[vector].virq = ret;
457 s->msi_vectors[vector].pdev = pdev;
660c97ee
MAL
458}
459
1309cf44 460static void setup_interrupt(IVShmemState *s, int vector, Error **errp)
660c97ee
MAL
461{
462 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
463 bool with_irqfd = kvm_msi_via_irqfd_enabled() &&
464 ivshmem_has_feature(s, IVSHMEM_MSI);
465 PCIDevice *pdev = PCI_DEVICE(s);
1309cf44 466 Error *err = NULL;
660c97ee
MAL
467
468 IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector);
469
470 if (!with_irqfd) {
97553976 471 IVSHMEM_DPRINTF("with eventfd\n");
9940c323 472 watch_vector_notifier(s, n, vector);
660c97ee 473 } else if (msix_enabled(pdev)) {
97553976 474 IVSHMEM_DPRINTF("with irqfd\n");
1309cf44
MA
475 ivshmem_add_kvm_msi_virq(s, vector, &err);
476 if (err) {
477 error_propagate(errp, err);
660c97ee
MAL
478 return;
479 }
480
481 if (!msix_is_masked(pdev, vector)) {
482 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL,
483 s->msi_vectors[vector].virq);
1309cf44 484 /* TODO handle error */
660c97ee
MAL
485 }
486 } else {
487 /* it will be delayed until msix is enabled, in write_config */
97553976 488 IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n");
660c97ee
MAL
489 }
490}
491
1309cf44 492static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
6cbf4c8c 493{
8381d89b 494 Error *local_err = NULL;
8baeb22b 495 struct stat buf;
5400c02b 496 size_t size;
6cbf4c8c 497
c2d8019c 498 if (s->ivshmem_bar2) {
1309cf44 499 error_setg(errp, "server sent unexpected shared memory message");
ca0b7566 500 close(fd);
0f14fd71 501 return;
a2e9011b
SH
502 }
503
8baeb22b
MA
504 if (fstat(fd, &buf) < 0) {
505 error_setg_errno(errp, errno,
506 "can't determine size of shared memory sent by server");
507 close(fd);
508 return;
509 }
510
5400c02b
MA
511 size = buf.st_size;
512
513 /* Legacy cruft */
514 if (s->legacy_size != SIZE_MAX) {
515 if (size < s->legacy_size) {
516 error_setg(errp, "server sent only %zd bytes of shared memory",
517 (size_t)buf.st_size);
518 close(fd);
519 return;
520 }
521 size = s->legacy_size;
cd9953f7
MA
522 }
523
ca0b7566 524 /* mmap the region and map into the BAR2 */
8381d89b
MAL
525 memory_region_init_ram_from_fd(&s->server_bar2, OBJECT(s),
526 "ivshmem.bar2", size, true, fd, &local_err);
527 if (local_err) {
528 error_propagate(errp, local_err);
ca0b7566 529 return;
6cbf4c8c 530 }
8381d89b 531
c2d8019c 532 s->ivshmem_bar2 = &s->server_bar2;
ca0b7566
MA
533}
534
1309cf44
MA
535static void process_msg_disconnect(IVShmemState *s, uint16_t posn,
536 Error **errp)
ca0b7566
MA
537{
538 IVSHMEM_DPRINTF("posn %d has gone away\n", posn);
9db51b4d 539 if (posn >= s->nb_peers || posn == s->vm_id) {
1309cf44 540 error_setg(errp, "invalid peer %d", posn);
9db51b4d
MA
541 return;
542 }
ca0b7566
MA
543 close_peer_eventfds(s, posn);
544}
6cbf4c8c 545
1309cf44
MA
546static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd,
547 Error **errp)
ca0b7566
MA
548{
549 Peer *peer = &s->peers[posn];
550 int vector;
9a2f0e64 551
ca0b7566
MA
552 /*
553 * The N-th connect message for this peer comes with the file
554 * descriptor for vector N-1. Count messages to find the vector.
555 */
556 if (peer->nb_eventfds >= s->vectors) {
1309cf44
MA
557 error_setg(errp, "Too many eventfd received, device has %d vectors",
558 s->vectors);
ca0b7566 559 close(fd);
6f8a16d5 560 return;
6cbf4c8c 561 }
ca0b7566 562 vector = peer->nb_eventfds++;
6cbf4c8c 563
ca0b7566
MA
564 IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd);
565 event_notifier_init_fd(&peer->eventfds[vector], fd);
566 fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */
945001a1 567
ca0b7566 568 if (posn == s->vm_id) {
1309cf44
MA
569 setup_interrupt(s, vector, errp);
570 /* TODO do we need to handle the error? */
ca0b7566 571 }
6cbf4c8c 572
ca0b7566
MA
573 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
574 ivshmem_add_eventfd(s, posn, vector);
575 }
576}
6cbf4c8c 577
1309cf44 578static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp)
ca0b7566
MA
579{
580 IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd);
6cbf4c8c 581
ca0b7566 582 if (msg < -1 || msg > IVSHMEM_MAX_PEERS) {
1309cf44 583 error_setg(errp, "server sent invalid message %" PRId64, msg);
ca0b7566 584 close(fd);
6cbf4c8c
CM
585 return;
586 }
587
ca0b7566 588 if (msg == -1) {
1309cf44 589 process_msg_shmem(s, fd, errp);
1ee57de4
MAL
590 return;
591 }
592
ca0b7566
MA
593 if (msg >= s->nb_peers) {
594 resize_peers(s, msg + 1);
595 }
6cbf4c8c 596
ca0b7566 597 if (fd >= 0) {
1309cf44 598 process_msg_connect(s, msg, fd, errp);
ca0b7566 599 } else {
1309cf44 600 process_msg_disconnect(s, msg, errp);
6cbf4c8c 601 }
ca0b7566 602}
6cbf4c8c 603
ee276391
MA
604static int ivshmem_can_receive(void *opaque)
605{
606 IVShmemState *s = opaque;
607
608 assert(s->msg_buffered_bytes < sizeof(s->msg_buf));
609 return sizeof(s->msg_buf) - s->msg_buffered_bytes;
610}
611
ca0b7566
MA
612static void ivshmem_read(void *opaque, const uint8_t *buf, int size)
613{
614 IVShmemState *s = opaque;
1309cf44 615 Error *err = NULL;
ca0b7566
MA
616 int fd;
617 int64_t msg;
618
ee276391
MA
619 assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf));
620 memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size);
621 s->msg_buffered_bytes += size;
622 if (s->msg_buffered_bytes < sizeof(s->msg_buf)) {
ca0b7566 623 return;
6cbf4c8c 624 }
ee276391
MA
625 msg = le64_to_cpu(s->msg_buf);
626 s->msg_buffered_bytes = 0;
ca0b7566 627
5345fdb4 628 fd = qemu_chr_fe_get_msgfd(&s->server_chr);
ca0b7566 629
1309cf44
MA
630 process_msg(s, msg, fd, &err);
631 if (err) {
632 error_report_err(err);
633 }
6cbf4c8c
CM
634}
635
1309cf44 636static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp)
5105b1d8 637{
3a55fc0f
MA
638 int64_t msg;
639 int n, ret;
640
641 n = 0;
642 do {
5345fdb4
MAL
643 ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n,
644 sizeof(msg) - n);
b7b1e9dd
PMD
645 if (ret < 0) {
646 if (ret == -EINTR) {
647 continue;
648 }
1309cf44 649 error_setg_errno(errp, -ret, "read from server failed");
3a55fc0f
MA
650 return INT64_MIN;
651 }
652 n += ret;
653 } while (n < sizeof(msg));
5105b1d8 654
5345fdb4 655 *pfd = qemu_chr_fe_get_msgfd(&s->server_chr);
51af0ec9 656 return le64_to_cpu(msg);
3a55fc0f 657}
5105b1d8 658
1309cf44 659static void ivshmem_recv_setup(IVShmemState *s, Error **errp)
3a55fc0f 660{
1309cf44 661 Error *err = NULL;
3a55fc0f
MA
662 int64_t msg;
663 int fd;
664
1309cf44
MA
665 msg = ivshmem_recv_msg(s, &fd, &err);
666 if (err) {
667 error_propagate(errp, err);
668 return;
669 }
670 if (msg != IVSHMEM_PROTOCOL_VERSION) {
671 error_setg(errp, "server sent version %" PRId64 ", expecting %d",
672 msg, IVSHMEM_PROTOCOL_VERSION);
673 return;
674 }
675 if (fd != -1) {
676 error_setg(errp, "server sent invalid version message");
5105b1d8
DM
677 return;
678 }
679
a3feb086
MA
680 /*
681 * ivshmem-server sends the remaining initial messages in a fixed
682 * order, but the device has always accepted them in any order.
683 * Stay as compatible as practical, just in case people use
684 * servers that behave differently.
685 */
686
687 /*
688 * ivshmem_device_spec.txt has always required the ID message
689 * right here, and ivshmem-server has always complied. However,
690 * older versions of the device accepted it out of order, but
691 * broke when an interrupt setup message arrived before it.
692 */
693 msg = ivshmem_recv_msg(s, &fd, &err);
694 if (err) {
695 error_propagate(errp, err);
696 return;
697 }
698 if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) {
699 error_setg(errp, "server sent invalid ID message");
700 return;
701 }
702 s->vm_id = msg;
703
3a55fc0f
MA
704 /*
705 * Receive more messages until we got shared memory.
706 */
707 do {
1309cf44
MA
708 msg = ivshmem_recv_msg(s, &fd, &err);
709 if (err) {
710 error_propagate(errp, err);
711 return;
712 }
713 process_msg(s, msg, fd, &err);
714 if (err) {
715 error_propagate(errp, err);
716 return;
717 }
3a55fc0f 718 } while (msg != -1);
1309cf44
MA
719
720 /*
721 * This function must either map the shared memory or fail. The
722 * loop above ensures that: it terminates normally only after it
723 * successfully processed the server's shared memory message.
724 * Assert that actually mapped the shared memory:
725 */
c2d8019c 726 assert(s->ivshmem_bar2);
5105b1d8
DM
727}
728
4490c711
MT
729/* Select the MSI-X vectors used by device.
730 * ivshmem maps events to vectors statically, so
731 * we just enable all vectors on init and after reset. */
082751e8 732static void ivshmem_msix_vector_use(IVShmemState *s)
4490c711 733{
b7578eaa 734 PCIDevice *d = PCI_DEVICE(s);
4490c711
MT
735 int i;
736
4490c711 737 for (i = 0; i < s->vectors; i++) {
b7578eaa 738 msix_vector_use(d, i);
4490c711
MT
739 }
740}
741
6cbf4c8c
CM
742static void ivshmem_reset(DeviceState *d)
743{
5400c02b 744 IVShmemState *s = IVSHMEM_COMMON(d);
6cbf4c8c
CM
745
746 s->intrstatus = 0;
972ad215 747 s->intrmask = 0;
082751e8
MA
748 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
749 ivshmem_msix_vector_use(s);
750 }
6cbf4c8c
CM
751}
752
ee640c62 753static int ivshmem_setup_interrupts(IVShmemState *s, Error **errp)
4490c711 754{
fd47bfe5
MAL
755 /* allocate QEMU callback data for receiving interrupts */
756 s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector));
6cbf4c8c 757
fd47bfe5 758 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
ee640c62 759 if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1, errp)) {
fd47bfe5
MAL
760 return -1;
761 }
1116b539 762
fd47bfe5 763 IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
082751e8 764 ivshmem_msix_vector_use(s);
fd47bfe5 765 }
4490c711 766
d58d7e84 767 return 0;
6cbf4c8c
CM
768}
769
660c97ee
MAL
770static void ivshmem_enable_irqfd(IVShmemState *s)
771{
772 PCIDevice *pdev = PCI_DEVICE(s);
773 int i;
774
775 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
1309cf44
MA
776 Error *err = NULL;
777
778 ivshmem_add_kvm_msi_virq(s, i, &err);
779 if (err) {
780 error_report_err(err);
781 /* TODO do we need to handle the error? */
782 }
660c97ee
MAL
783 }
784
785 if (msix_set_vector_notifiers(pdev,
786 ivshmem_vector_unmask,
787 ivshmem_vector_mask,
788 ivshmem_vector_poll)) {
789 error_report("ivshmem: msix_set_vector_notifiers failed");
790 }
791}
792
793static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector)
794{
795 IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector);
796
797 if (s->msi_vectors[vector].pdev == NULL) {
798 return;
799 }
800
801 /* it was cleaned when masked in the frontend. */
802 kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq);
803
804 s->msi_vectors[vector].pdev = NULL;
805}
806
807static void ivshmem_disable_irqfd(IVShmemState *s)
808{
809 PCIDevice *pdev = PCI_DEVICE(s);
810 int i;
811
812 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
813 ivshmem_remove_kvm_msi_virq(s, i);
814 }
815
816 msix_unset_vector_notifiers(pdev);
817}
818
819static void ivshmem_write_config(PCIDevice *pdev, uint32_t address,
d58d7e84 820 uint32_t val, int len)
4490c711 821{
5400c02b 822 IVShmemState *s = IVSHMEM_COMMON(pdev);
660c97ee
MAL
823 int is_enabled, was_enabled = msix_enabled(pdev);
824
825 pci_default_write_config(pdev, address, val, len);
826 is_enabled = msix_enabled(pdev);
827
1309cf44 828 if (kvm_msi_via_irqfd_enabled()) {
660c97ee
MAL
829 if (!was_enabled && is_enabled) {
830 ivshmem_enable_irqfd(s);
831 } else if (was_enabled && !is_enabled) {
832 ivshmem_disable_irqfd(s);
833 }
834 }
4490c711
MT
835}
836
5400c02b 837static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
6cbf4c8c 838{
5400c02b 839 IVShmemState *s = IVSHMEM_COMMON(dev);
d855e275 840 Error *err = NULL;
6cbf4c8c 841 uint8_t *pci_conf;
9113e3f3
MAL
842 uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY |
843 PCI_BASE_ADDRESS_MEM_PREFETCH;
fe44dc91 844 Error *local_err = NULL;
6cbf4c8c 845
6cbf4c8c
CM
846 /* IRQFD requires MSI */
847 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) &&
848 !ivshmem_has_feature(s, IVSHMEM_MSI)) {
d58d7e84
MAL
849 error_setg(errp, "ioeventfd/irqfd requires MSI");
850 return;
6cbf4c8c
CM
851 }
852
b7578eaa 853 pci_conf = dev->config;
6cbf4c8c 854 pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
6cbf4c8c 855
3c161542 856 memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s,
cb06608e
AK
857 "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE);
858
6cbf4c8c 859 /* region for registers*/
b7578eaa 860 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
e824b2cc 861 &s->ivshmem_mmio);
cb06608e 862
b2b79a69 863 if (s->not_legacy_32bit) {
9113e3f3 864 attr |= PCI_BASE_ADDRESS_MEM_TYPE_64;
c08ba66f 865 }
6cbf4c8c 866
d9453c93 867 if (s->hostmem != NULL) {
d9453c93
MAL
868 IVSHMEM_DPRINTF("using hostmem\n");
869
c2d8019c
MA
870 s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem,
871 &error_abort);
5503e285 872 } else {
0ec7b3e7 873 Chardev *chr = qemu_chr_fe_get_driver(&s->server_chr);
5345fdb4 874 assert(chr);
6dc64780 875
6cbf4c8c 876 IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n",
5345fdb4 877 chr->filename);
6cbf4c8c 878
f456179f 879 /* we allocate enough space for 16 peers and grow as needed */
1300b273 880 resize_peers(s, 16);
6cbf4c8c 881
3a55fc0f
MA
882 /*
883 * Receive setup messages from server synchronously.
884 * Older versions did it asynchronously, but that creates a
885 * number of entertaining race conditions.
3a55fc0f 886 */
1309cf44
MA
887 ivshmem_recv_setup(s, &err);
888 if (err) {
889 error_propagate(errp, err);
890 return;
3a55fc0f
MA
891 }
892
62a830b6
MA
893 if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) {
894 error_setg(errp,
895 "master must connect to the server before any peers");
896 return;
897 }
898
5345fdb4 899 qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive,
81517ba3 900 ivshmem_read, NULL, NULL, s, NULL, true);
1309cf44 901
ee640c62
C
902 if (ivshmem_setup_interrupts(s, errp) < 0) {
903 error_prepend(errp, "Failed to initialize interrupts: ");
3a55fc0f
MA
904 return;
905 }
d855e275
MA
906 }
907
2a845da7
MA
908 if (s->master == ON_OFF_AUTO_AUTO) {
909 s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
910 }
911
912 if (!ivshmem_is_master(s)) {
d855e275
MA
913 error_setg(&s->migration_blocker,
914 "Migration is disabled when using feature 'peer mode' in device 'ivshmem'");
fe44dc91
AA
915 migrate_add_blocker(s->migration_blocker, &local_err);
916 if (local_err) {
917 error_propagate(errp, local_err);
918 error_free(s->migration_blocker);
919 return;
920 }
6cbf4c8c 921 }
fe44dc91
AA
922
923 vmstate_register_ram(s->ivshmem_bar2, DEVICE(s));
924 pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2);
6cbf4c8c
CM
925}
926
5400c02b
MA
927static void ivshmem_exit(PCIDevice *dev)
928{
929 IVShmemState *s = IVSHMEM_COMMON(dev);
f64a078d
MAL
930 int i;
931
38e0735e
AL
932 if (s->migration_blocker) {
933 migrate_del_blocker(s->migration_blocker);
934 error_free(s->migration_blocker);
935 }
936
c2d8019c 937 if (memory_region_is_mapped(s->ivshmem_bar2)) {
d9453c93 938 if (!s->hostmem) {
c2d8019c 939 void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2);
56a571d9 940 int fd;
d9453c93 941
5400c02b 942 if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) {
d9453c93
MAL
943 error_report("Failed to munmap shared memory %s",
944 strerror(errno));
945 }
56a571d9 946
4ff87573 947 fd = memory_region_get_fd(s->ivshmem_bar2);
c2d8019c 948 close(fd);
d9453c93 949 }
f64a078d 950
c2d8019c 951 vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev));
f64a078d
MAL
952 }
953
f64a078d
MAL
954 if (s->peers) {
955 for (i = 0; i < s->nb_peers; i++) {
f456179f 956 close_peer_eventfds(s, i);
f64a078d
MAL
957 }
958 g_free(s->peers);
959 }
960
961 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
962 msix_uninit_exclusive_bar(dev);
963 }
964
0f57350e 965 g_free(s->msi_vectors);
6cbf4c8c
CM
966}
967
1f8552df
MAL
968static int ivshmem_pre_load(void *opaque)
969{
970 IVShmemState *s = opaque;
971
2a845da7 972 if (!ivshmem_is_master(s)) {
1f8552df
MAL
973 error_report("'peer' devices are not migratable");
974 return -EINVAL;
975 }
976
977 return 0;
978}
979
980static int ivshmem_post_load(void *opaque, int version_id)
981{
982 IVShmemState *s = opaque;
983
984 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8 985 ivshmem_msix_vector_use(s);
1f8552df 986 }
1f8552df
MAL
987 return 0;
988}
989
5400c02b 990static void ivshmem_common_class_init(ObjectClass *klass, void *data)
40021f08 991{
39bffca2 992 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL
993 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
994
5400c02b
MA
995 k->realize = ivshmem_common_realize;
996 k->exit = ivshmem_exit;
d58d7e84 997 k->config_write = ivshmem_write_config;
b8ef62a9
PB
998 k->vendor_id = PCI_VENDOR_ID_IVSHMEM;
999 k->device_id = PCI_DEVICE_ID_IVSHMEM;
40021f08 1000 k->class_id = PCI_CLASS_MEMORY_RAM;
5400c02b 1001 k->revision = 1;
39bffca2 1002 dc->reset = ivshmem_reset;
125ee0ed 1003 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
d383537d 1004 dc->desc = "Inter-VM shared memory";
40021f08
AL
1005}
1006
ddc85284
MA
1007static const TypeInfo ivshmem_common_info = {
1008 .name = TYPE_IVSHMEM_COMMON,
1009 .parent = TYPE_PCI_DEVICE,
1010 .instance_size = sizeof(IVShmemState),
1011 .abstract = true,
1012 .class_init = ivshmem_common_class_init,
fd3b02c8
EH
1013 .interfaces = (InterfaceInfo[]) {
1014 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1015 { },
1016 },
ddc85284 1017};
5400c02b 1018
5400c02b
MA
1019static const VMStateDescription ivshmem_plain_vmsd = {
1020 .name = TYPE_IVSHMEM_PLAIN,
1021 .version_id = 0,
1022 .minimum_version_id = 0,
1023 .pre_load = ivshmem_pre_load,
1024 .post_load = ivshmem_post_load,
1025 .fields = (VMStateField[]) {
1026 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1027 VMSTATE_UINT32(intrstatus, IVShmemState),
1028 VMSTATE_UINT32(intrmask, IVShmemState),
1029 VMSTATE_END_OF_LIST()
1030 },
1031};
1032
1033static Property ivshmem_plain_properties[] = {
1034 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
e9cb190a
FZ
1035 DEFINE_PROP_LINK("memdev", IVShmemState, hostmem, TYPE_MEMORY_BACKEND,
1036 HostMemoryBackend *),
5400c02b
MA
1037 DEFINE_PROP_END_OF_LIST(),
1038};
1039
1040static void ivshmem_plain_init(Object *obj)
1041{
1042 IVShmemState *s = IVSHMEM_PLAIN(obj);
1043
b2b79a69 1044 s->not_legacy_32bit = 1;
5400c02b
MA
1045}
1046
6dc64780
MAL
1047static void ivshmem_plain_realize(PCIDevice *dev, Error **errp)
1048{
1049 IVShmemState *s = IVSHMEM_COMMON(dev);
1050
1051 if (!s->hostmem) {
1052 error_setg(errp, "You must specify a 'memdev'");
1053 return;
e9cb190a
FZ
1054 } else if (host_memory_backend_is_mapped(s->hostmem)) {
1055 char *path = object_get_canonical_path_component(OBJECT(s->hostmem));
1056 error_setg(errp, "can't use already busy memdev: %s", path);
1057 g_free(path);
1058 return;
6dc64780
MAL
1059 }
1060
1061 ivshmem_common_realize(dev, errp);
2aece63c
XG
1062 host_memory_backend_set_mapped(s->hostmem, true);
1063}
1064
1065static void ivshmem_plain_exit(PCIDevice *pci_dev)
1066{
1067 IVShmemState *s = IVSHMEM_COMMON(pci_dev);
1068
1069 host_memory_backend_set_mapped(s->hostmem, false);
6dc64780
MAL
1070}
1071
5400c02b
MA
1072static void ivshmem_plain_class_init(ObjectClass *klass, void *data)
1073{
1074 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1075 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1076
6dc64780 1077 k->realize = ivshmem_plain_realize;
2aece63c 1078 k->exit = ivshmem_plain_exit;
5400c02b
MA
1079 dc->props = ivshmem_plain_properties;
1080 dc->vmsd = &ivshmem_plain_vmsd;
1081}
1082
1083static const TypeInfo ivshmem_plain_info = {
1084 .name = TYPE_IVSHMEM_PLAIN,
1085 .parent = TYPE_IVSHMEM_COMMON,
1086 .instance_size = sizeof(IVShmemState),
1087 .instance_init = ivshmem_plain_init,
1088 .class_init = ivshmem_plain_class_init,
1089};
1090
1091static const VMStateDescription ivshmem_doorbell_vmsd = {
1092 .name = TYPE_IVSHMEM_DOORBELL,
1093 .version_id = 0,
1094 .minimum_version_id = 0,
1095 .pre_load = ivshmem_pre_load,
1096 .post_load = ivshmem_post_load,
1097 .fields = (VMStateField[]) {
1098 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1099 VMSTATE_MSIX(parent_obj, IVShmemState),
1100 VMSTATE_UINT32(intrstatus, IVShmemState),
1101 VMSTATE_UINT32(intrmask, IVShmemState),
1102 VMSTATE_END_OF_LIST()
1103 },
1104};
1105
1106static Property ivshmem_doorbell_properties[] = {
1107 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1108 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1109 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1110 true),
1111 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1112 DEFINE_PROP_END_OF_LIST(),
1113};
1114
1115static void ivshmem_doorbell_init(Object *obj)
1116{
1117 IVShmemState *s = IVSHMEM_DOORBELL(obj);
1118
1119 s->features |= (1 << IVSHMEM_MSI);
1120 s->legacy_size = SIZE_MAX; /* whatever the server sends */
b2b79a69 1121 s->not_legacy_32bit = 1;
5400c02b
MA
1122}
1123
6dc64780
MAL
1124static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp)
1125{
1126 IVShmemState *s = IVSHMEM_COMMON(dev);
1127
30650701 1128 if (!qemu_chr_fe_backend_connected(&s->server_chr)) {
6dc64780
MAL
1129 error_setg(errp, "You must specify a 'chardev'");
1130 return;
1131 }
1132
1133 ivshmem_common_realize(dev, errp);
1134}
1135
5400c02b
MA
1136static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data)
1137{
1138 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1139 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1140
6dc64780 1141 k->realize = ivshmem_doorbell_realize;
5400c02b
MA
1142 dc->props = ivshmem_doorbell_properties;
1143 dc->vmsd = &ivshmem_doorbell_vmsd;
1144}
1145
1146static const TypeInfo ivshmem_doorbell_info = {
1147 .name = TYPE_IVSHMEM_DOORBELL,
1148 .parent = TYPE_IVSHMEM_COMMON,
1149 .instance_size = sizeof(IVShmemState),
1150 .instance_init = ivshmem_doorbell_init,
1151 .class_init = ivshmem_doorbell_class_init,
1152};
1153
ddc85284
MA
1154static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id)
1155{
1156 IVShmemState *s = opaque;
1157 PCIDevice *pdev = PCI_DEVICE(s);
1158 int ret;
1159
1160 IVSHMEM_DPRINTF("ivshmem_load_old\n");
1161
1162 if (version_id != 0) {
1163 return -EINVAL;
1164 }
1165
1166 ret = ivshmem_pre_load(s);
1167 if (ret) {
1168 return ret;
1169 }
1170
1171 ret = pci_device_load(pdev, f);
1172 if (ret) {
1173 return ret;
1174 }
1175
1176 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
1177 msix_load(pdev, f);
1178 ivshmem_msix_vector_use(s);
1179 } else {
1180 s->intrstatus = qemu_get_be32(f);
1181 s->intrmask = qemu_get_be32(f);
1182 }
1183
1184 return 0;
1185}
1186
1187static bool test_msix(void *opaque, int version_id)
1188{
1189 IVShmemState *s = opaque;
1190
1191 return ivshmem_has_feature(s, IVSHMEM_MSI);
1192}
1193
1194static bool test_no_msix(void *opaque, int version_id)
1195{
1196 return !test_msix(opaque, version_id);
1197}
1198
1199static const VMStateDescription ivshmem_vmsd = {
1200 .name = "ivshmem",
1201 .version_id = 1,
1202 .minimum_version_id = 1,
1203 .pre_load = ivshmem_pre_load,
1204 .post_load = ivshmem_post_load,
1205 .fields = (VMStateField[]) {
1206 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1207
1208 VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix),
1209 VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix),
1210 VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix),
1211
1212 VMSTATE_END_OF_LIST()
1213 },
1214 .load_state_old = ivshmem_load_old,
1215 .minimum_version_id_old = 0
1216};
1217
1218static Property ivshmem_properties[] = {
1219 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1220 DEFINE_PROP_STRING("size", IVShmemState, sizearg),
1221 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1222 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1223 false),
1224 DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
1225 DEFINE_PROP_STRING("shm", IVShmemState, shmobj),
1226 DEFINE_PROP_STRING("role", IVShmemState, role),
1227 DEFINE_PROP_UINT32("use64", IVShmemState, not_legacy_32bit, 1),
1228 DEFINE_PROP_END_OF_LIST(),
1229};
1230
1231static void desugar_shm(IVShmemState *s)
1232{
1233 Object *obj;
1234 char *path;
1235
1236 obj = object_new("memory-backend-file");
1237 path = g_strdup_printf("/dev/shm/%s", s->shmobj);
1238 object_property_set_str(obj, path, "mem-path", &error_abort);
1239 g_free(path);
1240 object_property_set_int(obj, s->legacy_size, "size", &error_abort);
1241 object_property_set_bool(obj, true, "share", &error_abort);
1242 object_property_add_child(OBJECT(s), "internal-shm-backend", obj,
1243 &error_abort);
1244 user_creatable_complete(obj, &error_abort);
1245 s->hostmem = MEMORY_BACKEND(obj);
1246}
1247
1248static void ivshmem_realize(PCIDevice *dev, Error **errp)
1249{
1250 IVShmemState *s = IVSHMEM_COMMON(dev);
1251
1252 if (!qtest_enabled()) {
1253 error_report("ivshmem is deprecated, please use ivshmem-plain"
1254 " or ivshmem-doorbell instead");
1255 }
1256
30650701 1257 if (qemu_chr_fe_backend_connected(&s->server_chr) + !!s->shmobj != 1) {
13fd2cb6 1258 error_setg(errp, "You must specify either 'shm' or 'chardev'");
ddc85284
MA
1259 return;
1260 }
1261
13fd2cb6 1262 if (s->sizearg == NULL) {
ddc85284
MA
1263 s->legacy_size = 4 << 20; /* 4 MB default */
1264 } else {
f17fd4fd 1265 int ret;
f46bfdbf 1266 uint64_t size;
f17fd4fd
MA
1267
1268 ret = qemu_strtosz_MiB(s->sizearg, NULL, &size);
1269 if (ret < 0 || (size_t)size != size || !is_power_of_2(size)) {
ddc85284
MA
1270 error_setg(errp, "Invalid size %s", s->sizearg);
1271 return;
1272 }
1273 s->legacy_size = size;
1274 }
1275
1276 /* check that role is reasonable */
1277 if (s->role) {
1278 if (strncmp(s->role, "peer", 5) == 0) {
1279 s->master = ON_OFF_AUTO_OFF;
1280 } else if (strncmp(s->role, "master", 7) == 0) {
1281 s->master = ON_OFF_AUTO_ON;
1282 } else {
1283 error_setg(errp, "'role' must be 'peer' or 'master'");
1284 return;
1285 }
1286 } else {
1287 s->master = ON_OFF_AUTO_AUTO;
1288 }
1289
1290 if (s->shmobj) {
1291 desugar_shm(s);
1292 }
1293
1294 /*
1295 * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a
1296 * bald-faced lie then. But it's a backwards compatible lie.
1297 */
1298 pci_config_set_interrupt_pin(dev->config, 1);
1299
1300 ivshmem_common_realize(dev, errp);
1301}
1302
ddc85284
MA
1303static void ivshmem_class_init(ObjectClass *klass, void *data)
1304{
1305 DeviceClass *dc = DEVICE_CLASS(klass);
1306 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1307
1308 k->realize = ivshmem_realize;
1309 k->revision = 0;
1310 dc->desc = "Inter-VM shared memory (legacy)";
1311 dc->props = ivshmem_properties;
1312 dc->vmsd = &ivshmem_vmsd;
1313}
1314
1315static const TypeInfo ivshmem_info = {
1316 .name = TYPE_IVSHMEM,
1317 .parent = TYPE_IVSHMEM_COMMON,
1318 .instance_size = sizeof(IVShmemState),
ddc85284
MA
1319 .class_init = ivshmem_class_init,
1320};
1321
83f7d43a 1322static void ivshmem_register_types(void)
6cbf4c8c 1323{
5400c02b
MA
1324 type_register_static(&ivshmem_common_info);
1325 type_register_static(&ivshmem_plain_info);
1326 type_register_static(&ivshmem_doorbell_info);
39bffca2 1327 type_register_static(&ivshmem_info);
6cbf4c8c
CM
1328}
1329
83f7d43a 1330type_init(ivshmem_register_types)
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