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ivshmem: Clean up after the previous commit
[qemu.git] / hw / misc / ivshmem.c
CommitLineData
6cbf4c8c
CM
1/*
2 * Inter-VM Shared Memory PCI device.
3 *
4 * Author:
5 * Cam Macdonell <[email protected]>
6 *
7 * Based On: cirrus_vga.c
8 * Copyright (c) 2004 Fabrice Bellard
9 * Copyright (c) 2004 Makoto Suzuki (suzu)
10 *
11 * and rtl8139.c
12 * Copyright (c) 2006 Igor Kovalenko
13 *
14 * This code is licensed under the GNU GPL v2.
6b620ca3
PB
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
6cbf4c8c 18 */
0d1c9782 19#include "qemu/osdep.h"
83c9f4ca 20#include "hw/hw.h"
0d09e41a 21#include "hw/i386/pc.h"
83c9f4ca 22#include "hw/pci/pci.h"
660c97ee 23#include "hw/pci/msi.h"
83c9f4ca 24#include "hw/pci/msix.h"
9c17d615 25#include "sysemu/kvm.h"
caf71f86 26#include "migration/migration.h"
d49b6836 27#include "qemu/error-report.h"
1de7afc9 28#include "qemu/event_notifier.h"
5503e285 29#include "qom/object_interfaces.h"
dccfcd0e 30#include "sysemu/char.h"
d9453c93 31#include "sysemu/hostmem.h"
5400c02b 32#include "sysemu/qtest.h"
d9453c93 33#include "qapi/visitor.h"
56a571d9 34#include "exec/ram_addr.h"
6cbf4c8c 35
5105b1d8
DM
36#include "hw/misc/ivshmem.h"
37
6cbf4c8c 38#include <sys/mman.h>
6cbf4c8c 39
b8ef62a9
PB
40#define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET
41#define PCI_DEVICE_ID_IVSHMEM 0x1110
42
cd9953f7 43#define IVSHMEM_MAX_PEERS UINT16_MAX
6cbf4c8c
CM
44#define IVSHMEM_IOEVENTFD 0
45#define IVSHMEM_MSI 1
46
6cbf4c8c
CM
47#define IVSHMEM_REG_BAR_SIZE 0x100
48
a4fa93bf
MA
49#define IVSHMEM_DEBUG 0
50#define IVSHMEM_DPRINTF(fmt, ...) \
51 do { \
52 if (IVSHMEM_DEBUG) { \
53 printf("IVSHMEM: " fmt, ## __VA_ARGS__); \
54 } \
55 } while (0)
6cbf4c8c 56
5400c02b
MA
57#define TYPE_IVSHMEM_COMMON "ivshmem-common"
58#define IVSHMEM_COMMON(obj) \
59 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON)
60
61#define TYPE_IVSHMEM_PLAIN "ivshmem-plain"
62#define IVSHMEM_PLAIN(obj) \
63 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN)
64
65#define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell"
66#define IVSHMEM_DOORBELL(obj) \
67 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL)
68
eb3fedf3
PC
69#define TYPE_IVSHMEM "ivshmem"
70#define IVSHMEM(obj) \
71 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
72
6cbf4c8c
CM
73typedef struct Peer {
74 int nb_eventfds;
563027cc 75 EventNotifier *eventfds;
6cbf4c8c
CM
76} Peer;
77
0f57350e 78typedef struct MSIVector {
6cbf4c8c 79 PCIDevice *pdev;
660c97ee 80 int virq;
0f57350e 81} MSIVector;
6cbf4c8c
CM
82
83typedef struct IVShmemState {
b7578eaa
AF
84 /*< private >*/
85 PCIDevice parent_obj;
86 /*< public >*/
87
ddc85284
MA
88 uint32_t features;
89
90 /* exactly one of these two may be set */
91 HostMemoryBackend *hostmem; /* with interrupts */
92 CharDriverState *server_chr; /* without interrupts */
93
94 /* registers */
6cbf4c8c
CM
95 uint32_t intrmask;
96 uint32_t intrstatus;
ddc85284 97 int vm_id;
6cbf4c8c 98
ddc85284
MA
99 /* BARs */
100 MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */
c2d8019c
MA
101 MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */
102 MemoryRegion server_bar2; /* used with server_chr */
6cbf4c8c 103
ddc85284 104 /* interrupt support */
6cbf4c8c 105 Peer *peers;
cd9953f7 106 int nb_peers; /* space in @peers[] */
6cbf4c8c 107 uint32_t vectors;
0f57350e 108 MSIVector *msi_vectors;
ee276391
MA
109 uint64_t msg_buf; /* buffer for receiving server messages */
110 int msg_buffered_bytes; /* #bytes in @msg_buf */
6cbf4c8c 111
ddc85284 112 /* migration stuff */
2a845da7 113 OnOffAuto master;
38e0735e
AL
114 Error *migration_blocker;
115
5400c02b
MA
116 /* legacy cruft */
117 char *role;
118 char *shmobj;
119 char *sizearg;
120 size_t legacy_size;
121 uint32_t not_legacy_32bit;
6cbf4c8c
CM
122} IVShmemState;
123
124/* registers for the Inter-VM shared memory device */
125enum ivshmem_registers {
126 INTRMASK = 0,
127 INTRSTATUS = 4,
128 IVPOSITION = 8,
129 DOORBELL = 12,
130};
131
132static inline uint32_t ivshmem_has_feature(IVShmemState *ivs,
133 unsigned int feature) {
134 return (ivs->features & (1 << feature));
135}
136
2a845da7
MA
137static inline bool ivshmem_is_master(IVShmemState *s)
138{
139 assert(s->master != ON_OFF_AUTO_AUTO);
140 return s->master == ON_OFF_AUTO_ON;
141}
142
d8a5da07 143static void ivshmem_update_irq(IVShmemState *s)
6cbf4c8c 144{
b7578eaa 145 PCIDevice *d = PCI_DEVICE(s);
434ad76d 146 uint32_t isr = s->intrstatus & s->intrmask;
6cbf4c8c 147
5400c02b
MA
148 /*
149 * Do nothing unless the device actually uses INTx. Here's how
150 * the device variants signal interrupts, what they put in PCI
151 * config space:
152 * Device variant Interrupt Interrupt Pin MSI-X cap.
153 * ivshmem-plain none 0 no
154 * ivshmem-doorbell MSI-X 1 yes(1)
155 * ivshmem,msi=off INTx 1 no
156 * ivshmem,msi=on MSI-X 1(2) yes(1)
157 * (1) if guest enabled MSI-X
158 * (2) the device lies
159 * Leads to the condition for doing nothing:
160 */
161 if (ivshmem_has_feature(s, IVSHMEM_MSI)
162 || !d->config[PCI_INTERRUPT_PIN]) {
2d1d422d
MA
163 return;
164 }
165
6cbf4c8c
CM
166 /* don't print ISR resets */
167 if (isr) {
168 IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n",
dbc464d4 169 isr ? 1 : 0, s->intrstatus, s->intrmask);
6cbf4c8c
CM
170 }
171
434ad76d 172 pci_set_irq(d, isr != 0);
6cbf4c8c
CM
173}
174
175static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
176{
177 IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val);
178
179 s->intrmask = val;
d8a5da07 180 ivshmem_update_irq(s);
6cbf4c8c
CM
181}
182
183static uint32_t ivshmem_IntrMask_read(IVShmemState *s)
184{
185 uint32_t ret = s->intrmask;
186
187 IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret);
6cbf4c8c
CM
188 return ret;
189}
190
191static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val)
192{
193 IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val);
194
195 s->intrstatus = val;
d8a5da07 196 ivshmem_update_irq(s);
6cbf4c8c
CM
197}
198
199static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
200{
201 uint32_t ret = s->intrstatus;
202
203 /* reading ISR clears all interrupts */
204 s->intrstatus = 0;
d8a5da07 205 ivshmem_update_irq(s);
6cbf4c8c
CM
206 return ret;
207}
208
a8170e5e 209static void ivshmem_io_write(void *opaque, hwaddr addr,
cb06608e 210 uint64_t val, unsigned size)
6cbf4c8c
CM
211{
212 IVShmemState *s = opaque;
213
6cbf4c8c
CM
214 uint16_t dest = val >> 16;
215 uint16_t vector = val & 0xff;
216
217 addr &= 0xfc;
218
219 IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr);
220 switch (addr)
221 {
222 case INTRMASK:
223 ivshmem_IntrMask_write(s, val);
224 break;
225
226 case INTRSTATUS:
227 ivshmem_IntrStatus_write(s, val);
228 break;
229
230 case DOORBELL:
231 /* check that dest VM ID is reasonable */
95c8425c 232 if (dest >= s->nb_peers) {
6cbf4c8c
CM
233 IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest);
234 break;
235 }
236
237 /* check doorbell range */
1b27d7a1 238 if (vector < s->peers[dest].nb_eventfds) {
563027cc
PB
239 IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector);
240 event_notifier_set(&s->peers[dest].eventfds[vector]);
f59bb378
MAL
241 } else {
242 IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n",
243 vector, dest);
6cbf4c8c
CM
244 }
245 break;
246 default:
f59bb378 247 IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr);
6cbf4c8c
CM
248 }
249}
250
a8170e5e 251static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
cb06608e 252 unsigned size)
6cbf4c8c
CM
253{
254
255 IVShmemState *s = opaque;
256 uint32_t ret;
257
258 switch (addr)
259 {
260 case INTRMASK:
261 ret = ivshmem_IntrMask_read(s);
262 break;
263
264 case INTRSTATUS:
265 ret = ivshmem_IntrStatus_read(s);
266 break;
267
268 case IVPOSITION:
1309cf44 269 ret = s->vm_id;
6cbf4c8c
CM
270 break;
271
272 default:
273 IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr);
274 ret = 0;
275 }
276
277 return ret;
278}
279
cb06608e
AK
280static const MemoryRegionOps ivshmem_mmio_ops = {
281 .read = ivshmem_io_read,
282 .write = ivshmem_io_write,
283 .endianness = DEVICE_NATIVE_ENDIAN,
284 .impl = {
285 .min_access_size = 4,
286 .max_access_size = 4,
287 },
6cbf4c8c
CM
288};
289
9940c323
MAL
290static void ivshmem_vector_notify(void *opaque)
291{
0f57350e 292 MSIVector *entry = opaque;
6cbf4c8c 293 PCIDevice *pdev = entry->pdev;
5400c02b 294 IVShmemState *s = IVSHMEM_COMMON(pdev);
0f57350e 295 int vector = entry - s->msi_vectors;
9940c323
MAL
296 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
297
298 if (!event_notifier_test_and_clear(n)) {
299 return;
300 }
6cbf4c8c 301
d160f3f7 302 IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector);
9940c323 303 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8
MA
304 if (msix_enabled(pdev)) {
305 msix_notify(pdev, vector);
306 }
9940c323
MAL
307 } else {
308 ivshmem_IntrStatus_write(s, 1);
309 }
6cbf4c8c
CM
310}
311
660c97ee
MAL
312static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector,
313 MSIMessage msg)
314{
5400c02b 315 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
316 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
317 MSIVector *v = &s->msi_vectors[vector];
318 int ret;
319
320 IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector);
321
322 ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev);
323 if (ret < 0) {
324 return ret;
325 }
326
327 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq);
328}
329
330static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector)
331{
5400c02b 332 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
333 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
334 int ret;
335
336 IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector);
337
338 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n,
339 s->msi_vectors[vector].virq);
340 if (ret != 0) {
341 error_report("remove_irqfd_notifier_gsi failed");
342 }
343}
344
345static void ivshmem_vector_poll(PCIDevice *dev,
346 unsigned int vector_start,
347 unsigned int vector_end)
348{
5400c02b 349 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
350 unsigned int vector;
351
352 IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end);
353
354 vector_end = MIN(vector_end, s->vectors);
355
356 for (vector = vector_start; vector < vector_end; vector++) {
357 EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector];
358
359 if (!msix_is_masked(dev, vector)) {
360 continue;
361 }
362
363 if (event_notifier_test_and_clear(notifier)) {
364 msix_set_pending(dev, vector);
365 }
366 }
367}
368
9940c323
MAL
369static void watch_vector_notifier(IVShmemState *s, EventNotifier *n,
370 int vector)
6cbf4c8c 371{
563027cc 372 int eventfd = event_notifier_get_fd(n);
6cbf4c8c 373
3c27969b 374 assert(!s->msi_vectors[vector].pdev);
9940c323 375 s->msi_vectors[vector].pdev = PCI_DEVICE(s);
6cbf4c8c 376
9940c323
MAL
377 qemu_set_fd_handler(eventfd, ivshmem_vector_notify,
378 NULL, &s->msi_vectors[vector]);
6cbf4c8c
CM
379}
380
563027cc
PB
381static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i)
382{
383 memory_region_add_eventfd(&s->ivshmem_mmio,
384 DOORBELL,
385 4,
386 true,
387 (posn << 16) | i,
753d5e14 388 &s->peers[posn].eventfds[i]);
563027cc
PB
389}
390
391static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i)
392{
393 memory_region_del_eventfd(&s->ivshmem_mmio,
394 DOORBELL,
395 4,
396 true,
397 (posn << 16) | i,
753d5e14 398 &s->peers[posn].eventfds[i]);
563027cc
PB
399}
400
f456179f 401static void close_peer_eventfds(IVShmemState *s, int posn)
6cbf4c8c 402{
f456179f 403 int i, n;
6cbf4c8c 404
9db51b4d 405 assert(posn >= 0 && posn < s->nb_peers);
f456179f 406 n = s->peers[posn].nb_eventfds;
6cbf4c8c 407
9db51b4d
MA
408 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
409 memory_region_transaction_begin();
410 for (i = 0; i < n; i++) {
411 ivshmem_del_eventfd(s, posn, i);
412 }
413 memory_region_transaction_commit();
b6a1f3a5 414 }
9db51b4d 415
f456179f 416 for (i = 0; i < n; i++) {
563027cc 417 event_notifier_cleanup(&s->peers[posn].eventfds[i]);
6cbf4c8c
CM
418 }
419
7267c094 420 g_free(s->peers[posn].eventfds);
6cbf4c8c
CM
421 s->peers[posn].nb_eventfds = 0;
422}
423
cd9953f7 424static void resize_peers(IVShmemState *s, int nb_peers)
34bc07c5 425{
cd9953f7
MA
426 int old_nb_peers = s->nb_peers;
427 int i;
6cbf4c8c 428
cd9953f7
MA
429 assert(nb_peers > old_nb_peers);
430 IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers);
6cbf4c8c 431
cd9953f7
MA
432 s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer));
433 s->nb_peers = nb_peers;
1300b273 434
cd9953f7
MA
435 for (i = old_nb_peers; i < nb_peers; i++) {
436 s->peers[i].eventfds = g_new0(EventNotifier, s->vectors);
437 s->peers[i].nb_eventfds = 0;
6cbf4c8c
CM
438 }
439}
440
1309cf44
MA
441static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector,
442 Error **errp)
660c97ee
MAL
443{
444 PCIDevice *pdev = PCI_DEVICE(s);
445 MSIMessage msg = msix_get_message(pdev, vector);
446 int ret;
447
448 IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector);
3c27969b 449 assert(!s->msi_vectors[vector].pdev);
660c97ee
MAL
450
451 ret = kvm_irqchip_add_msi_route(kvm_state, msg, pdev);
452 if (ret < 0) {
1309cf44
MA
453 error_setg(errp, "kvm_irqchip_add_msi_route failed");
454 return;
660c97ee
MAL
455 }
456
457 s->msi_vectors[vector].virq = ret;
458 s->msi_vectors[vector].pdev = pdev;
660c97ee
MAL
459}
460
1309cf44 461static void setup_interrupt(IVShmemState *s, int vector, Error **errp)
660c97ee
MAL
462{
463 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
464 bool with_irqfd = kvm_msi_via_irqfd_enabled() &&
465 ivshmem_has_feature(s, IVSHMEM_MSI);
466 PCIDevice *pdev = PCI_DEVICE(s);
1309cf44 467 Error *err = NULL;
660c97ee
MAL
468
469 IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector);
470
471 if (!with_irqfd) {
97553976 472 IVSHMEM_DPRINTF("with eventfd\n");
9940c323 473 watch_vector_notifier(s, n, vector);
660c97ee 474 } else if (msix_enabled(pdev)) {
97553976 475 IVSHMEM_DPRINTF("with irqfd\n");
1309cf44
MA
476 ivshmem_add_kvm_msi_virq(s, vector, &err);
477 if (err) {
478 error_propagate(errp, err);
660c97ee
MAL
479 return;
480 }
481
482 if (!msix_is_masked(pdev, vector)) {
483 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL,
484 s->msi_vectors[vector].virq);
1309cf44 485 /* TODO handle error */
660c97ee
MAL
486 }
487 } else {
488 /* it will be delayed until msix is enabled, in write_config */
97553976 489 IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n");
660c97ee
MAL
490 }
491}
492
1309cf44 493static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
6cbf4c8c 494{
8baeb22b 495 struct stat buf;
5400c02b 496 size_t size;
ca0b7566 497 void *ptr;
6cbf4c8c 498
c2d8019c 499 if (s->ivshmem_bar2) {
1309cf44 500 error_setg(errp, "server sent unexpected shared memory message");
ca0b7566 501 close(fd);
0f14fd71 502 return;
a2e9011b
SH
503 }
504
8baeb22b
MA
505 if (fstat(fd, &buf) < 0) {
506 error_setg_errno(errp, errno,
507 "can't determine size of shared memory sent by server");
508 close(fd);
509 return;
510 }
511
5400c02b
MA
512 size = buf.st_size;
513
514 /* Legacy cruft */
515 if (s->legacy_size != SIZE_MAX) {
516 if (size < s->legacy_size) {
517 error_setg(errp, "server sent only %zd bytes of shared memory",
518 (size_t)buf.st_size);
519 close(fd);
520 return;
521 }
522 size = s->legacy_size;
cd9953f7
MA
523 }
524
ca0b7566 525 /* mmap the region and map into the BAR2 */
5400c02b 526 ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
ca0b7566 527 if (ptr == MAP_FAILED) {
1309cf44 528 error_setg_errno(errp, errno, "Failed to mmap shared memory");
ca0b7566
MA
529 close(fd);
530 return;
6cbf4c8c 531 }
c2d8019c 532 memory_region_init_ram_ptr(&s->server_bar2, OBJECT(s),
5400c02b 533 "ivshmem.bar2", size, ptr);
c2d8019c
MA
534 qemu_set_ram_fd(memory_region_get_ram_addr(&s->server_bar2), fd);
535 s->ivshmem_bar2 = &s->server_bar2;
ca0b7566
MA
536}
537
1309cf44
MA
538static void process_msg_disconnect(IVShmemState *s, uint16_t posn,
539 Error **errp)
ca0b7566
MA
540{
541 IVSHMEM_DPRINTF("posn %d has gone away\n", posn);
9db51b4d 542 if (posn >= s->nb_peers || posn == s->vm_id) {
1309cf44 543 error_setg(errp, "invalid peer %d", posn);
9db51b4d
MA
544 return;
545 }
ca0b7566
MA
546 close_peer_eventfds(s, posn);
547}
6cbf4c8c 548
1309cf44
MA
549static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd,
550 Error **errp)
ca0b7566
MA
551{
552 Peer *peer = &s->peers[posn];
553 int vector;
9a2f0e64 554
ca0b7566
MA
555 /*
556 * The N-th connect message for this peer comes with the file
557 * descriptor for vector N-1. Count messages to find the vector.
558 */
559 if (peer->nb_eventfds >= s->vectors) {
1309cf44
MA
560 error_setg(errp, "Too many eventfd received, device has %d vectors",
561 s->vectors);
ca0b7566 562 close(fd);
6f8a16d5 563 return;
6cbf4c8c 564 }
ca0b7566 565 vector = peer->nb_eventfds++;
6cbf4c8c 566
ca0b7566
MA
567 IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd);
568 event_notifier_init_fd(&peer->eventfds[vector], fd);
569 fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */
945001a1 570
ca0b7566 571 if (posn == s->vm_id) {
1309cf44
MA
572 setup_interrupt(s, vector, errp);
573 /* TODO do we need to handle the error? */
ca0b7566 574 }
6cbf4c8c 575
ca0b7566
MA
576 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
577 ivshmem_add_eventfd(s, posn, vector);
578 }
579}
6cbf4c8c 580
1309cf44 581static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp)
ca0b7566
MA
582{
583 IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd);
6cbf4c8c 584
ca0b7566 585 if (msg < -1 || msg > IVSHMEM_MAX_PEERS) {
1309cf44 586 error_setg(errp, "server sent invalid message %" PRId64, msg);
ca0b7566 587 close(fd);
6cbf4c8c
CM
588 return;
589 }
590
ca0b7566 591 if (msg == -1) {
1309cf44 592 process_msg_shmem(s, fd, errp);
1ee57de4
MAL
593 return;
594 }
595
ca0b7566
MA
596 if (msg >= s->nb_peers) {
597 resize_peers(s, msg + 1);
598 }
6cbf4c8c 599
ca0b7566 600 if (fd >= 0) {
1309cf44 601 process_msg_connect(s, msg, fd, errp);
ca0b7566 602 } else {
1309cf44 603 process_msg_disconnect(s, msg, errp);
6cbf4c8c 604 }
ca0b7566 605}
6cbf4c8c 606
ee276391
MA
607static int ivshmem_can_receive(void *opaque)
608{
609 IVShmemState *s = opaque;
610
611 assert(s->msg_buffered_bytes < sizeof(s->msg_buf));
612 return sizeof(s->msg_buf) - s->msg_buffered_bytes;
613}
614
ca0b7566
MA
615static void ivshmem_read(void *opaque, const uint8_t *buf, int size)
616{
617 IVShmemState *s = opaque;
1309cf44 618 Error *err = NULL;
ca0b7566
MA
619 int fd;
620 int64_t msg;
621
ee276391
MA
622 assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf));
623 memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size);
624 s->msg_buffered_bytes += size;
625 if (s->msg_buffered_bytes < sizeof(s->msg_buf)) {
ca0b7566 626 return;
6cbf4c8c 627 }
ee276391
MA
628 msg = le64_to_cpu(s->msg_buf);
629 s->msg_buffered_bytes = 0;
ca0b7566
MA
630
631 fd = qemu_chr_fe_get_msgfd(s->server_chr);
632 IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd);
633
1309cf44
MA
634 process_msg(s, msg, fd, &err);
635 if (err) {
636 error_report_err(err);
637 }
6cbf4c8c
CM
638}
639
1309cf44 640static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp)
5105b1d8 641{
3a55fc0f
MA
642 int64_t msg;
643 int n, ret;
644
645 n = 0;
646 do {
647 ret = qemu_chr_fe_read_all(s->server_chr, (uint8_t *)&msg + n,
648 sizeof(msg) - n);
649 if (ret < 0 && ret != -EINTR) {
1309cf44 650 error_setg_errno(errp, -ret, "read from server failed");
3a55fc0f
MA
651 return INT64_MIN;
652 }
653 n += ret;
654 } while (n < sizeof(msg));
5105b1d8 655
3a55fc0f
MA
656 *pfd = qemu_chr_fe_get_msgfd(s->server_chr);
657 return msg;
658}
5105b1d8 659
1309cf44 660static void ivshmem_recv_setup(IVShmemState *s, Error **errp)
3a55fc0f 661{
1309cf44 662 Error *err = NULL;
3a55fc0f
MA
663 int64_t msg;
664 int fd;
665
1309cf44
MA
666 msg = ivshmem_recv_msg(s, &fd, &err);
667 if (err) {
668 error_propagate(errp, err);
669 return;
670 }
671 if (msg != IVSHMEM_PROTOCOL_VERSION) {
672 error_setg(errp, "server sent version %" PRId64 ", expecting %d",
673 msg, IVSHMEM_PROTOCOL_VERSION);
674 return;
675 }
676 if (fd != -1) {
677 error_setg(errp, "server sent invalid version message");
5105b1d8
DM
678 return;
679 }
680
a3feb086
MA
681 /*
682 * ivshmem-server sends the remaining initial messages in a fixed
683 * order, but the device has always accepted them in any order.
684 * Stay as compatible as practical, just in case people use
685 * servers that behave differently.
686 */
687
688 /*
689 * ivshmem_device_spec.txt has always required the ID message
690 * right here, and ivshmem-server has always complied. However,
691 * older versions of the device accepted it out of order, but
692 * broke when an interrupt setup message arrived before it.
693 */
694 msg = ivshmem_recv_msg(s, &fd, &err);
695 if (err) {
696 error_propagate(errp, err);
697 return;
698 }
699 if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) {
700 error_setg(errp, "server sent invalid ID message");
701 return;
702 }
703 s->vm_id = msg;
704
3a55fc0f
MA
705 /*
706 * Receive more messages until we got shared memory.
707 */
708 do {
1309cf44
MA
709 msg = ivshmem_recv_msg(s, &fd, &err);
710 if (err) {
711 error_propagate(errp, err);
712 return;
713 }
714 process_msg(s, msg, fd, &err);
715 if (err) {
716 error_propagate(errp, err);
717 return;
718 }
3a55fc0f 719 } while (msg != -1);
1309cf44
MA
720
721 /*
722 * This function must either map the shared memory or fail. The
723 * loop above ensures that: it terminates normally only after it
724 * successfully processed the server's shared memory message.
725 * Assert that actually mapped the shared memory:
726 */
c2d8019c 727 assert(s->ivshmem_bar2);
5105b1d8
DM
728}
729
4490c711
MT
730/* Select the MSI-X vectors used by device.
731 * ivshmem maps events to vectors statically, so
732 * we just enable all vectors on init and after reset. */
082751e8 733static void ivshmem_msix_vector_use(IVShmemState *s)
4490c711 734{
b7578eaa 735 PCIDevice *d = PCI_DEVICE(s);
4490c711
MT
736 int i;
737
4490c711 738 for (i = 0; i < s->vectors; i++) {
b7578eaa 739 msix_vector_use(d, i);
4490c711
MT
740 }
741}
742
6cbf4c8c
CM
743static void ivshmem_reset(DeviceState *d)
744{
5400c02b 745 IVShmemState *s = IVSHMEM_COMMON(d);
6cbf4c8c
CM
746
747 s->intrstatus = 0;
972ad215 748 s->intrmask = 0;
082751e8
MA
749 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
750 ivshmem_msix_vector_use(s);
751 }
6cbf4c8c
CM
752}
753
fd47bfe5 754static int ivshmem_setup_interrupts(IVShmemState *s)
4490c711 755{
fd47bfe5
MAL
756 /* allocate QEMU callback data for receiving interrupts */
757 s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector));
6cbf4c8c 758
fd47bfe5
MAL
759 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
760 if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) {
761 return -1;
762 }
1116b539 763
fd47bfe5 764 IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
082751e8 765 ivshmem_msix_vector_use(s);
fd47bfe5 766 }
4490c711 767
d58d7e84 768 return 0;
6cbf4c8c
CM
769}
770
660c97ee
MAL
771static void ivshmem_enable_irqfd(IVShmemState *s)
772{
773 PCIDevice *pdev = PCI_DEVICE(s);
774 int i;
775
776 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
1309cf44
MA
777 Error *err = NULL;
778
779 ivshmem_add_kvm_msi_virq(s, i, &err);
780 if (err) {
781 error_report_err(err);
782 /* TODO do we need to handle the error? */
783 }
660c97ee
MAL
784 }
785
786 if (msix_set_vector_notifiers(pdev,
787 ivshmem_vector_unmask,
788 ivshmem_vector_mask,
789 ivshmem_vector_poll)) {
790 error_report("ivshmem: msix_set_vector_notifiers failed");
791 }
792}
793
794static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector)
795{
796 IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector);
797
798 if (s->msi_vectors[vector].pdev == NULL) {
799 return;
800 }
801
802 /* it was cleaned when masked in the frontend. */
803 kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq);
804
805 s->msi_vectors[vector].pdev = NULL;
806}
807
808static void ivshmem_disable_irqfd(IVShmemState *s)
809{
810 PCIDevice *pdev = PCI_DEVICE(s);
811 int i;
812
813 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
814 ivshmem_remove_kvm_msi_virq(s, i);
815 }
816
817 msix_unset_vector_notifiers(pdev);
818}
819
820static void ivshmem_write_config(PCIDevice *pdev, uint32_t address,
d58d7e84 821 uint32_t val, int len)
4490c711 822{
5400c02b 823 IVShmemState *s = IVSHMEM_COMMON(pdev);
660c97ee
MAL
824 int is_enabled, was_enabled = msix_enabled(pdev);
825
826 pci_default_write_config(pdev, address, val, len);
827 is_enabled = msix_enabled(pdev);
828
1309cf44 829 if (kvm_msi_via_irqfd_enabled()) {
660c97ee
MAL
830 if (!was_enabled && is_enabled) {
831 ivshmem_enable_irqfd(s);
832 } else if (was_enabled && !is_enabled) {
833 ivshmem_disable_irqfd(s);
834 }
835 }
4490c711
MT
836}
837
5400c02b 838static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
6cbf4c8c 839{
5400c02b 840 IVShmemState *s = IVSHMEM_COMMON(dev);
d855e275 841 Error *err = NULL;
6cbf4c8c 842 uint8_t *pci_conf;
9113e3f3
MAL
843 uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY |
844 PCI_BASE_ADDRESS_MEM_PREFETCH;
6cbf4c8c 845
6cbf4c8c
CM
846 /* IRQFD requires MSI */
847 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) &&
848 !ivshmem_has_feature(s, IVSHMEM_MSI)) {
d58d7e84
MAL
849 error_setg(errp, "ioeventfd/irqfd requires MSI");
850 return;
6cbf4c8c
CM
851 }
852
b7578eaa 853 pci_conf = dev->config;
6cbf4c8c 854 pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
6cbf4c8c 855
3c161542 856 memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s,
cb06608e
AK
857 "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE);
858
6cbf4c8c 859 /* region for registers*/
b7578eaa 860 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
e824b2cc 861 &s->ivshmem_mmio);
cb06608e 862
5400c02b 863 if (!s->not_legacy_32bit) {
9113e3f3 864 attr |= PCI_BASE_ADDRESS_MEM_TYPE_64;
c08ba66f 865 }
6cbf4c8c 866
d9453c93 867 if (s->hostmem != NULL) {
d9453c93
MAL
868 IVSHMEM_DPRINTF("using hostmem\n");
869
c2d8019c
MA
870 s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem,
871 &error_abort);
5503e285 872 } else {
6cbf4c8c 873 IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n",
dbc464d4 874 s->server_chr->filename);
6cbf4c8c 875
f456179f 876 /* we allocate enough space for 16 peers and grow as needed */
1300b273 877 resize_peers(s, 16);
6cbf4c8c 878
3a55fc0f
MA
879 /*
880 * Receive setup messages from server synchronously.
881 * Older versions did it asynchronously, but that creates a
882 * number of entertaining race conditions.
3a55fc0f 883 */
1309cf44
MA
884 ivshmem_recv_setup(s, &err);
885 if (err) {
886 error_propagate(errp, err);
887 return;
3a55fc0f
MA
888 }
889
1309cf44
MA
890 qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive,
891 ivshmem_read, NULL, s);
892
3a55fc0f
MA
893 if (ivshmem_setup_interrupts(s) < 0) {
894 error_setg(errp, "failed to initialize interrupts");
895 return;
896 }
d855e275
MA
897 }
898
c2d8019c
MA
899 vmstate_register_ram(s->ivshmem_bar2, DEVICE(s));
900 pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2);
901
2a845da7
MA
902 if (s->master == ON_OFF_AUTO_AUTO) {
903 s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
904 }
905
906 if (!ivshmem_is_master(s)) {
d855e275
MA
907 error_setg(&s->migration_blocker,
908 "Migration is disabled when using feature 'peer mode' in device 'ivshmem'");
909 migrate_add_blocker(s->migration_blocker);
6cbf4c8c 910 }
6cbf4c8c
CM
911}
912
5400c02b
MA
913static void ivshmem_exit(PCIDevice *dev)
914{
915 IVShmemState *s = IVSHMEM_COMMON(dev);
f64a078d
MAL
916 int i;
917
38e0735e
AL
918 if (s->migration_blocker) {
919 migrate_del_blocker(s->migration_blocker);
920 error_free(s->migration_blocker);
921 }
922
c2d8019c 923 if (memory_region_is_mapped(s->ivshmem_bar2)) {
d9453c93 924 if (!s->hostmem) {
c2d8019c 925 void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2);
56a571d9 926 int fd;
d9453c93 927
5400c02b 928 if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) {
d9453c93
MAL
929 error_report("Failed to munmap shared memory %s",
930 strerror(errno));
931 }
56a571d9 932
c2d8019c
MA
933 fd = qemu_get_ram_fd(memory_region_get_ram_addr(s->ivshmem_bar2));
934 close(fd);
d9453c93 935 }
f64a078d 936
c2d8019c 937 vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev));
f64a078d
MAL
938 }
939
f64a078d
MAL
940 if (s->peers) {
941 for (i = 0; i < s->nb_peers; i++) {
f456179f 942 close_peer_eventfds(s, i);
f64a078d
MAL
943 }
944 g_free(s->peers);
945 }
946
947 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
948 msix_uninit_exclusive_bar(dev);
949 }
950
0f57350e 951 g_free(s->msi_vectors);
6cbf4c8c
CM
952}
953
1f8552df
MAL
954static int ivshmem_pre_load(void *opaque)
955{
956 IVShmemState *s = opaque;
957
2a845da7 958 if (!ivshmem_is_master(s)) {
1f8552df
MAL
959 error_report("'peer' devices are not migratable");
960 return -EINVAL;
961 }
962
963 return 0;
964}
965
966static int ivshmem_post_load(void *opaque, int version_id)
967{
968 IVShmemState *s = opaque;
969
970 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8 971 ivshmem_msix_vector_use(s);
1f8552df 972 }
1f8552df
MAL
973 return 0;
974}
975
5400c02b 976static void ivshmem_common_class_init(ObjectClass *klass, void *data)
40021f08 977{
39bffca2 978 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL
979 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
980
5400c02b
MA
981 k->realize = ivshmem_common_realize;
982 k->exit = ivshmem_exit;
d58d7e84 983 k->config_write = ivshmem_write_config;
b8ef62a9
PB
984 k->vendor_id = PCI_VENDOR_ID_IVSHMEM;
985 k->device_id = PCI_DEVICE_ID_IVSHMEM;
40021f08 986 k->class_id = PCI_CLASS_MEMORY_RAM;
5400c02b 987 k->revision = 1;
39bffca2 988 dc->reset = ivshmem_reset;
125ee0ed 989 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
d383537d 990 dc->desc = "Inter-VM shared memory";
40021f08
AL
991}
992
ddc85284
MA
993static const TypeInfo ivshmem_common_info = {
994 .name = TYPE_IVSHMEM_COMMON,
995 .parent = TYPE_PCI_DEVICE,
996 .instance_size = sizeof(IVShmemState),
997 .abstract = true,
998 .class_init = ivshmem_common_class_init,
999};
5400c02b 1000
d9453c93
MAL
1001static void ivshmem_check_memdev_is_busy(Object *obj, const char *name,
1002 Object *val, Error **errp)
1003{
1004 MemoryRegion *mr;
1005
9cf70c52 1006 mr = host_memory_backend_get_memory(MEMORY_BACKEND(val), &error_abort);
d9453c93
MAL
1007 if (memory_region_is_mapped(mr)) {
1008 char *path = object_get_canonical_path_component(val);
1009 error_setg(errp, "can't use already busy memdev: %s", path);
1010 g_free(path);
1011 } else {
1012 qdev_prop_allow_set_link_before_realize(obj, name, val, errp);
1013 }
1014}
1015
5400c02b
MA
1016static const VMStateDescription ivshmem_plain_vmsd = {
1017 .name = TYPE_IVSHMEM_PLAIN,
1018 .version_id = 0,
1019 .minimum_version_id = 0,
1020 .pre_load = ivshmem_pre_load,
1021 .post_load = ivshmem_post_load,
1022 .fields = (VMStateField[]) {
1023 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1024 VMSTATE_UINT32(intrstatus, IVShmemState),
1025 VMSTATE_UINT32(intrmask, IVShmemState),
1026 VMSTATE_END_OF_LIST()
1027 },
1028};
1029
1030static Property ivshmem_plain_properties[] = {
1031 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1032 DEFINE_PROP_END_OF_LIST(),
1033};
1034
1035static void ivshmem_plain_init(Object *obj)
1036{
1037 IVShmemState *s = IVSHMEM_PLAIN(obj);
1038
1039 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
1040 (Object **)&s->hostmem,
1041 ivshmem_check_memdev_is_busy,
1042 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1043 &error_abort);
1044}
1045
1046static void ivshmem_plain_class_init(ObjectClass *klass, void *data)
1047{
1048 DeviceClass *dc = DEVICE_CLASS(klass);
1049
1050 dc->props = ivshmem_plain_properties;
1051 dc->vmsd = &ivshmem_plain_vmsd;
1052}
1053
1054static const TypeInfo ivshmem_plain_info = {
1055 .name = TYPE_IVSHMEM_PLAIN,
1056 .parent = TYPE_IVSHMEM_COMMON,
1057 .instance_size = sizeof(IVShmemState),
1058 .instance_init = ivshmem_plain_init,
1059 .class_init = ivshmem_plain_class_init,
1060};
1061
1062static const VMStateDescription ivshmem_doorbell_vmsd = {
1063 .name = TYPE_IVSHMEM_DOORBELL,
1064 .version_id = 0,
1065 .minimum_version_id = 0,
1066 .pre_load = ivshmem_pre_load,
1067 .post_load = ivshmem_post_load,
1068 .fields = (VMStateField[]) {
1069 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1070 VMSTATE_MSIX(parent_obj, IVShmemState),
1071 VMSTATE_UINT32(intrstatus, IVShmemState),
1072 VMSTATE_UINT32(intrmask, IVShmemState),
1073 VMSTATE_END_OF_LIST()
1074 },
1075};
1076
1077static Property ivshmem_doorbell_properties[] = {
1078 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1079 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1080 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1081 true),
1082 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1083 DEFINE_PROP_END_OF_LIST(),
1084};
1085
1086static void ivshmem_doorbell_init(Object *obj)
1087{
1088 IVShmemState *s = IVSHMEM_DOORBELL(obj);
1089
1090 s->features |= (1 << IVSHMEM_MSI);
1091 s->legacy_size = SIZE_MAX; /* whatever the server sends */
1092}
1093
1094static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data)
1095{
1096 DeviceClass *dc = DEVICE_CLASS(klass);
1097
1098 dc->props = ivshmem_doorbell_properties;
1099 dc->vmsd = &ivshmem_doorbell_vmsd;
1100}
1101
1102static const TypeInfo ivshmem_doorbell_info = {
1103 .name = TYPE_IVSHMEM_DOORBELL,
1104 .parent = TYPE_IVSHMEM_COMMON,
1105 .instance_size = sizeof(IVShmemState),
1106 .instance_init = ivshmem_doorbell_init,
1107 .class_init = ivshmem_doorbell_class_init,
1108};
1109
ddc85284
MA
1110static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id)
1111{
1112 IVShmemState *s = opaque;
1113 PCIDevice *pdev = PCI_DEVICE(s);
1114 int ret;
1115
1116 IVSHMEM_DPRINTF("ivshmem_load_old\n");
1117
1118 if (version_id != 0) {
1119 return -EINVAL;
1120 }
1121
1122 ret = ivshmem_pre_load(s);
1123 if (ret) {
1124 return ret;
1125 }
1126
1127 ret = pci_device_load(pdev, f);
1128 if (ret) {
1129 return ret;
1130 }
1131
1132 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
1133 msix_load(pdev, f);
1134 ivshmem_msix_vector_use(s);
1135 } else {
1136 s->intrstatus = qemu_get_be32(f);
1137 s->intrmask = qemu_get_be32(f);
1138 }
1139
1140 return 0;
1141}
1142
1143static bool test_msix(void *opaque, int version_id)
1144{
1145 IVShmemState *s = opaque;
1146
1147 return ivshmem_has_feature(s, IVSHMEM_MSI);
1148}
1149
1150static bool test_no_msix(void *opaque, int version_id)
1151{
1152 return !test_msix(opaque, version_id);
1153}
1154
1155static const VMStateDescription ivshmem_vmsd = {
1156 .name = "ivshmem",
1157 .version_id = 1,
1158 .minimum_version_id = 1,
1159 .pre_load = ivshmem_pre_load,
1160 .post_load = ivshmem_post_load,
1161 .fields = (VMStateField[]) {
1162 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1163
1164 VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix),
1165 VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix),
1166 VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix),
1167
1168 VMSTATE_END_OF_LIST()
1169 },
1170 .load_state_old = ivshmem_load_old,
1171 .minimum_version_id_old = 0
1172};
1173
1174static Property ivshmem_properties[] = {
1175 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1176 DEFINE_PROP_STRING("size", IVShmemState, sizearg),
1177 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1178 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1179 false),
1180 DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
1181 DEFINE_PROP_STRING("shm", IVShmemState, shmobj),
1182 DEFINE_PROP_STRING("role", IVShmemState, role),
1183 DEFINE_PROP_UINT32("use64", IVShmemState, not_legacy_32bit, 1),
1184 DEFINE_PROP_END_OF_LIST(),
1185};
1186
1187static void desugar_shm(IVShmemState *s)
1188{
1189 Object *obj;
1190 char *path;
1191
1192 obj = object_new("memory-backend-file");
1193 path = g_strdup_printf("/dev/shm/%s", s->shmobj);
1194 object_property_set_str(obj, path, "mem-path", &error_abort);
1195 g_free(path);
1196 object_property_set_int(obj, s->legacy_size, "size", &error_abort);
1197 object_property_set_bool(obj, true, "share", &error_abort);
1198 object_property_add_child(OBJECT(s), "internal-shm-backend", obj,
1199 &error_abort);
1200 user_creatable_complete(obj, &error_abort);
1201 s->hostmem = MEMORY_BACKEND(obj);
1202}
1203
1204static void ivshmem_realize(PCIDevice *dev, Error **errp)
1205{
1206 IVShmemState *s = IVSHMEM_COMMON(dev);
1207
1208 if (!qtest_enabled()) {
1209 error_report("ivshmem is deprecated, please use ivshmem-plain"
1210 " or ivshmem-doorbell instead");
1211 }
1212
1213 if (!!s->server_chr + !!s->shmobj + !!s->hostmem != 1) {
1214 error_setg(errp,
1215 "You must specify either 'shm', 'chardev' or 'x-memdev'");
1216 return;
1217 }
1218
1219 if (s->hostmem) {
1220 if (s->sizearg) {
1221 g_warning("size argument ignored with hostmem");
1222 }
1223 } else if (s->sizearg == NULL) {
1224 s->legacy_size = 4 << 20; /* 4 MB default */
1225 } else {
1226 char *end;
1227 int64_t size = qemu_strtosz(s->sizearg, &end);
1228 if (size < 0 || (size_t)size != size || *end != '\0'
1229 || !is_power_of_2(size)) {
1230 error_setg(errp, "Invalid size %s", s->sizearg);
1231 return;
1232 }
1233 s->legacy_size = size;
1234 }
1235
1236 /* check that role is reasonable */
1237 if (s->role) {
1238 if (strncmp(s->role, "peer", 5) == 0) {
1239 s->master = ON_OFF_AUTO_OFF;
1240 } else if (strncmp(s->role, "master", 7) == 0) {
1241 s->master = ON_OFF_AUTO_ON;
1242 } else {
1243 error_setg(errp, "'role' must be 'peer' or 'master'");
1244 return;
1245 }
1246 } else {
1247 s->master = ON_OFF_AUTO_AUTO;
1248 }
1249
1250 if (s->shmobj) {
1251 desugar_shm(s);
1252 }
1253
1254 /*
1255 * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a
1256 * bald-faced lie then. But it's a backwards compatible lie.
1257 */
1258 pci_config_set_interrupt_pin(dev->config, 1);
1259
1260 ivshmem_common_realize(dev, errp);
1261}
1262
1263static void ivshmem_init(Object *obj)
1264{
1265 IVShmemState *s = IVSHMEM(obj);
1266
1267 object_property_add_link(obj, "x-memdev", TYPE_MEMORY_BACKEND,
1268 (Object **)&s->hostmem,
1269 ivshmem_check_memdev_is_busy,
1270 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1271 &error_abort);
1272}
1273
1274static void ivshmem_class_init(ObjectClass *klass, void *data)
1275{
1276 DeviceClass *dc = DEVICE_CLASS(klass);
1277 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1278
1279 k->realize = ivshmem_realize;
1280 k->revision = 0;
1281 dc->desc = "Inter-VM shared memory (legacy)";
1282 dc->props = ivshmem_properties;
1283 dc->vmsd = &ivshmem_vmsd;
1284}
1285
1286static const TypeInfo ivshmem_info = {
1287 .name = TYPE_IVSHMEM,
1288 .parent = TYPE_IVSHMEM_COMMON,
1289 .instance_size = sizeof(IVShmemState),
1290 .instance_init = ivshmem_init,
1291 .class_init = ivshmem_class_init,
1292};
1293
83f7d43a 1294static void ivshmem_register_types(void)
6cbf4c8c 1295{
5400c02b
MA
1296 type_register_static(&ivshmem_common_info);
1297 type_register_static(&ivshmem_plain_info);
1298 type_register_static(&ivshmem_doorbell_info);
39bffca2 1299 type_register_static(&ivshmem_info);
6cbf4c8c
CM
1300}
1301
83f7d43a 1302type_init(ivshmem_register_types)
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