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Commit | Line | Data |
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6cbf4c8c CM |
1 | /* |
2 | * Inter-VM Shared Memory PCI device. | |
3 | * | |
4 | * Author: | |
5 | * Cam Macdonell <[email protected]> | |
6 | * | |
7 | * Based On: cirrus_vga.c | |
8 | * Copyright (c) 2004 Fabrice Bellard | |
9 | * Copyright (c) 2004 Makoto Suzuki (suzu) | |
10 | * | |
11 | * and rtl8139.c | |
12 | * Copyright (c) 2006 Igor Kovalenko | |
13 | * | |
14 | * This code is licensed under the GNU GPL v2. | |
6b620ca3 PB |
15 | * |
16 | * Contributions after 2012-01-13 are licensed under the terms of the | |
17 | * GNU GPL, version 2 or (at your option) any later version. | |
6cbf4c8c | 18 | */ |
0d1c9782 | 19 | #include "qemu/osdep.h" |
83c9f4ca | 20 | #include "hw/hw.h" |
0d09e41a | 21 | #include "hw/i386/pc.h" |
83c9f4ca | 22 | #include "hw/pci/pci.h" |
660c97ee | 23 | #include "hw/pci/msi.h" |
83c9f4ca | 24 | #include "hw/pci/msix.h" |
9c17d615 | 25 | #include "sysemu/kvm.h" |
caf71f86 | 26 | #include "migration/migration.h" |
d49b6836 | 27 | #include "qemu/error-report.h" |
1de7afc9 | 28 | #include "qemu/event_notifier.h" |
5503e285 | 29 | #include "qom/object_interfaces.h" |
dccfcd0e | 30 | #include "sysemu/char.h" |
d9453c93 | 31 | #include "sysemu/hostmem.h" |
5400c02b | 32 | #include "sysemu/qtest.h" |
d9453c93 | 33 | #include "qapi/visitor.h" |
56a571d9 | 34 | #include "exec/ram_addr.h" |
6cbf4c8c | 35 | |
5105b1d8 DM |
36 | #include "hw/misc/ivshmem.h" |
37 | ||
6cbf4c8c | 38 | #include <sys/mman.h> |
6cbf4c8c | 39 | |
b8ef62a9 PB |
40 | #define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET |
41 | #define PCI_DEVICE_ID_IVSHMEM 0x1110 | |
42 | ||
cd9953f7 | 43 | #define IVSHMEM_MAX_PEERS UINT16_MAX |
6cbf4c8c CM |
44 | #define IVSHMEM_IOEVENTFD 0 |
45 | #define IVSHMEM_MSI 1 | |
46 | ||
6cbf4c8c CM |
47 | #define IVSHMEM_REG_BAR_SIZE 0x100 |
48 | ||
a4fa93bf MA |
49 | #define IVSHMEM_DEBUG 0 |
50 | #define IVSHMEM_DPRINTF(fmt, ...) \ | |
51 | do { \ | |
52 | if (IVSHMEM_DEBUG) { \ | |
53 | printf("IVSHMEM: " fmt, ## __VA_ARGS__); \ | |
54 | } \ | |
55 | } while (0) | |
6cbf4c8c | 56 | |
5400c02b MA |
57 | #define TYPE_IVSHMEM_COMMON "ivshmem-common" |
58 | #define IVSHMEM_COMMON(obj) \ | |
59 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON) | |
60 | ||
61 | #define TYPE_IVSHMEM_PLAIN "ivshmem-plain" | |
62 | #define IVSHMEM_PLAIN(obj) \ | |
63 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN) | |
64 | ||
65 | #define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell" | |
66 | #define IVSHMEM_DOORBELL(obj) \ | |
67 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL) | |
68 | ||
eb3fedf3 PC |
69 | #define TYPE_IVSHMEM "ivshmem" |
70 | #define IVSHMEM(obj) \ | |
71 | OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM) | |
72 | ||
6cbf4c8c CM |
73 | typedef struct Peer { |
74 | int nb_eventfds; | |
563027cc | 75 | EventNotifier *eventfds; |
6cbf4c8c CM |
76 | } Peer; |
77 | ||
0f57350e | 78 | typedef struct MSIVector { |
6cbf4c8c | 79 | PCIDevice *pdev; |
660c97ee | 80 | int virq; |
0f57350e | 81 | } MSIVector; |
6cbf4c8c CM |
82 | |
83 | typedef struct IVShmemState { | |
b7578eaa AF |
84 | /*< private >*/ |
85 | PCIDevice parent_obj; | |
86 | /*< public >*/ | |
87 | ||
d9453c93 | 88 | HostMemoryBackend *hostmem; |
6cbf4c8c CM |
89 | uint32_t intrmask; |
90 | uint32_t intrstatus; | |
6cbf4c8c | 91 | |
6cbf4c8c | 92 | CharDriverState *server_chr; |
cb06608e | 93 | MemoryRegion ivshmem_mmio; |
6cbf4c8c | 94 | |
c2d8019c MA |
95 | MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */ |
96 | MemoryRegion server_bar2; /* used with server_chr */ | |
6cbf4c8c CM |
97 | |
98 | Peer *peers; | |
cd9953f7 | 99 | int nb_peers; /* space in @peers[] */ |
6cbf4c8c CM |
100 | |
101 | int vm_id; | |
102 | uint32_t vectors; | |
103 | uint32_t features; | |
0f57350e | 104 | MSIVector *msi_vectors; |
ee276391 MA |
105 | uint64_t msg_buf; /* buffer for receiving server messages */ |
106 | int msg_buffered_bytes; /* #bytes in @msg_buf */ | |
6cbf4c8c | 107 | |
2a845da7 | 108 | OnOffAuto master; |
38e0735e AL |
109 | Error *migration_blocker; |
110 | ||
5400c02b MA |
111 | /* legacy cruft */ |
112 | char *role; | |
113 | char *shmobj; | |
114 | char *sizearg; | |
115 | size_t legacy_size; | |
116 | uint32_t not_legacy_32bit; | |
6cbf4c8c CM |
117 | } IVShmemState; |
118 | ||
119 | /* registers for the Inter-VM shared memory device */ | |
120 | enum ivshmem_registers { | |
121 | INTRMASK = 0, | |
122 | INTRSTATUS = 4, | |
123 | IVPOSITION = 8, | |
124 | DOORBELL = 12, | |
125 | }; | |
126 | ||
127 | static inline uint32_t ivshmem_has_feature(IVShmemState *ivs, | |
128 | unsigned int feature) { | |
129 | return (ivs->features & (1 << feature)); | |
130 | } | |
131 | ||
2a845da7 MA |
132 | static inline bool ivshmem_is_master(IVShmemState *s) |
133 | { | |
134 | assert(s->master != ON_OFF_AUTO_AUTO); | |
135 | return s->master == ON_OFF_AUTO_ON; | |
136 | } | |
137 | ||
d8a5da07 | 138 | static void ivshmem_update_irq(IVShmemState *s) |
6cbf4c8c | 139 | { |
b7578eaa | 140 | PCIDevice *d = PCI_DEVICE(s); |
434ad76d | 141 | uint32_t isr = s->intrstatus & s->intrmask; |
6cbf4c8c | 142 | |
5400c02b MA |
143 | /* |
144 | * Do nothing unless the device actually uses INTx. Here's how | |
145 | * the device variants signal interrupts, what they put in PCI | |
146 | * config space: | |
147 | * Device variant Interrupt Interrupt Pin MSI-X cap. | |
148 | * ivshmem-plain none 0 no | |
149 | * ivshmem-doorbell MSI-X 1 yes(1) | |
150 | * ivshmem,msi=off INTx 1 no | |
151 | * ivshmem,msi=on MSI-X 1(2) yes(1) | |
152 | * (1) if guest enabled MSI-X | |
153 | * (2) the device lies | |
154 | * Leads to the condition for doing nothing: | |
155 | */ | |
156 | if (ivshmem_has_feature(s, IVSHMEM_MSI) | |
157 | || !d->config[PCI_INTERRUPT_PIN]) { | |
2d1d422d MA |
158 | return; |
159 | } | |
160 | ||
6cbf4c8c CM |
161 | /* don't print ISR resets */ |
162 | if (isr) { | |
163 | IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n", | |
dbc464d4 | 164 | isr ? 1 : 0, s->intrstatus, s->intrmask); |
6cbf4c8c CM |
165 | } |
166 | ||
434ad76d | 167 | pci_set_irq(d, isr != 0); |
6cbf4c8c CM |
168 | } |
169 | ||
170 | static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val) | |
171 | { | |
172 | IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val); | |
173 | ||
174 | s->intrmask = val; | |
d8a5da07 | 175 | ivshmem_update_irq(s); |
6cbf4c8c CM |
176 | } |
177 | ||
178 | static uint32_t ivshmem_IntrMask_read(IVShmemState *s) | |
179 | { | |
180 | uint32_t ret = s->intrmask; | |
181 | ||
182 | IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret); | |
6cbf4c8c CM |
183 | return ret; |
184 | } | |
185 | ||
186 | static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val) | |
187 | { | |
188 | IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val); | |
189 | ||
190 | s->intrstatus = val; | |
d8a5da07 | 191 | ivshmem_update_irq(s); |
6cbf4c8c CM |
192 | } |
193 | ||
194 | static uint32_t ivshmem_IntrStatus_read(IVShmemState *s) | |
195 | { | |
196 | uint32_t ret = s->intrstatus; | |
197 | ||
198 | /* reading ISR clears all interrupts */ | |
199 | s->intrstatus = 0; | |
d8a5da07 | 200 | ivshmem_update_irq(s); |
6cbf4c8c CM |
201 | return ret; |
202 | } | |
203 | ||
a8170e5e | 204 | static void ivshmem_io_write(void *opaque, hwaddr addr, |
cb06608e | 205 | uint64_t val, unsigned size) |
6cbf4c8c CM |
206 | { |
207 | IVShmemState *s = opaque; | |
208 | ||
6cbf4c8c CM |
209 | uint16_t dest = val >> 16; |
210 | uint16_t vector = val & 0xff; | |
211 | ||
212 | addr &= 0xfc; | |
213 | ||
214 | IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); | |
215 | switch (addr) | |
216 | { | |
217 | case INTRMASK: | |
218 | ivshmem_IntrMask_write(s, val); | |
219 | break; | |
220 | ||
221 | case INTRSTATUS: | |
222 | ivshmem_IntrStatus_write(s, val); | |
223 | break; | |
224 | ||
225 | case DOORBELL: | |
226 | /* check that dest VM ID is reasonable */ | |
95c8425c | 227 | if (dest >= s->nb_peers) { |
6cbf4c8c CM |
228 | IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest); |
229 | break; | |
230 | } | |
231 | ||
232 | /* check doorbell range */ | |
1b27d7a1 | 233 | if (vector < s->peers[dest].nb_eventfds) { |
563027cc PB |
234 | IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector); |
235 | event_notifier_set(&s->peers[dest].eventfds[vector]); | |
f59bb378 MAL |
236 | } else { |
237 | IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n", | |
238 | vector, dest); | |
6cbf4c8c CM |
239 | } |
240 | break; | |
241 | default: | |
f59bb378 | 242 | IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); |
6cbf4c8c CM |
243 | } |
244 | } | |
245 | ||
a8170e5e | 246 | static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, |
cb06608e | 247 | unsigned size) |
6cbf4c8c CM |
248 | { |
249 | ||
250 | IVShmemState *s = opaque; | |
251 | uint32_t ret; | |
252 | ||
253 | switch (addr) | |
254 | { | |
255 | case INTRMASK: | |
256 | ret = ivshmem_IntrMask_read(s); | |
257 | break; | |
258 | ||
259 | case INTRSTATUS: | |
260 | ret = ivshmem_IntrStatus_read(s); | |
261 | break; | |
262 | ||
263 | case IVPOSITION: | |
1309cf44 | 264 | ret = s->vm_id; |
6cbf4c8c CM |
265 | break; |
266 | ||
267 | default: | |
268 | IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); | |
269 | ret = 0; | |
270 | } | |
271 | ||
272 | return ret; | |
273 | } | |
274 | ||
cb06608e AK |
275 | static const MemoryRegionOps ivshmem_mmio_ops = { |
276 | .read = ivshmem_io_read, | |
277 | .write = ivshmem_io_write, | |
278 | .endianness = DEVICE_NATIVE_ENDIAN, | |
279 | .impl = { | |
280 | .min_access_size = 4, | |
281 | .max_access_size = 4, | |
282 | }, | |
6cbf4c8c CM |
283 | }; |
284 | ||
9940c323 MAL |
285 | static void ivshmem_vector_notify(void *opaque) |
286 | { | |
0f57350e | 287 | MSIVector *entry = opaque; |
6cbf4c8c | 288 | PCIDevice *pdev = entry->pdev; |
5400c02b | 289 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
0f57350e | 290 | int vector = entry - s->msi_vectors; |
9940c323 MAL |
291 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
292 | ||
293 | if (!event_notifier_test_and_clear(n)) { | |
294 | return; | |
295 | } | |
6cbf4c8c | 296 | |
d160f3f7 | 297 | IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector); |
9940c323 | 298 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
082751e8 MA |
299 | if (msix_enabled(pdev)) { |
300 | msix_notify(pdev, vector); | |
301 | } | |
9940c323 MAL |
302 | } else { |
303 | ivshmem_IntrStatus_write(s, 1); | |
304 | } | |
6cbf4c8c CM |
305 | } |
306 | ||
660c97ee MAL |
307 | static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector, |
308 | MSIMessage msg) | |
309 | { | |
5400c02b | 310 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
311 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
312 | MSIVector *v = &s->msi_vectors[vector]; | |
313 | int ret; | |
314 | ||
315 | IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector); | |
316 | ||
317 | ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev); | |
318 | if (ret < 0) { | |
319 | return ret; | |
320 | } | |
321 | ||
322 | return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq); | |
323 | } | |
324 | ||
325 | static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector) | |
326 | { | |
5400c02b | 327 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
328 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; |
329 | int ret; | |
330 | ||
331 | IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector); | |
332 | ||
333 | ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n, | |
334 | s->msi_vectors[vector].virq); | |
335 | if (ret != 0) { | |
336 | error_report("remove_irqfd_notifier_gsi failed"); | |
337 | } | |
338 | } | |
339 | ||
340 | static void ivshmem_vector_poll(PCIDevice *dev, | |
341 | unsigned int vector_start, | |
342 | unsigned int vector_end) | |
343 | { | |
5400c02b | 344 | IVShmemState *s = IVSHMEM_COMMON(dev); |
660c97ee MAL |
345 | unsigned int vector; |
346 | ||
347 | IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end); | |
348 | ||
349 | vector_end = MIN(vector_end, s->vectors); | |
350 | ||
351 | for (vector = vector_start; vector < vector_end; vector++) { | |
352 | EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector]; | |
353 | ||
354 | if (!msix_is_masked(dev, vector)) { | |
355 | continue; | |
356 | } | |
357 | ||
358 | if (event_notifier_test_and_clear(notifier)) { | |
359 | msix_set_pending(dev, vector); | |
360 | } | |
361 | } | |
362 | } | |
363 | ||
9940c323 MAL |
364 | static void watch_vector_notifier(IVShmemState *s, EventNotifier *n, |
365 | int vector) | |
6cbf4c8c | 366 | { |
563027cc | 367 | int eventfd = event_notifier_get_fd(n); |
6cbf4c8c | 368 | |
3c27969b | 369 | assert(!s->msi_vectors[vector].pdev); |
9940c323 | 370 | s->msi_vectors[vector].pdev = PCI_DEVICE(s); |
6cbf4c8c | 371 | |
9940c323 MAL |
372 | qemu_set_fd_handler(eventfd, ivshmem_vector_notify, |
373 | NULL, &s->msi_vectors[vector]); | |
6cbf4c8c CM |
374 | } |
375 | ||
563027cc PB |
376 | static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i) |
377 | { | |
378 | memory_region_add_eventfd(&s->ivshmem_mmio, | |
379 | DOORBELL, | |
380 | 4, | |
381 | true, | |
382 | (posn << 16) | i, | |
753d5e14 | 383 | &s->peers[posn].eventfds[i]); |
563027cc PB |
384 | } |
385 | ||
386 | static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i) | |
387 | { | |
388 | memory_region_del_eventfd(&s->ivshmem_mmio, | |
389 | DOORBELL, | |
390 | 4, | |
391 | true, | |
392 | (posn << 16) | i, | |
753d5e14 | 393 | &s->peers[posn].eventfds[i]); |
563027cc PB |
394 | } |
395 | ||
f456179f | 396 | static void close_peer_eventfds(IVShmemState *s, int posn) |
6cbf4c8c | 397 | { |
f456179f | 398 | int i, n; |
6cbf4c8c | 399 | |
9db51b4d | 400 | assert(posn >= 0 && posn < s->nb_peers); |
f456179f | 401 | n = s->peers[posn].nb_eventfds; |
6cbf4c8c | 402 | |
9db51b4d MA |
403 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
404 | memory_region_transaction_begin(); | |
405 | for (i = 0; i < n; i++) { | |
406 | ivshmem_del_eventfd(s, posn, i); | |
407 | } | |
408 | memory_region_transaction_commit(); | |
b6a1f3a5 | 409 | } |
9db51b4d | 410 | |
f456179f | 411 | for (i = 0; i < n; i++) { |
563027cc | 412 | event_notifier_cleanup(&s->peers[posn].eventfds[i]); |
6cbf4c8c CM |
413 | } |
414 | ||
7267c094 | 415 | g_free(s->peers[posn].eventfds); |
6cbf4c8c CM |
416 | s->peers[posn].nb_eventfds = 0; |
417 | } | |
418 | ||
cd9953f7 | 419 | static void resize_peers(IVShmemState *s, int nb_peers) |
34bc07c5 | 420 | { |
cd9953f7 MA |
421 | int old_nb_peers = s->nb_peers; |
422 | int i; | |
6cbf4c8c | 423 | |
cd9953f7 MA |
424 | assert(nb_peers > old_nb_peers); |
425 | IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers); | |
6cbf4c8c | 426 | |
cd9953f7 MA |
427 | s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer)); |
428 | s->nb_peers = nb_peers; | |
1300b273 | 429 | |
cd9953f7 MA |
430 | for (i = old_nb_peers; i < nb_peers; i++) { |
431 | s->peers[i].eventfds = g_new0(EventNotifier, s->vectors); | |
432 | s->peers[i].nb_eventfds = 0; | |
6cbf4c8c CM |
433 | } |
434 | } | |
435 | ||
1309cf44 MA |
436 | static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector, |
437 | Error **errp) | |
660c97ee MAL |
438 | { |
439 | PCIDevice *pdev = PCI_DEVICE(s); | |
440 | MSIMessage msg = msix_get_message(pdev, vector); | |
441 | int ret; | |
442 | ||
443 | IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector); | |
3c27969b | 444 | assert(!s->msi_vectors[vector].pdev); |
660c97ee MAL |
445 | |
446 | ret = kvm_irqchip_add_msi_route(kvm_state, msg, pdev); | |
447 | if (ret < 0) { | |
1309cf44 MA |
448 | error_setg(errp, "kvm_irqchip_add_msi_route failed"); |
449 | return; | |
660c97ee MAL |
450 | } |
451 | ||
452 | s->msi_vectors[vector].virq = ret; | |
453 | s->msi_vectors[vector].pdev = pdev; | |
660c97ee MAL |
454 | } |
455 | ||
1309cf44 | 456 | static void setup_interrupt(IVShmemState *s, int vector, Error **errp) |
660c97ee MAL |
457 | { |
458 | EventNotifier *n = &s->peers[s->vm_id].eventfds[vector]; | |
459 | bool with_irqfd = kvm_msi_via_irqfd_enabled() && | |
460 | ivshmem_has_feature(s, IVSHMEM_MSI); | |
461 | PCIDevice *pdev = PCI_DEVICE(s); | |
1309cf44 | 462 | Error *err = NULL; |
660c97ee MAL |
463 | |
464 | IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector); | |
465 | ||
466 | if (!with_irqfd) { | |
97553976 | 467 | IVSHMEM_DPRINTF("with eventfd\n"); |
9940c323 | 468 | watch_vector_notifier(s, n, vector); |
660c97ee | 469 | } else if (msix_enabled(pdev)) { |
97553976 | 470 | IVSHMEM_DPRINTF("with irqfd\n"); |
1309cf44 MA |
471 | ivshmem_add_kvm_msi_virq(s, vector, &err); |
472 | if (err) { | |
473 | error_propagate(errp, err); | |
660c97ee MAL |
474 | return; |
475 | } | |
476 | ||
477 | if (!msix_is_masked(pdev, vector)) { | |
478 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, | |
479 | s->msi_vectors[vector].virq); | |
1309cf44 | 480 | /* TODO handle error */ |
660c97ee MAL |
481 | } |
482 | } else { | |
483 | /* it will be delayed until msix is enabled, in write_config */ | |
97553976 | 484 | IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n"); |
660c97ee MAL |
485 | } |
486 | } | |
487 | ||
1309cf44 | 488 | static void process_msg_shmem(IVShmemState *s, int fd, Error **errp) |
6cbf4c8c | 489 | { |
8baeb22b | 490 | struct stat buf; |
5400c02b | 491 | size_t size; |
ca0b7566 | 492 | void *ptr; |
6cbf4c8c | 493 | |
c2d8019c | 494 | if (s->ivshmem_bar2) { |
1309cf44 | 495 | error_setg(errp, "server sent unexpected shared memory message"); |
ca0b7566 | 496 | close(fd); |
0f14fd71 | 497 | return; |
a2e9011b SH |
498 | } |
499 | ||
8baeb22b MA |
500 | if (fstat(fd, &buf) < 0) { |
501 | error_setg_errno(errp, errno, | |
502 | "can't determine size of shared memory sent by server"); | |
503 | close(fd); | |
504 | return; | |
505 | } | |
506 | ||
5400c02b MA |
507 | size = buf.st_size; |
508 | ||
509 | /* Legacy cruft */ | |
510 | if (s->legacy_size != SIZE_MAX) { | |
511 | if (size < s->legacy_size) { | |
512 | error_setg(errp, "server sent only %zd bytes of shared memory", | |
513 | (size_t)buf.st_size); | |
514 | close(fd); | |
515 | return; | |
516 | } | |
517 | size = s->legacy_size; | |
cd9953f7 MA |
518 | } |
519 | ||
ca0b7566 | 520 | /* mmap the region and map into the BAR2 */ |
5400c02b | 521 | ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); |
ca0b7566 | 522 | if (ptr == MAP_FAILED) { |
1309cf44 | 523 | error_setg_errno(errp, errno, "Failed to mmap shared memory"); |
ca0b7566 MA |
524 | close(fd); |
525 | return; | |
6cbf4c8c | 526 | } |
c2d8019c | 527 | memory_region_init_ram_ptr(&s->server_bar2, OBJECT(s), |
5400c02b | 528 | "ivshmem.bar2", size, ptr); |
c2d8019c MA |
529 | qemu_set_ram_fd(memory_region_get_ram_addr(&s->server_bar2), fd); |
530 | s->ivshmem_bar2 = &s->server_bar2; | |
ca0b7566 MA |
531 | } |
532 | ||
1309cf44 MA |
533 | static void process_msg_disconnect(IVShmemState *s, uint16_t posn, |
534 | Error **errp) | |
ca0b7566 MA |
535 | { |
536 | IVSHMEM_DPRINTF("posn %d has gone away\n", posn); | |
9db51b4d | 537 | if (posn >= s->nb_peers || posn == s->vm_id) { |
1309cf44 | 538 | error_setg(errp, "invalid peer %d", posn); |
9db51b4d MA |
539 | return; |
540 | } | |
ca0b7566 MA |
541 | close_peer_eventfds(s, posn); |
542 | } | |
6cbf4c8c | 543 | |
1309cf44 MA |
544 | static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd, |
545 | Error **errp) | |
ca0b7566 MA |
546 | { |
547 | Peer *peer = &s->peers[posn]; | |
548 | int vector; | |
9a2f0e64 | 549 | |
ca0b7566 MA |
550 | /* |
551 | * The N-th connect message for this peer comes with the file | |
552 | * descriptor for vector N-1. Count messages to find the vector. | |
553 | */ | |
554 | if (peer->nb_eventfds >= s->vectors) { | |
1309cf44 MA |
555 | error_setg(errp, "Too many eventfd received, device has %d vectors", |
556 | s->vectors); | |
ca0b7566 | 557 | close(fd); |
6f8a16d5 | 558 | return; |
6cbf4c8c | 559 | } |
ca0b7566 | 560 | vector = peer->nb_eventfds++; |
6cbf4c8c | 561 | |
ca0b7566 MA |
562 | IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd); |
563 | event_notifier_init_fd(&peer->eventfds[vector], fd); | |
564 | fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */ | |
945001a1 | 565 | |
ca0b7566 | 566 | if (posn == s->vm_id) { |
1309cf44 MA |
567 | setup_interrupt(s, vector, errp); |
568 | /* TODO do we need to handle the error? */ | |
ca0b7566 | 569 | } |
6cbf4c8c | 570 | |
ca0b7566 MA |
571 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) { |
572 | ivshmem_add_eventfd(s, posn, vector); | |
573 | } | |
574 | } | |
6cbf4c8c | 575 | |
1309cf44 | 576 | static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp) |
ca0b7566 MA |
577 | { |
578 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
6cbf4c8c | 579 | |
ca0b7566 | 580 | if (msg < -1 || msg > IVSHMEM_MAX_PEERS) { |
1309cf44 | 581 | error_setg(errp, "server sent invalid message %" PRId64, msg); |
ca0b7566 | 582 | close(fd); |
6cbf4c8c CM |
583 | return; |
584 | } | |
585 | ||
ca0b7566 | 586 | if (msg == -1) { |
1309cf44 | 587 | process_msg_shmem(s, fd, errp); |
1ee57de4 MAL |
588 | return; |
589 | } | |
590 | ||
ca0b7566 MA |
591 | if (msg >= s->nb_peers) { |
592 | resize_peers(s, msg + 1); | |
593 | } | |
6cbf4c8c | 594 | |
ca0b7566 | 595 | if (fd >= 0) { |
1309cf44 | 596 | process_msg_connect(s, msg, fd, errp); |
ca0b7566 | 597 | } else { |
1309cf44 | 598 | process_msg_disconnect(s, msg, errp); |
6cbf4c8c | 599 | } |
ca0b7566 | 600 | } |
6cbf4c8c | 601 | |
ee276391 MA |
602 | static int ivshmem_can_receive(void *opaque) |
603 | { | |
604 | IVShmemState *s = opaque; | |
605 | ||
606 | assert(s->msg_buffered_bytes < sizeof(s->msg_buf)); | |
607 | return sizeof(s->msg_buf) - s->msg_buffered_bytes; | |
608 | } | |
609 | ||
ca0b7566 MA |
610 | static void ivshmem_read(void *opaque, const uint8_t *buf, int size) |
611 | { | |
612 | IVShmemState *s = opaque; | |
1309cf44 | 613 | Error *err = NULL; |
ca0b7566 MA |
614 | int fd; |
615 | int64_t msg; | |
616 | ||
ee276391 MA |
617 | assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf)); |
618 | memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size); | |
619 | s->msg_buffered_bytes += size; | |
620 | if (s->msg_buffered_bytes < sizeof(s->msg_buf)) { | |
ca0b7566 | 621 | return; |
6cbf4c8c | 622 | } |
ee276391 MA |
623 | msg = le64_to_cpu(s->msg_buf); |
624 | s->msg_buffered_bytes = 0; | |
ca0b7566 MA |
625 | |
626 | fd = qemu_chr_fe_get_msgfd(s->server_chr); | |
627 | IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd); | |
628 | ||
1309cf44 MA |
629 | process_msg(s, msg, fd, &err); |
630 | if (err) { | |
631 | error_report_err(err); | |
632 | } | |
6cbf4c8c CM |
633 | } |
634 | ||
1309cf44 | 635 | static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp) |
5105b1d8 | 636 | { |
3a55fc0f MA |
637 | int64_t msg; |
638 | int n, ret; | |
639 | ||
640 | n = 0; | |
641 | do { | |
642 | ret = qemu_chr_fe_read_all(s->server_chr, (uint8_t *)&msg + n, | |
643 | sizeof(msg) - n); | |
644 | if (ret < 0 && ret != -EINTR) { | |
1309cf44 | 645 | error_setg_errno(errp, -ret, "read from server failed"); |
3a55fc0f MA |
646 | return INT64_MIN; |
647 | } | |
648 | n += ret; | |
649 | } while (n < sizeof(msg)); | |
5105b1d8 | 650 | |
3a55fc0f MA |
651 | *pfd = qemu_chr_fe_get_msgfd(s->server_chr); |
652 | return msg; | |
653 | } | |
5105b1d8 | 654 | |
1309cf44 | 655 | static void ivshmem_recv_setup(IVShmemState *s, Error **errp) |
3a55fc0f | 656 | { |
1309cf44 | 657 | Error *err = NULL; |
3a55fc0f MA |
658 | int64_t msg; |
659 | int fd; | |
660 | ||
1309cf44 MA |
661 | msg = ivshmem_recv_msg(s, &fd, &err); |
662 | if (err) { | |
663 | error_propagate(errp, err); | |
664 | return; | |
665 | } | |
666 | if (msg != IVSHMEM_PROTOCOL_VERSION) { | |
667 | error_setg(errp, "server sent version %" PRId64 ", expecting %d", | |
668 | msg, IVSHMEM_PROTOCOL_VERSION); | |
669 | return; | |
670 | } | |
671 | if (fd != -1) { | |
672 | error_setg(errp, "server sent invalid version message"); | |
5105b1d8 DM |
673 | return; |
674 | } | |
675 | ||
a3feb086 MA |
676 | /* |
677 | * ivshmem-server sends the remaining initial messages in a fixed | |
678 | * order, but the device has always accepted them in any order. | |
679 | * Stay as compatible as practical, just in case people use | |
680 | * servers that behave differently. | |
681 | */ | |
682 | ||
683 | /* | |
684 | * ivshmem_device_spec.txt has always required the ID message | |
685 | * right here, and ivshmem-server has always complied. However, | |
686 | * older versions of the device accepted it out of order, but | |
687 | * broke when an interrupt setup message arrived before it. | |
688 | */ | |
689 | msg = ivshmem_recv_msg(s, &fd, &err); | |
690 | if (err) { | |
691 | error_propagate(errp, err); | |
692 | return; | |
693 | } | |
694 | if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) { | |
695 | error_setg(errp, "server sent invalid ID message"); | |
696 | return; | |
697 | } | |
698 | s->vm_id = msg; | |
699 | ||
3a55fc0f MA |
700 | /* |
701 | * Receive more messages until we got shared memory. | |
702 | */ | |
703 | do { | |
1309cf44 MA |
704 | msg = ivshmem_recv_msg(s, &fd, &err); |
705 | if (err) { | |
706 | error_propagate(errp, err); | |
707 | return; | |
708 | } | |
709 | process_msg(s, msg, fd, &err); | |
710 | if (err) { | |
711 | error_propagate(errp, err); | |
712 | return; | |
713 | } | |
3a55fc0f | 714 | } while (msg != -1); |
1309cf44 MA |
715 | |
716 | /* | |
717 | * This function must either map the shared memory or fail. The | |
718 | * loop above ensures that: it terminates normally only after it | |
719 | * successfully processed the server's shared memory message. | |
720 | * Assert that actually mapped the shared memory: | |
721 | */ | |
c2d8019c | 722 | assert(s->ivshmem_bar2); |
5105b1d8 DM |
723 | } |
724 | ||
4490c711 MT |
725 | /* Select the MSI-X vectors used by device. |
726 | * ivshmem maps events to vectors statically, so | |
727 | * we just enable all vectors on init and after reset. */ | |
082751e8 | 728 | static void ivshmem_msix_vector_use(IVShmemState *s) |
4490c711 | 729 | { |
b7578eaa | 730 | PCIDevice *d = PCI_DEVICE(s); |
4490c711 MT |
731 | int i; |
732 | ||
4490c711 | 733 | for (i = 0; i < s->vectors; i++) { |
b7578eaa | 734 | msix_vector_use(d, i); |
4490c711 MT |
735 | } |
736 | } | |
737 | ||
6cbf4c8c CM |
738 | static void ivshmem_reset(DeviceState *d) |
739 | { | |
5400c02b | 740 | IVShmemState *s = IVSHMEM_COMMON(d); |
6cbf4c8c CM |
741 | |
742 | s->intrstatus = 0; | |
972ad215 | 743 | s->intrmask = 0; |
082751e8 MA |
744 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
745 | ivshmem_msix_vector_use(s); | |
746 | } | |
6cbf4c8c CM |
747 | } |
748 | ||
fd47bfe5 | 749 | static int ivshmem_setup_interrupts(IVShmemState *s) |
4490c711 | 750 | { |
fd47bfe5 MAL |
751 | /* allocate QEMU callback data for receiving interrupts */ |
752 | s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector)); | |
6cbf4c8c | 753 | |
fd47bfe5 MAL |
754 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { |
755 | if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) { | |
756 | return -1; | |
757 | } | |
1116b539 | 758 | |
fd47bfe5 | 759 | IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors); |
082751e8 | 760 | ivshmem_msix_vector_use(s); |
fd47bfe5 | 761 | } |
4490c711 | 762 | |
d58d7e84 | 763 | return 0; |
6cbf4c8c CM |
764 | } |
765 | ||
660c97ee MAL |
766 | static void ivshmem_enable_irqfd(IVShmemState *s) |
767 | { | |
768 | PCIDevice *pdev = PCI_DEVICE(s); | |
769 | int i; | |
770 | ||
771 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
1309cf44 MA |
772 | Error *err = NULL; |
773 | ||
774 | ivshmem_add_kvm_msi_virq(s, i, &err); | |
775 | if (err) { | |
776 | error_report_err(err); | |
777 | /* TODO do we need to handle the error? */ | |
778 | } | |
660c97ee MAL |
779 | } |
780 | ||
781 | if (msix_set_vector_notifiers(pdev, | |
782 | ivshmem_vector_unmask, | |
783 | ivshmem_vector_mask, | |
784 | ivshmem_vector_poll)) { | |
785 | error_report("ivshmem: msix_set_vector_notifiers failed"); | |
786 | } | |
787 | } | |
788 | ||
789 | static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector) | |
790 | { | |
791 | IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector); | |
792 | ||
793 | if (s->msi_vectors[vector].pdev == NULL) { | |
794 | return; | |
795 | } | |
796 | ||
797 | /* it was cleaned when masked in the frontend. */ | |
798 | kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq); | |
799 | ||
800 | s->msi_vectors[vector].pdev = NULL; | |
801 | } | |
802 | ||
803 | static void ivshmem_disable_irqfd(IVShmemState *s) | |
804 | { | |
805 | PCIDevice *pdev = PCI_DEVICE(s); | |
806 | int i; | |
807 | ||
808 | for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) { | |
809 | ivshmem_remove_kvm_msi_virq(s, i); | |
810 | } | |
811 | ||
812 | msix_unset_vector_notifiers(pdev); | |
813 | } | |
814 | ||
815 | static void ivshmem_write_config(PCIDevice *pdev, uint32_t address, | |
d58d7e84 | 816 | uint32_t val, int len) |
4490c711 | 817 | { |
5400c02b | 818 | IVShmemState *s = IVSHMEM_COMMON(pdev); |
660c97ee MAL |
819 | int is_enabled, was_enabled = msix_enabled(pdev); |
820 | ||
821 | pci_default_write_config(pdev, address, val, len); | |
822 | is_enabled = msix_enabled(pdev); | |
823 | ||
1309cf44 | 824 | if (kvm_msi_via_irqfd_enabled()) { |
660c97ee MAL |
825 | if (!was_enabled && is_enabled) { |
826 | ivshmem_enable_irqfd(s); | |
827 | } else if (was_enabled && !is_enabled) { | |
828 | ivshmem_disable_irqfd(s); | |
829 | } | |
830 | } | |
4490c711 MT |
831 | } |
832 | ||
5503e285 MA |
833 | static void desugar_shm(IVShmemState *s) |
834 | { | |
835 | Object *obj; | |
836 | char *path; | |
837 | ||
838 | obj = object_new("memory-backend-file"); | |
839 | path = g_strdup_printf("/dev/shm/%s", s->shmobj); | |
840 | object_property_set_str(obj, path, "mem-path", &error_abort); | |
841 | g_free(path); | |
5400c02b | 842 | object_property_set_int(obj, s->legacy_size, "size", &error_abort); |
5503e285 MA |
843 | object_property_set_bool(obj, true, "share", &error_abort); |
844 | object_property_add_child(OBJECT(s), "internal-shm-backend", obj, | |
845 | &error_abort); | |
846 | user_creatable_complete(obj, &error_abort); | |
847 | s->hostmem = MEMORY_BACKEND(obj); | |
848 | } | |
849 | ||
5400c02b | 850 | static void ivshmem_common_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 851 | { |
5400c02b | 852 | IVShmemState *s = IVSHMEM_COMMON(dev); |
d855e275 | 853 | Error *err = NULL; |
6cbf4c8c | 854 | uint8_t *pci_conf; |
9113e3f3 MAL |
855 | uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY | |
856 | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
6cbf4c8c | 857 | |
6cbf4c8c CM |
858 | /* IRQFD requires MSI */ |
859 | if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) && | |
860 | !ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
d58d7e84 MAL |
861 | error_setg(errp, "ioeventfd/irqfd requires MSI"); |
862 | return; | |
6cbf4c8c CM |
863 | } |
864 | ||
b7578eaa | 865 | pci_conf = dev->config; |
6cbf4c8c | 866 | pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
6cbf4c8c | 867 | |
3c161542 | 868 | memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s, |
cb06608e AK |
869 | "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE); |
870 | ||
6cbf4c8c | 871 | /* region for registers*/ |
b7578eaa | 872 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, |
e824b2cc | 873 | &s->ivshmem_mmio); |
cb06608e | 874 | |
5400c02b | 875 | if (!s->not_legacy_32bit) { |
9113e3f3 | 876 | attr |= PCI_BASE_ADDRESS_MEM_TYPE_64; |
c08ba66f | 877 | } |
6cbf4c8c | 878 | |
d9453c93 | 879 | if (s->hostmem != NULL) { |
d9453c93 MAL |
880 | IVSHMEM_DPRINTF("using hostmem\n"); |
881 | ||
c2d8019c MA |
882 | s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem, |
883 | &error_abort); | |
5503e285 | 884 | } else { |
6cbf4c8c | 885 | IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n", |
dbc464d4 | 886 | s->server_chr->filename); |
6cbf4c8c | 887 | |
f456179f | 888 | /* we allocate enough space for 16 peers and grow as needed */ |
1300b273 | 889 | resize_peers(s, 16); |
6cbf4c8c | 890 | |
3a55fc0f MA |
891 | /* |
892 | * Receive setup messages from server synchronously. | |
893 | * Older versions did it asynchronously, but that creates a | |
894 | * number of entertaining race conditions. | |
3a55fc0f | 895 | */ |
1309cf44 MA |
896 | ivshmem_recv_setup(s, &err); |
897 | if (err) { | |
898 | error_propagate(errp, err); | |
899 | return; | |
3a55fc0f MA |
900 | } |
901 | ||
1309cf44 MA |
902 | qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, |
903 | ivshmem_read, NULL, s); | |
904 | ||
3a55fc0f MA |
905 | if (ivshmem_setup_interrupts(s) < 0) { |
906 | error_setg(errp, "failed to initialize interrupts"); | |
907 | return; | |
908 | } | |
d855e275 MA |
909 | } |
910 | ||
c2d8019c MA |
911 | vmstate_register_ram(s->ivshmem_bar2, DEVICE(s)); |
912 | pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2); | |
913 | ||
2a845da7 MA |
914 | if (s->master == ON_OFF_AUTO_AUTO) { |
915 | s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; | |
916 | } | |
917 | ||
918 | if (!ivshmem_is_master(s)) { | |
d855e275 MA |
919 | error_setg(&s->migration_blocker, |
920 | "Migration is disabled when using feature 'peer mode' in device 'ivshmem'"); | |
921 | migrate_add_blocker(s->migration_blocker); | |
6cbf4c8c | 922 | } |
6cbf4c8c CM |
923 | } |
924 | ||
5400c02b | 925 | static void ivshmem_realize(PCIDevice *dev, Error **errp) |
6cbf4c8c | 926 | { |
5400c02b MA |
927 | IVShmemState *s = IVSHMEM_COMMON(dev); |
928 | ||
929 | if (!qtest_enabled()) { | |
930 | error_report("ivshmem is deprecated, please use ivshmem-plain" | |
931 | " or ivshmem-doorbell instead"); | |
932 | } | |
933 | ||
934 | if (!!s->server_chr + !!s->shmobj + !!s->hostmem != 1) { | |
935 | error_setg(errp, | |
936 | "You must specify either 'shm', 'chardev' or 'x-memdev'"); | |
937 | return; | |
938 | } | |
939 | ||
940 | if (s->hostmem) { | |
941 | if (s->sizearg) { | |
942 | g_warning("size argument ignored with hostmem"); | |
943 | } | |
944 | } else if (s->sizearg == NULL) { | |
945 | s->legacy_size = 4 << 20; /* 4 MB default */ | |
946 | } else { | |
947 | char *end; | |
948 | int64_t size = qemu_strtosz(s->sizearg, &end); | |
949 | if (size < 0 || (size_t)size != size || *end != '\0' | |
950 | || !is_power_of_2(size)) { | |
951 | error_setg(errp, "Invalid size %s", s->sizearg); | |
952 | return; | |
953 | } | |
954 | s->legacy_size = size; | |
955 | } | |
956 | ||
957 | /* check that role is reasonable */ | |
958 | if (s->role) { | |
959 | if (strncmp(s->role, "peer", 5) == 0) { | |
960 | s->master = ON_OFF_AUTO_OFF; | |
961 | } else if (strncmp(s->role, "master", 7) == 0) { | |
962 | s->master = ON_OFF_AUTO_ON; | |
963 | } else { | |
964 | error_setg(errp, "'role' must be 'peer' or 'master'"); | |
965 | return; | |
966 | } | |
967 | } else { | |
968 | s->master = ON_OFF_AUTO_AUTO; | |
969 | } | |
970 | ||
971 | if (s->shmobj) { | |
972 | desugar_shm(s); | |
973 | } | |
974 | ||
975 | /* | |
976 | * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a | |
977 | * bald-faced lie then. But it's a backwards compatible lie. | |
978 | */ | |
979 | pci_config_set_interrupt_pin(dev->config, 1); | |
980 | ||
981 | ivshmem_common_realize(dev, errp); | |
982 | } | |
983 | ||
984 | static void ivshmem_exit(PCIDevice *dev) | |
985 | { | |
986 | IVShmemState *s = IVSHMEM_COMMON(dev); | |
f64a078d MAL |
987 | int i; |
988 | ||
38e0735e AL |
989 | if (s->migration_blocker) { |
990 | migrate_del_blocker(s->migration_blocker); | |
991 | error_free(s->migration_blocker); | |
992 | } | |
993 | ||
c2d8019c | 994 | if (memory_region_is_mapped(s->ivshmem_bar2)) { |
d9453c93 | 995 | if (!s->hostmem) { |
c2d8019c | 996 | void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2); |
56a571d9 | 997 | int fd; |
d9453c93 | 998 | |
5400c02b | 999 | if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) { |
d9453c93 MAL |
1000 | error_report("Failed to munmap shared memory %s", |
1001 | strerror(errno)); | |
1002 | } | |
56a571d9 | 1003 | |
c2d8019c MA |
1004 | fd = qemu_get_ram_fd(memory_region_get_ram_addr(s->ivshmem_bar2)); |
1005 | close(fd); | |
d9453c93 | 1006 | } |
f64a078d | 1007 | |
c2d8019c | 1008 | vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev)); |
f64a078d MAL |
1009 | } |
1010 | ||
f64a078d MAL |
1011 | if (s->peers) { |
1012 | for (i = 0; i < s->nb_peers; i++) { | |
f456179f | 1013 | close_peer_eventfds(s, i); |
f64a078d MAL |
1014 | } |
1015 | g_free(s->peers); | |
1016 | } | |
1017 | ||
1018 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1019 | msix_uninit_exclusive_bar(dev); | |
1020 | } | |
1021 | ||
0f57350e | 1022 | g_free(s->msi_vectors); |
6cbf4c8c CM |
1023 | } |
1024 | ||
1f8552df MAL |
1025 | static bool test_msix(void *opaque, int version_id) |
1026 | { | |
1027 | IVShmemState *s = opaque; | |
1028 | ||
1029 | return ivshmem_has_feature(s, IVSHMEM_MSI); | |
1030 | } | |
1031 | ||
1032 | static bool test_no_msix(void *opaque, int version_id) | |
1033 | { | |
1034 | return !test_msix(opaque, version_id); | |
1035 | } | |
1036 | ||
1037 | static int ivshmem_pre_load(void *opaque) | |
1038 | { | |
1039 | IVShmemState *s = opaque; | |
1040 | ||
2a845da7 | 1041 | if (!ivshmem_is_master(s)) { |
1f8552df MAL |
1042 | error_report("'peer' devices are not migratable"); |
1043 | return -EINVAL; | |
1044 | } | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static int ivshmem_post_load(void *opaque, int version_id) | |
1050 | { | |
1051 | IVShmemState *s = opaque; | |
1052 | ||
1053 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
082751e8 | 1054 | ivshmem_msix_vector_use(s); |
1f8552df | 1055 | } |
1f8552df MAL |
1056 | return 0; |
1057 | } | |
1058 | ||
1059 | static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id) | |
1060 | { | |
1061 | IVShmemState *s = opaque; | |
1062 | PCIDevice *pdev = PCI_DEVICE(s); | |
1063 | int ret; | |
1064 | ||
1065 | IVSHMEM_DPRINTF("ivshmem_load_old\n"); | |
1066 | ||
1067 | if (version_id != 0) { | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
2a845da7 MA |
1071 | ret = ivshmem_pre_load(s); |
1072 | if (ret) { | |
1073 | return ret; | |
1f8552df MAL |
1074 | } |
1075 | ||
1076 | ret = pci_device_load(pdev, f); | |
1077 | if (ret) { | |
1078 | return ret; | |
1079 | } | |
1080 | ||
1081 | if (ivshmem_has_feature(s, IVSHMEM_MSI)) { | |
1082 | msix_load(pdev, f); | |
082751e8 | 1083 | ivshmem_msix_vector_use(s); |
1f8552df MAL |
1084 | } else { |
1085 | s->intrstatus = qemu_get_be32(f); | |
1086 | s->intrmask = qemu_get_be32(f); | |
1087 | } | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static const VMStateDescription ivshmem_vmsd = { | |
1093 | .name = "ivshmem", | |
1094 | .version_id = 1, | |
1095 | .minimum_version_id = 1, | |
1096 | .pre_load = ivshmem_pre_load, | |
1097 | .post_load = ivshmem_post_load, | |
1098 | .fields = (VMStateField[]) { | |
1099 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1100 | ||
1101 | VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix), | |
1102 | VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix), | |
1103 | VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix), | |
1104 | ||
1105 | VMSTATE_END_OF_LIST() | |
1106 | }, | |
1107 | .load_state_old = ivshmem_load_old, | |
1108 | .minimum_version_id_old = 0 | |
1109 | }; | |
1110 | ||
40021f08 AL |
1111 | static Property ivshmem_properties[] = { |
1112 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1113 | DEFINE_PROP_STRING("size", IVShmemState, sizearg), | |
1114 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1115 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, false), | |
1116 | DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true), | |
1117 | DEFINE_PROP_STRING("shm", IVShmemState, shmobj), | |
1118 | DEFINE_PROP_STRING("role", IVShmemState, role), | |
5400c02b | 1119 | DEFINE_PROP_UINT32("use64", IVShmemState, not_legacy_32bit, 1), |
40021f08 AL |
1120 | DEFINE_PROP_END_OF_LIST(), |
1121 | }; | |
1122 | ||
5400c02b | 1123 | static void ivshmem_common_class_init(ObjectClass *klass, void *data) |
40021f08 | 1124 | { |
39bffca2 | 1125 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1126 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1127 | ||
5400c02b MA |
1128 | k->realize = ivshmem_common_realize; |
1129 | k->exit = ivshmem_exit; | |
d58d7e84 | 1130 | k->config_write = ivshmem_write_config; |
b8ef62a9 PB |
1131 | k->vendor_id = PCI_VENDOR_ID_IVSHMEM; |
1132 | k->device_id = PCI_DEVICE_ID_IVSHMEM; | |
40021f08 | 1133 | k->class_id = PCI_CLASS_MEMORY_RAM; |
5400c02b | 1134 | k->revision = 1; |
39bffca2 | 1135 | dc->reset = ivshmem_reset; |
125ee0ed | 1136 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
d383537d | 1137 | dc->desc = "Inter-VM shared memory"; |
40021f08 AL |
1138 | } |
1139 | ||
5400c02b MA |
1140 | static void ivshmem_class_init(ObjectClass *klass, void *data) |
1141 | { | |
1142 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1143 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1144 | ||
1145 | k->realize = ivshmem_realize; | |
1146 | k->revision = 0; | |
1147 | dc->desc = "Inter-VM shared memory (legacy)"; | |
1148 | dc->props = ivshmem_properties; | |
1149 | dc->vmsd = &ivshmem_vmsd; | |
1150 | } | |
1151 | ||
d9453c93 MAL |
1152 | static void ivshmem_check_memdev_is_busy(Object *obj, const char *name, |
1153 | Object *val, Error **errp) | |
1154 | { | |
1155 | MemoryRegion *mr; | |
1156 | ||
9cf70c52 | 1157 | mr = host_memory_backend_get_memory(MEMORY_BACKEND(val), &error_abort); |
d9453c93 MAL |
1158 | if (memory_region_is_mapped(mr)) { |
1159 | char *path = object_get_canonical_path_component(val); | |
1160 | error_setg(errp, "can't use already busy memdev: %s", path); | |
1161 | g_free(path); | |
1162 | } else { | |
1163 | qdev_prop_allow_set_link_before_realize(obj, name, val, errp); | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | static void ivshmem_init(Object *obj) | |
1168 | { | |
1169 | IVShmemState *s = IVSHMEM(obj); | |
1170 | ||
1d649244 | 1171 | object_property_add_link(obj, "x-memdev", TYPE_MEMORY_BACKEND, |
d9453c93 MAL |
1172 | (Object **)&s->hostmem, |
1173 | ivshmem_check_memdev_is_busy, | |
1174 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
1175 | &error_abort); | |
1176 | } | |
1177 | ||
5400c02b MA |
1178 | static const TypeInfo ivshmem_common_info = { |
1179 | .name = TYPE_IVSHMEM_COMMON, | |
1180 | .parent = TYPE_PCI_DEVICE, | |
1181 | .instance_size = sizeof(IVShmemState), | |
1182 | .abstract = true, | |
1183 | .class_init = ivshmem_common_class_init, | |
1184 | }; | |
1185 | ||
8c43a6f0 | 1186 | static const TypeInfo ivshmem_info = { |
eb3fedf3 | 1187 | .name = TYPE_IVSHMEM, |
5400c02b | 1188 | .parent = TYPE_IVSHMEM_COMMON, |
39bffca2 | 1189 | .instance_size = sizeof(IVShmemState), |
d9453c93 | 1190 | .instance_init = ivshmem_init, |
39bffca2 | 1191 | .class_init = ivshmem_class_init, |
6cbf4c8c CM |
1192 | }; |
1193 | ||
5400c02b MA |
1194 | static const VMStateDescription ivshmem_plain_vmsd = { |
1195 | .name = TYPE_IVSHMEM_PLAIN, | |
1196 | .version_id = 0, | |
1197 | .minimum_version_id = 0, | |
1198 | .pre_load = ivshmem_pre_load, | |
1199 | .post_load = ivshmem_post_load, | |
1200 | .fields = (VMStateField[]) { | |
1201 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1202 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1203 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1204 | VMSTATE_END_OF_LIST() | |
1205 | }, | |
1206 | }; | |
1207 | ||
1208 | static Property ivshmem_plain_properties[] = { | |
1209 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
1210 | DEFINE_PROP_END_OF_LIST(), | |
1211 | }; | |
1212 | ||
1213 | static void ivshmem_plain_init(Object *obj) | |
1214 | { | |
1215 | IVShmemState *s = IVSHMEM_PLAIN(obj); | |
1216 | ||
1217 | object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, | |
1218 | (Object **)&s->hostmem, | |
1219 | ivshmem_check_memdev_is_busy, | |
1220 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
1221 | &error_abort); | |
1222 | } | |
1223 | ||
1224 | static void ivshmem_plain_class_init(ObjectClass *klass, void *data) | |
1225 | { | |
1226 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1227 | ||
1228 | dc->props = ivshmem_plain_properties; | |
1229 | dc->vmsd = &ivshmem_plain_vmsd; | |
1230 | } | |
1231 | ||
1232 | static const TypeInfo ivshmem_plain_info = { | |
1233 | .name = TYPE_IVSHMEM_PLAIN, | |
1234 | .parent = TYPE_IVSHMEM_COMMON, | |
1235 | .instance_size = sizeof(IVShmemState), | |
1236 | .instance_init = ivshmem_plain_init, | |
1237 | .class_init = ivshmem_plain_class_init, | |
1238 | }; | |
1239 | ||
1240 | static const VMStateDescription ivshmem_doorbell_vmsd = { | |
1241 | .name = TYPE_IVSHMEM_DOORBELL, | |
1242 | .version_id = 0, | |
1243 | .minimum_version_id = 0, | |
1244 | .pre_load = ivshmem_pre_load, | |
1245 | .post_load = ivshmem_post_load, | |
1246 | .fields = (VMStateField[]) { | |
1247 | VMSTATE_PCI_DEVICE(parent_obj, IVShmemState), | |
1248 | VMSTATE_MSIX(parent_obj, IVShmemState), | |
1249 | VMSTATE_UINT32(intrstatus, IVShmemState), | |
1250 | VMSTATE_UINT32(intrmask, IVShmemState), | |
1251 | VMSTATE_END_OF_LIST() | |
1252 | }, | |
1253 | }; | |
1254 | ||
1255 | static Property ivshmem_doorbell_properties[] = { | |
1256 | DEFINE_PROP_CHR("chardev", IVShmemState, server_chr), | |
1257 | DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1), | |
1258 | DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, | |
1259 | true), | |
1260 | DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), | |
1261 | DEFINE_PROP_END_OF_LIST(), | |
1262 | }; | |
1263 | ||
1264 | static void ivshmem_doorbell_init(Object *obj) | |
1265 | { | |
1266 | IVShmemState *s = IVSHMEM_DOORBELL(obj); | |
1267 | ||
1268 | s->features |= (1 << IVSHMEM_MSI); | |
1269 | s->legacy_size = SIZE_MAX; /* whatever the server sends */ | |
1270 | } | |
1271 | ||
1272 | static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data) | |
1273 | { | |
1274 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1275 | ||
1276 | dc->props = ivshmem_doorbell_properties; | |
1277 | dc->vmsd = &ivshmem_doorbell_vmsd; | |
1278 | } | |
1279 | ||
1280 | static const TypeInfo ivshmem_doorbell_info = { | |
1281 | .name = TYPE_IVSHMEM_DOORBELL, | |
1282 | .parent = TYPE_IVSHMEM_COMMON, | |
1283 | .instance_size = sizeof(IVShmemState), | |
1284 | .instance_init = ivshmem_doorbell_init, | |
1285 | .class_init = ivshmem_doorbell_class_init, | |
1286 | }; | |
1287 | ||
83f7d43a | 1288 | static void ivshmem_register_types(void) |
6cbf4c8c | 1289 | { |
5400c02b MA |
1290 | type_register_static(&ivshmem_common_info); |
1291 | type_register_static(&ivshmem_plain_info); | |
1292 | type_register_static(&ivshmem_doorbell_info); | |
39bffca2 | 1293 | type_register_static(&ivshmem_info); |
6cbf4c8c CM |
1294 | } |
1295 | ||
83f7d43a | 1296 | type_init(ivshmem_register_types) |