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tcg: Pass generic CPUState to gen_intermediate_code()
[qemu.git] / target / sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <[email protected]>
3475187d 5 Copyright (C) 2003-2005 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
8167ee88 18 License along with this library; if not, see <http://www.gnu.org/licenses/>.
7a3f1944
FB		 19 */
20
db5ebe5f 21#include "qemu/osdep.h"
7a3f1944
FB		 22
23#include "cpu.h"
76cad711 24#include "disas/disas.h"
2ef6175a 25#include "exec/helper-proto.h"
63c91552 26#include "exec/exec-all.h"
57fec1fe 27#include "tcg-op.h"
f08b6170 28#include "exec/cpu_ldst.h"
7a3f1944 29
2ef6175a 30#include "exec/helper-gen.h"
a7812ae4 31
a7e30d84 32#include "trace-tcg.h"
508127e2 33#include "exec/log.h"
0cc1f4bf 34#include "asi.h"
a7e30d84
LV		 35
36
7a3f1944
FB		 37#define DEBUG_DISAS
38
72cbca10
FB		 39#define DYNAMIC_PC 1 /* dynamic pc value */
40#define JUMP_PC 2 /* dynamic pc value which takes only two values
41 according to jump_pc[T2] */
42
1a2fb1c0 43/* global register indexes */
1bcea73e
LV		 44static TCGv_env cpu_env;
45static TCGv_ptr cpu_regwptr;
25517f99
PB		 46static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
47static TCGv_i32 cpu_cc_op;
a7812ae4 48static TCGv_i32 cpu_psr;
d2dc4069
RH		 49static TCGv cpu_fsr, cpu_pc, cpu_npc;
50static TCGv cpu_regs[32];
255e1fcb
BS		 51static TCGv cpu_y;
52#ifndef CONFIG_USER_ONLY
53static TCGv cpu_tbr;
54#endif
5793f2a4 55static TCGv cpu_cond;
dc99a3f2 56#ifdef TARGET_SPARC64
a6d567e5 57static TCGv_i32 cpu_xcc, cpu_fprs;
a7812ae4 58static TCGv cpu_gsr;
255e1fcb 59static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
a7812ae4 60static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
255e1fcb
BS		 61#else
62static TCGv cpu_wim;
dc99a3f2 63#endif
714547bb 64/* Floating point registers */
30038fd8 65static TCGv_i64 cpu_fpr[TARGET_DPREGS];
1a2fb1c0 66
022c62cb 67#include "exec/gen-icount.h"
2e70f6ef 68
7a3f1944 69typedef struct DisasContext {
0f8a249a
BS		 70 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
71 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
72cbca10 72 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 73 int is_br;
e8af50a3 74 int mem_idx;
c9b459aa
AT		 75 bool fpu_enabled;
76 bool address_mask_32bit;
77 bool singlestep;
78#ifndef CONFIG_USER_ONLY
79 bool supervisor;
80#ifdef TARGET_SPARC64
81 bool hypervisor;
82#endif
83#endif
84
8393617c 85 uint32_t cc_op; /* current CC operation */
cf495bcf 86 struct TranslationBlock *tb;
5578ceab 87 sparc_def_t *def;
30038fd8 88 TCGv_i32 t32[3];
88023616 89 TCGv ttl[5];
30038fd8 90 int n_t32;
88023616 91 int n_ttl;
a6d567e5 92#ifdef TARGET_SPARC64
f9c816c0 93 int fprs_dirty;
a6d567e5
RH		 94 int asi;
95#endif
7a3f1944
FB		 96} DisasContext;
97
416fcaea
RH		 98typedef struct {
99 TCGCond cond;
100 bool is_bool;
101 bool g1, g2;
102 TCGv c1, c2;
103} DisasCompare;
104
3475187d 105// This function uses non-native bit order
dc1a6971
BS		 106#define GET_FIELD(X, FROM, TO) \
107 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
7a3f1944 108
3475187d 109// This function uses the order in the manuals, i.e. bit 0 is 2^0
dc1a6971 110#define GET_FIELD_SP(X, FROM, TO) \
3475187d
FB		 111 GET_FIELD(X, 31 - (TO), 31 - (FROM))
112
113#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
46d38ba8 114#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
3475187d
FB		 115
116#ifdef TARGET_SPARC64
0387d928 117#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
1f587329 118#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
3475187d 119#else
c185970a 120#define DFPREG(r) (r & 0x1e)
1f587329 121#define QFPREG(r) (r & 0x1c)
3475187d
FB		 122#endif
123
b158a785
BS		 124#define UA2005_HTRAP_MASK 0xff
125#define V8_TRAP_MASK 0x7f
126
3475187d
FB		 127static int sign_extend(int x, int len)
128{
129 len = 32 - len;
130 return (x << len) >> len;
131}
132
7a3f1944
FB		 133#define IS_IMM (insn & (1<<13))
134
2ae23e17
RH		 135static inline TCGv_i32 get_temp_i32(DisasContext *dc)
136{
137 TCGv_i32 t;
138 assert(dc->n_t32 < ARRAY_SIZE(dc->t32));
139 dc->t32[dc->n_t32++] = t = tcg_temp_new_i32();
140 return t;
141}
142
143static inline TCGv get_temp_tl(DisasContext *dc)
144{
145 TCGv t;
146 assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
147 dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
148 return t;
149}
150
f9c816c0 151static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
141ae5c1
RH		 152{
153#if defined(TARGET_SPARC64)
f9c816c0
RH		 154 int bit = (rd < 32) ? 1 : 2;
155 /* If we know we've already set this bit within the TB,
156 we can avoid setting it again. */
157 if (!(dc->fprs_dirty & bit)) {
158 dc->fprs_dirty |= bit;
159 tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
160 }
141ae5c1
RH		 161#endif
162}
163
ff07ec83 164/* floating point registers moves */
208ae657
RH		 165static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src)
166{
30038fd8
RH		 167#if TCG_TARGET_REG_BITS == 32
168 if (src & 1) {
169 return TCGV_LOW(cpu_fpr[src / 2]);
170 } else {
171 return TCGV_HIGH(cpu_fpr[src / 2]);
172 }
173#else
174 if (src & 1) {
175 return MAKE_TCGV_I32(GET_TCGV_I64(cpu_fpr[src / 2]));
176 } else {
2ae23e17 177 TCGv_i32 ret = get_temp_i32(dc);
30038fd8
RH		 178 TCGv_i64 t = tcg_temp_new_i64();
179
180 tcg_gen_shri_i64(t, cpu_fpr[src / 2], 32);
ecc7b3aa 181 tcg_gen_extrl_i64_i32(ret, t);
30038fd8
RH		 182 tcg_temp_free_i64(t);
183
30038fd8
RH		 184 return ret;
185 }
186#endif
208ae657
RH		 187}
188
189static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
190{
30038fd8
RH		 191#if TCG_TARGET_REG_BITS == 32
192 if (dst & 1) {
193 tcg_gen_mov_i32(TCGV_LOW(cpu_fpr[dst / 2]), v);
194 } else {
195 tcg_gen_mov_i32(TCGV_HIGH(cpu_fpr[dst / 2]), v);
196 }
197#else
198 TCGv_i64 t = MAKE_TCGV_I64(GET_TCGV_I32(v));
199 tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
200 (dst & 1 ? 0 : 32), 32);
201#endif
f9c816c0 202 gen_update_fprs_dirty(dc, dst);
208ae657
RH		 203}
204
ba5f5179 205static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
208ae657 206{
ba5f5179 207 return get_temp_i32(dc);
208ae657
RH		 208}
209
96eda024
RH		 210static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src)
211{
96eda024 212 src = DFPREG(src);
30038fd8 213 return cpu_fpr[src / 2];
96eda024
RH		 214}
215
216static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
217{
218 dst = DFPREG(dst);
30038fd8 219 tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
f9c816c0 220 gen_update_fprs_dirty(dc, dst);
96eda024
RH		 221}
222
3886b8a3 223static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
96eda024 224{
3886b8a3 225 return cpu_fpr[DFPREG(dst) / 2];
96eda024
RH		 226}
227
ff07ec83
BS		 228static void gen_op_load_fpr_QT0(unsigned int src)
229{
30038fd8
RH		 230 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
231 offsetof(CPU_QuadU, ll.upper));
232 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
233 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 234}
235
236static void gen_op_load_fpr_QT1(unsigned int src)
237{
30038fd8
RH		 238 tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1) +
239 offsetof(CPU_QuadU, ll.upper));
240 tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
241 offsetof(CPU_QuadU, ll.lower));
ff07ec83
BS		 242}
243
244static void gen_op_store_QT0_fpr(unsigned int dst)
245{
30038fd8
RH		 246 tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0) +
247 offsetof(CPU_QuadU, ll.upper));
248 tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
249 offsetof(CPU_QuadU, ll.lower));
ff07ec83 250}
1f587329 251
f939ffe5
RH		 252static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst,
253 TCGv_i64 v1, TCGv_i64 v2)
254{
255 dst = QFPREG(dst);
256
257 tcg_gen_mov_i64(cpu_fpr[dst / 2], v1);
258 tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2);
259 gen_update_fprs_dirty(dc, dst);
260}
261
ac11f776 262#ifdef TARGET_SPARC64
f939ffe5
RH		 263static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src)
264{
265 src = QFPREG(src);
266 return cpu_fpr[src / 2];
267}
268
269static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src)
270{
271 src = QFPREG(src);
272 return cpu_fpr[src / 2 + 1];
273}
274
f9c816c0 275static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
ac11f776
RH		 276{
277 rd = QFPREG(rd);
278 rs = QFPREG(rs);
279
30038fd8
RH		 280 tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
281 tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
f9c816c0 282 gen_update_fprs_dirty(dc, rd);
ac11f776
RH		 283}
284#endif
285
81ad8ba2
BS		 286/* moves */
287#ifdef CONFIG_USER_ONLY
3475187d 288#define supervisor(dc) 0
81ad8ba2 289#ifdef TARGET_SPARC64
e9ebed4d 290#define hypervisor(dc) 0
81ad8ba2 291#endif
3475187d 292#else
81ad8ba2 293#ifdef TARGET_SPARC64
c9b459aa
AT		 294#define hypervisor(dc) (dc->hypervisor)
295#define supervisor(dc) (dc->supervisor | dc->hypervisor)
6f27aba6 296#else
c9b459aa 297#define supervisor(dc) (dc->supervisor)
3475187d 298#endif
81ad8ba2
BS		 299#endif
300
2cade6a3
BS		 301#ifdef TARGET_SPARC64
302#ifndef TARGET_ABI32
303#define AM_CHECK(dc) ((dc)->address_mask_32bit)
1a2fb1c0 304#else
2cade6a3
BS		 305#define AM_CHECK(dc) (1)
306#endif
1a2fb1c0 307#endif
3391c818 308
2cade6a3
BS		 309static inline void gen_address_mask(DisasContext *dc, TCGv addr)
310{
311#ifdef TARGET_SPARC64
312 if (AM_CHECK(dc))
313 tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
314#endif
315}
316
88023616
RH		 317static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
318{
d2dc4069
RH		 319 if (reg > 0) {
320 assert(reg < 32);
321 return cpu_regs[reg];
322 } else {
88023616 323 TCGv t = get_temp_tl(dc);
d2dc4069 324 tcg_gen_movi_tl(t, 0);
88023616 325 return t;
88023616
RH		 326 }
327}
328
329static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
330{
331 if (reg > 0) {
d2dc4069
RH		 332 assert(reg < 32);
333 tcg_gen_mov_tl(cpu_regs[reg], v);
88023616
RH		 334 }
335}
336
337static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
338{
d2dc4069
RH		 339 if (reg > 0) {
340 assert(reg < 32);
341 return cpu_regs[reg];
88023616 342 } else {
d2dc4069 343 return get_temp_tl(dc);
88023616
RH		 344 }
345}
346
90aa39a1
SF		 347static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
348 target_ulong npc)
349{
350 if (unlikely(s->singlestep)) {
351 return false;
352 }
353
354#ifndef CONFIG_USER_ONLY
355 return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
356 (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
357#else
358 return true;
359#endif
360}
361
5fafdf24 362static inline void gen_goto_tb(DisasContext *s, int tb_num,
6e256c93
FB		 363 target_ulong pc, target_ulong npc)
364{
90aa39a1 365 if (use_goto_tb(s, pc, npc)) {
6e256c93 366 /* jump to same page: we can use a direct jump */
57fec1fe 367 tcg_gen_goto_tb(tb_num);
2f5680ee
BS		 368 tcg_gen_movi_tl(cpu_pc, pc);
369 tcg_gen_movi_tl(cpu_npc, npc);
90aa39a1 370 tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
6e256c93
FB		 371 } else {
372 /* jump to another page: currently not optimized */
2f5680ee
BS		 373 tcg_gen_movi_tl(cpu_pc, pc);
374 tcg_gen_movi_tl(cpu_npc, npc);
57fec1fe 375 tcg_gen_exit_tb(0);
6e256c93
FB		 376 }
377}
378
19f329ad 379// XXX suboptimal
a7812ae4 380static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
19f329ad 381{
8911f501 382 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 383 tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
19f329ad
BS		 384}
385
a7812ae4 386static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
19f329ad 387{
8911f501 388 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 389 tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
19f329ad
BS		 390}
391
a7812ae4 392static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
19f329ad 393{
8911f501 394 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 395 tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
19f329ad
BS		 396}
397
a7812ae4 398static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
19f329ad 399{
8911f501 400 tcg_gen_extu_i32_tl(reg, src);
0b1183e3 401 tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
19f329ad
BS		 402}
403
4af984a7 404static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 405{
4af984a7 406 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 407 tcg_gen_mov_tl(cpu_cc_src2, src2);
5c6a0628 408 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
bdf9f35d 409 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 410}
411
70c48285 412static TCGv_i32 gen_add32_carry32(void)
dc99a3f2 413{
70c48285
RH		 414 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
415
416 /* Carry is computed from a previous add: (dst < src) */
417#if TARGET_LONG_BITS == 64
418 cc_src1_32 = tcg_temp_new_i32();
419 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 420 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_dst);
421 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src);
70c48285
RH		 422#else
423 cc_src1_32 = cpu_cc_dst;
424 cc_src2_32 = cpu_cc_src;
425#endif
426
427 carry_32 = tcg_temp_new_i32();
428 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
429
430#if TARGET_LONG_BITS == 64
431 tcg_temp_free_i32(cc_src1_32);
432 tcg_temp_free_i32(cc_src2_32);
433#endif
434
435 return carry_32;
41d72852
BS		 436}
437
70c48285 438static TCGv_i32 gen_sub32_carry32(void)
41d72852 439{
70c48285
RH		 440 TCGv_i32 carry_32, cc_src1_32, cc_src2_32;
441
442 /* Carry is computed from a previous borrow: (src1 < src2) */
443#if TARGET_LONG_BITS == 64
444 cc_src1_32 = tcg_temp_new_i32();
445 cc_src2_32 = tcg_temp_new_i32();
ecc7b3aa
RH		 446 tcg_gen_extrl_i64_i32(cc_src1_32, cpu_cc_src);
447 tcg_gen_extrl_i64_i32(cc_src2_32, cpu_cc_src2);
70c48285
RH		 448#else
449 cc_src1_32 = cpu_cc_src;
450 cc_src2_32 = cpu_cc_src2;
451#endif
452
453 carry_32 = tcg_temp_new_i32();
454 tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32);
455
456#if TARGET_LONG_BITS == 64
457 tcg_temp_free_i32(cc_src1_32);
458 tcg_temp_free_i32(cc_src2_32);
459#endif
460
461 return carry_32;
462}
463
464static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
465 TCGv src2, int update_cc)
466{
467 TCGv_i32 carry_32;
468 TCGv carry;
469
470 switch (dc->cc_op) {
471 case CC_OP_DIV:
472 case CC_OP_LOGIC:
473 /* Carry is known to be zero. Fall back to plain ADD. */
474 if (update_cc) {
475 gen_op_add_cc(dst, src1, src2);
476 } else {
477 tcg_gen_add_tl(dst, src1, src2);
478 }
479 return;
480
481 case CC_OP_ADD:
482 case CC_OP_TADD:
483 case CC_OP_TADDTV:
15fe216f
RH		 484 if (TARGET_LONG_BITS == 32) {
485 /* We can re-use the host's hardware carry generation by using
486 an ADD2 opcode. We discard the low part of the output.
487 Ideally we'd combine this operation with the add that
488 generated the carry in the first place. */
489 carry = tcg_temp_new();
490 tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
491 tcg_temp_free(carry);
70c48285
RH		 492 goto add_done;
493 }
70c48285
RH		 494 carry_32 = gen_add32_carry32();
495 break;
496
497 case CC_OP_SUB:
498 case CC_OP_TSUB:
499 case CC_OP_TSUBTV:
500 carry_32 = gen_sub32_carry32();
501 break;
502
503 default:
504 /* We need external help to produce the carry. */
505 carry_32 = tcg_temp_new_i32();
2ffd9176 506 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 507 break;
508 }
509
510#if TARGET_LONG_BITS == 64
511 carry = tcg_temp_new();
512 tcg_gen_extu_i32_i64(carry, carry_32);
513#else
514 carry = carry_32;
515#endif
516
517 tcg_gen_add_tl(dst, src1, src2);
518 tcg_gen_add_tl(dst, dst, carry);
519
520 tcg_temp_free_i32(carry_32);
521#if TARGET_LONG_BITS == 64
522 tcg_temp_free(carry);
523#endif
524
70c48285 525 add_done:
70c48285
RH		 526 if (update_cc) {
527 tcg_gen_mov_tl(cpu_cc_src, src1);
528 tcg_gen_mov_tl(cpu_cc_src2, src2);
529 tcg_gen_mov_tl(cpu_cc_dst, dst);
530 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
531 dc->cc_op = CC_OP_ADDX;
532 }
dc99a3f2
BS		 533}
534
41d72852 535static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
dc99a3f2 536{
4af984a7 537 tcg_gen_mov_tl(cpu_cc_src, src1);
6f551262 538 tcg_gen_mov_tl(cpu_cc_src2, src2);
41d72852 539 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d4b0d468 540 tcg_gen_mov_tl(dst, cpu_cc_dst);
41d72852
BS		 541}
542
70c48285
RH		 543static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
544 TCGv src2, int update_cc)
41d72852 545{
70c48285
RH		 546 TCGv_i32 carry_32;
547 TCGv carry;
41d72852 548
70c48285
RH		 549 switch (dc->cc_op) {
550 case CC_OP_DIV:
551 case CC_OP_LOGIC:
552 /* Carry is known to be zero. Fall back to plain SUB. */
553 if (update_cc) {
554 gen_op_sub_cc(dst, src1, src2);
555 } else {
556 tcg_gen_sub_tl(dst, src1, src2);
557 }
558 return;
559
560 case CC_OP_ADD:
561 case CC_OP_TADD:
562 case CC_OP_TADDTV:
563 carry_32 = gen_add32_carry32();
564 break;
565
566 case CC_OP_SUB:
567 case CC_OP_TSUB:
568 case CC_OP_TSUBTV:
15fe216f
RH		 569 if (TARGET_LONG_BITS == 32) {
570 /* We can re-use the host's hardware carry generation by using
571 a SUB2 opcode. We discard the low part of the output.
572 Ideally we'd combine this operation with the add that
573 generated the carry in the first place. */
574 carry = tcg_temp_new();
575 tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src2);
576 tcg_temp_free(carry);
70c48285
RH		 577 goto sub_done;
578 }
70c48285
RH		 579 carry_32 = gen_sub32_carry32();
580 break;
581
582 default:
583 /* We need external help to produce the carry. */
584 carry_32 = tcg_temp_new_i32();
2ffd9176 585 gen_helper_compute_C_icc(carry_32, cpu_env);
70c48285
RH		 586 break;
587 }
588
589#if TARGET_LONG_BITS == 64
590 carry = tcg_temp_new();
591 tcg_gen_extu_i32_i64(carry, carry_32);
592#else
593 carry = carry_32;
594#endif
595
596 tcg_gen_sub_tl(dst, src1, src2);
597 tcg_gen_sub_tl(dst, dst, carry);
598
599 tcg_temp_free_i32(carry_32);
600#if TARGET_LONG_BITS == 64
601 tcg_temp_free(carry);
602#endif
603
70c48285 604 sub_done:
70c48285
RH		 605 if (update_cc) {
606 tcg_gen_mov_tl(cpu_cc_src, src1);
607 tcg_gen_mov_tl(cpu_cc_src2, src2);
608 tcg_gen_mov_tl(cpu_cc_dst, dst);
609 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX);
610 dc->cc_op = CC_OP_SUBX;
611 }
dc99a3f2
BS		 612}
613
4af984a7 614static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
d9bdab86 615{
de9e9d9f 616 TCGv r_temp, zero, t0;
d9bdab86 617
a7812ae4 618 r_temp = tcg_temp_new();
de9e9d9f 619 t0 = tcg_temp_new();
d9bdab86
BS		 620
621 /* old op:
622 if (!(env->y & 1))
623 T1 = 0;
624 */
6cb675b0 625 zero = tcg_const_tl(0);
72ccba79 626 tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
255e1fcb 627 tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
72ccba79 628 tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
6cb675b0
RH		 629 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero,
630 zero, cpu_cc_src2);
631 tcg_temp_free(zero);
d9bdab86
BS		 632
633 // b2 = T0 & 1;
634 // env->y = (b2 << 31) | (env->y >> 1);
0b1183e3 635 tcg_gen_extract_tl(t0, cpu_y, 1, 31);
08d64e0d 636 tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
d9bdab86
BS		 637
638 // b1 = N ^ V;
de9e9d9f 639 gen_mov_reg_N(t0, cpu_psr);
d9bdab86 640 gen_mov_reg_V(r_temp, cpu_psr);
de9e9d9f 641 tcg_gen_xor_tl(t0, t0, r_temp);
2ea815ca 642 tcg_temp_free(r_temp);
d9bdab86
BS		 643
644 // T0 = (b1 << 31) | (T0 >> 1);
645 // src1 = T0;
de9e9d9f 646 tcg_gen_shli_tl(t0, t0, 31);
6f551262 647 tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
de9e9d9f
RH		 648 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
649 tcg_temp_free(t0);
d9bdab86 650
5c6a0628 651 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
d9bdab86 652
5c6a0628 653 tcg_gen_mov_tl(dst, cpu_cc_dst);
d9bdab86
BS		 654}
655
fb170183 656static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
8879d139 657{
528692a8 658#if TARGET_LONG_BITS == 32
fb170183 659 if (sign_ext) {
528692a8 660 tcg_gen_muls2_tl(dst, cpu_y, src1, src2);
fb170183 661 } else {
528692a8 662 tcg_gen_mulu2_tl(dst, cpu_y, src1, src2);
fb170183 663 }
528692a8
RH		 664#else
665 TCGv t0 = tcg_temp_new_i64();
666 TCGv t1 = tcg_temp_new_i64();
fb170183 667
528692a8
RH		 668 if (sign_ext) {
669 tcg_gen_ext32s_i64(t0, src1);
670 tcg_gen_ext32s_i64(t1, src2);
671 } else {
672 tcg_gen_ext32u_i64(t0, src1);
673 tcg_gen_ext32u_i64(t1, src2);
674 }
fb170183 675
528692a8
RH		 676 tcg_gen_mul_i64(dst, t0, t1);
677 tcg_temp_free(t0);
678 tcg_temp_free(t1);
fb170183 679
528692a8
RH		 680 tcg_gen_shri_i64(cpu_y, dst, 32);
681#endif
8879d139
BS		 682}
683
fb170183 684static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
8879d139 685{
fb170183
IK		 686 /* zero-extend truncated operands before multiplication */
687 gen_op_multiply(dst, src1, src2, 0);
688}
8879d139 689
fb170183
IK		 690static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
691{
692 /* sign-extend truncated operands before multiplication */
693 gen_op_multiply(dst, src1, src2, 1);
8879d139
BS		 694}
695
19f329ad
BS		 696// 1
697static inline void gen_op_eval_ba(TCGv dst)
698{
699 tcg_gen_movi_tl(dst, 1);
700}
701
702// Z
a7812ae4 703static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
19f329ad
BS		 704{
705 gen_mov_reg_Z(dst, src);
706}
707
708// Z | (N ^ V)
a7812ae4 709static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
19f329ad 710{
de9e9d9f
RH		 711 TCGv t0 = tcg_temp_new();
712 gen_mov_reg_N(t0, src);
19f329ad 713 gen_mov_reg_V(dst, src);
de9e9d9f
RH		 714 tcg_gen_xor_tl(dst, dst, t0);
715 gen_mov_reg_Z(t0, src);
716 tcg_gen_or_tl(dst, dst, t0);
717 tcg_temp_free(t0);
19f329ad
BS		 718}
719
720// N ^ V
a7812ae4 721static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
19f329ad 722{
de9e9d9f
RH		 723 TCGv t0 = tcg_temp_new();
724 gen_mov_reg_V(t0, src);
19f329ad 725 gen_mov_reg_N(dst, src);
de9e9d9f
RH		 726 tcg_gen_xor_tl(dst, dst, t0);
727 tcg_temp_free(t0);
19f329ad
BS		 728}
729
730// C | Z
a7812ae4 731static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
19f329ad 732{
de9e9d9f
RH		 733 TCGv t0 = tcg_temp_new();
734 gen_mov_reg_Z(t0, src);
19f329ad 735 gen_mov_reg_C(dst, src);
de9e9d9f
RH		 736 tcg_gen_or_tl(dst, dst, t0);
737 tcg_temp_free(t0);
19f329ad
BS		 738}
739
740// C
a7812ae4 741static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 742{
743 gen_mov_reg_C(dst, src);
744}
745
746// V
a7812ae4 747static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
19f329ad
BS		 748{
749 gen_mov_reg_V(dst, src);
750}
751
752// 0
753static inline void gen_op_eval_bn(TCGv dst)
754{
755 tcg_gen_movi_tl(dst, 0);
756}
757
758// N
a7812ae4 759static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
19f329ad
BS		 760{
761 gen_mov_reg_N(dst, src);
762}
763
764// !Z
a7812ae4 765static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
19f329ad
BS		 766{
767 gen_mov_reg_Z(dst, src);
768 tcg_gen_xori_tl(dst, dst, 0x1);
769}
770
771// !(Z | (N ^ V))
a7812ae4 772static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
19f329ad 773{
de9e9d9f 774 gen_op_eval_ble(dst, src);
19f329ad
BS		 775 tcg_gen_xori_tl(dst, dst, 0x1);
776}
777
778// !(N ^ V)
a7812ae4 779static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
19f329ad 780{
de9e9d9f 781 gen_op_eval_bl(dst, src);
19f329ad
BS		 782 tcg_gen_xori_tl(dst, dst, 0x1);
783}
784
785// !(C | Z)
a7812ae4 786static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
19f329ad 787{
de9e9d9f 788 gen_op_eval_bleu(dst, src);
19f329ad
BS		 789 tcg_gen_xori_tl(dst, dst, 0x1);
790}
791
792// !C
a7812ae4 793static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 794{
795 gen_mov_reg_C(dst, src);
796 tcg_gen_xori_tl(dst, dst, 0x1);
797}
798
799// !N
a7812ae4 800static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
19f329ad
BS		 801{
802 gen_mov_reg_N(dst, src);
803 tcg_gen_xori_tl(dst, dst, 0x1);
804}
805
806// !V
a7812ae4 807static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
19f329ad
BS		 808{
809 gen_mov_reg_V(dst, src);
810 tcg_gen_xori_tl(dst, dst, 0x1);
811}
812
813/*
814 FPSR bit field FCC1 | FCC0:
815 0 =
816 1 <
817 2 >
818 3 unordered
819*/
820static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
821 unsigned int fcc_offset)
822{
ba6a9d8c 823 tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
19f329ad
BS		 824 tcg_gen_andi_tl(reg, reg, 0x1);
825}
826
827static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
828 unsigned int fcc_offset)
829{
ba6a9d8c 830 tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
19f329ad
BS		 831 tcg_gen_andi_tl(reg, reg, 0x1);
832}
833
834// !0: FCC0 | FCC1
835static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
836 unsigned int fcc_offset)
837{
de9e9d9f 838 TCGv t0 = tcg_temp_new();
19f329ad 839 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 840 gen_mov_reg_FCC1(t0, src, fcc_offset);
841 tcg_gen_or_tl(dst, dst, t0);
842 tcg_temp_free(t0);
19f329ad
BS		 843}
844
845// 1 or 2: FCC0 ^ FCC1
846static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
847 unsigned int fcc_offset)
848{
de9e9d9f 849 TCGv t0 = tcg_temp_new();
19f329ad 850 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 851 gen_mov_reg_FCC1(t0, src, fcc_offset);
852 tcg_gen_xor_tl(dst, dst, t0);
853 tcg_temp_free(t0);
19f329ad
BS		 854}
855
856// 1 or 3: FCC0
857static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
858 unsigned int fcc_offset)
859{
860 gen_mov_reg_FCC0(dst, src, fcc_offset);
861}
862
863// 1: FCC0 & !FCC1
864static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
865 unsigned int fcc_offset)
866{
de9e9d9f 867 TCGv t0 = tcg_temp_new();
19f329ad 868 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 869 gen_mov_reg_FCC1(t0, src, fcc_offset);
870 tcg_gen_andc_tl(dst, dst, t0);
871 tcg_temp_free(t0);
19f329ad
BS		 872}
873
874// 2 or 3: FCC1
875static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
876 unsigned int fcc_offset)
877{
878 gen_mov_reg_FCC1(dst, src, fcc_offset);
879}
880
881// 2: !FCC0 & FCC1
882static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
883 unsigned int fcc_offset)
884{
de9e9d9f 885 TCGv t0 = tcg_temp_new();
19f329ad 886 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 887 gen_mov_reg_FCC1(t0, src, fcc_offset);
888 tcg_gen_andc_tl(dst, t0, dst);
889 tcg_temp_free(t0);
19f329ad
BS		 890}
891
892// 3: FCC0 & FCC1
893static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
894 unsigned int fcc_offset)
895{
de9e9d9f 896 TCGv t0 = tcg_temp_new();
19f329ad 897 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 898 gen_mov_reg_FCC1(t0, src, fcc_offset);
899 tcg_gen_and_tl(dst, dst, t0);
900 tcg_temp_free(t0);
19f329ad
BS		 901}
902
903// 0: !(FCC0 | FCC1)
904static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
905 unsigned int fcc_offset)
906{
de9e9d9f 907 TCGv t0 = tcg_temp_new();
19f329ad 908 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 909 gen_mov_reg_FCC1(t0, src, fcc_offset);
910 tcg_gen_or_tl(dst, dst, t0);
19f329ad 911 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 912 tcg_temp_free(t0);
19f329ad
BS		 913}
914
915// 0 or 3: !(FCC0 ^ FCC1)
916static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
917 unsigned int fcc_offset)
918{
de9e9d9f 919 TCGv t0 = tcg_temp_new();
19f329ad 920 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 921 gen_mov_reg_FCC1(t0, src, fcc_offset);
922 tcg_gen_xor_tl(dst, dst, t0);
19f329ad 923 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 924 tcg_temp_free(t0);
19f329ad
BS		 925}
926
927// 0 or 2: !FCC0
928static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
929 unsigned int fcc_offset)
930{
931 gen_mov_reg_FCC0(dst, src, fcc_offset);
932 tcg_gen_xori_tl(dst, dst, 0x1);
933}
934
935// !1: !(FCC0 & !FCC1)
936static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
937 unsigned int fcc_offset)
938{
de9e9d9f 939 TCGv t0 = tcg_temp_new();
19f329ad 940 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 941 gen_mov_reg_FCC1(t0, src, fcc_offset);
942 tcg_gen_andc_tl(dst, dst, t0);
19f329ad 943 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 944 tcg_temp_free(t0);
19f329ad
BS		 945}
946
947// 0 or 1: !FCC1
948static inline void gen_op_eval_fble(TCGv dst, TCGv src,
949 unsigned int fcc_offset)
950{
951 gen_mov_reg_FCC1(dst, src, fcc_offset);
952 tcg_gen_xori_tl(dst, dst, 0x1);
953}
954
955// !2: !(!FCC0 & FCC1)
956static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
957 unsigned int fcc_offset)
958{
de9e9d9f 959 TCGv t0 = tcg_temp_new();
19f329ad 960 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 961 gen_mov_reg_FCC1(t0, src, fcc_offset);
962 tcg_gen_andc_tl(dst, t0, dst);
19f329ad 963 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 964 tcg_temp_free(t0);
19f329ad
BS		 965}
966
967// !3: !(FCC0 & FCC1)
968static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
969 unsigned int fcc_offset)
970{
de9e9d9f 971 TCGv t0 = tcg_temp_new();
19f329ad 972 gen_mov_reg_FCC0(dst, src, fcc_offset);
de9e9d9f
RH		 973 gen_mov_reg_FCC1(t0, src, fcc_offset);
974 tcg_gen_and_tl(dst, dst, t0);
19f329ad 975 tcg_gen_xori_tl(dst, dst, 0x1);
de9e9d9f 976 tcg_temp_free(t0);
19f329ad
BS		 977}
978
46525e1f 979static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
19f329ad 980 target_ulong pc2, TCGv r_cond)
83469015 981{
42a268c2 982 TCGLabel *l1 = gen_new_label();
83469015 983
cb63669a 984 tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
83469015 985
6e256c93 986 gen_goto_tb(dc, 0, pc1, pc1 + 4);
83469015
FB		 987
988 gen_set_label(l1);
6e256c93 989 gen_goto_tb(dc, 1, pc2, pc2 + 4);
83469015
FB		 990}
991
bfa31b76 992static void gen_branch_a(DisasContext *dc, target_ulong pc1)
83469015 993{
42a268c2 994 TCGLabel *l1 = gen_new_label();
bfa31b76 995 target_ulong npc = dc->npc;
83469015 996
bfa31b76 997 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
83469015 998
bfa31b76 999 gen_goto_tb(dc, 0, npc, pc1);
83469015
FB		 1000
1001 gen_set_label(l1);
bfa31b76
RH		 1002 gen_goto_tb(dc, 1, npc + 4, npc + 8);
1003
1004 dc->is_br = 1;
83469015
FB		 1005}
1006
2bf2e019
RH		 1007static void gen_branch_n(DisasContext *dc, target_ulong pc1)
1008{
1009 target_ulong npc = dc->npc;
1010
1011 if (likely(npc != DYNAMIC_PC)) {
1012 dc->pc = npc;
1013 dc->jump_pc[0] = pc1;
1014 dc->jump_pc[1] = npc + 4;
1015 dc->npc = JUMP_PC;
1016 } else {
1017 TCGv t, z;
1018
1019 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1020
1021 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1022 t = tcg_const_tl(pc1);
1023 z = tcg_const_tl(0);
1024 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
1025 tcg_temp_free(t);
1026 tcg_temp_free(z);
1027
1028 dc->pc = DYNAMIC_PC;
1029 }
1030}
1031
2e655fe7 1032static inline void gen_generic_branch(DisasContext *dc)
83469015 1033{
61316742
RH		 1034 TCGv npc0 = tcg_const_tl(dc->jump_pc[0]);
1035 TCGv npc1 = tcg_const_tl(dc->jump_pc[1]);
1036 TCGv zero = tcg_const_tl(0);
19f329ad 1037
61316742 1038 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
83469015 1039
61316742
RH		 1040 tcg_temp_free(npc0);
1041 tcg_temp_free(npc1);
1042 tcg_temp_free(zero);
83469015
FB		 1043}
1044
4af984a7
BS		 1045/* call this function before using the condition register as it may
1046 have been set for a jump */
dee8913c 1047static inline void flush_cond(DisasContext *dc)
83469015
FB		 1048{
1049 if (dc->npc == JUMP_PC) {
2e655fe7 1050 gen_generic_branch(dc);
83469015
FB		 1051 dc->npc = DYNAMIC_PC;
1052 }
1053}
1054
934da7ee 1055static inline void save_npc(DisasContext *dc)
72cbca10
FB		 1056{
1057 if (dc->npc == JUMP_PC) {
2e655fe7 1058 gen_generic_branch(dc);
72cbca10
FB		 1059 dc->npc = DYNAMIC_PC;
1060 } else if (dc->npc != DYNAMIC_PC) {
2f5680ee 1061 tcg_gen_movi_tl(cpu_npc, dc->npc);
72cbca10
FB		 1062 }
1063}
1064
20132b96 1065static inline void update_psr(DisasContext *dc)
72cbca10 1066{
cfa90513
BS		 1067 if (dc->cc_op != CC_OP_FLAGS) {
1068 dc->cc_op = CC_OP_FLAGS;
2ffd9176 1069 gen_helper_compute_psr(cpu_env);
cfa90513 1070 }
20132b96
RH		 1071}
1072
1073static inline void save_state(DisasContext *dc)
1074{
1075 tcg_gen_movi_tl(cpu_pc, dc->pc);
934da7ee 1076 save_npc(dc);
72cbca10
FB		 1077}
1078
4fbe0067
RH		 1079static void gen_exception(DisasContext *dc, int which)
1080{
1081 TCGv_i32 t;
1082
1083 save_state(dc);
1084 t = tcg_const_i32(which);
1085 gen_helper_raise_exception(cpu_env, t);
1086 tcg_temp_free_i32(t);
1087 dc->is_br = 1;
1088}
1089
35e94905
RH		 1090static void gen_check_align(TCGv addr, int mask)
1091{
1092 TCGv_i32 r_mask = tcg_const_i32(mask);
1093 gen_helper_check_align(cpu_env, addr, r_mask);
1094 tcg_temp_free_i32(r_mask);
1095}
1096
13a6dd00 1097static inline void gen_mov_pc_npc(DisasContext *dc)
0bee699e
FB		 1098{
1099 if (dc->npc == JUMP_PC) {
2e655fe7 1100 gen_generic_branch(dc);
48d5c82b 1101 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1102 dc->pc = DYNAMIC_PC;
1103 } else if (dc->npc == DYNAMIC_PC) {
48d5c82b 1104 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0bee699e
FB		 1105 dc->pc = DYNAMIC_PC;
1106 } else {
1107 dc->pc = dc->npc;
1108 }
1109}
1110
38bc628b
BS		 1111static inline void gen_op_next_insn(void)
1112{
48d5c82b
BS		 1113 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1114 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
38bc628b
BS		 1115}
1116
416fcaea
RH		 1117static void free_compare(DisasCompare *cmp)
1118{
1119 if (!cmp->g1) {
1120 tcg_temp_free(cmp->c1);
1121 }
1122 if (!cmp->g2) {
1123 tcg_temp_free(cmp->c2);
1124 }
1125}
1126
2a484ecf 1127static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
416fcaea 1128 DisasContext *dc)
19f329ad 1129{
2a484ecf 1130 static int subcc_cond[16] = {
96b5a3d3 1131 TCG_COND_NEVER,
2a484ecf
RH		 1132 TCG_COND_EQ,
1133 TCG_COND_LE,
1134 TCG_COND_LT,
1135 TCG_COND_LEU,
1136 TCG_COND_LTU,
1137 -1, /* neg */
1138 -1, /* overflow */
96b5a3d3 1139 TCG_COND_ALWAYS,
2a484ecf
RH		 1140 TCG_COND_NE,
1141 TCG_COND_GT,
1142 TCG_COND_GE,
1143 TCG_COND_GTU,
1144 TCG_COND_GEU,
1145 -1, /* pos */
1146 -1, /* no overflow */
1147 };
1148
96b5a3d3
RH		 1149 static int logic_cond[16] = {
1150 TCG_COND_NEVER,
1151 TCG_COND_EQ, /* eq: Z */
1152 TCG_COND_LE, /* le: Z | (N ^ V) -> Z | N */
1153 TCG_COND_LT, /* lt: N ^ V -> N */
1154 TCG_COND_EQ, /* leu: C | Z -> Z */
1155 TCG_COND_NEVER, /* ltu: C -> 0 */
1156 TCG_COND_LT, /* neg: N */
1157 TCG_COND_NEVER, /* vs: V -> 0 */
1158 TCG_COND_ALWAYS,
1159 TCG_COND_NE, /* ne: !Z */
1160 TCG_COND_GT, /* gt: !(Z | (N ^ V)) -> !(Z | N) */
1161 TCG_COND_GE, /* ge: !(N ^ V) -> !N */
1162 TCG_COND_NE, /* gtu: !(C | Z) -> !Z */
1163 TCG_COND_ALWAYS, /* geu: !C -> 1 */
1164 TCG_COND_GE, /* pos: !N */
1165 TCG_COND_ALWAYS, /* vc: !V -> 1 */
1166 };
1167
a7812ae4 1168 TCGv_i32 r_src;
416fcaea
RH		 1169 TCGv r_dst;
1170
3475187d 1171#ifdef TARGET_SPARC64
2a484ecf 1172 if (xcc) {
dc99a3f2 1173 r_src = cpu_xcc;
2a484ecf 1174 } else {
dc99a3f2 1175 r_src = cpu_psr;
2a484ecf 1176 }
3475187d 1177#else
dc99a3f2 1178 r_src = cpu_psr;
3475187d 1179#endif
2a484ecf 1180
8393617c 1181 switch (dc->cc_op) {
96b5a3d3
RH		 1182 case CC_OP_LOGIC:
1183 cmp->cond = logic_cond[cond];
1184 do_compare_dst_0:
1185 cmp->is_bool = false;
1186 cmp->g2 = false;
1187 cmp->c2 = tcg_const_tl(0);
1188#ifdef TARGET_SPARC64
1189 if (!xcc) {
1190 cmp->g1 = false;
1191 cmp->c1 = tcg_temp_new();
1192 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
1193 break;
1194 }
1195#endif
1196 cmp->g1 = true;
1197 cmp->c1 = cpu_cc_dst;
1198 break;
1199
2a484ecf
RH		 1200 case CC_OP_SUB:
1201 switch (cond) {
1202 case 6: /* neg */
1203 case 14: /* pos */
1204 cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
96b5a3d3 1205 goto do_compare_dst_0;
2a484ecf 1206
2a484ecf
RH		 1207 case 7: /* overflow */
1208 case 15: /* !overflow */
1209 goto do_dynamic;
1210
1211 default:
1212 cmp->cond = subcc_cond[cond];
1213 cmp->is_bool = false;
1214#ifdef TARGET_SPARC64
1215 if (!xcc) {
1216 /* Note that sign-extension works for unsigned compares as
1217 long as both operands are sign-extended. */
1218 cmp->g1 = cmp->g2 = false;
1219 cmp->c1 = tcg_temp_new();
1220 cmp->c2 = tcg_temp_new();
1221 tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
1222 tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
0fa2a066 1223 break;
2a484ecf
RH		 1224 }
1225#endif
1226 cmp->g1 = cmp->g2 = true;
1227 cmp->c1 = cpu_cc_src;
1228 cmp->c2 = cpu_cc_src2;
1229 break;
1230 }
8393617c 1231 break;
2a484ecf 1232
8393617c 1233 default:
2a484ecf 1234 do_dynamic:
2ffd9176 1235 gen_helper_compute_psr(cpu_env);
8393617c 1236 dc->cc_op = CC_OP_FLAGS;
2a484ecf
RH		 1237 /* FALLTHRU */
1238
1239 case CC_OP_FLAGS:
1240 /* We're going to generate a boolean result. */
1241 cmp->cond = TCG_COND_NE;
1242 cmp->is_bool = true;
1243 cmp->g1 = cmp->g2 = false;
1244 cmp->c1 = r_dst = tcg_temp_new();
1245 cmp->c2 = tcg_const_tl(0);
1246
1247 switch (cond) {
1248 case 0x0:
1249 gen_op_eval_bn(r_dst);
1250 break;
1251 case 0x1:
1252 gen_op_eval_be(r_dst, r_src);
1253 break;
1254 case 0x2:
1255 gen_op_eval_ble(r_dst, r_src);
1256 break;
1257 case 0x3:
1258 gen_op_eval_bl(r_dst, r_src);
1259 break;
1260 case 0x4:
1261 gen_op_eval_bleu(r_dst, r_src);
1262 break;
1263 case 0x5:
1264 gen_op_eval_bcs(r_dst, r_src);
1265 break;
1266 case 0x6:
1267 gen_op_eval_bneg(r_dst, r_src);
1268 break;
1269 case 0x7:
1270 gen_op_eval_bvs(r_dst, r_src);
1271 break;
1272 case 0x8:
1273 gen_op_eval_ba(r_dst);
1274 break;
1275 case 0x9:
1276 gen_op_eval_bne(r_dst, r_src);
1277 break;
1278 case 0xa:
1279 gen_op_eval_bg(r_dst, r_src);
1280 break;
1281 case 0xb:
1282 gen_op_eval_bge(r_dst, r_src);
1283 break;
1284 case 0xc:
1285 gen_op_eval_bgu(r_dst, r_src);
1286 break;
1287 case 0xd:
1288 gen_op_eval_bcc(r_dst, r_src);
1289 break;
1290 case 0xe:
1291 gen_op_eval_bpos(r_dst, r_src);
1292 break;
1293 case 0xf:
1294 gen_op_eval_bvc(r_dst, r_src);
1295 break;
1296 }
19f329ad
BS		 1297 break;
1298 }
1299}
7a3f1944 1300
416fcaea 1301static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond)
e8af50a3 1302{
19f329ad 1303 unsigned int offset;
416fcaea
RH		 1304 TCGv r_dst;
1305
1306 /* For now we still generate a straight boolean result. */
1307 cmp->cond = TCG_COND_NE;
1308 cmp->is_bool = true;
1309 cmp->g1 = cmp->g2 = false;
1310 cmp->c1 = r_dst = tcg_temp_new();
1311 cmp->c2 = tcg_const_tl(0);
19f329ad 1312
19f329ad
BS		 1313 switch (cc) {
1314 default:
1315 case 0x0:
1316 offset = 0;
1317 break;
1318 case 0x1:
1319 offset = 32 - 10;
1320 break;
1321 case 0x2:
1322 offset = 34 - 10;
1323 break;
1324 case 0x3:
1325 offset = 36 - 10;
1326 break;
1327 }
1328
1329 switch (cond) {
1330 case 0x0:
1331 gen_op_eval_bn(r_dst);
1332 break;
1333 case 0x1:
87e92502 1334 gen_op_eval_fbne(r_dst, cpu_fsr, offset);
19f329ad
BS		 1335 break;
1336 case 0x2:
87e92502 1337 gen_op_eval_fblg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1338 break;
1339 case 0x3:
87e92502 1340 gen_op_eval_fbul(r_dst, cpu_fsr, offset);
19f329ad
BS		 1341 break;
1342 case 0x4:
87e92502 1343 gen_op_eval_fbl(r_dst, cpu_fsr, offset);
19f329ad
BS		 1344 break;
1345 case 0x5:
87e92502 1346 gen_op_eval_fbug(r_dst, cpu_fsr, offset);
19f329ad
BS		 1347 break;
1348 case 0x6:
87e92502 1349 gen_op_eval_fbg(r_dst, cpu_fsr, offset);
19f329ad
BS		 1350 break;
1351 case 0x7:
87e92502 1352 gen_op_eval_fbu(r_dst, cpu_fsr, offset);
19f329ad
BS		 1353 break;
1354 case 0x8:
1355 gen_op_eval_ba(r_dst);
1356 break;
1357 case 0x9:
87e92502 1358 gen_op_eval_fbe(r_dst, cpu_fsr, offset);
19f329ad
BS		 1359 break;
1360 case 0xa:
87e92502 1361 gen_op_eval_fbue(r_dst, cpu_fsr, offset);
19f329ad
BS		 1362 break;
1363 case 0xb:
87e92502 1364 gen_op_eval_fbge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1365 break;
1366 case 0xc:
87e92502 1367 gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
19f329ad
BS		 1368 break;
1369 case 0xd:
87e92502 1370 gen_op_eval_fble(r_dst, cpu_fsr, offset);
19f329ad
BS		 1371 break;
1372 case 0xe:
87e92502 1373 gen_op_eval_fbule(r_dst, cpu_fsr, offset);
19f329ad
BS		 1374 break;
1375 case 0xf:
87e92502 1376 gen_op_eval_fbo(r_dst, cpu_fsr, offset);
19f329ad
BS		 1377 break;
1378 }
e8af50a3 1379}
00f219bf 1380
416fcaea
RH		 1381static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond,
1382 DisasContext *dc)
1383{
1384 DisasCompare cmp;
1385 gen_compare(&cmp, cc, cond, dc);
1386
1387 /* The interface is to return a boolean in r_dst. */
1388 if (cmp.is_bool) {
1389 tcg_gen_mov_tl(r_dst, cmp.c1);
1390 } else {
1391 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1392 }
1393
1394 free_compare(&cmp);
1395}
1396
1397static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1398{
1399 DisasCompare cmp;
1400 gen_fcompare(&cmp, cc, cond);
1401
1402 /* The interface is to return a boolean in r_dst. */
1403 if (cmp.is_bool) {
1404 tcg_gen_mov_tl(r_dst, cmp.c1);
1405 } else {
1406 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1407 }
1408
1409 free_compare(&cmp);
1410}
1411
19f329ad 1412#ifdef TARGET_SPARC64
00f219bf
BS		 1413// Inverted logic
1414static const int gen_tcg_cond_reg[8] = {
1415 -1,
1416 TCG_COND_NE,
1417 TCG_COND_GT,
1418 TCG_COND_GE,
1419 -1,
1420 TCG_COND_EQ,
1421 TCG_COND_LE,
1422 TCG_COND_LT,
1423};
19f329ad 1424
416fcaea
RH		 1425static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
1426{
1427 cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
1428 cmp->is_bool = false;
1429 cmp->g1 = true;
1430 cmp->g2 = false;
1431 cmp->c1 = r_src;
1432 cmp->c2 = tcg_const_tl(0);
1433}
1434
4af984a7 1435static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
19f329ad 1436{
416fcaea
RH		 1437 DisasCompare cmp;
1438 gen_compare_reg(&cmp, cond, r_src);
19f329ad 1439
416fcaea
RH		 1440 /* The interface is to return a boolean in r_dst. */
1441 tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
1442
1443 free_compare(&cmp);
19f329ad 1444}
3475187d 1445#endif
cf495bcf 1446
d4a288ef 1447static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
7a3f1944 1448{
cf495bcf 1449 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b 1450 target_ulong target = dc->pc + offset;
5fafdf24 1451
22036a49
AT		 1452#ifdef TARGET_SPARC64
1453 if (unlikely(AM_CHECK(dc))) {
1454 target &= 0xffffffffULL;
1455 }
1456#endif
cf495bcf 1457 if (cond == 0x0) {
0f8a249a
BS		 1458 /* unconditional not taken */
1459 if (a) {
1460 dc->pc = dc->npc + 4;
1461 dc->npc = dc->pc + 4;
1462 } else {
1463 dc->pc = dc->npc;
1464 dc->npc = dc->pc + 4;
1465 }
cf495bcf 1466 } else if (cond == 0x8) {
0f8a249a
BS		 1467 /* unconditional taken */
1468 if (a) {
1469 dc->pc = target;
1470 dc->npc = dc->pc + 4;
1471 } else {
1472 dc->pc = dc->npc;
1473 dc->npc = target;
c27e2752 1474 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1475 }
cf495bcf 1476 } else {
dee8913c 1477 flush_cond(dc);
d4a288ef 1478 gen_cond(cpu_cond, cc, cond, dc);
0f8a249a 1479 if (a) {
bfa31b76 1480 gen_branch_a(dc, target);
0f8a249a 1481 } else {
2bf2e019 1482 gen_branch_n(dc, target);
0f8a249a 1483 }
cf495bcf 1484 }
7a3f1944
FB		 1485}
1486
d4a288ef 1487static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
e8af50a3
FB		 1488{
1489 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
af7bf89b
FB		 1490 target_ulong target = dc->pc + offset;
1491
22036a49
AT		 1492#ifdef TARGET_SPARC64
1493 if (unlikely(AM_CHECK(dc))) {
1494 target &= 0xffffffffULL;
1495 }
1496#endif
e8af50a3 1497 if (cond == 0x0) {
0f8a249a
BS		 1498 /* unconditional not taken */
1499 if (a) {
1500 dc->pc = dc->npc + 4;
1501 dc->npc = dc->pc + 4;
1502 } else {
1503 dc->pc = dc->npc;
1504 dc->npc = dc->pc + 4;
1505 }
e8af50a3 1506 } else if (cond == 0x8) {
0f8a249a
BS		 1507 /* unconditional taken */
1508 if (a) {
1509 dc->pc = target;
1510 dc->npc = dc->pc + 4;
1511 } else {
1512 dc->pc = dc->npc;
1513 dc->npc = target;
c27e2752 1514 tcg_gen_mov_tl(cpu_pc, cpu_npc);
0f8a249a 1515 }
e8af50a3 1516 } else {
dee8913c 1517 flush_cond(dc);
d4a288ef 1518 gen_fcond(cpu_cond, cc, cond);
0f8a249a 1519 if (a) {
bfa31b76 1520 gen_branch_a(dc, target);
0f8a249a 1521 } else {
2bf2e019 1522 gen_branch_n(dc, target);
0f8a249a 1523 }
e8af50a3
FB		 1524 }
1525}
1526
3475187d 1527#ifdef TARGET_SPARC64
4af984a7 1528static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
d4a288ef 1529 TCGv r_reg)
7a3f1944 1530{
3475187d
FB		 1531 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1532 target_ulong target = dc->pc + offset;
1533
22036a49
AT		 1534 if (unlikely(AM_CHECK(dc))) {
1535 target &= 0xffffffffULL;
1536 }
dee8913c 1537 flush_cond(dc);
d4a288ef 1538 gen_cond_reg(cpu_cond, cond, r_reg);
3475187d 1539 if (a) {
bfa31b76 1540 gen_branch_a(dc, target);
3475187d 1541 } else {
2bf2e019 1542 gen_branch_n(dc, target);
3475187d 1543 }
7a3f1944
FB		 1544}
1545
a7812ae4 1546static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1547{
714547bb
BS		 1548 switch (fccno) {
1549 case 0:
7385aed2 1550 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1551 break;
1552 case 1:
7385aed2 1553 gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1554 break;
1555 case 2:
7385aed2 1556 gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1557 break;
1558 case 3:
7385aed2 1559 gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1560 break;
1561 }
7e8c2b6c
BS		 1562}
1563
03fb8cfc 1564static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1565{
a7812ae4
PB		 1566 switch (fccno) {
1567 case 0:
7385aed2 1568 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1569 break;
1570 case 1:
7385aed2 1571 gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1572 break;
1573 case 2:
7385aed2 1574 gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1575 break;
1576 case 3:
7385aed2 1577 gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1578 break;
1579 }
7e8c2b6c
BS		 1580}
1581
7e8c2b6c
BS		 1582static inline void gen_op_fcmpq(int fccno)
1583{
a7812ae4
PB		 1584 switch (fccno) {
1585 case 0:
7385aed2 1586 gen_helper_fcmpq(cpu_fsr, cpu_env);
a7812ae4
PB		 1587 break;
1588 case 1:
7385aed2 1589 gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1590 break;
1591 case 2:
7385aed2 1592 gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1593 break;
1594 case 3:
7385aed2 1595 gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1596 break;
1597 }
7e8c2b6c 1598}
7e8c2b6c 1599
a7812ae4 1600static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
7e8c2b6c 1601{
714547bb
BS		 1602 switch (fccno) {
1603 case 0:
7385aed2 1604 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1605 break;
1606 case 1:
7385aed2 1607 gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1608 break;
1609 case 2:
7385aed2 1610 gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1611 break;
1612 case 3:
7385aed2 1613 gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
714547bb
BS		 1614 break;
1615 }
7e8c2b6c
BS		 1616}
1617
03fb8cfc 1618static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1619{
a7812ae4
PB		 1620 switch (fccno) {
1621 case 0:
7385aed2 1622 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1623 break;
1624 case 1:
7385aed2 1625 gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1626 break;
1627 case 2:
7385aed2 1628 gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1629 break;
1630 case 3:
7385aed2 1631 gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2);
a7812ae4
PB		 1632 break;
1633 }
7e8c2b6c
BS		 1634}
1635
7e8c2b6c
BS		 1636static inline void gen_op_fcmpeq(int fccno)
1637{
a7812ae4
PB		 1638 switch (fccno) {
1639 case 0:
7385aed2 1640 gen_helper_fcmpeq(cpu_fsr, cpu_env);
a7812ae4
PB		 1641 break;
1642 case 1:
7385aed2 1643 gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env);
a7812ae4
PB		 1644 break;
1645 case 2:
7385aed2 1646 gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env);
a7812ae4
PB		 1647 break;
1648 case 3:
7385aed2 1649 gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env);
a7812ae4
PB		 1650 break;
1651 }
7e8c2b6c 1652}
7e8c2b6c
BS		 1653
1654#else
1655
714547bb 1656static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1657{
7385aed2 1658 gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1659}
1660
03fb8cfc 1661static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1662{
7385aed2 1663 gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1664}
1665
7e8c2b6c
BS		 1666static inline void gen_op_fcmpq(int fccno)
1667{
7385aed2 1668 gen_helper_fcmpq(cpu_fsr, cpu_env);
7e8c2b6c 1669}
7e8c2b6c 1670
714547bb 1671static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
7e8c2b6c 1672{
7385aed2 1673 gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1674}
1675
03fb8cfc 1676static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
7e8c2b6c 1677{
7385aed2 1678 gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2);
7e8c2b6c
BS		 1679}
1680
7e8c2b6c
BS		 1681static inline void gen_op_fcmpeq(int fccno)
1682{
7385aed2 1683 gen_helper_fcmpeq(cpu_fsr, cpu_env);
7e8c2b6c
BS		 1684}
1685#endif
1686
4fbe0067 1687static void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
134d77a1 1688{
47ad35f1 1689 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
87e92502 1690 tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
4fbe0067 1691 gen_exception(dc, TT_FP_EXCP);
134d77a1
BS		 1692}
1693
5b12f1e8 1694static int gen_trap_ifnofpu(DisasContext *dc)
a80dde08
FB		 1695{
1696#if !defined(CONFIG_USER_ONLY)
1697 if (!dc->fpu_enabled) {
4fbe0067 1698 gen_exception(dc, TT_NFPU_INSN);
a80dde08
FB		 1699 return 1;
1700 }
1701#endif
1702 return 0;
1703}
1704
7e8c2b6c
BS		 1705static inline void gen_op_clear_ieee_excp_and_FTT(void)
1706{
47ad35f1 1707 tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
7e8c2b6c
BS		 1708}
1709
61f17f6e
RH		 1710static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
1711 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32))
1712{
1713 TCGv_i32 dst, src;
1714
61f17f6e 1715 src = gen_load_fpr_F(dc, rs);
ba5f5179 1716 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1717
1718 gen(dst, cpu_env, src);
7385aed2 1719 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1720
61f17f6e
RH		 1721 gen_store_fpr_F(dc, rd, dst);
1722}
1723
1724static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
1725 void (*gen)(TCGv_i32, TCGv_i32))
1726{
1727 TCGv_i32 dst, src;
1728
1729 src = gen_load_fpr_F(dc, rs);
ba5f5179 1730 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1731
1732 gen(dst, src);
1733
1734 gen_store_fpr_F(dc, rd, dst);
1735}
1736
1737static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1738 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
1739{
1740 TCGv_i32 dst, src1, src2;
1741
61f17f6e
RH		 1742 src1 = gen_load_fpr_F(dc, rs1);
1743 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1744 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1745
1746 gen(dst, cpu_env, src1, src2);
7385aed2 1747 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1748
61f17f6e
RH		 1749 gen_store_fpr_F(dc, rd, dst);
1750}
1751
1752#ifdef TARGET_SPARC64
1753static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
1754 void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
1755{
1756 TCGv_i32 dst, src1, src2;
1757
1758 src1 = gen_load_fpr_F(dc, rs1);
1759 src2 = gen_load_fpr_F(dc, rs2);
ba5f5179 1760 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1761
1762 gen(dst, src1, src2);
1763
1764 gen_store_fpr_F(dc, rd, dst);
1765}
1766#endif
1767
1768static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
1769 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64))
1770{
1771 TCGv_i64 dst, src;
1772
61f17f6e 1773 src = gen_load_fpr_D(dc, rs);
3886b8a3 1774 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1775
1776 gen(dst, cpu_env, src);
7385aed2 1777 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1778
61f17f6e
RH		 1779 gen_store_fpr_D(dc, rd, dst);
1780}
1781
1782#ifdef TARGET_SPARC64
1783static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
1784 void (*gen)(TCGv_i64, TCGv_i64))
1785{
1786 TCGv_i64 dst, src;
1787
1788 src = gen_load_fpr_D(dc, rs);
3886b8a3 1789 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1790
1791 gen(dst, src);
1792
1793 gen_store_fpr_D(dc, rd, dst);
1794}
1795#endif
1796
1797static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1798 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
1799{
1800 TCGv_i64 dst, src1, src2;
1801
61f17f6e
RH		 1802 src1 = gen_load_fpr_D(dc, rs1);
1803 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1804 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1805
1806 gen(dst, cpu_env, src1, src2);
7385aed2 1807 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1808
61f17f6e
RH		 1809 gen_store_fpr_D(dc, rd, dst);
1810}
1811
1812#ifdef TARGET_SPARC64
1813static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1814 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
1815{
1816 TCGv_i64 dst, src1, src2;
1817
1818 src1 = gen_load_fpr_D(dc, rs1);
1819 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1820 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1821
1822 gen(dst, src1, src2);
1823
1824 gen_store_fpr_D(dc, rd, dst);
1825}
f888300b 1826
2dedf314
RH		 1827static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
1828 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1829{
1830 TCGv_i64 dst, src1, src2;
1831
1832 src1 = gen_load_fpr_D(dc, rs1);
1833 src2 = gen_load_fpr_D(dc, rs2);
3886b8a3 1834 dst = gen_dest_fpr_D(dc, rd);
2dedf314
RH		 1835
1836 gen(dst, cpu_gsr, src1, src2);
1837
1838 gen_store_fpr_D(dc, rd, dst);
1839}
1840
f888300b
RH		 1841static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
1842 void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
1843{
1844 TCGv_i64 dst, src0, src1, src2;
1845
1846 src1 = gen_load_fpr_D(dc, rs1);
1847 src2 = gen_load_fpr_D(dc, rs2);
1848 src0 = gen_load_fpr_D(dc, rd);
3886b8a3 1849 dst = gen_dest_fpr_D(dc, rd);
f888300b
RH		 1850
1851 gen(dst, src0, src1, src2);
1852
1853 gen_store_fpr_D(dc, rd, dst);
1854}
61f17f6e
RH		 1855#endif
1856
1857static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
1858 void (*gen)(TCGv_ptr))
1859{
61f17f6e
RH		 1860 gen_op_load_fpr_QT1(QFPREG(rs));
1861
1862 gen(cpu_env);
7385aed2 1863 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1864
61f17f6e 1865 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1866 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1867}
1868
1869#ifdef TARGET_SPARC64
1870static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
1871 void (*gen)(TCGv_ptr))
1872{
1873 gen_op_load_fpr_QT1(QFPREG(rs));
1874
1875 gen(cpu_env);
1876
1877 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1878 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1879}
1880#endif
1881
1882static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
1883 void (*gen)(TCGv_ptr))
1884{
61f17f6e
RH		 1885 gen_op_load_fpr_QT0(QFPREG(rs1));
1886 gen_op_load_fpr_QT1(QFPREG(rs2));
1887
1888 gen(cpu_env);
7385aed2 1889 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1890
61f17f6e 1891 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1892 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1893}
1894
1895static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
1896 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
1897{
1898 TCGv_i64 dst;
1899 TCGv_i32 src1, src2;
1900
61f17f6e
RH		 1901 src1 = gen_load_fpr_F(dc, rs1);
1902 src2 = gen_load_fpr_F(dc, rs2);
3886b8a3 1903 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1904
1905 gen(dst, cpu_env, src1, src2);
7385aed2 1906 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1907
61f17f6e
RH		 1908 gen_store_fpr_D(dc, rd, dst);
1909}
1910
1911static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
1912 void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
1913{
1914 TCGv_i64 src1, src2;
1915
61f17f6e
RH		 1916 src1 = gen_load_fpr_D(dc, rs1);
1917 src2 = gen_load_fpr_D(dc, rs2);
1918
1919 gen(cpu_env, src1, src2);
7385aed2 1920 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1921
61f17f6e 1922 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 1923 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 1924}
1925
1926#ifdef TARGET_SPARC64
1927static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
1928 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1929{
1930 TCGv_i64 dst;
1931 TCGv_i32 src;
1932
61f17f6e 1933 src = gen_load_fpr_F(dc, rs);
3886b8a3 1934 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1935
1936 gen(dst, cpu_env, src);
7385aed2 1937 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1938
61f17f6e
RH		 1939 gen_store_fpr_D(dc, rd, dst);
1940}
1941#endif
1942
1943static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
1944 void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
1945{
1946 TCGv_i64 dst;
1947 TCGv_i32 src;
1948
1949 src = gen_load_fpr_F(dc, rs);
3886b8a3 1950 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1951
1952 gen(dst, cpu_env, src);
1953
1954 gen_store_fpr_D(dc, rd, dst);
1955}
1956
1957static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
1958 void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64))
1959{
1960 TCGv_i32 dst;
1961 TCGv_i64 src;
1962
61f17f6e 1963 src = gen_load_fpr_D(dc, rs);
ba5f5179 1964 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1965
1966 gen(dst, cpu_env, src);
7385aed2 1967 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1968
61f17f6e
RH		 1969 gen_store_fpr_F(dc, rd, dst);
1970}
1971
1972static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
1973 void (*gen)(TCGv_i32, TCGv_ptr))
1974{
1975 TCGv_i32 dst;
1976
61f17f6e 1977 gen_op_load_fpr_QT1(QFPREG(rs));
ba5f5179 1978 dst = gen_dest_fpr_F(dc);
61f17f6e
RH		 1979
1980 gen(dst, cpu_env);
7385aed2 1981 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1982
61f17f6e
RH		 1983 gen_store_fpr_F(dc, rd, dst);
1984}
1985
1986static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
1987 void (*gen)(TCGv_i64, TCGv_ptr))
1988{
1989 TCGv_i64 dst;
1990
61f17f6e 1991 gen_op_load_fpr_QT1(QFPREG(rs));
3886b8a3 1992 dst = gen_dest_fpr_D(dc, rd);
61f17f6e
RH		 1993
1994 gen(dst, cpu_env);
7385aed2 1995 gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
61f17f6e 1996
61f17f6e
RH		 1997 gen_store_fpr_D(dc, rd, dst);
1998}
1999
2000static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
2001 void (*gen)(TCGv_ptr, TCGv_i32))
2002{
2003 TCGv_i32 src;
2004
2005 src = gen_load_fpr_F(dc, rs);
2006
2007 gen(cpu_env, src);
2008
2009 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2010 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2011}
2012
2013static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
2014 void (*gen)(TCGv_ptr, TCGv_i64))
2015{
2016 TCGv_i64 src;
2017
2018 src = gen_load_fpr_D(dc, rs);
2019
2020 gen(cpu_env, src);
2021
2022 gen_op_store_QT0_fpr(QFPREG(rd));
f9c816c0 2023 gen_update_fprs_dirty(dc, QFPREG(rd));
61f17f6e
RH		 2024}
2025
4fb554bc
RH		 2026static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
2027 TCGv addr, int mmu_idx, TCGMemOp memop)
2028{
4fb554bc 2029 gen_address_mask(dc, addr);
da1bcae6 2030 tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop);
4fb554bc
RH		 2031}
2032
fbb4bbb6
RH		 2033static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
2034{
da1bcae6 2035 TCGv m1 = tcg_const_tl(0xff);
fbb4bbb6 2036 gen_address_mask(dc, addr);
da1bcae6
RH		 2037 tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
2038 tcg_temp_free(m1);
fbb4bbb6
RH		 2039}
2040
1a2fb1c0 2041/* asi moves */
22e70060 2042#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
7ec1e5ea
RH		 2043typedef enum {
2044 GET_ASI_HELPER,
2045 GET_ASI_EXCP,
f0913be0 2046 GET_ASI_DIRECT,
e4dc0052 2047 GET_ASI_DTWINX,
ca5ce572
RH		 2048 GET_ASI_BLOCK,
2049 GET_ASI_SHORT,
34810610
RH		 2050 GET_ASI_BCOPY,
2051 GET_ASI_BFILL,
7ec1e5ea
RH		 2052} ASIType;
2053
2054typedef struct {
2055 ASIType type;
a6d567e5 2056 int asi;
f0913be0
RH		 2057 int mem_idx;
2058 TCGMemOp memop;
7ec1e5ea 2059} DisasASI;
1a2fb1c0 2060
f0913be0 2061static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
7ec1e5ea
RH		 2062{
2063 int asi = GET_FIELD(insn, 19, 26);
2064 ASIType type = GET_ASI_HELPER;
f0913be0 2065 int mem_idx = dc->mem_idx;
7ec1e5ea
RH		 2066
2067#ifndef TARGET_SPARC64
2068 /* Before v9, all asis are immediate and privileged. */
1a2fb1c0 2069 if (IS_IMM) {
22e70060 2070 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2071 type = GET_ASI_EXCP;
2072 } else if (supervisor(dc)
2073 /* Note that LEON accepts ASI_USERDATA in user mode, for
2074 use with CASA. Also note that previous versions of
0cc1f4bf
RH		 2075 QEMU allowed (and old versions of gcc emitted) ASI_P
2076 for LEON, which is incorrect. */
2077 || (asi == ASI_USERDATA
7ec1e5ea 2078 && (dc->def->features & CPU_FEATURE_CASA))) {
f0913be0
RH		 2079 switch (asi) {
2080 case ASI_USERDATA: /* User data access */
2081 mem_idx = MMU_USER_IDX;
2082 type = GET_ASI_DIRECT;
2083 break;
2084 case ASI_KERNELDATA: /* Supervisor data access */
2085 mem_idx = MMU_KERNEL_IDX;
2086 type = GET_ASI_DIRECT;
2087 break;
7f87c905
RH		 2088 case ASI_M_BYPASS: /* MMU passthrough */
2089 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
2090 mem_idx = MMU_PHYS_IDX;
2091 type = GET_ASI_DIRECT;
2092 break;
34810610
RH		 2093 case ASI_M_BCOPY: /* Block copy, sta access */
2094 mem_idx = MMU_KERNEL_IDX;
2095 type = GET_ASI_BCOPY;
2096 break;
2097 case ASI_M_BFILL: /* Block fill, stda access */
2098 mem_idx = MMU_KERNEL_IDX;
2099 type = GET_ASI_BFILL;
2100 break;
f0913be0 2101 }
1a2fb1c0 2102 } else {
7ec1e5ea
RH		 2103 gen_exception(dc, TT_PRIV_INSN);
2104 type = GET_ASI_EXCP;
2105 }
2106#else
2107 if (IS_IMM) {
2108 asi = dc->asi;
1a2fb1c0 2109 }
f0913be0
RH		 2110 /* With v9, all asis below 0x80 are privileged. */
2111 /* ??? We ought to check cpu_has_hypervisor, but we didn't copy
2112 down that bit into DisasContext. For the moment that's ok,
2113 since the direct implementations below doesn't have any ASIs
2114 in the restricted [0x30, 0x7f] range, and the check will be
2115 done properly in the helper. */
2116 if (!supervisor(dc) && asi < 0x80) {
2117 gen_exception(dc, TT_PRIV_ACT);
2118 type = GET_ASI_EXCP;
2119 } else {
2120 switch (asi) {
7f87c905
RH		 2121 case ASI_REAL: /* Bypass */
2122 case ASI_REAL_IO: /* Bypass, non-cacheable */
2123 case ASI_REAL_L: /* Bypass LE */
2124 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
2125 case ASI_TWINX_REAL: /* Real address, twinx */
2126 case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
34a6e13d
RH		 2127 case ASI_QUAD_LDD_PHYS:
2128 case ASI_QUAD_LDD_PHYS_L:
7f87c905
RH		 2129 mem_idx = MMU_PHYS_IDX;
2130 break;
f0913be0
RH		 2131 case ASI_N: /* Nucleus */
2132 case ASI_NL: /* Nucleus LE */
e4dc0052
RH		 2133 case ASI_TWINX_N:
2134 case ASI_TWINX_NL:
34a6e13d
RH		 2135 case ASI_NUCLEUS_QUAD_LDD:
2136 case ASI_NUCLEUS_QUAD_LDD_L:
9a10756d 2137 if (hypervisor(dc)) {
84f8f587 2138 mem_idx = MMU_PHYS_IDX;
9a10756d
AT		 2139 } else {
2140 mem_idx = MMU_NUCLEUS_IDX;
2141 }
f0913be0
RH		 2142 break;
2143 case ASI_AIUP: /* As if user primary */
2144 case ASI_AIUPL: /* As if user primary LE */
e4dc0052
RH		 2145 case ASI_TWINX_AIUP:
2146 case ASI_TWINX_AIUP_L:
ca5ce572
RH		 2147 case ASI_BLK_AIUP_4V:
2148 case ASI_BLK_AIUP_L_4V:
2149 case ASI_BLK_AIUP:
2150 case ASI_BLK_AIUPL:
f0913be0
RH		 2151 mem_idx = MMU_USER_IDX;
2152 break;
2153 case ASI_AIUS: /* As if user secondary */
2154 case ASI_AIUSL: /* As if user secondary LE */
e4dc0052
RH		 2155 case ASI_TWINX_AIUS:
2156 case ASI_TWINX_AIUS_L:
ca5ce572
RH		 2157 case ASI_BLK_AIUS_4V:
2158 case ASI_BLK_AIUS_L_4V:
2159 case ASI_BLK_AIUS:
2160 case ASI_BLK_AIUSL:
f0913be0
RH		 2161 mem_idx = MMU_USER_SECONDARY_IDX;
2162 break;
2163 case ASI_S: /* Secondary */
2164 case ASI_SL: /* Secondary LE */
e4dc0052
RH		 2165 case ASI_TWINX_S:
2166 case ASI_TWINX_SL:
ca5ce572
RH		 2167 case ASI_BLK_COMMIT_S:
2168 case ASI_BLK_S:
2169 case ASI_BLK_SL:
2170 case ASI_FL8_S:
2171 case ASI_FL8_SL:
2172 case ASI_FL16_S:
2173 case ASI_FL16_SL:
f0913be0
RH		 2174 if (mem_idx == MMU_USER_IDX) {
2175 mem_idx = MMU_USER_SECONDARY_IDX;
2176 } else if (mem_idx == MMU_KERNEL_IDX) {
2177 mem_idx = MMU_KERNEL_SECONDARY_IDX;
2178 }
2179 break;
2180 case ASI_P: /* Primary */
2181 case ASI_PL: /* Primary LE */
e4dc0052
RH		 2182 case ASI_TWINX_P:
2183 case ASI_TWINX_PL:
ca5ce572
RH		 2184 case ASI_BLK_COMMIT_P:
2185 case ASI_BLK_P:
2186 case ASI_BLK_PL:
2187 case ASI_FL8_P:
2188 case ASI_FL8_PL:
2189 case ASI_FL16_P:
2190 case ASI_FL16_PL:
f0913be0
RH		 2191 break;
2192 }
2193 switch (asi) {
7f87c905
RH		 2194 case ASI_REAL:
2195 case ASI_REAL_IO:
2196 case ASI_REAL_L:
2197 case ASI_REAL_IO_L:
f0913be0
RH		 2198 case ASI_N:
2199 case ASI_NL:
2200 case ASI_AIUP:
2201 case ASI_AIUPL:
2202 case ASI_AIUS:
2203 case ASI_AIUSL:
2204 case ASI_S:
2205 case ASI_SL:
2206 case ASI_P:
2207 case ASI_PL:
2208 type = GET_ASI_DIRECT;
2209 break;
7f87c905
RH		 2210 case ASI_TWINX_REAL:
2211 case ASI_TWINX_REAL_L:
e4dc0052
RH		 2212 case ASI_TWINX_N:
2213 case ASI_TWINX_NL:
2214 case ASI_TWINX_AIUP:
2215 case ASI_TWINX_AIUP_L:
2216 case ASI_TWINX_AIUS:
2217 case ASI_TWINX_AIUS_L:
2218 case ASI_TWINX_P:
2219 case ASI_TWINX_PL:
2220 case ASI_TWINX_S:
2221 case ASI_TWINX_SL:
34a6e13d
RH		 2222 case ASI_QUAD_LDD_PHYS:
2223 case ASI_QUAD_LDD_PHYS_L:
2224 case ASI_NUCLEUS_QUAD_LDD:
2225 case ASI_NUCLEUS_QUAD_LDD_L:
e4dc0052
RH		 2226 type = GET_ASI_DTWINX;
2227 break;
ca5ce572
RH		 2228 case ASI_BLK_COMMIT_P:
2229 case ASI_BLK_COMMIT_S:
2230 case ASI_BLK_AIUP_4V:
2231 case ASI_BLK_AIUP_L_4V:
2232 case ASI_BLK_AIUP:
2233 case ASI_BLK_AIUPL:
2234 case ASI_BLK_AIUS_4V:
2235 case ASI_BLK_AIUS_L_4V:
2236 case ASI_BLK_AIUS:
2237 case ASI_BLK_AIUSL:
2238 case ASI_BLK_S:
2239 case ASI_BLK_SL:
2240 case ASI_BLK_P:
2241 case ASI_BLK_PL:
2242 type = GET_ASI_BLOCK;
2243 break;
2244 case ASI_FL8_S:
2245 case ASI_FL8_SL:
2246 case ASI_FL8_P:
2247 case ASI_FL8_PL:
2248 memop = MO_UB;
2249 type = GET_ASI_SHORT;
2250 break;
2251 case ASI_FL16_S:
2252 case ASI_FL16_SL:
2253 case ASI_FL16_P:
2254 case ASI_FL16_PL:
2255 memop = MO_TEUW;
2256 type = GET_ASI_SHORT;
2257 break;
f0913be0
RH		 2258 }
2259 /* The little-endian asis all have bit 3 set. */
2260 if (asi & 8) {
2261 memop ^= MO_BSWAP;
2262 }
2263 }
7ec1e5ea
RH		 2264#endif
2265
f0913be0 2266 return (DisasASI){ type, asi, mem_idx, memop };
0425bee5
BS		 2267}
2268
22e70060 2269static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
1d65b0f5 2270 int insn, TCGMemOp memop)
0425bee5 2271{
f0913be0 2272 DisasASI da = get_asi(dc, insn, memop);
0425bee5 2273
7ec1e5ea
RH		 2274 switch (da.type) {
2275 case GET_ASI_EXCP:
2276 break;
e4dc0052
RH		 2277 case GET_ASI_DTWINX: /* Reserved for ldda. */
2278 gen_exception(dc, TT_ILL_INSN);
2279 break;
f0913be0
RH		 2280 case GET_ASI_DIRECT:
2281 gen_address_mask(dc, addr);
2282 tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop);
2283 break;
7ec1e5ea
RH		 2284 default:
2285 {
2286 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2287 TCGv_i32 r_mop = tcg_const_i32(memop);
7ec1e5ea
RH		 2288
2289 save_state(dc);
22e70060 2290#ifdef TARGET_SPARC64
6850811e 2291 gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop);
22e70060 2292#else
7ec1e5ea
RH		 2293 {
2294 TCGv_i64 t64 = tcg_temp_new_i64();
6850811e 2295 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
7ec1e5ea
RH		 2296 tcg_gen_trunc_i64_tl(dst, t64);
2297 tcg_temp_free_i64(t64);
2298 }
22e70060 2299#endif
6850811e 2300 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2301 tcg_temp_free_i32(r_asi);
2302 }
2303 break;
2304 }
1a2fb1c0
BS		 2305}
2306
22e70060 2307static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
1d65b0f5 2308 int insn, TCGMemOp memop)
1a2fb1c0 2309{
f0913be0 2310 DisasASI da = get_asi(dc, insn, memop);
1a2fb1c0 2311
7ec1e5ea
RH		 2312 switch (da.type) {
2313 case GET_ASI_EXCP:
2314 break;
e4dc0052 2315 case GET_ASI_DTWINX: /* Reserved for stda. */
3390537b 2316#ifndef TARGET_SPARC64
e4dc0052
RH		 2317 gen_exception(dc, TT_ILL_INSN);
2318 break;
3390537b
AT		 2319#else
2320 if (!(dc->def->features & CPU_FEATURE_HYPV)) {
2321 /* Pre OpenSPARC CPUs don't have these */
2322 gen_exception(dc, TT_ILL_INSN);
2323 return;
2324 }
2325 /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions
2326 * are ST_BLKINIT_ ASIs */
2327 /* fall through */
2328#endif
f0913be0
RH		 2329 case GET_ASI_DIRECT:
2330 gen_address_mask(dc, addr);
2331 tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);
2332 break;
34810610
RH		 2333#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
2334 case GET_ASI_BCOPY:
2335 /* Copy 32 bytes from the address in SRC to ADDR. */
2336 /* ??? The original qemu code suggests 4-byte alignment, dropping
2337 the low bits, but the only place I can see this used is in the
2338 Linux kernel with 32 byte alignment, which would make more sense
2339 as a cacheline-style operation. */
2340 {
2341 TCGv saddr = tcg_temp_new();
2342 TCGv daddr = tcg_temp_new();
2343 TCGv four = tcg_const_tl(4);
2344 TCGv_i32 tmp = tcg_temp_new_i32();
2345 int i;
2346
2347 tcg_gen_andi_tl(saddr, src, -4);
2348 tcg_gen_andi_tl(daddr, addr, -4);
2349 for (i = 0; i < 32; i += 4) {
2350 /* Since the loads and stores are paired, allow the
2351 copy to happen in the host endianness. */
2352 tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL);
2353 tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL);
2354 tcg_gen_add_tl(saddr, saddr, four);
2355 tcg_gen_add_tl(daddr, daddr, four);
2356 }
2357
2358 tcg_temp_free(saddr);
2359 tcg_temp_free(daddr);
2360 tcg_temp_free(four);
2361 tcg_temp_free_i32(tmp);
2362 }
2363 break;
2364#endif
7ec1e5ea
RH		 2365 default:
2366 {
2367 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2368 TCGv_i32 r_mop = tcg_const_i32(memop & MO_SIZE);
7ec1e5ea
RH		 2369
2370 save_state(dc);
22e70060 2371#ifdef TARGET_SPARC64
6850811e 2372 gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop);
22e70060 2373#else
7ec1e5ea
RH		 2374 {
2375 TCGv_i64 t64 = tcg_temp_new_i64();
2376 tcg_gen_extu_tl_i64(t64, src);
6850811e 2377 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
7ec1e5ea
RH		 2378 tcg_temp_free_i64(t64);
2379 }
22e70060 2380#endif
6850811e 2381 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2382 tcg_temp_free_i32(r_asi);
2383
2384 /* A write to a TLB register may alter page maps. End the TB. */
2385 dc->npc = DYNAMIC_PC;
2386 }
2387 break;
2388 }
1a2fb1c0
BS		 2389}
2390
22e70060
RH		 2391static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src,
2392 TCGv addr, int insn)
1a2fb1c0 2393{
f0913be0 2394 DisasASI da = get_asi(dc, insn, MO_TEUL);
22e70060 2395
7ec1e5ea
RH		 2396 switch (da.type) {
2397 case GET_ASI_EXCP:
2398 break;
4fb554bc
RH		 2399 case GET_ASI_DIRECT:
2400 gen_swap(dc, dst, src, addr, da.mem_idx, da.memop);
2401 break;
7ec1e5ea 2402 default:
4fb554bc
RH		 2403 /* ??? Should be DAE_invalid_asi. */
2404 gen_exception(dc, TT_DATA_ACCESS);
7ec1e5ea
RH		 2405 break;
2406 }
1a2fb1c0
BS		 2407}
2408
5a7267b6 2409static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060
RH		 2410 int insn, int rd)
2411{
f0913be0 2412 DisasASI da = get_asi(dc, insn, MO_TEUL);
5a7267b6 2413 TCGv oldv;
22e70060 2414
7268adeb
RH		 2415 switch (da.type) {
2416 case GET_ASI_EXCP:
7ec1e5ea 2417 return;
7268adeb 2418 case GET_ASI_DIRECT:
7268adeb 2419 oldv = tcg_temp_new();
5a7267b6
RH		 2420 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2421 da.mem_idx, da.memop);
7268adeb 2422 gen_store_gpr(dc, rd, oldv);
7268adeb 2423 tcg_temp_free(oldv);
7268adeb
RH		 2424 break;
2425 default:
2426 /* ??? Should be DAE_invalid_asi. */
2427 gen_exception(dc, TT_DATA_ACCESS);
2428 break;
7ec1e5ea 2429 }
22e70060
RH		 2430}
2431
2432static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
2433{
f0913be0 2434 DisasASI da = get_asi(dc, insn, MO_UB);
22e70060 2435
7ec1e5ea
RH		 2436 switch (da.type) {
2437 case GET_ASI_EXCP:
2438 break;
fbb4bbb6
RH		 2439 case GET_ASI_DIRECT:
2440 gen_ldstub(dc, dst, addr, da.mem_idx);
2441 break;
7ec1e5ea 2442 default:
3db010c3
RH		 2443 /* ??? In theory, this should be raise DAE_invalid_asi.
2444 But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
2445 if (parallel_cpus) {
2446 gen_helper_exit_atomic(cpu_env);
2447 } else {
2448 TCGv_i32 r_asi = tcg_const_i32(da.asi);
2449 TCGv_i32 r_mop = tcg_const_i32(MO_UB);
2450 TCGv_i64 s64, t64;
2451
2452 save_state(dc);
2453 t64 = tcg_temp_new_i64();
2454 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2455
2456 s64 = tcg_const_i64(0xff);
2457 gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop);
2458 tcg_temp_free_i64(s64);
2459 tcg_temp_free_i32(r_mop);
2460 tcg_temp_free_i32(r_asi);
2461
2462 tcg_gen_trunc_i64_tl(dst, t64);
2463 tcg_temp_free_i64(t64);
2464
2465 /* End the TB. */
2466 dc->npc = DYNAMIC_PC;
2467 }
7ec1e5ea
RH		 2468 break;
2469 }
22e70060
RH		 2470}
2471#endif
2472
2473#ifdef TARGET_SPARC64
2474static void gen_ldf_asi(DisasContext *dc, TCGv addr,
2475 int insn, int size, int rd)
1a2fb1c0 2476{
f0913be0 2477 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2478 TCGv_i32 d32;
cb21b4da 2479 TCGv_i64 d64;
1a2fb1c0 2480
7ec1e5ea
RH		 2481 switch (da.type) {
2482 case GET_ASI_EXCP:
2483 break;
7705091c
RH		 2484
2485 case GET_ASI_DIRECT:
2486 gen_address_mask(dc, addr);
2487 switch (size) {
2488 case 4:
2489 d32 = gen_dest_fpr_F(dc);
2490 tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop);
2491 gen_store_fpr_F(dc, rd, d32);
2492 break;
2493 case 8:
cb21b4da
RH		 2494 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2495 da.memop | MO_ALIGN_4);
7705091c
RH		 2496 break;
2497 case 16:
cb21b4da
RH		 2498 d64 = tcg_temp_new_i64();
2499 tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
7705091c 2500 tcg_gen_addi_tl(addr, addr, 8);
cb21b4da
RH		 2501 tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
2502 da.memop | MO_ALIGN_4);
2503 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2504 tcg_temp_free_i64(d64);
7705091c
RH		 2505 break;
2506 default:
2507 g_assert_not_reached();
2508 }
2509 break;
2510
ca5ce572
RH		 2511 case GET_ASI_BLOCK:
2512 /* Valid for lddfa on aligned registers only. */
2513 if (size == 8 && (rd & 7) == 0) {
80883227 2514 TCGMemOp memop;
ca5ce572
RH		 2515 TCGv eight;
2516 int i;
2517
ca5ce572
RH		 2518 gen_address_mask(dc, addr);
2519
80883227
RH		 2520 /* The first operation checks required alignment. */
2521 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2522 eight = tcg_const_tl(8);
2523 for (i = 0; ; ++i) {
2524 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2525 da.mem_idx, memop);
ca5ce572
RH		 2526 if (i == 7) {
2527 break;
2528 }
2529 tcg_gen_add_tl(addr, addr, eight);
80883227 2530 memop = da.memop;
ca5ce572
RH		 2531 }
2532 tcg_temp_free(eight);
2533 } else {
2534 gen_exception(dc, TT_ILL_INSN);
2535 }
2536 break;
2537
2538 case GET_ASI_SHORT:
2539 /* Valid for lddfa only. */
2540 if (size == 8) {
2541 gen_address_mask(dc, addr);
2542 tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2543 } else {
2544 gen_exception(dc, TT_ILL_INSN);
2545 }
2546 break;
2547
7ec1e5ea
RH		 2548 default:
2549 {
2550 TCGv_i32 r_asi = tcg_const_i32(da.asi);
f2fe396f 2551 TCGv_i32 r_mop = tcg_const_i32(da.memop);
7ec1e5ea
RH		 2552
2553 save_state(dc);
f2fe396f
RH		 2554 /* According to the table in the UA2011 manual, the only
2555 other asis that are valid for ldfa/lddfa/ldqfa are
2556 the NO_FAULT asis. We still need a helper for these,
2557 but we can just use the integer asi helper for them. */
2558 switch (size) {
2559 case 4:
cb21b4da
RH		 2560 d64 = tcg_temp_new_i64();
2561 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
2562 d32 = gen_dest_fpr_F(dc);
2563 tcg_gen_extrl_i64_i32(d32, d64);
2564 tcg_temp_free_i64(d64);
2565 gen_store_fpr_F(dc, rd, d32);
f2fe396f
RH		 2566 break;
2567 case 8:
2568 gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r_mop);
2569 break;
2570 case 16:
cb21b4da
RH		 2571 d64 = tcg_temp_new_i64();
2572 gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop);
f2fe396f
RH		 2573 tcg_gen_addi_tl(addr, addr, 8);
2574 gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r_mop);
cb21b4da
RH		 2575 tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
2576 tcg_temp_free_i64(d64);
f2fe396f
RH		 2577 break;
2578 default:
2579 g_assert_not_reached();
2580 }
2581 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2582 tcg_temp_free_i32(r_asi);
2583 }
2584 break;
2585 }
1a2fb1c0
BS		 2586}
2587
22e70060
RH		 2588static void gen_stf_asi(DisasContext *dc, TCGv addr,
2589 int insn, int size, int rd)
1a2fb1c0 2590{
f0913be0 2591 DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
7705091c 2592 TCGv_i32 d32;
1a2fb1c0 2593
7ec1e5ea
RH		 2594 switch (da.type) {
2595 case GET_ASI_EXCP:
2596 break;
7705091c
RH		 2597
2598 case GET_ASI_DIRECT:
2599 gen_address_mask(dc, addr);
2600 switch (size) {
2601 case 4:
2602 d32 = gen_load_fpr_F(dc, rd);
2603 tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop);
2604 break;
2605 case 8:
cb21b4da
RH		 2606 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2607 da.memop | MO_ALIGN_4);
7705091c
RH		 2608 break;
2609 case 16:
cb21b4da
RH		 2610 /* Only 4-byte alignment required. However, it is legal for the
2611 cpu to signal the alignment fault, and the OS trap handler is
2612 required to fix it up. Requiring 16-byte alignment here avoids
2613 having to probe the second page before performing the first
2614 write. */
f939ffe5
RH		 2615 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
2616 da.memop | MO_ALIGN_16);
7705091c
RH		 2617 tcg_gen_addi_tl(addr, addr, 8);
2618 tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
2619 break;
2620 default:
2621 g_assert_not_reached();
2622 }
2623 break;
2624
ca5ce572
RH		 2625 case GET_ASI_BLOCK:
2626 /* Valid for stdfa on aligned registers only. */
2627 if (size == 8 && (rd & 7) == 0) {
80883227 2628 TCGMemOp memop;
ca5ce572
RH		 2629 TCGv eight;
2630 int i;
2631
ca5ce572
RH		 2632 gen_address_mask(dc, addr);
2633
80883227
RH		 2634 /* The first operation checks required alignment. */
2635 memop = da.memop | MO_ALIGN_64;
ca5ce572
RH		 2636 eight = tcg_const_tl(8);
2637 for (i = 0; ; ++i) {
2638 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
80883227 2639 da.mem_idx, memop);
ca5ce572
RH		 2640 if (i == 7) {
2641 break;
2642 }
2643 tcg_gen_add_tl(addr, addr, eight);
80883227 2644 memop = da.memop;
ca5ce572
RH		 2645 }
2646 tcg_temp_free(eight);
2647 } else {
2648 gen_exception(dc, TT_ILL_INSN);
2649 }
2650 break;
2651
2652 case GET_ASI_SHORT:
2653 /* Valid for stdfa only. */
2654 if (size == 8) {
2655 gen_address_mask(dc, addr);
2656 tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
2657 } else {
2658 gen_exception(dc, TT_ILL_INSN);
2659 }
2660 break;
2661
7ec1e5ea 2662 default:
f2fe396f
RH		 2663 /* According to the table in the UA2011 manual, the only
2664 other asis that are valid for ldfa/lddfa/ldqfa are
2665 the PST* asis, which aren't currently handled. */
2666 gen_exception(dc, TT_ILL_INSN);
7ec1e5ea
RH		 2667 break;
2668 }
1a2fb1c0
BS		 2669}
2670
e4dc0052 2671static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2672{
f0913be0 2673 DisasASI da = get_asi(dc, insn, MO_TEQ);
e4dc0052
RH		 2674 TCGv_i64 hi = gen_dest_gpr(dc, rd);
2675 TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
1a2fb1c0 2676
7ec1e5ea
RH		 2677 switch (da.type) {
2678 case GET_ASI_EXCP:
e4dc0052
RH		 2679 return;
2680
2681 case GET_ASI_DTWINX:
e4dc0052 2682 gen_address_mask(dc, addr);
80883227 2683 tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2684 tcg_gen_addi_tl(addr, addr, 8);
2685 tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop);
7ec1e5ea 2686 break;
e4dc0052
RH		 2687
2688 case GET_ASI_DIRECT:
2689 {
2690 TCGv_i64 tmp = tcg_temp_new_i64();
2691
2692 gen_address_mask(dc, addr);
2693 tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop);
2694
2695 /* Note that LE ldda acts as if each 32-bit register
2696 result is byte swapped. Having just performed one
2697 64-bit bswap, we need now to swap the writebacks. */
2698 if ((da.memop & MO_BSWAP) == MO_TE) {
2699 tcg_gen_extr32_i64(lo, hi, tmp);
2700 } else {
2701 tcg_gen_extr32_i64(hi, lo, tmp);
2702 }
2703 tcg_temp_free_i64(tmp);
2704 }
2705 break;
2706
7ec1e5ea 2707 default:
918d9a2c
RH		 2708 /* ??? In theory we've handled all of the ASIs that are valid
2709 for ldda, and this should raise DAE_invalid_asi. However,
2710 real hardware allows others. This can be seen with e.g.
2711 FreeBSD 10.3 wrt ASI_IC_TAG. */
7ec1e5ea
RH		 2712 {
2713 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2714 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2715 TCGv_i64 tmp = tcg_temp_new_i64();
7ec1e5ea
RH		 2716
2717 save_state(dc);
918d9a2c 2718 gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop);
7ec1e5ea 2719 tcg_temp_free_i32(r_asi);
918d9a2c 2720 tcg_temp_free_i32(r_mop);
3f4288eb 2721
918d9a2c
RH		 2722 /* See above. */
2723 if ((da.memop & MO_BSWAP) == MO_TE) {
2724 tcg_gen_extr32_i64(lo, hi, tmp);
2725 } else {
2726 tcg_gen_extr32_i64(hi, lo, tmp);
2727 }
2728 tcg_temp_free_i64(tmp);
7ec1e5ea
RH		 2729 }
2730 break;
2731 }
e4dc0052
RH		 2732
2733 gen_store_gpr(dc, rd, hi);
2734 gen_store_gpr(dc, rd + 1, lo);
0425bee5
BS		 2735}
2736
22e70060
RH		 2737static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2738 int insn, int rd)
0425bee5 2739{
f0913be0 2740 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2741 TCGv lo = gen_load_gpr(dc, rd + 1);
a7ec4229 2742
7ec1e5ea
RH		 2743 switch (da.type) {
2744 case GET_ASI_EXCP:
2745 break;
e4dc0052
RH		 2746
2747 case GET_ASI_DTWINX:
e4dc0052 2748 gen_address_mask(dc, addr);
80883227 2749 tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
e4dc0052
RH		 2750 tcg_gen_addi_tl(addr, addr, 8);
2751 tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop);
2752 break;
2753
2754 case GET_ASI_DIRECT:
2755 {
2756 TCGv_i64 t64 = tcg_temp_new_i64();
2757
2758 /* Note that LE stda acts as if each 32-bit register result is
2759 byte swapped. We will perform one 64-bit LE store, so now
2760 we must swap the order of the construction. */
2761 if ((da.memop & MO_BSWAP) == MO_TE) {
2762 tcg_gen_concat32_i64(t64, lo, hi);
2763 } else {
2764 tcg_gen_concat32_i64(t64, hi, lo);
2765 }
2766 gen_address_mask(dc, addr);
2767 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2768 tcg_temp_free_i64(t64);
2769 }
2770 break;
2771
7ec1e5ea 2772 default:
918d9a2c
RH		 2773 /* ??? In theory we've handled all of the ASIs that are valid
2774 for stda, and this should raise DAE_invalid_asi. */
7ec1e5ea
RH		 2775 {
2776 TCGv_i32 r_asi = tcg_const_i32(da.asi);
918d9a2c
RH		 2777 TCGv_i32 r_mop = tcg_const_i32(da.memop);
2778 TCGv_i64 t64 = tcg_temp_new_i64();
7ec1e5ea 2779
918d9a2c
RH		 2780 /* See above. */
2781 if ((da.memop & MO_BSWAP) == MO_TE) {
2782 tcg_gen_concat32_i64(t64, lo, hi);
2783 } else {
2784 tcg_gen_concat32_i64(t64, hi, lo);
2785 }
7ec1e5ea 2786
918d9a2c 2787 save_state(dc);
6850811e
RH		 2788 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2789 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2790 tcg_temp_free_i32(r_asi);
2791 tcg_temp_free_i64(t64);
2792 }
2793 break;
2794 }
1a2fb1c0
BS		 2795}
2796
7268adeb 2797static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
22e70060 2798 int insn, int rd)
1a2fb1c0 2799{
f0913be0 2800 DisasASI da = get_asi(dc, insn, MO_TEQ);
5a7267b6 2801 TCGv oldv;
1a2fb1c0 2802
7268adeb
RH		 2803 switch (da.type) {
2804 case GET_ASI_EXCP:
7ec1e5ea 2805 return;
7268adeb
RH		 2806 case GET_ASI_DIRECT:
2807 oldv = tcg_temp_new();
5a7267b6
RH		 2808 tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd),
2809 da.mem_idx, da.memop);
7268adeb
RH		 2810 gen_store_gpr(dc, rd, oldv);
2811 tcg_temp_free(oldv);
7268adeb
RH		 2812 break;
2813 default:
2814 /* ??? Should be DAE_invalid_asi. */
2815 gen_exception(dc, TT_DATA_ACCESS);
2816 break;
2817 }
1a2fb1c0
BS		 2818}
2819
2820#elif !defined(CONFIG_USER_ONLY)
e4dc0052 2821static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
1a2fb1c0 2822{
d2dc4069
RH		 2823 /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12,
2824 whereby "rd + 1" elicits "error: array subscript is above array".
2825 Since we have already asserted that rd is even, the semantics
2826 are unchanged. */
7ec1e5ea 2827 TCGv lo = gen_dest_gpr(dc, rd | 1);
e4dc0052 2828 TCGv hi = gen_dest_gpr(dc, rd);
7ec1e5ea 2829 TCGv_i64 t64 = tcg_temp_new_i64();
f0913be0 2830 DisasASI da = get_asi(dc, insn, MO_TEQ);
7ec1e5ea
RH		 2831
2832 switch (da.type) {
2833 case GET_ASI_EXCP:
2834 tcg_temp_free_i64(t64);
2835 return;
e4dc0052
RH		 2836 case GET_ASI_DIRECT:
2837 gen_address_mask(dc, addr);
2838 tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop);
2839 break;
7ec1e5ea
RH		 2840 default:
2841 {
2842 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2843 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2844
2845 save_state(dc);
6850811e
RH		 2846 gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
2847 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2848 tcg_temp_free_i32(r_asi);
2849 }
2850 break;
2851 }
c7785e16 2852
7ec1e5ea 2853 tcg_gen_extr_i64_i32(lo, hi, t64);
1ec789ab 2854 tcg_temp_free_i64(t64);
7ec1e5ea 2855 gen_store_gpr(dc, rd | 1, lo);
c7785e16 2856 gen_store_gpr(dc, rd, hi);
0425bee5
BS		 2857}
2858
22e70060
RH		 2859static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
2860 int insn, int rd)
0425bee5 2861{
f0913be0 2862 DisasASI da = get_asi(dc, insn, MO_TEQ);
c7785e16 2863 TCGv lo = gen_load_gpr(dc, rd + 1);
1ec789ab 2864 TCGv_i64 t64 = tcg_temp_new_i64();
a7ec4229 2865
1ec789ab 2866 tcg_gen_concat_tl_i64(t64, lo, hi);
7ec1e5ea
RH		 2867
2868 switch (da.type) {
2869 case GET_ASI_EXCP:
2870 break;
e4dc0052
RH		 2871 case GET_ASI_DIRECT:
2872 gen_address_mask(dc, addr);
2873 tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop);
2874 break;
34810610
RH		 2875 case GET_ASI_BFILL:
2876 /* Store 32 bytes of T64 to ADDR. */
2877 /* ??? The original qemu code suggests 8-byte alignment, dropping
2878 the low bits, but the only place I can see this used is in the
2879 Linux kernel with 32 byte alignment, which would make more sense
2880 as a cacheline-style operation. */
2881 {
2882 TCGv d_addr = tcg_temp_new();
2883 TCGv eight = tcg_const_tl(8);
2884 int i;
2885
2886 tcg_gen_andi_tl(d_addr, addr, -8);
2887 for (i = 0; i < 32; i += 8) {
2888 tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop);
2889 tcg_gen_add_tl(d_addr, d_addr, eight);
2890 }
2891
2892 tcg_temp_free(d_addr);
2893 tcg_temp_free(eight);
2894 }
2895 break;
7ec1e5ea
RH		 2896 default:
2897 {
2898 TCGv_i32 r_asi = tcg_const_i32(da.asi);
6850811e 2899 TCGv_i32 r_mop = tcg_const_i32(MO_Q);
7ec1e5ea
RH		 2900
2901 save_state(dc);
6850811e
RH		 2902 gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
2903 tcg_temp_free_i32(r_mop);
7ec1e5ea
RH		 2904 tcg_temp_free_i32(r_asi);
2905 }
2906 break;
2907 }
2908
1ec789ab 2909 tcg_temp_free_i64(t64);
1a2fb1c0
BS		 2910}
2911#endif
2912
9d1d4e34 2913static TCGv get_src1(DisasContext *dc, unsigned int insn)
9322a4bf 2914{
9d1d4e34
RH		 2915 unsigned int rs1 = GET_FIELD(insn, 13, 17);
2916 return gen_load_gpr(dc, rs1);
9322a4bf
BS		 2917}
2918
9d1d4e34 2919static TCGv get_src2(DisasContext *dc, unsigned int insn)
a49d9390 2920{
a49d9390 2921 if (IS_IMM) { /* immediate */
42a8aa83 2922 target_long simm = GET_FIELDs(insn, 19, 31);
9d1d4e34
RH		 2923 TCGv t = get_temp_tl(dc);
2924 tcg_gen_movi_tl(t, simm);
2925 return t;
2926 } else { /* register */
42a8aa83 2927 unsigned int rs2 = GET_FIELD(insn, 27, 31);
9d1d4e34 2928 return gen_load_gpr(dc, rs2);
a49d9390 2929 }
a49d9390
BS		 2930}
2931
8194f35a 2932#ifdef TARGET_SPARC64
7e480893
RH		 2933static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2934{
2935 TCGv_i32 c32, zero, dst, s1, s2;
2936
2937 /* We have two choices here: extend the 32 bit data and use movcond_i64,
2938 or fold the comparison down to 32 bits and use movcond_i32. Choose
2939 the later. */
2940 c32 = tcg_temp_new_i32();
2941 if (cmp->is_bool) {
ecc7b3aa 2942 tcg_gen_extrl_i64_i32(c32, cmp->c1);
7e480893
RH		 2943 } else {
2944 TCGv_i64 c64 = tcg_temp_new_i64();
2945 tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
ecc7b3aa 2946 tcg_gen_extrl_i64_i32(c32, c64);
7e480893
RH		 2947 tcg_temp_free_i64(c64);
2948 }
2949
2950 s1 = gen_load_fpr_F(dc, rs);
2951 s2 = gen_load_fpr_F(dc, rd);
ba5f5179 2952 dst = gen_dest_fpr_F(dc);
7e480893
RH		 2953 zero = tcg_const_i32(0);
2954
2955 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
2956
2957 tcg_temp_free_i32(c32);
2958 tcg_temp_free_i32(zero);
2959 gen_store_fpr_F(dc, rd, dst);
2960}
2961
2962static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2963{
3886b8a3 2964 TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
7e480893
RH		 2965 tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
2966 gen_load_fpr_D(dc, rs),
2967 gen_load_fpr_D(dc, rd));
2968 gen_store_fpr_D(dc, rd, dst);
2969}
2970
2971static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
2972{
2973 int qd = QFPREG(rd);
2974 int qs = QFPREG(rs);
2975
2976 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2], cmp->c1, cmp->c2,
2977 cpu_fpr[qs / 2], cpu_fpr[qd / 2]);
2978 tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
2979 cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
2980
f9c816c0 2981 gen_update_fprs_dirty(dc, qd);
7e480893
RH		 2982}
2983
a2035e83 2984#ifndef CONFIG_USER_ONLY
1bcea73e 2985static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
8194f35a 2986{
b551ec04 2987 TCGv_i32 r_tl = tcg_temp_new_i32();
8194f35a
IK		 2988
2989 /* load env->tl into r_tl */
b551ec04 2990 tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl));
8194f35a
IK		 2991
2992 /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
b551ec04 2993 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK);
8194f35a
IK		 2994
2995 /* calculate offset to current trap state from env->ts, reuse r_tl */
b551ec04 2996 tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
c5f9864e 2997 tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts));
8194f35a
IK		 2998
2999 /* tsptr = env->ts[env->tl & MAXTL_MASK] */
b551ec04
JF		 3000 {
3001 TCGv_ptr r_tl_tmp = tcg_temp_new_ptr();
3002 tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl);
3003 tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
bc57c114 3004 tcg_temp_free_ptr(r_tl_tmp);
b551ec04 3005 }
8194f35a 3006
b551ec04 3007 tcg_temp_free_i32(r_tl);
8194f35a 3008}
a2035e83 3009#endif
6c073553
RH		 3010
3011static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
3012 int width, bool cc, bool left)
3013{
3014 TCGv lo1, lo2, t1, t2;
3015 uint64_t amask, tabl, tabr;
3016 int shift, imask, omask;
3017
3018 if (cc) {
3019 tcg_gen_mov_tl(cpu_cc_src, s1);
3020 tcg_gen_mov_tl(cpu_cc_src2, s2);
3021 tcg_gen_sub_tl(cpu_cc_dst, s1, s2);
3022 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
3023 dc->cc_op = CC_OP_SUB;
3024 }
3025
3026 /* Theory of operation: there are two tables, left and right (not to
3027 be confused with the left and right versions of the opcode). These
3028 are indexed by the low 3 bits of the inputs. To make things "easy",
3029 these tables are loaded into two constants, TABL and TABR below.
3030 The operation index = (input & imask) << shift calculates the index
3031 into the constant, while val = (table >> index) & omask calculates
3032 the value we're looking for. */
3033 switch (width) {
3034 case 8:
3035 imask = 0x7;
3036 shift = 3;
3037 omask = 0xff;
3038 if (left) {
3039 tabl = 0x80c0e0f0f8fcfeffULL;
3040 tabr = 0xff7f3f1f0f070301ULL;
3041 } else {
3042 tabl = 0x0103070f1f3f7fffULL;
3043 tabr = 0xfffefcf8f0e0c080ULL;
3044 }
3045 break;
3046 case 16:
3047 imask = 0x6;
3048 shift = 1;
3049 omask = 0xf;
3050 if (left) {
3051 tabl = 0x8cef;
3052 tabr = 0xf731;
3053 } else {
3054 tabl = 0x137f;
3055 tabr = 0xfec8;
3056 }
3057 break;
3058 case 32:
3059 imask = 0x4;
3060 shift = 0;
3061 omask = 0x3;
3062 if (left) {
3063 tabl = (2 << 2) | 3;
3064 tabr = (3 << 2) | 1;
3065 } else {
3066 tabl = (1 << 2) | 3;
3067 tabr = (3 << 2) | 2;
3068 }
3069 break;
3070 default:
3071 abort();
3072 }
3073
3074 lo1 = tcg_temp_new();
3075 lo2 = tcg_temp_new();
3076 tcg_gen_andi_tl(lo1, s1, imask);
3077 tcg_gen_andi_tl(lo2, s2, imask);
3078 tcg_gen_shli_tl(lo1, lo1, shift);
3079 tcg_gen_shli_tl(lo2, lo2, shift);
3080
3081 t1 = tcg_const_tl(tabl);
3082 t2 = tcg_const_tl(tabr);
3083 tcg_gen_shr_tl(lo1, t1, lo1);
3084 tcg_gen_shr_tl(lo2, t2, lo2);
3085 tcg_gen_andi_tl(dst, lo1, omask);
3086 tcg_gen_andi_tl(lo2, lo2, omask);
3087
3088 amask = -8;
3089 if (AM_CHECK(dc)) {
3090 amask &= 0xffffffffULL;
3091 }
3092 tcg_gen_andi_tl(s1, s1, amask);
3093 tcg_gen_andi_tl(s2, s2, amask);
3094
3095 /* We want to compute
3096 dst = (s1 == s2 ? lo1 : lo1 & lo2).
3097 We've already done dst = lo1, so this reduces to
3098 dst &= (s1 == s2 ? -1 : lo2)
3099 Which we perform by
3100 lo2 |= -(s1 == s2)
3101 dst &= lo2
3102 */
3103 tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
3104 tcg_gen_neg_tl(t1, t1);
3105 tcg_gen_or_tl(lo2, lo2, t1);
3106 tcg_gen_and_tl(dst, dst, lo2);
3107
3108 tcg_temp_free(lo1);
3109 tcg_temp_free(lo2);
3110 tcg_temp_free(t1);
3111 tcg_temp_free(t2);
3112}
add545ab
RH		 3113
3114static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left)
3115{
3116 TCGv tmp = tcg_temp_new();
3117
3118 tcg_gen_add_tl(tmp, s1, s2);
3119 tcg_gen_andi_tl(dst, tmp, -8);
3120 if (left) {
3121 tcg_gen_neg_tl(tmp, tmp);
3122 }
3123 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3);
3124
3125 tcg_temp_free(tmp);
3126}
50c796f9
RH		 3127
3128static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
3129{
3130 TCGv t1, t2, shift;
3131
3132 t1 = tcg_temp_new();
3133 t2 = tcg_temp_new();
3134 shift = tcg_temp_new();
3135
3136 tcg_gen_andi_tl(shift, gsr, 7);
3137 tcg_gen_shli_tl(shift, shift, 3);
3138 tcg_gen_shl_tl(t1, s1, shift);
3139
3140 /* A shift of 64 does not produce 0 in TCG. Divide this into a
3141 shift of (up to 63) followed by a constant shift of 1. */
3142 tcg_gen_xori_tl(shift, shift, 63);
3143 tcg_gen_shr_tl(t2, s2, shift);
3144 tcg_gen_shri_tl(t2, t2, 1);
3145
3146 tcg_gen_or_tl(dst, t1, t2);
3147
3148 tcg_temp_free(t1);
3149 tcg_temp_free(t2);
3150 tcg_temp_free(shift);
3151}
8194f35a
IK		 3152#endif
3153
64a88d5d 3154#define CHECK_IU_FEATURE(dc, FEATURE) \
5578ceab 3155 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3156 goto illegal_insn;
3157#define CHECK_FPU_FEATURE(dc, FEATURE) \
5578ceab 3158 if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
64a88d5d
BS		 3159 goto nfpu_insn;
3160
0bee699e 3161/* before an instruction, dc->pc must be static */
0184e266 3162static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
cf495bcf 3163{
0184e266 3164 unsigned int opc, rs1, rs2, rd;
a4273524 3165 TCGv cpu_src1, cpu_src2;
208ae657 3166 TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
96eda024 3167 TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
67526b20 3168 target_long simm;
7a3f1944 3169
cf495bcf 3170 opc = GET_FIELD(insn, 0, 1);
cf495bcf 3171 rd = GET_FIELD(insn, 2, 6);
6ae20372 3172
cf495bcf 3173 switch (opc) {
0f8a249a
BS		 3174 case 0: /* branches/sethi */
3175 {
3176 unsigned int xop = GET_FIELD(insn, 7, 9);
3177 int32_t target;
3178 switch (xop) {
3475187d 3179#ifdef TARGET_SPARC64
0f8a249a
BS		 3180 case 0x1: /* V9 BPcc */
3181 {
3182 int cc;
3183
3184 target = GET_FIELD_SP(insn, 0, 18);
86f1f2ae 3185 target = sign_extend(target, 19);
0f8a249a
BS		 3186 target <<= 2;
3187 cc = GET_FIELD_SP(insn, 20, 21);
3188 if (cc == 0)
d4a288ef 3189 do_branch(dc, target, insn, 0);
0f8a249a 3190 else if (cc == 2)
d4a288ef 3191 do_branch(dc, target, insn, 1);
0f8a249a
BS		 3192 else
3193 goto illegal_insn;
3194 goto jmp_insn;
3195 }
3196 case 0x3: /* V9 BPr */
3197 {
3198 target = GET_FIELD_SP(insn, 0, 13) |
13846e70 3199 (GET_FIELD_SP(insn, 20, 21) << 14);
0f8a249a
BS		 3200 target = sign_extend(target, 16);
3201 target <<= 2;
9d1d4e34 3202 cpu_src1 = get_src1(dc, insn);
d4a288ef 3203 do_branch_reg(dc, target, insn, cpu_src1);
0f8a249a
BS		 3204 goto jmp_insn;
3205 }
3206 case 0x5: /* V9 FBPcc */
3207 {
3208 int cc = GET_FIELD_SP(insn, 20, 21);
5b12f1e8 3209 if (gen_trap_ifnofpu(dc)) {
a80dde08 3210 goto jmp_insn;
5b12f1e8 3211 }
0f8a249a
BS		 3212 target = GET_FIELD_SP(insn, 0, 18);
3213 target = sign_extend(target, 19);
3214 target <<= 2;
d4a288ef 3215 do_fbranch(dc, target, insn, cc);
0f8a249a
BS		 3216 goto jmp_insn;
3217 }
a4d17f19 3218#else
0f8a249a
BS		 3219 case 0x7: /* CBN+x */
3220 {
3221 goto ncp_insn;
3222 }
3223#endif
3224 case 0x2: /* BN+x */
3225 {
3226 target = GET_FIELD(insn, 10, 31);
3227 target = sign_extend(target, 22);
3228 target <<= 2;
d4a288ef 3229 do_branch(dc, target, insn, 0);
0f8a249a
BS		 3230 goto jmp_insn;
3231 }
3232 case 0x6: /* FBN+x */
3233 {
5b12f1e8 3234 if (gen_trap_ifnofpu(dc)) {
a80dde08 3235 goto jmp_insn;
5b12f1e8 3236 }
0f8a249a
BS		 3237 target = GET_FIELD(insn, 10, 31);
3238 target = sign_extend(target, 22);
3239 target <<= 2;
d4a288ef 3240 do_fbranch(dc, target, insn, 0);
0f8a249a
BS		 3241 goto jmp_insn;
3242 }
3243 case 0x4: /* SETHI */
97ea2859
RH		 3244 /* Special-case %g0 because that's the canonical nop. */
3245 if (rd) {
0f8a249a 3246 uint32_t value = GET_FIELD(insn, 10, 31);
97ea2859
RH		 3247 TCGv t = gen_dest_gpr(dc, rd);
3248 tcg_gen_movi_tl(t, value << 10);
3249 gen_store_gpr(dc, rd, t);
0f8a249a 3250 }
0f8a249a
BS		 3251 break;
3252 case 0x0: /* UNIMPL */
3253 default:
3475187d 3254 goto illegal_insn;
0f8a249a
BS		 3255 }
3256 break;
3257 }
3258 break;
dc1a6971
BS		 3259 case 1: /*CALL*/
3260 {
0f8a249a 3261 target_long target = GET_FIELDs(insn, 2, 31) << 2;
97ea2859 3262 TCGv o7 = gen_dest_gpr(dc, 15);
cf495bcf 3263
97ea2859
RH		 3264 tcg_gen_movi_tl(o7, dc->pc);
3265 gen_store_gpr(dc, 15, o7);
0f8a249a 3266 target += dc->pc;
13a6dd00 3267 gen_mov_pc_npc(dc);
22036a49
AT		 3268#ifdef TARGET_SPARC64
3269 if (unlikely(AM_CHECK(dc))) {
3270 target &= 0xffffffffULL;
3271 }
3272#endif
0f8a249a
BS		 3273 dc->npc = target;
3274 }
3275 goto jmp_insn;
3276 case 2: /* FPU & Logical Operations */
3277 {
3278 unsigned int xop = GET_FIELD(insn, 7, 12);
e7d51b34 3279 TCGv cpu_dst = get_temp_tl(dc);
de9e9d9f 3280 TCGv cpu_tmp0;
5793f2a4 3281
0f8a249a 3282 if (xop == 0x3a) { /* generate trap */
bd49ed41
RH		 3283 int cond = GET_FIELD(insn, 3, 6);
3284 TCGv_i32 trap;
42a268c2
RH		 3285 TCGLabel *l1 = NULL;
3286 int mask;
3475187d 3287
bd49ed41
RH		 3288 if (cond == 0) {
3289 /* Trap never. */
3290 break;
cf495bcf 3291 }
b04d9890 3292
bd49ed41 3293 save_state(dc);
b04d9890 3294
bd49ed41
RH		 3295 if (cond != 8) {
3296 /* Conditional trap. */
3a49e759 3297 DisasCompare cmp;
3475187d 3298#ifdef TARGET_SPARC64
0f8a249a
BS		 3299 /* V9 icc/xcc */
3300 int cc = GET_FIELD_SP(insn, 11, 12);
3a49e759
RH		 3301 if (cc == 0) {
3302 gen_compare(&cmp, 0, cond, dc);
3303 } else if (cc == 2) {
3304 gen_compare(&cmp, 1, cond, dc);
3305 } else {
0f8a249a 3306 goto illegal_insn;
3a49e759 3307 }
3475187d 3308#else
3a49e759 3309 gen_compare(&cmp, 0, cond, dc);
3475187d 3310#endif
b158a785 3311 l1 = gen_new_label();
3a49e759
RH		 3312 tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond),
3313 cmp.c1, cmp.c2, l1);
3314 free_compare(&cmp);
bd49ed41 3315 }
b158a785 3316
bd49ed41
RH		 3317 mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
3318 ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
3319
3320 /* Don't use the normal temporaries, as they may well have
3321 gone out of scope with the branch above. While we're
3322 doing that we might as well pre-truncate to 32-bit. */
3323 trap = tcg_temp_new_i32();
3324
3325 rs1 = GET_FIELD_SP(insn, 14, 18);
3326 if (IS_IMM) {
5c65df36 3327 rs2 = GET_FIELD_SP(insn, 0, 7);
bd49ed41
RH		 3328 if (rs1 == 0) {
3329 tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP);
3330 /* Signal that the trap value is fully constant. */
3331 mask = 0;
3332 } else {
97ea2859 3333 TCGv t1 = gen_load_gpr(dc, rs1);
bd49ed41 3334 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3335 tcg_gen_addi_i32(trap, trap, rs2);
3336 }
3337 } else {
97ea2859 3338 TCGv t1, t2;
bd49ed41 3339 rs2 = GET_FIELD_SP(insn, 0, 4);
97ea2859
RH		 3340 t1 = gen_load_gpr(dc, rs1);
3341 t2 = gen_load_gpr(dc, rs2);
bd49ed41
RH		 3342 tcg_gen_add_tl(t1, t1, t2);
3343 tcg_gen_trunc_tl_i32(trap, t1);
bd49ed41
RH		 3344 }
3345 if (mask != 0) {
3346 tcg_gen_andi_i32(trap, trap, mask);
3347 tcg_gen_addi_i32(trap, trap, TT_TRAP);
3348 }
3349
3350 gen_helper_raise_exception(cpu_env, trap);
3351 tcg_temp_free_i32(trap);
b158a785 3352
fe1755cb
RH		 3353 if (cond == 8) {
3354 /* An unconditional trap ends the TB. */
3355 dc->is_br = 1;
3356 goto jmp_insn;
3357 } else {
3358 /* A conditional trap falls through to the next insn. */
b158a785 3359 gen_set_label(l1);
fe1755cb 3360 break;
cf495bcf
FB		 3361 }
3362 } else if (xop == 0x28) {
3363 rs1 = GET_FIELD(insn, 13, 17);
3364 switch(rs1) {
3365 case 0: /* rdy */
65fe7b09
BS		 3366#ifndef TARGET_SPARC64
3367 case 0x01 ... 0x0e: /* undefined in the SPARCv8
3368 manual, rdy on the microSPARC
3369 II */
3370 case 0x0f: /* stbar in the SPARCv8 manual,
3371 rdy on the microSPARC II */
3372 case 0x10 ... 0x1f: /* implementation-dependent in the
3373 SPARCv8 manual, rdy on the
3374 microSPARC II */
4a2ba232
FC		 3375 /* Read Asr17 */
3376 if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) {
97ea2859 3377 TCGv t = gen_dest_gpr(dc, rd);
4a2ba232 3378 /* Read Asr17 for a Leon3 monoprocessor */
97ea2859
RH		 3379 tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1));
3380 gen_store_gpr(dc, rd, t);
4a2ba232
FC		 3381 break;
3382 }
65fe7b09 3383#endif
97ea2859 3384 gen_store_gpr(dc, rd, cpu_y);
cf495bcf 3385 break;
3475187d 3386#ifdef TARGET_SPARC64
0f8a249a 3387 case 0x2: /* V9 rdccr */
20132b96 3388 update_psr(dc);
063c3675 3389 gen_helper_rdccr(cpu_dst, cpu_env);
97ea2859 3390 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3391 break;
0f8a249a 3392 case 0x3: /* V9 rdasi */
a6d567e5 3393 tcg_gen_movi_tl(cpu_dst, dc->asi);
97ea2859 3394 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3395 break;
0f8a249a 3396 case 0x4: /* V9 rdtick */
ccd4a219 3397 {
a7812ae4 3398 TCGv_ptr r_tickptr;
c9a46442 3399 TCGv_i32 r_const;
ccd4a219 3400
a7812ae4 3401 r_tickptr = tcg_temp_new_ptr();
c9a46442 3402 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3403 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3404 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3405 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3406 r_const);
a7812ae4 3407 tcg_temp_free_ptr(r_tickptr);
c9a46442 3408 tcg_temp_free_i32(r_const);
97ea2859 3409 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3410 }
3475187d 3411 break;
0f8a249a 3412 case 0x5: /* V9 rdpc */
2ea815ca 3413 {
97ea2859 3414 TCGv t = gen_dest_gpr(dc, rd);
22036a49 3415 if (unlikely(AM_CHECK(dc))) {
97ea2859 3416 tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL);
22036a49 3417 } else {
97ea2859 3418 tcg_gen_movi_tl(t, dc->pc);
22036a49 3419 }
97ea2859 3420 gen_store_gpr(dc, rd, t);
2ea815ca 3421 }
0f8a249a
BS		 3422 break;
3423 case 0x6: /* V9 rdfprs */
255e1fcb 3424 tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
97ea2859 3425 gen_store_gpr(dc, rd, cpu_dst);
3475187d 3426 break;
65fe7b09
BS		 3427 case 0xf: /* V9 membar */
3428 break; /* no effect */
0f8a249a 3429 case 0x13: /* Graphics Status */
5b12f1e8 3430 if (gen_trap_ifnofpu(dc)) {
725cb90b 3431 goto jmp_insn;
5b12f1e8 3432 }
97ea2859 3433 gen_store_gpr(dc, rd, cpu_gsr);
725cb90b 3434 break;
9d926598 3435 case 0x16: /* Softint */
e86ceb0d
RH		 3436 tcg_gen_ld32s_tl(cpu_dst, cpu_env,
3437 offsetof(CPUSPARCState, softint));
97ea2859 3438 gen_store_gpr(dc, rd, cpu_dst);
9d926598 3439 break;
0f8a249a 3440 case 0x17: /* Tick compare */
97ea2859 3441 gen_store_gpr(dc, rd, cpu_tick_cmpr);
83469015 3442 break;
0f8a249a 3443 case 0x18: /* System tick */
ccd4a219 3444 {
a7812ae4 3445 TCGv_ptr r_tickptr;
c9a46442 3446 TCGv_i32 r_const;
ccd4a219 3447
a7812ae4 3448 r_tickptr = tcg_temp_new_ptr();
c9a46442 3449 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3450 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3451 offsetof(CPUSPARCState, stick));
c9a46442
MCA		 3452 gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
3453 r_const);
a7812ae4 3454 tcg_temp_free_ptr(r_tickptr);
c9a46442 3455 tcg_temp_free_i32(r_const);
97ea2859 3456 gen_store_gpr(dc, rd, cpu_dst);
ccd4a219 3457 }
83469015 3458 break;
0f8a249a 3459 case 0x19: /* System tick compare */
97ea2859 3460 gen_store_gpr(dc, rd, cpu_stick_cmpr);
83469015 3461 break;
b8e31b3c
AT		 3462 case 0x1a: /* UltraSPARC-T1 Strand status */
3463 /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe
3464 * this ASR as impl. dep
3465 */
3466 CHECK_IU_FEATURE(dc, HYPV);
3467 {
3468 TCGv t = gen_dest_gpr(dc, rd);
3469 tcg_gen_movi_tl(t, 1UL);
3470 gen_store_gpr(dc, rd, t);
3471 }
3472 break;
0f8a249a
BS		 3473 case 0x10: /* Performance Control */
3474 case 0x11: /* Performance Instrumentation Counter */
3475 case 0x12: /* Dispatch Control */
3476 case 0x14: /* Softint set, WO */
3477 case 0x15: /* Softint clear, WO */
3475187d
FB		 3478#endif
3479 default:
cf495bcf
FB		 3480 goto illegal_insn;
3481 }
e8af50a3 3482#if !defined(CONFIG_USER_ONLY)
e9ebed4d 3483 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
3475187d 3484#ifndef TARGET_SPARC64
20132b96 3485 if (!supervisor(dc)) {
0f8a249a 3486 goto priv_insn;
20132b96
RH		 3487 }
3488 update_psr(dc);
063c3675 3489 gen_helper_rdpsr(cpu_dst, cpu_env);
e9ebed4d 3490#else
fb79ceb9 3491 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3492 if (!hypervisor(dc))
3493 goto priv_insn;
3494 rs1 = GET_FIELD(insn, 13, 17);
3495 switch (rs1) {
3496 case 0: // hpstate
f7f17ef7
AT		 3497 tcg_gen_ld_i64(cpu_dst, cpu_env,
3498 offsetof(CPUSPARCState, hpstate));
e9ebed4d
BS		 3499 break;
3500 case 1: // htstate
3501 // gen_op_rdhtstate();
3502 break;
3503 case 3: // hintp
255e1fcb 3504 tcg_gen_mov_tl(cpu_dst, cpu_hintp);
e9ebed4d
BS		 3505 break;
3506 case 5: // htba
255e1fcb 3507 tcg_gen_mov_tl(cpu_dst, cpu_htba);
e9ebed4d
BS		 3508 break;
3509 case 6: // hver
255e1fcb 3510 tcg_gen_mov_tl(cpu_dst, cpu_hver);
e9ebed4d
BS		 3511 break;
3512 case 31: // hstick_cmpr
255e1fcb 3513 tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
e9ebed4d
BS		 3514 break;
3515 default:
3516 goto illegal_insn;
3517 }
3518#endif
97ea2859 3519 gen_store_gpr(dc, rd, cpu_dst);
e8af50a3 3520 break;
3475187d 3521 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
de9e9d9f 3522 if (!supervisor(dc)) {
0f8a249a 3523 goto priv_insn;
de9e9d9f
RH		 3524 }
3525 cpu_tmp0 = get_temp_tl(dc);
3475187d
FB		 3526#ifdef TARGET_SPARC64
3527 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3528 switch (rs1) {
3529 case 0: // tpc
375ee38b 3530 {
a7812ae4 3531 TCGv_ptr r_tsptr;
375ee38b 3532
a7812ae4 3533 r_tsptr = tcg_temp_new_ptr();
8194f35a 3534 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
a7812ae4 3535 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3536 offsetof(trap_state, tpc));
a7812ae4 3537 tcg_temp_free_ptr(r_tsptr);
375ee38b 3538 }
0f8a249a
BS		 3539 break;
3540 case 1: // tnpc
375ee38b 3541 {
a7812ae4 3542 TCGv_ptr r_tsptr;
375ee38b 3543
a7812ae4 3544 r_tsptr = tcg_temp_new_ptr();
8194f35a 3545 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3546 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3547 offsetof(trap_state, tnpc));
a7812ae4 3548 tcg_temp_free_ptr(r_tsptr);
375ee38b 3549 }
0f8a249a
BS		 3550 break;
3551 case 2: // tstate
375ee38b 3552 {
a7812ae4 3553 TCGv_ptr r_tsptr;
375ee38b 3554
a7812ae4 3555 r_tsptr = tcg_temp_new_ptr();
8194f35a 3556 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 3557 tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
375ee38b 3558 offsetof(trap_state, tstate));
a7812ae4 3559 tcg_temp_free_ptr(r_tsptr);
375ee38b 3560 }
0f8a249a
BS		 3561 break;
3562 case 3: // tt
375ee38b 3563 {
45778f99 3564 TCGv_ptr r_tsptr = tcg_temp_new_ptr();
375ee38b 3565
8194f35a 3566 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
45778f99
RH		 3567 tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr,
3568 offsetof(trap_state, tt));
a7812ae4 3569 tcg_temp_free_ptr(r_tsptr);
375ee38b 3570 }
0f8a249a
BS		 3571 break;
3572 case 4: // tick
ccd4a219 3573 {
a7812ae4 3574 TCGv_ptr r_tickptr;
c9a46442 3575 TCGv_i32 r_const;
ccd4a219 3576
a7812ae4 3577 r_tickptr = tcg_temp_new_ptr();
c9a46442 3578 r_const = tcg_const_i32(dc->mem_idx);
ccd4a219 3579 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 3580 offsetof(CPUSPARCState, tick));
c9a46442
MCA		 3581 gen_helper_tick_get_count(cpu_tmp0, cpu_env,
3582 r_tickptr, r_const);
a7812ae4 3583 tcg_temp_free_ptr(r_tickptr);
c9a46442 3584 tcg_temp_free_i32(r_const);
ccd4a219 3585 }
0f8a249a
BS		 3586 break;
3587 case 5: // tba
255e1fcb 3588 tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
0f8a249a
BS		 3589 break;
3590 case 6: // pstate
45778f99
RH		 3591 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3592 offsetof(CPUSPARCState, pstate));
0f8a249a
BS		 3593 break;
3594 case 7: // tl
45778f99
RH		 3595 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3596 offsetof(CPUSPARCState, tl));
0f8a249a
BS		 3597 break;
3598 case 8: // pil
45778f99
RH		 3599 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3600 offsetof(CPUSPARCState, psrpil));
0f8a249a
BS		 3601 break;
3602 case 9: // cwp
063c3675 3603 gen_helper_rdcwp(cpu_tmp0, cpu_env);
0f8a249a
BS		 3604 break;
3605 case 10: // cansave
45778f99
RH		 3606 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3607 offsetof(CPUSPARCState, cansave));
0f8a249a
BS		 3608 break;
3609 case 11: // canrestore
45778f99
RH		 3610 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3611 offsetof(CPUSPARCState, canrestore));
0f8a249a
BS		 3612 break;
3613 case 12: // cleanwin
45778f99
RH		 3614 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3615 offsetof(CPUSPARCState, cleanwin));
0f8a249a
BS		 3616 break;
3617 case 13: // otherwin
45778f99
RH		 3618 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3619 offsetof(CPUSPARCState, otherwin));
0f8a249a
BS		 3620 break;
3621 case 14: // wstate
45778f99
RH		 3622 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3623 offsetof(CPUSPARCState, wstate));
0f8a249a 3624 break;
e9ebed4d 3625 case 16: // UA2005 gl
fb79ceb9 3626 CHECK_IU_FEATURE(dc, GL);
45778f99
RH		 3627 tcg_gen_ld32s_tl(cpu_tmp0, cpu_env,
3628 offsetof(CPUSPARCState, gl));
e9ebed4d
BS		 3629 break;
3630 case 26: // UA2005 strand status
fb79ceb9 3631 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 3632 if (!hypervisor(dc))
3633 goto priv_insn;
527067d8 3634 tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
e9ebed4d 3635 break;
0f8a249a 3636 case 31: // ver
255e1fcb 3637 tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
0f8a249a
BS		 3638 break;
3639 case 15: // fq
3640 default:
3641 goto illegal_insn;
3642 }
3475187d 3643#else
255e1fcb 3644 tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
3475187d 3645#endif
97ea2859 3646 gen_store_gpr(dc, rd, cpu_tmp0);
e8af50a3 3647 break;
3475187d
FB		 3648 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
3649#ifdef TARGET_SPARC64
063c3675 3650 gen_helper_flushw(cpu_env);
3475187d 3651#else
0f8a249a
BS		 3652 if (!supervisor(dc))
3653 goto priv_insn;
97ea2859 3654 gen_store_gpr(dc, rd, cpu_tbr);
3475187d 3655#endif
e8af50a3
FB		 3656 break;
3657#endif
0f8a249a 3658 } else if (xop == 0x34) { /* FPU Operations */
5b12f1e8 3659 if (gen_trap_ifnofpu(dc)) {
a80dde08 3660 goto jmp_insn;
5b12f1e8 3661 }
0f8a249a 3662 gen_op_clear_ieee_excp_and_FTT();
e8af50a3 3663 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3664 rs2 = GET_FIELD(insn, 27, 31);
3665 xop = GET_FIELD(insn, 18, 26);
02c79d78 3666
0f8a249a 3667 switch (xop) {
dc1a6971 3668 case 0x1: /* fmovs */
208ae657
RH		 3669 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
3670 gen_store_fpr_F(dc, rd, cpu_src1_32);
dc1a6971
BS		 3671 break;
3672 case 0x5: /* fnegs */
61f17f6e 3673 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs);
dc1a6971
BS		 3674 break;
3675 case 0x9: /* fabss */
61f17f6e 3676 gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss);
dc1a6971
BS		 3677 break;
3678 case 0x29: /* fsqrts */
3679 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3680 gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
dc1a6971
BS		 3681 break;
3682 case 0x2a: /* fsqrtd */
3683 CHECK_FPU_FEATURE(dc, FSQRT);
61f17f6e 3684 gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd);
dc1a6971
BS		 3685 break;
3686 case 0x2b: /* fsqrtq */
3687 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3688 gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq);
dc1a6971
BS		 3689 break;
3690 case 0x41: /* fadds */
61f17f6e 3691 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
dc1a6971
BS		 3692 break;
3693 case 0x42: /* faddd */
61f17f6e 3694 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
dc1a6971
BS		 3695 break;
3696 case 0x43: /* faddq */
3697 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3698 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
dc1a6971
BS		 3699 break;
3700 case 0x45: /* fsubs */
61f17f6e 3701 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
dc1a6971
BS		 3702 break;
3703 case 0x46: /* fsubd */
61f17f6e 3704 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
dc1a6971
BS		 3705 break;
3706 case 0x47: /* fsubq */
3707 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3708 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
dc1a6971
BS		 3709 break;
3710 case 0x49: /* fmuls */
3711 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3712 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
dc1a6971
BS		 3713 break;
3714 case 0x4a: /* fmuld */
3715 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3716 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
dc1a6971
BS		 3717 break;
3718 case 0x4b: /* fmulq */
3719 CHECK_FPU_FEATURE(dc, FLOAT128);
3720 CHECK_FPU_FEATURE(dc, FMUL);
61f17f6e 3721 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
dc1a6971
BS		 3722 break;
3723 case 0x4d: /* fdivs */
61f17f6e 3724 gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
dc1a6971
BS		 3725 break;
3726 case 0x4e: /* fdivd */
61f17f6e 3727 gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
dc1a6971
BS		 3728 break;
3729 case 0x4f: /* fdivq */
3730 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3731 gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq);
dc1a6971
BS		 3732 break;
3733 case 0x69: /* fsmuld */
3734 CHECK_FPU_FEATURE(dc, FSMULD);
61f17f6e 3735 gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld);
dc1a6971
BS		 3736 break;
3737 case 0x6e: /* fdmulq */
3738 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3739 gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
dc1a6971
BS		 3740 break;
3741 case 0xc4: /* fitos */
61f17f6e 3742 gen_fop_FF(dc, rd, rs2, gen_helper_fitos);
dc1a6971
BS		 3743 break;
3744 case 0xc6: /* fdtos */
61f17f6e 3745 gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
dc1a6971
BS		 3746 break;
3747 case 0xc7: /* fqtos */
3748 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3749 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos);
dc1a6971
BS		 3750 break;
3751 case 0xc8: /* fitod */
61f17f6e 3752 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod);
dc1a6971
BS		 3753 break;
3754 case 0xc9: /* fstod */
61f17f6e 3755 gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod);
dc1a6971
BS		 3756 break;
3757 case 0xcb: /* fqtod */
3758 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3759 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod);
dc1a6971
BS		 3760 break;
3761 case 0xcc: /* fitoq */
3762 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3763 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq);
dc1a6971
BS		 3764 break;
3765 case 0xcd: /* fstoq */
3766 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3767 gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq);
dc1a6971
BS		 3768 break;
3769 case 0xce: /* fdtoq */
3770 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3771 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq);
dc1a6971
BS		 3772 break;
3773 case 0xd1: /* fstoi */
61f17f6e 3774 gen_fop_FF(dc, rd, rs2, gen_helper_fstoi);
dc1a6971
BS		 3775 break;
3776 case 0xd2: /* fdtoi */
61f17f6e 3777 gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi);
dc1a6971
BS		 3778 break;
3779 case 0xd3: /* fqtoi */
3780 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3781 gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
dc1a6971 3782 break;
3475187d 3783#ifdef TARGET_SPARC64
dc1a6971 3784 case 0x2: /* V9 fmovd */
96eda024
RH		 3785 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
3786 gen_store_fpr_D(dc, rd, cpu_src1_64);
dc1a6971
BS		 3787 break;
3788 case 0x3: /* V9 fmovq */
3789 CHECK_FPU_FEATURE(dc, FLOAT128);
f9c816c0 3790 gen_move_Q(dc, rd, rs2);
dc1a6971
BS		 3791 break;
3792 case 0x6: /* V9 fnegd */
61f17f6e 3793 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
dc1a6971
BS		 3794 break;
3795 case 0x7: /* V9 fnegq */
3796 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3797 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
dc1a6971
BS		 3798 break;
3799 case 0xa: /* V9 fabsd */
61f17f6e 3800 gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
dc1a6971
BS		 3801 break;
3802 case 0xb: /* V9 fabsq */
3803 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3804 gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
dc1a6971
BS		 3805 break;
3806 case 0x81: /* V9 fstox */
61f17f6e 3807 gen_fop_DF(dc, rd, rs2, gen_helper_fstox);
dc1a6971
BS		 3808 break;
3809 case 0x82: /* V9 fdtox */
61f17f6e 3810 gen_fop_DD(dc, rd, rs2, gen_helper_fdtox);
dc1a6971
BS		 3811 break;
3812 case 0x83: /* V9 fqtox */
3813 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3814 gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox);
dc1a6971
BS		 3815 break;
3816 case 0x84: /* V9 fxtos */
61f17f6e 3817 gen_fop_FD(dc, rd, rs2, gen_helper_fxtos);
dc1a6971
BS		 3818 break;
3819 case 0x88: /* V9 fxtod */
61f17f6e 3820 gen_fop_DD(dc, rd, rs2, gen_helper_fxtod);
dc1a6971
BS		 3821 break;
3822 case 0x8c: /* V9 fxtoq */
3823 CHECK_FPU_FEATURE(dc, FLOAT128);
61f17f6e 3824 gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq);
dc1a6971 3825 break;
0f8a249a 3826#endif
dc1a6971
BS		 3827 default:
3828 goto illegal_insn;
0f8a249a
BS		 3829 }
3830 } else if (xop == 0x35) { /* FPU Operations */
3475187d 3831#ifdef TARGET_SPARC64
0f8a249a 3832 int cond;
3475187d 3833#endif
5b12f1e8 3834 if (gen_trap_ifnofpu(dc)) {
a80dde08 3835 goto jmp_insn;
5b12f1e8 3836 }
0f8a249a 3837 gen_op_clear_ieee_excp_and_FTT();
cf495bcf 3838 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a
BS		 3839 rs2 = GET_FIELD(insn, 27, 31);
3840 xop = GET_FIELD(insn, 18, 26);
dcf24905 3841
690995a6
RH		 3842#ifdef TARGET_SPARC64
3843#define FMOVR(sz) \
3844 do { \
3845 DisasCompare cmp; \
e7c8afb9 3846 cond = GET_FIELD_SP(insn, 10, 12); \
9d1d4e34 3847 cpu_src1 = get_src1(dc, insn); \
690995a6
RH		 3848 gen_compare_reg(&cmp, cond, cpu_src1); \
3849 gen_fmov##sz(dc, &cmp, rd, rs2); \
3850 free_compare(&cmp); \
3851 } while (0)
3852
3853 if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
3854 FMOVR(s);
0f8a249a
BS		 3855 break;
3856 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
690995a6 3857 FMOVR(d);
0f8a249a
BS		 3858 break;
3859 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
64a88d5d 3860 CHECK_FPU_FEATURE(dc, FLOAT128);
690995a6 3861 FMOVR(q);
1f587329 3862 break;
0f8a249a 3863 }
690995a6 3864#undef FMOVR
0f8a249a
BS		 3865#endif
3866 switch (xop) {
3475187d 3867#ifdef TARGET_SPARC64
7e480893
RH		 3868#define FMOVCC(fcc, sz) \
3869 do { \
3870 DisasCompare cmp; \
714547bb 3871 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3872 gen_fcompare(&cmp, fcc, cond); \
3873 gen_fmov##sz(dc, &cmp, rd, rs2); \
3874 free_compare(&cmp); \
3875 } while (0)
3876
0f8a249a 3877 case 0x001: /* V9 fmovscc %fcc0 */
7e480893 3878 FMOVCC(0, s);
0f8a249a
BS		 3879 break;
3880 case 0x002: /* V9 fmovdcc %fcc0 */
7e480893 3881 FMOVCC(0, d);
0f8a249a
BS		 3882 break;
3883 case 0x003: /* V9 fmovqcc %fcc0 */
64a88d5d 3884 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3885 FMOVCC(0, q);
1f587329 3886 break;
0f8a249a 3887 case 0x041: /* V9 fmovscc %fcc1 */
7e480893 3888 FMOVCC(1, s);
0f8a249a
BS		 3889 break;
3890 case 0x042: /* V9 fmovdcc %fcc1 */
7e480893 3891 FMOVCC(1, d);
0f8a249a
BS		 3892 break;
3893 case 0x043: /* V9 fmovqcc %fcc1 */
64a88d5d 3894 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3895 FMOVCC(1, q);
1f587329 3896 break;
0f8a249a 3897 case 0x081: /* V9 fmovscc %fcc2 */
7e480893 3898 FMOVCC(2, s);
0f8a249a
BS		 3899 break;
3900 case 0x082: /* V9 fmovdcc %fcc2 */
7e480893 3901 FMOVCC(2, d);
0f8a249a
BS		 3902 break;
3903 case 0x083: /* V9 fmovqcc %fcc2 */
64a88d5d 3904 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3905 FMOVCC(2, q);
1f587329 3906 break;
0f8a249a 3907 case 0x0c1: /* V9 fmovscc %fcc3 */
7e480893 3908 FMOVCC(3, s);
0f8a249a
BS		 3909 break;
3910 case 0x0c2: /* V9 fmovdcc %fcc3 */
7e480893 3911 FMOVCC(3, d);
0f8a249a
BS		 3912 break;
3913 case 0x0c3: /* V9 fmovqcc %fcc3 */
64a88d5d 3914 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3915 FMOVCC(3, q);
1f587329 3916 break;
7e480893
RH		 3917#undef FMOVCC
3918#define FMOVCC(xcc, sz) \
3919 do { \
3920 DisasCompare cmp; \
714547bb 3921 cond = GET_FIELD_SP(insn, 14, 17); \
7e480893
RH		 3922 gen_compare(&cmp, xcc, cond, dc); \
3923 gen_fmov##sz(dc, &cmp, rd, rs2); \
3924 free_compare(&cmp); \
3925 } while (0)
19f329ad 3926
0f8a249a 3927 case 0x101: /* V9 fmovscc %icc */
7e480893 3928 FMOVCC(0, s);
0f8a249a
BS		 3929 break;
3930 case 0x102: /* V9 fmovdcc %icc */
7e480893 3931 FMOVCC(0, d);
b7d69dc2 3932 break;
0f8a249a 3933 case 0x103: /* V9 fmovqcc %icc */
64a88d5d 3934 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3935 FMOVCC(0, q);
1f587329 3936 break;
0f8a249a 3937 case 0x181: /* V9 fmovscc %xcc */
7e480893 3938 FMOVCC(1, s);
0f8a249a
BS		 3939 break;
3940 case 0x182: /* V9 fmovdcc %xcc */
7e480893 3941 FMOVCC(1, d);
0f8a249a
BS		 3942 break;
3943 case 0x183: /* V9 fmovqcc %xcc */
64a88d5d 3944 CHECK_FPU_FEATURE(dc, FLOAT128);
7e480893 3945 FMOVCC(1, q);
1f587329 3946 break;
7e480893 3947#undef FMOVCC
1f587329
BS		 3948#endif
3949 case 0x51: /* fcmps, V9 %fcc */
208ae657
RH		 3950 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3951 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3952 gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a 3953 break;
1f587329 3954 case 0x52: /* fcmpd, V9 %fcc */
03fb8cfc
RH		 3955 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3956 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3957 gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3958 break;
1f587329 3959 case 0x53: /* fcmpq, V9 %fcc */
64a88d5d 3960 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3961 gen_op_load_fpr_QT0(QFPREG(rs1));
3962 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3963 gen_op_fcmpq(rd & 3);
1f587329 3964 break;
0f8a249a 3965 case 0x55: /* fcmpes, V9 %fcc */
208ae657
RH		 3966 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
3967 cpu_src2_32 = gen_load_fpr_F(dc, rs2);
3968 gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
0f8a249a
BS		 3969 break;
3970 case 0x56: /* fcmped, V9 %fcc */
03fb8cfc
RH		 3971 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
3972 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
3973 gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
0f8a249a 3974 break;
1f587329 3975 case 0x57: /* fcmpeq, V9 %fcc */
64a88d5d 3976 CHECK_FPU_FEATURE(dc, FLOAT128);
1f587329
BS		 3977 gen_op_load_fpr_QT0(QFPREG(rs1));
3978 gen_op_load_fpr_QT1(QFPREG(rs2));
7e8c2b6c 3979 gen_op_fcmpeq(rd & 3);
1f587329 3980 break;
0f8a249a
BS		 3981 default:
3982 goto illegal_insn;
3983 }
0f8a249a 3984 } else if (xop == 0x2) {
97ea2859 3985 TCGv dst = gen_dest_gpr(dc, rd);
e80cfcfc 3986 rs1 = GET_FIELD(insn, 13, 17);
0f8a249a 3987 if (rs1 == 0) {
97ea2859 3988 /* clr/mov shortcut : or %g0, x, y -> mov x, y */
0f8a249a 3989 if (IS_IMM) { /* immediate */
67526b20 3990 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 3991 tcg_gen_movi_tl(dst, simm);
3992 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 3993 } else { /* register */
3994 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 3995 if (rs2 == 0) {
3996 tcg_gen_movi_tl(dst, 0);
3997 gen_store_gpr(dc, rd, dst);
3998 } else {
3999 cpu_src2 = gen_load_gpr(dc, rs2);
4000 gen_store_gpr(dc, rd, cpu_src2);
4001 }
0f8a249a 4002 }
0f8a249a 4003 } else {
9d1d4e34 4004 cpu_src1 = get_src1(dc, insn);
0f8a249a 4005 if (IS_IMM) { /* immediate */
67526b20 4006 simm = GET_FIELDs(insn, 19, 31);
97ea2859
RH		 4007 tcg_gen_ori_tl(dst, cpu_src1, simm);
4008 gen_store_gpr(dc, rd, dst);
0f8a249a 4009 } else { /* register */
0f8a249a 4010 rs2 = GET_FIELD(insn, 27, 31);
97ea2859
RH		 4011 if (rs2 == 0) {
4012 /* mov shortcut: or x, %g0, y -> mov x, y */
4013 gen_store_gpr(dc, rd, cpu_src1);
4014 } else {
4015 cpu_src2 = gen_load_gpr(dc, rs2);
4016 tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
4017 gen_store_gpr(dc, rd, dst);
4018 }
0f8a249a 4019 }
0f8a249a 4020 }
83469015 4021#ifdef TARGET_SPARC64
0f8a249a 4022 } else if (xop == 0x25) { /* sll, V9 sllx */
9d1d4e34 4023 cpu_src1 = get_src1(dc, insn);
0f8a249a 4024 if (IS_IMM) { /* immediate */
67526b20 4025 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4026 if (insn & (1 << 12)) {
67526b20 4027 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4028 } else {
67526b20 4029 tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
1a2fb1c0 4030 }
0f8a249a 4031 } else { /* register */
83469015 4032 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4033 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4034 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4035 if (insn & (1 << 12)) {
6ae20372 4036 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
1a2fb1c0 4037 } else {
6ae20372 4038 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
1a2fb1c0 4039 }
01b1fa6d 4040 tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
83469015 4041 }
97ea2859 4042 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4043 } else if (xop == 0x26) { /* srl, V9 srlx */
9d1d4e34 4044 cpu_src1 = get_src1(dc, insn);
0f8a249a 4045 if (IS_IMM) { /* immediate */
67526b20 4046 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4047 if (insn & (1 << 12)) {
67526b20 4048 tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4049 } else {
6ae20372 4050 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
67526b20 4051 tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4052 }
0f8a249a 4053 } else { /* register */
83469015 4054 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4055 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4056 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4057 if (insn & (1 << 12)) {
6ae20372
BS		 4058 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4059 tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4060 } else {
6ae20372
BS		 4061 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
4062 tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
4063 tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4064 }
83469015 4065 }
97ea2859 4066 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a 4067 } else if (xop == 0x27) { /* sra, V9 srax */
9d1d4e34 4068 cpu_src1 = get_src1(dc, insn);
0f8a249a 4069 if (IS_IMM) { /* immediate */
67526b20 4070 simm = GET_FIELDs(insn, 20, 31);
1a2fb1c0 4071 if (insn & (1 << 12)) {
67526b20 4072 tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
1a2fb1c0 4073 } else {
97ea2859 4074 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
67526b20 4075 tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
1a2fb1c0 4076 }
0f8a249a 4077 } else { /* register */
83469015 4078 rs2 = GET_FIELD(insn, 27, 31);
97ea2859 4079 cpu_src2 = gen_load_gpr(dc, rs2);
de9e9d9f 4080 cpu_tmp0 = get_temp_tl(dc);
1a2fb1c0 4081 if (insn & (1 << 12)) {
6ae20372
BS		 4082 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
4083 tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
1a2fb1c0 4084 } else {
6ae20372 4085 tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
97ea2859 4086 tcg_gen_ext32s_i64(cpu_dst, cpu_src1);
6ae20372 4087 tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
1a2fb1c0 4088 }
83469015 4089 }
97ea2859 4090 gen_store_gpr(dc, rd, cpu_dst);
e80cfcfc 4091#endif
fcc72045 4092 } else if (xop < 0x36) {
cf495bcf 4093 if (xop < 0x20) {
9d1d4e34
RH		 4094 cpu_src1 = get_src1(dc, insn);
4095 cpu_src2 = get_src2(dc, insn);
cf495bcf 4096 switch (xop & ~0x10) {
b89e94af 4097 case 0x0: /* add */
97ea2859
RH		 4098 if (xop & 0x10) {
4099 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
4100 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4101 dc->cc_op = CC_OP_ADD;
41d72852 4102 } else {
97ea2859 4103 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4104 }
cf495bcf 4105 break;
b89e94af 4106 case 0x1: /* and */
97ea2859 4107 tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4108 if (xop & 0x10) {
38482a77
BS		 4109 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4110 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4111 dc->cc_op = CC_OP_LOGIC;
41d72852 4112 }
cf495bcf 4113 break;
b89e94af 4114 case 0x2: /* or */
97ea2859 4115 tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4116 if (xop & 0x10) {
38482a77
BS		 4117 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4118 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4119 dc->cc_op = CC_OP_LOGIC;
8393617c 4120 }
0f8a249a 4121 break;
b89e94af 4122 case 0x3: /* xor */
97ea2859 4123 tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4124 if (xop & 0x10) {
38482a77
BS		 4125 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4126 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4127 dc->cc_op = CC_OP_LOGIC;
8393617c 4128 }
cf495bcf 4129 break;
b89e94af 4130 case 0x4: /* sub */
97ea2859
RH		 4131 if (xop & 0x10) {
4132 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
4133 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
4134 dc->cc_op = CC_OP_SUB;
41d72852 4135 } else {
97ea2859 4136 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
41d72852 4137 }
cf495bcf 4138 break;
b89e94af 4139 case 0x5: /* andn */
97ea2859 4140 tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4141 if (xop & 0x10) {
38482a77
BS		 4142 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4143 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4144 dc->cc_op = CC_OP_LOGIC;
8393617c 4145 }
cf495bcf 4146 break;
b89e94af 4147 case 0x6: /* orn */
97ea2859 4148 tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4149 if (xop & 0x10) {
38482a77
BS		 4150 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4151 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4152 dc->cc_op = CC_OP_LOGIC;
8393617c 4153 }
cf495bcf 4154 break;
b89e94af 4155 case 0x7: /* xorn */
97ea2859 4156 tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
8393617c 4157 if (xop & 0x10) {
38482a77
BS		 4158 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4159 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4160 dc->cc_op = CC_OP_LOGIC;
8393617c 4161 }
cf495bcf 4162 break;
b89e94af 4163 case 0x8: /* addx, V9 addc */
70c48285
RH		 4164 gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4165 (xop & 0x10));
cf495bcf 4166 break;
ded3ab80 4167#ifdef TARGET_SPARC64
0f8a249a 4168 case 0x9: /* V9 mulx */
97ea2859 4169 tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
ded3ab80
PB		 4170 break;
4171#endif
b89e94af 4172 case 0xa: /* umul */
64a88d5d 4173 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4174 gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4175 if (xop & 0x10) {
38482a77
BS		 4176 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4177 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4178 dc->cc_op = CC_OP_LOGIC;
8393617c 4179 }
cf495bcf 4180 break;
b89e94af 4181 case 0xb: /* smul */
64a88d5d 4182 CHECK_IU_FEATURE(dc, MUL);
6ae20372 4183 gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
8393617c 4184 if (xop & 0x10) {
38482a77
BS		 4185 tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
4186 tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
4187 dc->cc_op = CC_OP_LOGIC;
8393617c 4188 }
cf495bcf 4189 break;
b89e94af 4190 case 0xc: /* subx, V9 subc */
70c48285
RH		 4191 gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
4192 (xop & 0x10));
cf495bcf 4193 break;
ded3ab80 4194#ifdef TARGET_SPARC64
0f8a249a 4195 case 0xd: /* V9 udivx */
c28ae41e 4196 gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
ded3ab80
PB		 4197 break;
4198#endif
b89e94af 4199 case 0xe: /* udiv */
64a88d5d 4200 CHECK_IU_FEATURE(dc, DIV);
8393617c 4201 if (xop & 0x10) {
7a5e4488
BS		 4202 gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1,
4203 cpu_src2);
6c78ea32 4204 dc->cc_op = CC_OP_DIV;
0fcec41e 4205 } else {
7a5e4488
BS		 4206 gen_helper_udiv(cpu_dst, cpu_env, cpu_src1,
4207 cpu_src2);
8393617c 4208 }
cf495bcf 4209 break;
b89e94af 4210 case 0xf: /* sdiv */
64a88d5d 4211 CHECK_IU_FEATURE(dc, DIV);
8393617c 4212 if (xop & 0x10) {
7a5e4488
BS		 4213 gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1,
4214 cpu_src2);
6c78ea32 4215 dc->cc_op = CC_OP_DIV;
0fcec41e 4216 } else {
7a5e4488
BS		 4217 gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1,
4218 cpu_src2);
8393617c 4219 }
cf495bcf
FB		 4220 break;
4221 default:
4222 goto illegal_insn;
4223 }
97ea2859 4224 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4225 } else {
9d1d4e34
RH		 4226 cpu_src1 = get_src1(dc, insn);
4227 cpu_src2 = get_src2(dc, insn);
cf495bcf 4228 switch (xop) {
0f8a249a 4229 case 0x20: /* taddcc */
a2ea4aa9 4230 gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4231 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4232 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD);
4233 dc->cc_op = CC_OP_TADD;
0f8a249a
BS		 4234 break;
4235 case 0x21: /* tsubcc */
a2ea4aa9 4236 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4237 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92
BS		 4238 tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB);
4239 dc->cc_op = CC_OP_TSUB;
0f8a249a
BS		 4240 break;
4241 case 0x22: /* taddcctv */
a2ea4aa9
RH		 4242 gen_helper_taddcctv(cpu_dst, cpu_env,
4243 cpu_src1, cpu_src2);
97ea2859 4244 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4245 dc->cc_op = CC_OP_TADDTV;
0f8a249a
BS		 4246 break;
4247 case 0x23: /* tsubcctv */
a2ea4aa9
RH		 4248 gen_helper_tsubcctv(cpu_dst, cpu_env,
4249 cpu_src1, cpu_src2);
97ea2859 4250 gen_store_gpr(dc, rd, cpu_dst);
3b2d1e92 4251 dc->cc_op = CC_OP_TSUBTV;
0f8a249a 4252 break;
cf495bcf 4253 case 0x24: /* mulscc */
20132b96 4254 update_psr(dc);
6ae20372 4255 gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4256 gen_store_gpr(dc, rd, cpu_dst);
d084469c
BS		 4257 tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
4258 dc->cc_op = CC_OP_ADD;
cf495bcf 4259 break;
83469015 4260#ifndef TARGET_SPARC64
0f8a249a 4261 case 0x25: /* sll */
e35298cd 4262 if (IS_IMM) { /* immediate */
67526b20
BS		 4263 simm = GET_FIELDs(insn, 20, 31);
4264 tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4265 } else { /* register */
de9e9d9f 4266 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4267 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4268 tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
4269 }
97ea2859 4270 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4271 break;
83469015 4272 case 0x26: /* srl */
e35298cd 4273 if (IS_IMM) { /* immediate */
67526b20
BS		 4274 simm = GET_FIELDs(insn, 20, 31);
4275 tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4276 } else { /* register */
de9e9d9f 4277 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4278 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4279 tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
4280 }
97ea2859 4281 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4282 break;
83469015 4283 case 0x27: /* sra */
e35298cd 4284 if (IS_IMM) { /* immediate */
67526b20
BS		 4285 simm = GET_FIELDs(insn, 20, 31);
4286 tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
e35298cd 4287 } else { /* register */
de9e9d9f 4288 cpu_tmp0 = get_temp_tl(dc);
e35298cd
BS		 4289 tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
4290 tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
4291 }
97ea2859 4292 gen_store_gpr(dc, rd, cpu_dst);
cf495bcf 4293 break;
83469015 4294#endif
cf495bcf
FB		 4295 case 0x30:
4296 {
de9e9d9f 4297 cpu_tmp0 = get_temp_tl(dc);
cf495bcf 4298 switch(rd) {
3475187d 4299 case 0: /* wry */
5068cbd9
BS		 4300 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4301 tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
cf495bcf 4302 break;
65fe7b09
BS		 4303#ifndef TARGET_SPARC64
4304 case 0x01 ... 0x0f: /* undefined in the
4305 SPARCv8 manual, nop
4306 on the microSPARC
4307 II */
4308 case 0x10 ... 0x1f: /* implementation-dependent
4309 in the SPARCv8
4310 manual, nop on the
4311 microSPARC II */
d1c36ba7
RH		 4312 if ((rd == 0x13) && (dc->def->features &
4313 CPU_FEATURE_POWERDOWN)) {
4314 /* LEON3 power-down */
1cf892ca 4315 save_state(dc);
d1c36ba7
RH		 4316 gen_helper_power_down(cpu_env);
4317 }
65fe7b09
BS		 4318 break;
4319#else
0f8a249a 4320 case 0x2: /* V9 wrccr */
7b04bd5c
RH		 4321 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4322 gen_helper_wrccr(cpu_env, cpu_tmp0);
8393617c
BS		 4323 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4324 dc->cc_op = CC_OP_FLAGS;
0f8a249a
BS		 4325 break;
4326 case 0x3: /* V9 wrasi */
7b04bd5c
RH		 4327 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4328 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff);
a6d567e5
RH		 4329 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4330 offsetof(CPUSPARCState, asi));
4331 /* End TB to notice changed ASI. */
4332 save_state(dc);
4333 gen_op_next_insn();
4334 tcg_gen_exit_tb(0);
4335 dc->is_br = 1;
0f8a249a
BS		 4336 break;
4337 case 0x6: /* V9 wrfprs */
7b04bd5c
RH		 4338 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4339 tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
f9c816c0 4340 dc->fprs_dirty = 0;
66442b07 4341 save_state(dc);
3299908c 4342 gen_op_next_insn();
57fec1fe 4343 tcg_gen_exit_tb(0);
3299908c 4344 dc->is_br = 1;
0f8a249a
BS		 4345 break;
4346 case 0xf: /* V9 sir, nop if user */
3475187d 4347#if !defined(CONFIG_USER_ONLY)
6ad6135d 4348 if (supervisor(dc)) {
1a2fb1c0 4349 ; // XXX
6ad6135d 4350 }
3475187d 4351#endif
0f8a249a
BS		 4352 break;
4353 case 0x13: /* Graphics Status */
5b12f1e8 4354 if (gen_trap_ifnofpu(dc)) {
725cb90b 4355 goto jmp_insn;
5b12f1e8 4356 }
255e1fcb 4357 tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
0f8a249a 4358 break;
9d926598
BS		 4359 case 0x14: /* Softint set */
4360 if (!supervisor(dc))
4361 goto illegal_insn;
aeff993c
RH		 4362 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4363 gen_helper_set_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4364 break;
4365 case 0x15: /* Softint clear */
4366 if (!supervisor(dc))
4367 goto illegal_insn;
aeff993c
RH		 4368 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4369 gen_helper_clear_softint(cpu_env, cpu_tmp0);
9d926598
BS		 4370 break;
4371 case 0x16: /* Softint write */
4372 if (!supervisor(dc))
4373 goto illegal_insn;
aeff993c
RH		 4374 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4375 gen_helper_write_softint(cpu_env, cpu_tmp0);
9d926598 4376 break;
0f8a249a 4377 case 0x17: /* Tick compare */
83469015 4378#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4379 if (!supervisor(dc))
4380 goto illegal_insn;
83469015 4381#endif
ccd4a219 4382 {
a7812ae4 4383 TCGv_ptr r_tickptr;
ccd4a219 4384
255e1fcb 4385 tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
6ae20372 4386 cpu_src2);
a7812ae4 4387 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4388 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4389 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4390 gen_helper_tick_set_limit(r_tickptr,
4391 cpu_tick_cmpr);
4392 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4393 }
0f8a249a
BS		 4394 break;
4395 case 0x18: /* System tick */
83469015 4396#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4397 if (!supervisor(dc))
4398 goto illegal_insn;
83469015 4399#endif
ccd4a219 4400 {
a7812ae4 4401 TCGv_ptr r_tickptr;
ccd4a219 4402
7b04bd5c 4403 tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
6ae20372 4404 cpu_src2);
a7812ae4 4405 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4406 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4407 offsetof(CPUSPARCState, stick));
a7812ae4 4408 gen_helper_tick_set_count(r_tickptr,
7b04bd5c 4409 cpu_tmp0);
a7812ae4 4410 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4411 }
0f8a249a
BS		 4412 break;
4413 case 0x19: /* System tick compare */
83469015 4414#if !defined(CONFIG_USER_ONLY)
0f8a249a
BS		 4415 if (!supervisor(dc))
4416 goto illegal_insn;
3475187d 4417#endif
ccd4a219 4418 {
a7812ae4 4419 TCGv_ptr r_tickptr;
ccd4a219 4420
255e1fcb 4421 tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
6ae20372 4422 cpu_src2);
a7812ae4 4423 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4424 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4425 offsetof(CPUSPARCState, stick));
a7812ae4
PB		 4426 gen_helper_tick_set_limit(r_tickptr,
4427 cpu_stick_cmpr);
4428 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4429 }
0f8a249a 4430 break;
83469015 4431
0f8a249a 4432 case 0x10: /* Performance Control */
77f193da
BS		 4433 case 0x11: /* Performance Instrumentation
4434 Counter */
0f8a249a 4435 case 0x12: /* Dispatch Control */
83469015 4436#endif
3475187d 4437 default:
cf495bcf
FB		 4438 goto illegal_insn;
4439 }
4440 }
4441 break;
e8af50a3 4442#if !defined(CONFIG_USER_ONLY)
af7bf89b 4443 case 0x31: /* wrpsr, V9 saved, restored */
e8af50a3 4444 {
0f8a249a
BS		 4445 if (!supervisor(dc))
4446 goto priv_insn;
3475187d 4447#ifdef TARGET_SPARC64
0f8a249a
BS		 4448 switch (rd) {
4449 case 0:
063c3675 4450 gen_helper_saved(cpu_env);
0f8a249a
BS		 4451 break;
4452 case 1:
063c3675 4453 gen_helper_restored(cpu_env);
0f8a249a 4454 break;
e9ebed4d
BS		 4455 case 2: /* UA2005 allclean */
4456 case 3: /* UA2005 otherw */
4457 case 4: /* UA2005 normalw */
4458 case 5: /* UA2005 invalw */
4459 // XXX
0f8a249a 4460 default:
3475187d
FB		 4461 goto illegal_insn;
4462 }
4463#else
de9e9d9f 4464 cpu_tmp0 = get_temp_tl(dc);
7b04bd5c
RH		 4465 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
4466 gen_helper_wrpsr(cpu_env, cpu_tmp0);
8393617c
BS		 4467 tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
4468 dc->cc_op = CC_OP_FLAGS;
66442b07 4469 save_state(dc);
9e61bde5 4470 gen_op_next_insn();
57fec1fe 4471 tcg_gen_exit_tb(0);
0f8a249a 4472 dc->is_br = 1;
3475187d 4473#endif
e8af50a3
FB		 4474 }
4475 break;
af7bf89b 4476 case 0x32: /* wrwim, V9 wrpr */
e8af50a3 4477 {
0f8a249a
BS		 4478 if (!supervisor(dc))
4479 goto priv_insn;
de9e9d9f 4480 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4481 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3475187d 4482#ifdef TARGET_SPARC64
0f8a249a
BS		 4483 switch (rd) {
4484 case 0: // tpc
375ee38b 4485 {
a7812ae4 4486 TCGv_ptr r_tsptr;
375ee38b 4487
a7812ae4 4488 r_tsptr = tcg_temp_new_ptr();
8194f35a 4489 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4490 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4491 offsetof(trap_state, tpc));
a7812ae4 4492 tcg_temp_free_ptr(r_tsptr);
375ee38b 4493 }
0f8a249a
BS		 4494 break;
4495 case 1: // tnpc
375ee38b 4496 {
a7812ae4 4497 TCGv_ptr r_tsptr;
375ee38b 4498
a7812ae4 4499 r_tsptr = tcg_temp_new_ptr();
8194f35a 4500 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4501 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
375ee38b 4502 offsetof(trap_state, tnpc));
a7812ae4 4503 tcg_temp_free_ptr(r_tsptr);
375ee38b 4504 }
0f8a249a
BS		 4505 break;
4506 case 2: // tstate
375ee38b 4507 {
a7812ae4 4508 TCGv_ptr r_tsptr;
375ee38b 4509
a7812ae4 4510 r_tsptr = tcg_temp_new_ptr();
8194f35a 4511 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
ece43b8d 4512 tcg_gen_st_tl(cpu_tmp0, r_tsptr,
77f193da
BS		 4513 offsetof(trap_state,
4514 tstate));
a7812ae4 4515 tcg_temp_free_ptr(r_tsptr);
375ee38b 4516 }
0f8a249a
BS		 4517 break;
4518 case 3: // tt
375ee38b 4519 {
a7812ae4 4520 TCGv_ptr r_tsptr;
375ee38b 4521
a7812ae4 4522 r_tsptr = tcg_temp_new_ptr();
8194f35a 4523 gen_load_trap_state_at_tl(r_tsptr, cpu_env);
7b9e066b
RH		 4524 tcg_gen_st32_tl(cpu_tmp0, r_tsptr,
4525 offsetof(trap_state, tt));
a7812ae4 4526 tcg_temp_free_ptr(r_tsptr);
375ee38b 4527 }
0f8a249a
BS		 4528 break;
4529 case 4: // tick
ccd4a219 4530 {
a7812ae4 4531 TCGv_ptr r_tickptr;
ccd4a219 4532
a7812ae4 4533 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4534 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4535 offsetof(CPUSPARCState, tick));
a7812ae4
PB		 4536 gen_helper_tick_set_count(r_tickptr,
4537 cpu_tmp0);
4538 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4539 }
0f8a249a
BS		 4540 break;
4541 case 5: // tba
255e1fcb 4542 tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
0f8a249a
BS		 4543 break;
4544 case 6: // pstate
6234ac09
RH		 4545 save_state(dc);
4546 gen_helper_wrpstate(cpu_env, cpu_tmp0);
4547 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4548 break;
4549 case 7: // tl
6234ac09 4550 save_state(dc);
7b9e066b 4551 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
6234ac09
RH		 4552 offsetof(CPUSPARCState, tl));
4553 dc->npc = DYNAMIC_PC;
0f8a249a
BS		 4554 break;
4555 case 8: // pil
063c3675 4556 gen_helper_wrpil(cpu_env, cpu_tmp0);
0f8a249a
BS		 4557 break;
4558 case 9: // cwp
063c3675 4559 gen_helper_wrcwp(cpu_env, cpu_tmp0);
0f8a249a
BS		 4560 break;
4561 case 10: // cansave
7b9e066b
RH		 4562 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4563 offsetof(CPUSPARCState,
4564 cansave));
0f8a249a
BS		 4565 break;
4566 case 11: // canrestore
7b9e066b
RH		 4567 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4568 offsetof(CPUSPARCState,
4569 canrestore));
0f8a249a
BS		 4570 break;
4571 case 12: // cleanwin
7b9e066b
RH		 4572 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4573 offsetof(CPUSPARCState,
4574 cleanwin));
0f8a249a
BS		 4575 break;
4576 case 13: // otherwin
7b9e066b
RH		 4577 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4578 offsetof(CPUSPARCState,
4579 otherwin));
0f8a249a
BS		 4580 break;
4581 case 14: // wstate
7b9e066b
RH		 4582 tcg_gen_st32_tl(cpu_tmp0, cpu_env,
4583 offsetof(CPUSPARCState,
4584 wstate));
0f8a249a 4585 break;
e9ebed4d 4586 case 16: // UA2005 gl
fb79ceb9 4587 CHECK_IU_FEATURE(dc, GL);
cbc3a6a4 4588 gen_helper_wrgl(cpu_env, cpu_tmp0);
e9ebed4d
BS		 4589 break;
4590 case 26: // UA2005 strand status
fb79ceb9 4591 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4592 if (!hypervisor(dc))
4593 goto priv_insn;
527067d8 4594 tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
e9ebed4d 4595 break;
0f8a249a
BS		 4596 default:
4597 goto illegal_insn;
4598 }
3475187d 4599#else
7b9e066b
RH		 4600 tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0);
4601 if (dc->def->nwindows != 32) {
4602 tcg_gen_andi_tl(cpu_wim, cpu_wim,
c93e7817 4603 (1 << dc->def->nwindows) - 1);
7b9e066b 4604 }
3475187d 4605#endif
e8af50a3
FB		 4606 }
4607 break;
e9ebed4d 4608 case 0x33: /* wrtbr, UA2005 wrhpr */
e8af50a3 4609 {
e9ebed4d 4610#ifndef TARGET_SPARC64
0f8a249a
BS		 4611 if (!supervisor(dc))
4612 goto priv_insn;
255e1fcb 4613 tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
e9ebed4d 4614#else
fb79ceb9 4615 CHECK_IU_FEATURE(dc, HYPV);
e9ebed4d
BS		 4616 if (!hypervisor(dc))
4617 goto priv_insn;
de9e9d9f 4618 cpu_tmp0 = get_temp_tl(dc);
ece43b8d 4619 tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
e9ebed4d
BS		 4620 switch (rd) {
4621 case 0: // hpstate
f7f17ef7
AT		 4622 tcg_gen_st_i64(cpu_tmp0, cpu_env,
4623 offsetof(CPUSPARCState,
4624 hpstate));
66442b07 4625 save_state(dc);
e9ebed4d 4626 gen_op_next_insn();
57fec1fe 4627 tcg_gen_exit_tb(0);
e9ebed4d
BS		 4628 dc->is_br = 1;
4629 break;
4630 case 1: // htstate
4631 // XXX gen_op_wrhtstate();
4632 break;
4633 case 3: // hintp
255e1fcb 4634 tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
e9ebed4d
BS		 4635 break;
4636 case 5: // htba
255e1fcb 4637 tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
e9ebed4d
BS		 4638 break;
4639 case 31: // hstick_cmpr
ccd4a219 4640 {
a7812ae4 4641 TCGv_ptr r_tickptr;
ccd4a219 4642
255e1fcb 4643 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
a7812ae4 4644 r_tickptr = tcg_temp_new_ptr();
ccd4a219 4645 tcg_gen_ld_ptr(r_tickptr, cpu_env,
c5f9864e 4646 offsetof(CPUSPARCState, hstick));
a7812ae4
PB		 4647 gen_helper_tick_set_limit(r_tickptr,
4648 cpu_hstick_cmpr);
4649 tcg_temp_free_ptr(r_tickptr);
ccd4a219 4650 }
e9ebed4d
BS		 4651 break;
4652 case 6: // hver readonly
4653 default:
4654 goto illegal_insn;
4655 }
4656#endif
e8af50a3
FB		 4657 }
4658 break;
4659#endif
3475187d 4660#ifdef TARGET_SPARC64
0f8a249a
BS		 4661 case 0x2c: /* V9 movcc */
4662 {
4663 int cc = GET_FIELD_SP(insn, 11, 12);
4664 int cond = GET_FIELD_SP(insn, 14, 17);
f52879b4 4665 DisasCompare cmp;
97ea2859 4666 TCGv dst;
00f219bf 4667
0f8a249a 4668 if (insn & (1 << 18)) {
f52879b4
RH		 4669 if (cc == 0) {
4670 gen_compare(&cmp, 0, cond, dc);
4671 } else if (cc == 2) {
4672 gen_compare(&cmp, 1, cond, dc);
4673 } else {
0f8a249a 4674 goto illegal_insn;
f52879b4 4675 }
0f8a249a 4676 } else {
f52879b4 4677 gen_fcompare(&cmp, cc, cond);
0f8a249a 4678 }
00f219bf 4679
f52879b4
RH		 4680 /* The get_src2 above loaded the normal 13-bit
4681 immediate field, not the 11-bit field we have
4682 in movcc. But it did handle the reg case. */
4683 if (IS_IMM) {
67526b20 4684 simm = GET_FIELD_SPs(insn, 0, 10);
f52879b4 4685 tcg_gen_movi_tl(cpu_src2, simm);
00f219bf 4686 }
f52879b4 4687
97ea2859
RH		 4688 dst = gen_load_gpr(dc, rd);
4689 tcg_gen_movcond_tl(cmp.cond, dst,
f52879b4 4690 cmp.c1, cmp.c2,
97ea2859 4691 cpu_src2, dst);
f52879b4 4692 free_compare(&cmp);
97ea2859 4693 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4694 break;
4695 }
4696 case 0x2d: /* V9 sdivx */
c28ae41e 4697 gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_src2);
97ea2859 4698 gen_store_gpr(dc, rd, cpu_dst);
0f8a249a
BS		 4699 break;
4700 case 0x2e: /* V9 popc */
08da3180 4701 tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
97ea2859
RH		 4702 gen_store_gpr(dc, rd, cpu_dst);
4703 break;
0f8a249a
BS		 4704 case 0x2f: /* V9 movr */
4705 {
4706 int cond = GET_FIELD_SP(insn, 10, 12);
c33f80f5 4707 DisasCompare cmp;
97ea2859 4708 TCGv dst;
00f219bf 4709
c33f80f5 4710 gen_compare_reg(&cmp, cond, cpu_src1);
2ea815ca 4711
c33f80f5
RH		 4712 /* The get_src2 above loaded the normal 13-bit
4713 immediate field, not the 10-bit field we have
4714 in movr. But it did handle the reg case. */
4715 if (IS_IMM) {
67526b20 4716 simm = GET_FIELD_SPs(insn, 0, 9);
c33f80f5 4717 tcg_gen_movi_tl(cpu_src2, simm);
0f8a249a 4718 }
c33f80f5 4719
97ea2859
RH		 4720 dst = gen_load_gpr(dc, rd);
4721 tcg_gen_movcond_tl(cmp.cond, dst,
c33f80f5 4722 cmp.c1, cmp.c2,
97ea2859 4723 cpu_src2, dst);
c33f80f5 4724 free_compare(&cmp);
97ea2859 4725 gen_store_gpr(dc, rd, dst);
0f8a249a
BS		 4726 break;
4727 }
4728#endif
4729 default:
4730 goto illegal_insn;
4731 }
4732 }
3299908c
BS		 4733 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
4734#ifdef TARGET_SPARC64
4735 int opf = GET_FIELD_SP(insn, 5, 13);
4736 rs1 = GET_FIELD(insn, 13, 17);
4737 rs2 = GET_FIELD(insn, 27, 31);
5b12f1e8 4738 if (gen_trap_ifnofpu(dc)) {
e9ebed4d 4739 goto jmp_insn;
5b12f1e8 4740 }
3299908c
BS		 4741
4742 switch (opf) {
e9ebed4d 4743 case 0x000: /* VIS I edge8cc */
6c073553 4744 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4745 cpu_src1 = gen_load_gpr(dc, rs1);
4746 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4747 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0);
97ea2859 4748 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4749 break;
e9ebed4d 4750 case 0x001: /* VIS II edge8n */
6c073553 4751 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4752 cpu_src1 = gen_load_gpr(dc, rs1);
4753 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4754 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0);
97ea2859 4755 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4756 break;
e9ebed4d 4757 case 0x002: /* VIS I edge8lcc */
6c073553 4758 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4759 cpu_src1 = gen_load_gpr(dc, rs1);
4760 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4761 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1);
97ea2859 4762 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4763 break;
e9ebed4d 4764 case 0x003: /* VIS II edge8ln */
6c073553 4765 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4766 cpu_src1 = gen_load_gpr(dc, rs1);
4767 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4768 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1);
97ea2859 4769 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4770 break;
e9ebed4d 4771 case 0x004: /* VIS I edge16cc */
6c073553 4772 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4773 cpu_src1 = gen_load_gpr(dc, rs1);
4774 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4775 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0);
97ea2859 4776 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4777 break;
e9ebed4d 4778 case 0x005: /* VIS II edge16n */
6c073553 4779 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4780 cpu_src1 = gen_load_gpr(dc, rs1);
4781 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4782 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0);
97ea2859 4783 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4784 break;
e9ebed4d 4785 case 0x006: /* VIS I edge16lcc */
6c073553 4786 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4787 cpu_src1 = gen_load_gpr(dc, rs1);
4788 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4789 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1);
97ea2859 4790 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4791 break;
e9ebed4d 4792 case 0x007: /* VIS II edge16ln */
6c073553 4793 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4794 cpu_src1 = gen_load_gpr(dc, rs1);
4795 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4796 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1);
97ea2859 4797 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4798 break;
e9ebed4d 4799 case 0x008: /* VIS I edge32cc */
6c073553 4800 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4801 cpu_src1 = gen_load_gpr(dc, rs1);
4802 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4803 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0);
97ea2859 4804 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4805 break;
e9ebed4d 4806 case 0x009: /* VIS II edge32n */
6c073553 4807 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4808 cpu_src1 = gen_load_gpr(dc, rs1);
4809 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4810 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0);
97ea2859 4811 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4812 break;
e9ebed4d 4813 case 0x00a: /* VIS I edge32lcc */
6c073553 4814 CHECK_FPU_FEATURE(dc, VIS1);
97ea2859
RH		 4815 cpu_src1 = gen_load_gpr(dc, rs1);
4816 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4817 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1);
97ea2859 4818 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4819 break;
e9ebed4d 4820 case 0x00b: /* VIS II edge32ln */
6c073553 4821 CHECK_FPU_FEATURE(dc, VIS2);
97ea2859
RH		 4822 cpu_src1 = gen_load_gpr(dc, rs1);
4823 cpu_src2 = gen_load_gpr(dc, rs2);
6c073553 4824 gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1);
97ea2859 4825 gen_store_gpr(dc, rd, cpu_dst);
6c073553 4826 break;
e9ebed4d 4827 case 0x010: /* VIS I array8 */
64a88d5d 4828 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4829 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4830 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4831 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
97ea2859 4832 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4833 break;
4834 case 0x012: /* VIS I array16 */
64a88d5d 4835 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4836 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4837 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4838 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4839 tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
97ea2859 4840 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4841 break;
4842 case 0x014: /* VIS I array32 */
64a88d5d 4843 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4844 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4845 cpu_src2 = gen_load_gpr(dc, rs2);
f027c3b1 4846 gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
6ae20372 4847 tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
97ea2859 4848 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d 4849 break;
3299908c 4850 case 0x018: /* VIS I alignaddr */
64a88d5d 4851 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4852 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4853 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4854 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0);
97ea2859 4855 gen_store_gpr(dc, rd, cpu_dst);
3299908c
BS		 4856 break;
4857 case 0x01a: /* VIS I alignaddrl */
add545ab 4858 CHECK_FPU_FEATURE(dc, VIS1);
9d1d4e34 4859 cpu_src1 = gen_load_gpr(dc, rs1);
97ea2859 4860 cpu_src2 = gen_load_gpr(dc, rs2);
add545ab 4861 gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1);
97ea2859 4862 gen_store_gpr(dc, rd, cpu_dst);
add545ab
RH		 4863 break;
4864 case 0x019: /* VIS II bmask */
793a137a 4865 CHECK_FPU_FEATURE(dc, VIS2);
9d1d4e34
RH		 4866 cpu_src1 = gen_load_gpr(dc, rs1);
4867 cpu_src2 = gen_load_gpr(dc, rs2);
793a137a
RH		 4868 tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4869 tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32);
97ea2859 4870 gen_store_gpr(dc, rd, cpu_dst);
793a137a 4871 break;
e9ebed4d 4872 case 0x020: /* VIS I fcmple16 */
64a88d5d 4873 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4874 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4875 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4876 gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4877 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4878 break;
4879 case 0x022: /* VIS I fcmpne16 */
64a88d5d 4880 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4881 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4882 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4883 gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4884 gen_store_gpr(dc, rd, cpu_dst);
3299908c 4885 break;
e9ebed4d 4886 case 0x024: /* VIS I fcmple32 */
64a88d5d 4887 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4888 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4889 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4890 gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4891 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4892 break;
4893 case 0x026: /* VIS I fcmpne32 */
64a88d5d 4894 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4895 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4896 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4897 gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4898 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4899 break;
4900 case 0x028: /* VIS I fcmpgt16 */
64a88d5d 4901 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4902 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4903 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4904 gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4905 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4906 break;
4907 case 0x02a: /* VIS I fcmpeq16 */
64a88d5d 4908 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4909 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4910 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4911 gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4912 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4913 break;
4914 case 0x02c: /* VIS I fcmpgt32 */
64a88d5d 4915 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4916 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4917 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4918 gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4919 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4920 break;
4921 case 0x02e: /* VIS I fcmpeq32 */
64a88d5d 4922 CHECK_FPU_FEATURE(dc, VIS1);
03fb8cfc
RH		 4923 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
4924 cpu_src2_64 = gen_load_fpr_D(dc, rs2);
f027c3b1 4925 gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
97ea2859 4926 gen_store_gpr(dc, rd, cpu_dst);
e9ebed4d
BS		 4927 break;
4928 case 0x031: /* VIS I fmul8x16 */
64a88d5d 4929 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4930 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16);
e9ebed4d
BS		 4931 break;
4932 case 0x033: /* VIS I fmul8x16au */
64a88d5d 4933 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4934 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au);
e9ebed4d
BS		 4935 break;
4936 case 0x035: /* VIS I fmul8x16al */
64a88d5d 4937 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4938 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al);
e9ebed4d
BS		 4939 break;
4940 case 0x036: /* VIS I fmul8sux16 */
64a88d5d 4941 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4942 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16);
e9ebed4d
BS		 4943 break;
4944 case 0x037: /* VIS I fmul8ulx16 */
64a88d5d 4945 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4946 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16);
e9ebed4d
BS		 4947 break;
4948 case 0x038: /* VIS I fmuld8sux16 */
64a88d5d 4949 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4950 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16);
e9ebed4d
BS		 4951 break;
4952 case 0x039: /* VIS I fmuld8ulx16 */
64a88d5d 4953 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4954 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16);
e9ebed4d
BS		 4955 break;
4956 case 0x03a: /* VIS I fpack32 */
2dedf314
RH		 4957 CHECK_FPU_FEATURE(dc, VIS1);
4958 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
4959 break;
e9ebed4d 4960 case 0x03b: /* VIS I fpack16 */
2dedf314
RH		 4961 CHECK_FPU_FEATURE(dc, VIS1);
4962 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4963 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4964 gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64);
4965 gen_store_fpr_F(dc, rd, cpu_dst_32);
4966 break;
e9ebed4d 4967 case 0x03d: /* VIS I fpackfix */
2dedf314
RH		 4968 CHECK_FPU_FEATURE(dc, VIS1);
4969 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
ba5f5179 4970 cpu_dst_32 = gen_dest_fpr_F(dc);
2dedf314
RH		 4971 gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
4972 gen_store_fpr_F(dc, rd, cpu_dst_32);
4973 break;
f888300b
RH		 4974 case 0x03e: /* VIS I pdist */
4975 CHECK_FPU_FEATURE(dc, VIS1);
4976 gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist);
4977 break;
3299908c 4978 case 0x048: /* VIS I faligndata */
64a88d5d 4979 CHECK_FPU_FEATURE(dc, VIS1);
50c796f9 4980 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
3299908c 4981 break;
e9ebed4d 4982 case 0x04b: /* VIS I fpmerge */
64a88d5d 4983 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4984 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
e9ebed4d
BS		 4985 break;
4986 case 0x04c: /* VIS II bshuffle */
793a137a
RH		 4987 CHECK_FPU_FEATURE(dc, VIS2);
4988 gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
4989 break;
e9ebed4d 4990 case 0x04d: /* VIS I fexpand */
64a88d5d 4991 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4992 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand);
e9ebed4d
BS		 4993 break;
4994 case 0x050: /* VIS I fpadd16 */
64a88d5d 4995 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 4996 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
e9ebed4d
BS		 4997 break;
4998 case 0x051: /* VIS I fpadd16s */
64a88d5d 4999 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5000 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
e9ebed4d
BS		 5001 break;
5002 case 0x052: /* VIS I fpadd32 */
64a88d5d 5003 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5004 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
e9ebed4d
BS		 5005 break;
5006 case 0x053: /* VIS I fpadd32s */
64a88d5d 5007 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5008 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32);
e9ebed4d
BS		 5009 break;
5010 case 0x054: /* VIS I fpsub16 */
64a88d5d 5011 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5012 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
e9ebed4d
BS		 5013 break;
5014 case 0x055: /* VIS I fpsub16s */
64a88d5d 5015 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5016 gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
e9ebed4d
BS		 5017 break;
5018 case 0x056: /* VIS I fpsub32 */
64a88d5d 5019 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5020 gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
e9ebed4d
BS		 5021 break;
5022 case 0x057: /* VIS I fpsub32s */
64a88d5d 5023 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5024 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32);
e9ebed4d 5025 break;
3299908c 5026 case 0x060: /* VIS I fzero */
64a88d5d 5027 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5028 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5029 tcg_gen_movi_i64(cpu_dst_64, 0);
5030 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5031 break;
5032 case 0x061: /* VIS I fzeros */
64a88d5d 5033 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5034 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5035 tcg_gen_movi_i32(cpu_dst_32, 0);
5036 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5037 break;
e9ebed4d 5038 case 0x062: /* VIS I fnor */
64a88d5d 5039 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5040 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64);
e9ebed4d
BS		 5041 break;
5042 case 0x063: /* VIS I fnors */
64a88d5d 5043 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5044 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32);
e9ebed4d
BS		 5045 break;
5046 case 0x064: /* VIS I fandnot2 */
64a88d5d 5047 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5048 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64);
e9ebed4d
BS		 5049 break;
5050 case 0x065: /* VIS I fandnot2s */
64a88d5d 5051 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5052 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
e9ebed4d
BS		 5053 break;
5054 case 0x066: /* VIS I fnot2 */
64a88d5d 5055 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5056 gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
e9ebed4d
BS		 5057 break;
5058 case 0x067: /* VIS I fnot2s */
64a88d5d 5059 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5060 gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32);
e9ebed4d
BS		 5061 break;
5062 case 0x068: /* VIS I fandnot1 */
64a88d5d 5063 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5064 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
e9ebed4d
BS		 5065 break;
5066 case 0x069: /* VIS I fandnot1s */
64a88d5d 5067 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5068 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
e9ebed4d
BS		 5069 break;
5070 case 0x06a: /* VIS I fnot1 */
64a88d5d 5071 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5072 gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
e9ebed4d
BS		 5073 break;
5074 case 0x06b: /* VIS I fnot1s */
64a88d5d 5075 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5076 gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32);
e9ebed4d
BS		 5077 break;
5078 case 0x06c: /* VIS I fxor */
64a88d5d 5079 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5080 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
e9ebed4d
BS		 5081 break;
5082 case 0x06d: /* VIS I fxors */
64a88d5d 5083 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5084 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32);
e9ebed4d
BS		 5085 break;
5086 case 0x06e: /* VIS I fnand */
64a88d5d 5087 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5088 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64);
e9ebed4d
BS		 5089 break;
5090 case 0x06f: /* VIS I fnands */
64a88d5d 5091 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5092 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32);
e9ebed4d
BS		 5093 break;
5094 case 0x070: /* VIS I fand */
64a88d5d 5095 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5096 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64);
e9ebed4d
BS		 5097 break;
5098 case 0x071: /* VIS I fands */
64a88d5d 5099 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5100 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32);
e9ebed4d
BS		 5101 break;
5102 case 0x072: /* VIS I fxnor */
64a88d5d 5103 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5104 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64);
e9ebed4d
BS		 5105 break;
5106 case 0x073: /* VIS I fxnors */
64a88d5d 5107 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5108 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
e9ebed4d 5109 break;
3299908c 5110 case 0x074: /* VIS I fsrc1 */
64a88d5d 5111 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5112 cpu_src1_64 = gen_load_fpr_D(dc, rs1);
5113 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5114 break;
5115 case 0x075: /* VIS I fsrc1s */
64a88d5d 5116 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5117 cpu_src1_32 = gen_load_fpr_F(dc, rs1);
5118 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5119 break;
e9ebed4d 5120 case 0x076: /* VIS I fornot2 */
64a88d5d 5121 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5122 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64);
e9ebed4d
BS		 5123 break;
5124 case 0x077: /* VIS I fornot2s */
64a88d5d 5125 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5126 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
e9ebed4d 5127 break;
3299908c 5128 case 0x078: /* VIS I fsrc2 */
64a88d5d 5129 CHECK_FPU_FEATURE(dc, VIS1);
96eda024
RH		 5130 cpu_src1_64 = gen_load_fpr_D(dc, rs2);
5131 gen_store_fpr_D(dc, rd, cpu_src1_64);
3299908c
BS		 5132 break;
5133 case 0x079: /* VIS I fsrc2s */
64a88d5d 5134 CHECK_FPU_FEATURE(dc, VIS1);
208ae657
RH		 5135 cpu_src1_32 = gen_load_fpr_F(dc, rs2);
5136 gen_store_fpr_F(dc, rd, cpu_src1_32);
3299908c 5137 break;
e9ebed4d 5138 case 0x07a: /* VIS I fornot1 */
64a88d5d 5139 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5140 gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
e9ebed4d
BS		 5141 break;
5142 case 0x07b: /* VIS I fornot1s */
64a88d5d 5143 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5144 gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32);
e9ebed4d
BS		 5145 break;
5146 case 0x07c: /* VIS I for */
64a88d5d 5147 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5148 gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64);
e9ebed4d
BS		 5149 break;
5150 case 0x07d: /* VIS I fors */
64a88d5d 5151 CHECK_FPU_FEATURE(dc, VIS1);
61f17f6e 5152 gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32);
e9ebed4d 5153 break;
3299908c 5154 case 0x07e: /* VIS I fone */
64a88d5d 5155 CHECK_FPU_FEATURE(dc, VIS1);
3886b8a3 5156 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
96eda024
RH		 5157 tcg_gen_movi_i64(cpu_dst_64, -1);
5158 gen_store_fpr_D(dc, rd, cpu_dst_64);
3299908c
BS		 5159 break;
5160 case 0x07f: /* VIS I fones */
64a88d5d 5161 CHECK_FPU_FEATURE(dc, VIS1);
ba5f5179 5162 cpu_dst_32 = gen_dest_fpr_F(dc);
208ae657
RH		 5163 tcg_gen_movi_i32(cpu_dst_32, -1);
5164 gen_store_fpr_F(dc, rd, cpu_dst_32);
3299908c 5165 break;
e9ebed4d
BS		 5166 case 0x080: /* VIS I shutdown */
5167 case 0x081: /* VIS II siam */
5168 // XXX
5169 goto illegal_insn;
3299908c
BS		 5170 default:
5171 goto illegal_insn;
5172 }
5173#else
0f8a249a 5174 goto ncp_insn;
3299908c
BS		 5175#endif
5176 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
fcc72045 5177#ifdef TARGET_SPARC64
0f8a249a 5178 goto illegal_insn;
fcc72045 5179#else
0f8a249a 5180 goto ncp_insn;
fcc72045 5181#endif
3475187d 5182#ifdef TARGET_SPARC64
0f8a249a 5183 } else if (xop == 0x39) { /* V9 return */
66442b07 5184 save_state(dc);
9d1d4e34 5185 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5186 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5187 if (IS_IMM) { /* immediate */
67526b20 5188 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5189 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5190 } else { /* register */
3475187d 5191 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5192 if (rs2) {
97ea2859 5193 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5194 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5195 } else {
7b04bd5c 5196 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5197 }
3475187d 5198 }
063c3675 5199 gen_helper_restore(cpu_env);
13a6dd00 5200 gen_mov_pc_npc(dc);
35e94905 5201 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5202 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5203 dc->npc = DYNAMIC_PC;
5204 goto jmp_insn;
3475187d 5205#endif
0f8a249a 5206 } else {
9d1d4e34 5207 cpu_src1 = get_src1(dc, insn);
de9e9d9f 5208 cpu_tmp0 = get_temp_tl(dc);
0f8a249a 5209 if (IS_IMM) { /* immediate */
67526b20 5210 simm = GET_FIELDs(insn, 19, 31);
7b04bd5c 5211 tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
0f8a249a 5212 } else { /* register */
e80cfcfc 5213 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5214 if (rs2) {
97ea2859 5215 cpu_src2 = gen_load_gpr(dc, rs2);
7b04bd5c 5216 tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
97ea2859 5217 } else {
7b04bd5c 5218 tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
97ea2859 5219 }
cf495bcf 5220 }
0f8a249a
BS		 5221 switch (xop) {
5222 case 0x38: /* jmpl */
5223 {
35e94905 5224 TCGv t = gen_dest_gpr(dc, rd);
97ea2859
RH		 5225 tcg_gen_movi_tl(t, dc->pc);
5226 gen_store_gpr(dc, rd, t);
35e94905 5227
13a6dd00 5228 gen_mov_pc_npc(dc);
35e94905 5229 gen_check_align(cpu_tmp0, 3);
7b04bd5c
RH		 5230 gen_address_mask(dc, cpu_tmp0);
5231 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a
BS		 5232 dc->npc = DYNAMIC_PC;
5233 }
5234 goto jmp_insn;
3475187d 5235#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
0f8a249a
BS		 5236 case 0x39: /* rett, V9 return */
5237 {
5238 if (!supervisor(dc))
5239 goto priv_insn;
13a6dd00 5240 gen_mov_pc_npc(dc);
35e94905 5241 gen_check_align(cpu_tmp0, 3);
7b04bd5c 5242 tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
0f8a249a 5243 dc->npc = DYNAMIC_PC;
063c3675 5244 gen_helper_rett(cpu_env);
0f8a249a
BS		 5245 }
5246 goto jmp_insn;
5247#endif
5248 case 0x3b: /* flush */
5578ceab 5249 if (!((dc)->def->features & CPU_FEATURE_FLUSH))
64a88d5d 5250 goto unimp_flush;
dcfd14b3 5251 /* nop */
0f8a249a
BS		 5252 break;
5253 case 0x3c: /* save */
063c3675 5254 gen_helper_save(cpu_env);
7b04bd5c 5255 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a
BS		 5256 break;
5257 case 0x3d: /* restore */
063c3675 5258 gen_helper_restore(cpu_env);
7b04bd5c 5259 gen_store_gpr(dc, rd, cpu_tmp0);
0f8a249a 5260 break;
3475187d 5261#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
0f8a249a
BS		 5262 case 0x3e: /* V9 done/retry */
5263 {
5264 switch (rd) {
5265 case 0:
5266 if (!supervisor(dc))
5267 goto priv_insn;
5268 dc->npc = DYNAMIC_PC;
5269 dc->pc = DYNAMIC_PC;
063c3675 5270 gen_helper_done(cpu_env);
0f8a249a
BS		 5271 goto jmp_insn;
5272 case 1:
5273 if (!supervisor(dc))
5274 goto priv_insn;
5275 dc->npc = DYNAMIC_PC;
5276 dc->pc = DYNAMIC_PC;
063c3675 5277 gen_helper_retry(cpu_env);
0f8a249a
BS		 5278 goto jmp_insn;
5279 default:
5280 goto illegal_insn;
5281 }
5282 }
5283 break;
5284#endif
5285 default:
5286 goto illegal_insn;
5287 }
cf495bcf 5288 }
0f8a249a
BS		 5289 break;
5290 }
5291 break;
5292 case 3: /* load/store instructions */
5293 {
5294 unsigned int xop = GET_FIELD(insn, 7, 12);
5e6ed439
RH		 5295 /* ??? gen_address_mask prevents us from using a source
5296 register directly. Always generate a temporary. */
5297 TCGv cpu_addr = get_temp_tl(dc);
9322a4bf 5298
5e6ed439
RH		 5299 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
5300 if (xop == 0x3c || xop == 0x3e) {
5301 /* V9 casa/casxa : no offset */
71817e48 5302 } else if (IS_IMM) { /* immediate */
67526b20 5303 simm = GET_FIELDs(insn, 19, 31);
5e6ed439
RH		 5304 if (simm != 0) {
5305 tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
5306 }
0f8a249a
BS		 5307 } else { /* register */
5308 rs2 = GET_FIELD(insn, 27, 31);
0f8a249a 5309 if (rs2 != 0) {
5e6ed439 5310 tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2));
97ea2859 5311 }
0f8a249a 5312 }
2f2ecb83
BS		 5313 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
5314 (xop > 0x17 && xop <= 0x1d ) ||
5315 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
81634eea
RH		 5316 TCGv cpu_val = gen_dest_gpr(dc, rd);
5317
0f8a249a 5318 switch (xop) {
b89e94af 5319 case 0x0: /* ld, V9 lduw, load unsigned word */
2cade6a3 5320 gen_address_mask(dc, cpu_addr);
6ae20372 5321 tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5322 break;
b89e94af 5323 case 0x1: /* ldub, load unsigned byte */
2cade6a3 5324 gen_address_mask(dc, cpu_addr);
6ae20372 5325 tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5326 break;
b89e94af 5327 case 0x2: /* lduh, load unsigned halfword */
2cade6a3 5328 gen_address_mask(dc, cpu_addr);
6ae20372 5329 tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5330 break;
b89e94af 5331 case 0x3: /* ldd, load double word */
0f8a249a 5332 if (rd & 1)
d4218d99 5333 goto illegal_insn;
1a2fb1c0 5334 else {
abcc7191 5335 TCGv_i64 t64;
2ea815ca 5336
2cade6a3 5337 gen_address_mask(dc, cpu_addr);
abcc7191
RH		 5338 t64 = tcg_temp_new_i64();
5339 tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx);
de9e9d9f
RH		 5340 tcg_gen_trunc_i64_tl(cpu_val, t64);
5341 tcg_gen_ext32u_tl(cpu_val, cpu_val);
5342 gen_store_gpr(dc, rd + 1, cpu_val);
abcc7191
RH		 5343 tcg_gen_shri_i64(t64, t64, 32);
5344 tcg_gen_trunc_i64_tl(cpu_val, t64);
5345 tcg_temp_free_i64(t64);
de9e9d9f 5346 tcg_gen_ext32u_tl(cpu_val, cpu_val);
1a2fb1c0 5347 }
0f8a249a 5348 break;
b89e94af 5349 case 0x9: /* ldsb, load signed byte */
2cade6a3 5350 gen_address_mask(dc, cpu_addr);
6ae20372 5351 tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5352 break;
b89e94af 5353 case 0xa: /* ldsh, load signed halfword */
2cade6a3 5354 gen_address_mask(dc, cpu_addr);
6ae20372 5355 tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5356 break;
fbb4bbb6
RH		 5357 case 0xd: /* ldstub */
5358 gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5359 break;
de9e9d9f
RH		 5360 case 0x0f:
5361 /* swap, swap register with memory. Also atomically */
4fb554bc
RH		 5362 CHECK_IU_FEATURE(dc, SWAP);
5363 cpu_src1 = gen_load_gpr(dc, rd);
5364 gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
5365 dc->mem_idx, MO_TEUL);
0f8a249a 5366 break;
3475187d 5367#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5368 case 0x10: /* lda, V9 lduwa, load word alternate */
1d65b0f5 5369 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
0f8a249a 5370 break;
b89e94af 5371 case 0x11: /* lduba, load unsigned byte alternate */
1d65b0f5 5372 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
0f8a249a 5373 break;
b89e94af 5374 case 0x12: /* lduha, load unsigned halfword alternate */
1d65b0f5 5375 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
0f8a249a 5376 break;
b89e94af 5377 case 0x13: /* ldda, load double word alternate */
7ec1e5ea 5378 if (rd & 1) {
d4218d99 5379 goto illegal_insn;
7ec1e5ea 5380 }
e4dc0052 5381 gen_ldda_asi(dc, cpu_addr, insn, rd);
db166940 5382 goto skip_move;
b89e94af 5383 case 0x19: /* ldsba, load signed byte alternate */
1d65b0f5 5384 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
0f8a249a 5385 break;
b89e94af 5386 case 0x1a: /* ldsha, load signed halfword alternate */
1d65b0f5 5387 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
0f8a249a
BS		 5388 break;
5389 case 0x1d: /* ldstuba -- XXX: should be atomically */
22e70060 5390 gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
0f8a249a 5391 break;
b89e94af 5392 case 0x1f: /* swapa, swap reg with alt. memory. Also
77f193da 5393 atomically */
64a88d5d 5394 CHECK_IU_FEATURE(dc, SWAP);
06828032 5395 cpu_src1 = gen_load_gpr(dc, rd);
22e70060 5396 gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
0f8a249a 5397 break;
3475187d
FB		 5398
5399#ifndef TARGET_SPARC64
0f8a249a
BS		 5400 case 0x30: /* ldc */
5401 case 0x31: /* ldcsr */
5402 case 0x33: /* lddc */
5403 goto ncp_insn;
3475187d
FB		 5404#endif
5405#endif
5406#ifdef TARGET_SPARC64
0f8a249a 5407 case 0x08: /* V9 ldsw */
2cade6a3 5408 gen_address_mask(dc, cpu_addr);
6ae20372 5409 tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5410 break;
5411 case 0x0b: /* V9 ldx */
2cade6a3 5412 gen_address_mask(dc, cpu_addr);
6ae20372 5413 tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5414 break;
5415 case 0x18: /* V9 ldswa */
1d65b0f5 5416 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
0f8a249a
BS		 5417 break;
5418 case 0x1b: /* V9 ldxa */
1d65b0f5 5419 gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a
BS		 5420 break;
5421 case 0x2d: /* V9 prefetch, no effect */
5422 goto skip_move;
5423 case 0x30: /* V9 ldfa */
5b12f1e8 5424 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5425 goto jmp_insn;
5426 }
22e70060 5427 gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
f9c816c0 5428 gen_update_fprs_dirty(dc, rd);
81ad8ba2 5429 goto skip_move;
0f8a249a 5430 case 0x33: /* V9 lddfa */
5b12f1e8 5431 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5432 goto jmp_insn;
5433 }
22e70060 5434 gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
f9c816c0 5435 gen_update_fprs_dirty(dc, DFPREG(rd));
81ad8ba2 5436 goto skip_move;
0f8a249a
BS		 5437 case 0x3d: /* V9 prefetcha, no effect */
5438 goto skip_move;
5439 case 0x32: /* V9 ldqfa */
64a88d5d 5440 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5441 if (gen_trap_ifnofpu(dc)) {
8872eb4f
TS		 5442 goto jmp_insn;
5443 }
22e70060 5444 gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
f9c816c0 5445 gen_update_fprs_dirty(dc, QFPREG(rd));
1f587329 5446 goto skip_move;
0f8a249a
BS		 5447#endif
5448 default:
5449 goto illegal_insn;
5450 }
97ea2859 5451 gen_store_gpr(dc, rd, cpu_val);
db166940 5452#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
0f8a249a 5453 skip_move: ;
3475187d 5454#endif
0f8a249a 5455 } else if (xop >= 0x20 && xop < 0x24) {
5b12f1e8 5456 if (gen_trap_ifnofpu(dc)) {
a80dde08 5457 goto jmp_insn;
5b12f1e8 5458 }
0f8a249a 5459 switch (xop) {
b89e94af 5460 case 0x20: /* ldf, load fpreg */
2cade6a3 5461 gen_address_mask(dc, cpu_addr);
ba5f5179 5462 cpu_dst_32 = gen_dest_fpr_F(dc);
cb21b4da
RH		 5463 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5464 dc->mem_idx, MO_TEUL);
208ae657 5465 gen_store_fpr_F(dc, rd, cpu_dst_32);
0f8a249a 5466 break;
3a3b925d
BS		 5467 case 0x21: /* ldfsr, V9 ldxfsr */
5468#ifdef TARGET_SPARC64
2cade6a3 5469 gen_address_mask(dc, cpu_addr);
3a3b925d 5470 if (rd == 1) {
abcc7191 5471 TCGv_i64 t64 = tcg_temp_new_i64();
cb21b4da
RH		 5472 tcg_gen_qemu_ld_i64(t64, cpu_addr,
5473 dc->mem_idx, MO_TEQ);
7385aed2 5474 gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64);
abcc7191 5475 tcg_temp_free_i64(t64);
f8641947 5476 break;
fe987e23 5477 }
f8641947 5478#endif
de9e9d9f 5479 cpu_dst_32 = get_temp_i32(dc);
cb21b4da
RH		 5480 tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr,
5481 dc->mem_idx, MO_TEUL);
7385aed2 5482 gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32);
0f8a249a 5483 break;
b89e94af 5484 case 0x22: /* ldqf, load quad fpreg */
f939ffe5
RH		 5485 CHECK_FPU_FEATURE(dc, FLOAT128);
5486 gen_address_mask(dc, cpu_addr);
5487 cpu_src1_64 = tcg_temp_new_i64();
cb21b4da
RH		 5488 tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5489 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5490 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5491 cpu_src2_64 = tcg_temp_new_i64();
cb21b4da
RH		 5492 tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx,
5493 MO_TEQ | MO_ALIGN_4);
f939ffe5
RH		 5494 gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
5495 tcg_temp_free_i64(cpu_src1_64);
5496 tcg_temp_free_i64(cpu_src2_64);
1f587329 5497 break;
b89e94af 5498 case 0x23: /* lddf, load double fpreg */
03fb8cfc 5499 gen_address_mask(dc, cpu_addr);
3886b8a3 5500 cpu_dst_64 = gen_dest_fpr_D(dc, rd);
cb21b4da
RH		 5501 tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx,
5502 MO_TEQ | MO_ALIGN_4);
03fb8cfc 5503 gen_store_fpr_D(dc, rd, cpu_dst_64);
0f8a249a
BS		 5504 break;
5505 default:
5506 goto illegal_insn;
5507 }
dc1a6971 5508 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
0f8a249a 5509 xop == 0xe || xop == 0x1e) {
81634eea
RH		 5510 TCGv cpu_val = gen_load_gpr(dc, rd);
5511
0f8a249a 5512 switch (xop) {
b89e94af 5513 case 0x4: /* st, store word */
2cade6a3 5514 gen_address_mask(dc, cpu_addr);
6ae20372 5515 tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5516 break;
b89e94af 5517 case 0x5: /* stb, store byte */
2cade6a3 5518 gen_address_mask(dc, cpu_addr);
6ae20372 5519 tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5520 break;
b89e94af 5521 case 0x6: /* sth, store halfword */
2cade6a3 5522 gen_address_mask(dc, cpu_addr);
6ae20372 5523 tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a 5524 break;
b89e94af 5525 case 0x7: /* std, store double word */
0f8a249a 5526 if (rd & 1)
d4218d99 5527 goto illegal_insn;
1a2fb1c0 5528 else {
abcc7191 5529 TCGv_i64 t64;
81634eea 5530 TCGv lo;
1a2fb1c0 5531
2cade6a3 5532 gen_address_mask(dc, cpu_addr);
81634eea 5533 lo = gen_load_gpr(dc, rd + 1);
abcc7191
RH		 5534 t64 = tcg_temp_new_i64();
5535 tcg_gen_concat_tl_i64(t64, lo, cpu_val);
5536 tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx);
5537 tcg_temp_free_i64(t64);
7fa76c0b 5538 }
0f8a249a 5539 break;
3475187d 5540#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
b89e94af 5541 case 0x14: /* sta, V9 stwa, store word alternate */
1d65b0f5 5542 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
d39c0b99 5543 break;
b89e94af 5544 case 0x15: /* stba, store byte alternate */
1d65b0f5 5545 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
d39c0b99 5546 break;
b89e94af 5547 case 0x16: /* stha, store halfword alternate */
1d65b0f5 5548 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
d39c0b99 5549 break;
b89e94af 5550 case 0x17: /* stda, store double word alternate */
7ec1e5ea 5551 if (rd & 1) {
0f8a249a 5552 goto illegal_insn;
1a2fb1c0 5553 }
7ec1e5ea 5554 gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
d39c0b99 5555 break;
e80cfcfc 5556#endif
3475187d 5557#ifdef TARGET_SPARC64
0f8a249a 5558 case 0x0e: /* V9 stx */
2cade6a3 5559 gen_address_mask(dc, cpu_addr);
6ae20372 5560 tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
0f8a249a
BS		 5561 break;
5562 case 0x1e: /* V9 stxa */
1d65b0f5 5563 gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
0f8a249a 5564 break;
3475187d 5565#endif
0f8a249a
BS		 5566 default:
5567 goto illegal_insn;
5568 }
5569 } else if (xop > 0x23 && xop < 0x28) {
5b12f1e8 5570 if (gen_trap_ifnofpu(dc)) {
a80dde08 5571 goto jmp_insn;
5b12f1e8 5572 }
0f8a249a 5573 switch (xop) {
b89e94af 5574 case 0x24: /* stf, store fpreg */
cb21b4da
RH		 5575 gen_address_mask(dc, cpu_addr);
5576 cpu_src1_32 = gen_load_fpr_F(dc, rd);
5577 tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr,
5578 dc->mem_idx, MO_TEUL);
0f8a249a
BS		 5579 break;
5580 case 0x25: /* stfsr, V9 stxfsr */
f8641947 5581 {
3a3b925d 5582#ifdef TARGET_SPARC64
f8641947
RH		 5583 gen_address_mask(dc, cpu_addr);
5584 if (rd == 1) {
ba2397d1 5585 tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947
RH		 5586 break;
5587 }
3a3b925d 5588#endif
ba2397d1 5589 tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx);
f8641947 5590 }
0f8a249a 5591 break;
1f587329
BS		 5592 case 0x26:
5593#ifdef TARGET_SPARC64
1f587329 5594 /* V9 stqf, store quad fpreg */
f939ffe5
RH		 5595 CHECK_FPU_FEATURE(dc, FLOAT128);
5596 gen_address_mask(dc, cpu_addr);
5597 /* ??? While stqf only requires 4-byte alignment, it is
5598 legal for the cpu to signal the unaligned exception.
5599 The OS trap handler is then required to fix it up.
5600 For qemu, this avoids having to probe the second page
5601 before performing the first write. */
5602 cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
5603 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5604 dc->mem_idx, MO_TEQ | MO_ALIGN_16);
5605 tcg_gen_addi_tl(cpu_addr, cpu_addr, 8);
5606 cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
5607 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr,
5608 dc->mem_idx, MO_TEQ);
1f587329 5609 break;
1f587329
BS		 5610#else /* !TARGET_SPARC64 */
5611 /* stdfq, store floating point queue */
5612#if defined(CONFIG_USER_ONLY)
5613 goto illegal_insn;
5614#else
0f8a249a
BS		 5615 if (!supervisor(dc))
5616 goto priv_insn;
5b12f1e8 5617 if (gen_trap_ifnofpu(dc)) {
0f8a249a 5618 goto jmp_insn;
5b12f1e8 5619 }
0f8a249a 5620 goto nfq_insn;
1f587329 5621#endif
0f8a249a 5622#endif
b89e94af 5623 case 0x27: /* stdf, store double fpreg */
03fb8cfc
RH		 5624 gen_address_mask(dc, cpu_addr);
5625 cpu_src1_64 = gen_load_fpr_D(dc, rd);
cb21b4da
RH		 5626 tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx,
5627 MO_TEQ | MO_ALIGN_4);
0f8a249a
BS		 5628 break;
5629 default:
5630 goto illegal_insn;
5631 }
5632 } else if (xop > 0x33 && xop < 0x3f) {
5633 switch (xop) {
a4d17f19 5634#ifdef TARGET_SPARC64
0f8a249a 5635 case 0x34: /* V9 stfa */
5b12f1e8 5636 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5637 goto jmp_insn;
5638 }
22e70060 5639 gen_stf_asi(dc, cpu_addr, insn, 4, rd);
0f8a249a 5640 break;
1f587329 5641 case 0x36: /* V9 stqfa */
2ea815ca 5642 {
2ea815ca 5643 CHECK_FPU_FEATURE(dc, FLOAT128);
5b12f1e8 5644 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5645 goto jmp_insn;
5646 }
22e70060 5647 gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
2ea815ca 5648 }
1f587329 5649 break;
0f8a249a 5650 case 0x37: /* V9 stdfa */
5b12f1e8 5651 if (gen_trap_ifnofpu(dc)) {
5f06b547
TS		 5652 goto jmp_insn;
5653 }
22e70060 5654 gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
0f8a249a 5655 break;
0f8a249a 5656 case 0x3e: /* V9 casxa */
a4273524
RH		 5657 rs2 = GET_FIELD(insn, 27, 31);
5658 cpu_src2 = gen_load_gpr(dc, rs2);
81634eea 5659 gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
0f8a249a 5660 break;
a4d17f19 5661#else
0f8a249a
BS		 5662 case 0x34: /* stc */
5663 case 0x35: /* stcsr */
5664 case 0x36: /* stdcq */
5665 case 0x37: /* stdc */
5666 goto ncp_insn;
16c358e9
SH		 5667#endif
5668#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
5669 case 0x3c: /* V9 or LEON3 casa */
5670#ifndef TARGET_SPARC64
5671 CHECK_IU_FEATURE(dc, CASA);
16c358e9
SH		 5672#endif
5673 rs2 = GET_FIELD(insn, 27, 31);
5674 cpu_src2 = gen_load_gpr(dc, rs2);
5675 gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
5676 break;
0f8a249a
BS		 5677#endif
5678 default:
5679 goto illegal_insn;
5680 }
a4273524 5681 } else {
0f8a249a 5682 goto illegal_insn;
a4273524 5683 }
0f8a249a
BS		 5684 }
5685 break;
cf495bcf
FB		 5686 }
5687 /* default case for non jump instructions */
72cbca10 5688 if (dc->npc == DYNAMIC_PC) {
0f8a249a
BS		 5689 dc->pc = DYNAMIC_PC;
5690 gen_op_next_insn();
72cbca10
FB		 5691 } else if (dc->npc == JUMP_PC) {
5692 /* we can do a static jump */
6ae20372 5693 gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
72cbca10
FB		 5694 dc->is_br = 1;
5695 } else {
0f8a249a
BS		 5696 dc->pc = dc->npc;
5697 dc->npc = dc->npc + 4;
cf495bcf 5698 }
e80cfcfc 5699 jmp_insn:
42a8aa83 5700 goto egress;
cf495bcf 5701 illegal_insn:
4fbe0067 5702 gen_exception(dc, TT_ILL_INSN);
42a8aa83 5703 goto egress;
64a88d5d 5704 unimp_flush:
4fbe0067 5705 gen_exception(dc, TT_UNIMP_FLUSH);
42a8aa83 5706 goto egress;
e80cfcfc 5707#if !defined(CONFIG_USER_ONLY)
e8af50a3 5708 priv_insn:
4fbe0067 5709 gen_exception(dc, TT_PRIV_INSN);
42a8aa83 5710 goto egress;
64a88d5d 5711#endif
e80cfcfc 5712 nfpu_insn:
4fbe0067 5713 gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
42a8aa83 5714 goto egress;
64a88d5d 5715#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
9143e598 5716 nfq_insn:
4fbe0067 5717 gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
42a8aa83 5718 goto egress;
9143e598 5719#endif
fcc72045
BS		 5720#ifndef TARGET_SPARC64
5721 ncp_insn:
4fbe0067 5722 gen_exception(dc, TT_NCP_INSN);
42a8aa83 5723 goto egress;
fcc72045 5724#endif
42a8aa83 5725 egress:
30038fd8
RH		 5726 if (dc->n_t32 != 0) {
5727 int i;
5728 for (i = dc->n_t32 - 1; i >= 0; --i) {
5729 tcg_temp_free_i32(dc->t32[i]);
5730 }
5731 dc->n_t32 = 0;
5732 }
88023616
RH		 5733 if (dc->n_ttl != 0) {
5734 int i;
5735 for (i = dc->n_ttl - 1; i >= 0; --i) {
5736 tcg_temp_free(dc->ttl[i]);
5737 }
5738 dc->n_ttl = 0;
5739 }
7a3f1944
FB		 5740}
5741
9c489ea6 5742void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
7a3f1944 5743{
9c489ea6 5744 CPUSPARCState *env = cs->env_ptr;
72cbca10 5745 target_ulong pc_start, last_pc;
cf495bcf 5746 DisasContext dc1, *dc = &dc1;
2e70f6ef
PB		 5747 int num_insns;
5748 int max_insns;
0184e266 5749 unsigned int insn;
cf495bcf
FB		 5750
5751 memset(dc, 0, sizeof(DisasContext));
cf495bcf 5752 dc->tb = tb;
72cbca10 5753 pc_start = tb->pc;
cf495bcf 5754 dc->pc = pc_start;
e80cfcfc 5755 last_pc = dc->pc;
72cbca10 5756 dc->npc = (target_ulong) tb->cs_base;
8393617c 5757 dc->cc_op = CC_OP_DYNAMIC;
99a23063 5758 dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
5578ceab 5759 dc->def = env->def;
f838e2c5
BS		 5760 dc->fpu_enabled = tb_fpu_enabled(tb->flags);
5761 dc->address_mask_32bit = tb_am_enabled(tb->flags);
ed2803da 5762 dc->singlestep = (cs->singlestep_enabled || singlestep);
c9b459aa
AT		 5763#ifndef CONFIG_USER_ONLY
5764 dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
5765#endif
a6d567e5 5766#ifdef TARGET_SPARC64
f9c816c0 5767 dc->fprs_dirty = 0;
a6d567e5 5768 dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
c9b459aa
AT		 5769#ifndef CONFIG_USER_ONLY
5770 dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
5771#endif
a6d567e5 5772#endif
cf495bcf 5773
2e70f6ef
PB		 5774 num_insns = 0;
5775 max_insns = tb->cflags & CF_COUNT_MASK;
190ce7fb 5776 if (max_insns == 0) {
2e70f6ef 5777 max_insns = CF_COUNT_MASK;
190ce7fb
RH		 5778 }
5779 if (max_insns > TCG_MAX_INSNS) {
5780 max_insns = TCG_MAX_INSNS;
5781 }
5782
cd42d5b2 5783 gen_tb_start(tb);
cf495bcf 5784 do {
a3d5ad76
RH		 5785 if (dc->npc & JUMP_PC) {
5786 assert(dc->jump_pc[1] == dc->pc + 4);
5787 tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
5788 } else {
5789 tcg_gen_insn_start(dc->pc, dc->npc);
5790 }
959082fc 5791 num_insns++;
522a0d4e 5792 last_pc = dc->pc;
667b8e29 5793
b933066a
RH		 5794 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5795 if (dc->pc != pc_start) {
5796 save_state(dc);
5797 }
5798 gen_helper_debug(cpu_env);
5799 tcg_gen_exit_tb(0);
5800 dc->is_br = 1;
5801 goto exit_gen_loop;
5802 }
5803
959082fc 5804 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
2e70f6ef 5805 gen_io_start();
667b8e29
RH		 5806 }
5807
0184e266 5808 insn = cpu_ldl_code(env, dc->pc);
b09b2fd3 5809
0184e266 5810 disas_sparc_insn(dc, insn);
0f8a249a
BS		 5811
5812 if (dc->is_br)
5813 break;
5814 /* if the next PC is different, we abort now */
5815 if (dc->pc != (last_pc + 4))
5816 break;
d39c0b99
FB		 5817 /* if we reach a page boundary, we stop generation so that the
5818 PC of a TT_TFAULT exception is always in the right page */
5819 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
5820 break;
e80cfcfc
FB		 5821 /* if single step mode, we generate only one instruction and
5822 generate an exception */
060718c1 5823 if (dc->singlestep) {
e80cfcfc
FB		 5824 break;
5825 }
fe700adb 5826 } while (!tcg_op_buf_full() &&
2e70f6ef
PB		 5827 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
5828 num_insns < max_insns);
e80cfcfc
FB		 5829
5830 exit_gen_loop:
b09b2fd3 5831 if (tb->cflags & CF_LAST_IO) {
2e70f6ef 5832 gen_io_end();
b09b2fd3 5833 }
72cbca10 5834 if (!dc->is_br) {
5fafdf24 5835 if (dc->pc != DYNAMIC_PC &&
72cbca10
FB		 5836 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
5837 /* static PC and NPC: we can use direct chaining */
2f5680ee 5838 gen_goto_tb(dc, 0, dc->pc, dc->npc);
72cbca10 5839 } else {
b09b2fd3 5840 if (dc->pc != DYNAMIC_PC) {
2f5680ee 5841 tcg_gen_movi_tl(cpu_pc, dc->pc);
b09b2fd3 5842 }
934da7ee 5843 save_npc(dc);
57fec1fe 5844 tcg_gen_exit_tb(0);
72cbca10
FB		 5845 }
5846 }
806f352d 5847 gen_tb_end(tb, num_insns);
0a7df5da 5848
4e5e1215
RH		 5849 tb->size = last_pc + 4 - pc_start;
5850 tb->icount = num_insns;
5851
7a3f1944 5852#ifdef DEBUG_DISAS
4910e6e4
RH		 5853 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5854 && qemu_log_in_addr_range(pc_start)) {
1ee73216 5855 qemu_log_lock();
93fcfe39
AL		 5856 qemu_log("--------------\n");
5857 qemu_log("IN: %s\n", lookup_symbol(pc_start));
d49190c4 5858 log_target_disas(cs, pc_start, last_pc + 4 - pc_start, 0);
93fcfe39 5859 qemu_log("\n");
1ee73216 5860 qemu_log_unlock();
cf495bcf 5861 }
7a3f1944 5862#endif
7a3f1944
FB		 5863}
5864
c48fcb47 5865void gen_intermediate_code_init(CPUSPARCState *env)
e80cfcfc 5866{
c48fcb47 5867 static int inited;
d2dc4069 5868 static const char gregnames[32][4] = {
0ea63844 5869 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
d2dc4069
RH		 5870 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
5871 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
5872 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
f5069b26 5873 };
0ea63844 5874 static const char fregnames[32][4] = {
30038fd8
RH		 5875 "f0", "f2", "f4", "f6", "f8", "f10", "f12", "f14",
5876 "f16", "f18", "f20", "f22", "f24", "f26", "f28", "f30",
5877 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
5878 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
714547bb 5879 };
aaed909a 5880
0ea63844 5881 static const struct { TCGv_i32 *ptr; int off; const char *name; } r32[] = {
1a2fb1c0 5882#ifdef TARGET_SPARC64
0ea63844 5883 { &cpu_xcc, offsetof(CPUSPARCState, xcc), "xcc" },
0ea63844 5884 { &cpu_fprs, offsetof(CPUSPARCState, fprs), "fprs" },
255e1fcb 5885#else
0ea63844
RH		 5886 { &cpu_wim, offsetof(CPUSPARCState, wim), "wim" },
5887#endif
5888 { &cpu_cc_op, offsetof(CPUSPARCState, cc_op), "cc_op" },
5889 { &cpu_psr, offsetof(CPUSPARCState, psr), "psr" },
5890 };
5891
5892 static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
5893#ifdef TARGET_SPARC64
5894 { &cpu_gsr, offsetof(CPUSPARCState, gsr), "gsr" },
5895 { &cpu_tick_cmpr, offsetof(CPUSPARCState, tick_cmpr), "tick_cmpr" },
5896 { &cpu_stick_cmpr, offsetof(CPUSPARCState, stick_cmpr), "stick_cmpr" },
5897 { &cpu_hstick_cmpr, offsetof(CPUSPARCState, hstick_cmpr),
5898 "hstick_cmpr" },
5899 { &cpu_hintp, offsetof(CPUSPARCState, hintp), "hintp" },
5900 { &cpu_htba, offsetof(CPUSPARCState, htba), "htba" },
5901 { &cpu_hver, offsetof(CPUSPARCState, hver), "hver" },
5902 { &cpu_ssr, offsetof(CPUSPARCState, ssr), "ssr" },
5903 { &cpu_ver, offsetof(CPUSPARCState, version), "ver" },
1a2fb1c0 5904#endif
0ea63844
RH		 5905 { &cpu_cond, offsetof(CPUSPARCState, cond), "cond" },
5906 { &cpu_cc_src, offsetof(CPUSPARCState, cc_src), "cc_src" },
5907 { &cpu_cc_src2, offsetof(CPUSPARCState, cc_src2), "cc_src2" },
5908 { &cpu_cc_dst, offsetof(CPUSPARCState, cc_dst), "cc_dst" },
5909 { &cpu_fsr, offsetof(CPUSPARCState, fsr), "fsr" },
5910 { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" },
5911 { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" },
5912 { &cpu_y, offsetof(CPUSPARCState, y), "y" },
255e1fcb 5913#ifndef CONFIG_USER_ONLY
0ea63844 5914 { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" },
255e1fcb 5915#endif
0ea63844
RH		 5916 };
5917
5918 unsigned int i;
5919
5920 /* init various static tables */
5921 if (inited) {
5922 return;
5923 }
5924 inited = 1;
5925
5926 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7c255043 5927 tcg_ctx.tcg_env = cpu_env;
0ea63844
RH		 5928
5929 cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
5930 offsetof(CPUSPARCState, regwptr),
5931 "regwptr");
5932
5933 for (i = 0; i < ARRAY_SIZE(r32); ++i) {
5934 *r32[i].ptr = tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i].name);
5935 }
5936
5937 for (i = 0; i < ARRAY_SIZE(rtl); ++i) {
5938 *rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
5939 }
5940
d2dc4069 5941 TCGV_UNUSED(cpu_regs[0]);
0ea63844 5942 for (i = 1; i < 8; ++i) {
d2dc4069
RH		 5943 cpu_regs[i] = tcg_global_mem_new(cpu_env,
5944 offsetof(CPUSPARCState, gregs[i]),
5945 gregnames[i]);
5946 }
5947
5948 for (i = 8; i < 32; ++i) {
5949 cpu_regs[i] = tcg_global_mem_new(cpu_regwptr,
5950 (i - 8) * sizeof(target_ulong),
5951 gregnames[i]);
0ea63844
RH		 5952 }
5953
5954 for (i = 0; i < TARGET_DPREGS; i++) {
5955 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
5956 offsetof(CPUSPARCState, fpr[i]),
5957 fregnames[i]);
1a2fb1c0 5958 }
658138bc 5959}
d2856f1a 5960
bad729e2
RH		 5961void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb,
5962 target_ulong *data)
d2856f1a 5963{
bad729e2
RH		 5964 target_ulong pc = data[0];
5965 target_ulong npc = data[1];
5966
5967 env->pc = pc;
6c42444f 5968 if (npc == DYNAMIC_PC) {
d2856f1a 5969 /* dynamic NPC: already stored */
6c42444f 5970 } else if (npc & JUMP_PC) {
d7da2a10
BS		 5971 /* jump PC: use 'cond' and the jump targets of the translation */
5972 if (env->cond) {
6c42444f 5973 env->npc = npc & ~3;
d7da2a10 5974 } else {
6c42444f 5975 env->npc = pc + 4;
d7da2a10 5976 }
d2856f1a
AJ		 5977 } else {
5978 env->npc = npc;
5979 }
5980}
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