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[qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
0442428a 24#include "qemu/qemu-print.h"
c6dc6f63
AP		 25
26#include "cpu.h"
63c91552 27#include "exec/exec-all.h"
9c17d615 28#include "sysemu/kvm.h"
71e8a915 29#include "sysemu/reset.h"
d6dcc558 30#include "sysemu/hvf.h"
8932cfdf 31#include "sysemu/cpus.h"
da278d58 32#include "sysemu/xen.h"
50a2c6e5 33#include "kvm_i386.h"
6cb8f2a6 34#include "sev_i386.h"
c6dc6f63 35
d49b6836 36#include "qemu/error-report.h"
0b8fa32f 37#include "qemu/module.h"
1de7afc9
PB		 38#include "qemu/option.h"
39#include "qemu/config-file.h"
e688df6b 40#include "qapi/error.h"
8ac25c84 41#include "qapi/qapi-visit-machine.h"
112ed241 42#include "qapi/qapi-visit-run-state.h"
452fcdbc 43#include "qapi/qmp/qdict.h"
7b1b5d19 44#include "qapi/qmp/qerror.h"
7b1b5d19 45#include "qapi/visitor.h"
f99fd7ca 46#include "qom/qom-qobject.h"
9c17d615 47#include "sysemu/arch_init.h"
7f7b4e7a 48#include "qapi/qapi-commands-machine-target.h"
71ad61d3 49
1814eab6 50#include "standard-headers/asm-x86/kvm_para.h"
65dee380 51
9c17d615 52#include "sysemu/sysemu.h"
14a48c1d 53#include "sysemu/tcg.h"
53a89e26 54#include "hw/qdev-properties.h"
5232d00a 55#include "hw/i386/topology.h"
bdeec802 56#ifndef CONFIG_USER_ONLY
2001d0cd 57#include "exec/address-spaces.h"
0d09e41a 58#include "hw/i386/apic_internal.h"
0e11fc69 59#include "hw/boards.h"
bdeec802
IM		 60#endif
61
b666d2a4
RH		 62#include "disas/capstone.h"
63
7e3482f8
EH		 64/* Helpers for building CPUID[2] descriptors: */
65
66struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72};
5e891bf8 73
7e3482f8
EH		 74/*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 80 .associativity = 4, .line_size = 32, },
5f00335a 81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 82 .associativity = 4, .line_size = 32, },
5f00335a 83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 84 .associativity = 4, .line_size = 64, },
5f00335a 85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 86 .associativity = 2, .line_size = 32, },
5f00335a 87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 88 .associativity = 4, .line_size = 32, },
5f00335a 89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 90 .associativity = 4, .line_size = 64, },
5f00335a 91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 92 .associativity = 6, .line_size = 64, },
5f00335a 93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 94 .associativity = 2, .line_size = 64, },
5f00335a 95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
5f00335a 100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
5f00335a 105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 106 .associativity = 8, .line_size = 64, },
5f00335a 107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 108 .associativity = 8, .line_size = 64, },
5f00335a 109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 110 .associativity = 4, .line_size = 32, },
5f00335a 111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 112 .associativity = 4, .line_size = 32, },
5f00335a 113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 114 .associativity = 4, .line_size = 32, },
5f00335a 115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 116 .associativity = 4, .line_size = 32, },
5f00335a 117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 118 .associativity = 4, .line_size = 32, },
5f00335a 119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 120 .associativity = 4, .line_size = 64, },
5f00335a 121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 122 .associativity = 8, .line_size = 64, },
5f00335a 123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 127 .associativity = 12, .line_size = 64, },
5f00335a 128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 129 .associativity = 16, .line_size = 64, },
5f00335a 130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 131 .associativity = 12, .line_size = 64, },
5f00335a 132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 133 .associativity = 16, .line_size = 64, },
5f00335a 134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 135 .associativity = 24, .line_size = 64, },
5f00335a 136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 137 .associativity = 8, .line_size = 64, },
5f00335a 138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 139 .associativity = 4, .line_size = 64, },
5f00335a 140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 141 .associativity = 4, .line_size = 64, },
5f00335a 142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 143 .associativity = 4, .line_size = 64, },
5f00335a 144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
5f00335a 149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 150 .associativity = 8, .line_size = 64, },
5f00335a 151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 152 .associativity = 2, .line_size = 64, },
5f00335a 153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 154 .associativity = 8, .line_size = 64, },
5f00335a 155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 156 .associativity = 8, .line_size = 32, },
5f00335a 157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 158 .associativity = 8, .line_size = 32, },
5f00335a 159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 160 .associativity = 8, .line_size = 32, },
5f00335a 161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 162 .associativity = 8, .line_size = 32, },
5f00335a 163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 164 .associativity = 4, .line_size = 64, },
5f00335a 165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 166 .associativity = 8, .line_size = 64, },
5f00335a 167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 168 .associativity = 4, .line_size = 64, },
5f00335a 169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 170 .associativity = 4, .line_size = 64, },
5f00335a 171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 172 .associativity = 4, .line_size = 64, },
5f00335a 173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 174 .associativity = 8, .line_size = 64, },
5f00335a 175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 176 .associativity = 8, .line_size = 64, },
5f00335a 177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 178 .associativity = 8, .line_size = 64, },
5f00335a 179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 180 .associativity = 12, .line_size = 64, },
5f00335a 181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 182 .associativity = 12, .line_size = 64, },
5f00335a 183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 184 .associativity = 12, .line_size = 64, },
5f00335a 185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 186 .associativity = 16, .line_size = 64, },
5f00335a 187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 188 .associativity = 16, .line_size = 64, },
5f00335a 189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 190 .associativity = 16, .line_size = 64, },
5f00335a 191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 192 .associativity = 24, .line_size = 64, },
5f00335a 193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 194 .associativity = 24, .line_size = 64, },
5f00335a 195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 196 .associativity = 24, .line_size = 64, },
197};
198
199/*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 204
7e3482f8
EH		 205/*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210{
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
5e891bf8 225
7e3482f8
EH		 226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227}
5e891bf8
EH		 228
229/* CPUID Leaf 4 constants: */
230
231/* EAX: */
7e3482f8
EH		 232#define CACHE_TYPE_D 1
233#define CACHE_TYPE_I 2
234#define CACHE_TYPE_UNIFIED 3
5e891bf8 235
7e3482f8 236#define CACHE_LEVEL(l) (l << 5)
5e891bf8 237
7e3482f8 238#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 239
240/* EDX: */
7e3482f8
EH		 241#define CACHE_NO_INVD_SHARING (1 << 0)
242#define CACHE_INCLUSIVE (1 << 1)
243#define CACHE_COMPLEX_IDX (1 << 2)
244
245/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 246#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
7e3482f8
EH		 250
251
252/* Encode cache info for CPUID[4] */
253static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257{
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283}
284
285/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287{
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294}
5e891bf8
EH		 295
296#define ASSOC_FULL 0xFF
297
298/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
7e3482f8
EH		 312/*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319{
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339}
5e891bf8 340
8f4202fb 341/* Encode cache info for CPUID[8000001D] */
dd08ef03
BM		 342static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
343 X86CPUTopoInfo *topo_info,
344 uint32_t *eax, uint32_t *ebx,
345 uint32_t *ecx, uint32_t *edx)
8f4202fb
BM		 346{
347 uint32_t l3_cores;
dd08ef03
BM		 348 unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
349
8f4202fb
BM		 350 assert(cache->size == cache->line_size * cache->associativity *
351 cache->partitions * cache->sets);
352
353 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
354 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
355
356 /* L3 is shared among multiple cores */
357 if (cache->level == 3) {
dd08ef03
BM		 358 l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
359 topo_info->cores_per_die *
360 topo_info->threads_per_core),
361 nodes);
362 *eax |= (l3_cores - 1) << 14;
8f4202fb 363 } else {
dd08ef03 364 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 365 }
366
367 assert(cache->line_size > 0);
368 assert(cache->partitions > 0);
369 assert(cache->associativity > 0);
370 /* We don't implement fully-associative caches */
371 assert(cache->associativity < cache->sets);
372 *ebx = (cache->line_size - 1) |
373 ((cache->partitions - 1) << 12) |
374 ((cache->associativity - 1) << 22);
375
376 assert(cache->sets > 0);
377 *ecx = cache->sets - 1;
378
379 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
380 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
381 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
382}
383
ed78467a 384/* Encode cache info for CPUID[8000001E] */
dd08ef03 385static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
ed78467a
BM		 386 uint32_t *eax, uint32_t *ebx,
387 uint32_t *ecx, uint32_t *edx)
388{
dd08ef03
BM		 389 X86CPUTopoIDs topo_ids = {0};
390 unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1);
631be321 391 int shift;
ed78467a 392
dd08ef03
BM		 393 x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids);
394
ed78467a
BM		 395 *eax = cpu->apic_id;
396 /*
397 * CPUID_Fn8000001E_EBX
398 * 31:16 Reserved
399 * 15:8 Threads per core (The number of threads per core is
400 * Threads per core + 1)
401 * 7:0 Core id (see bit decoding below)
402 * SMT:
403 * 4:3 node id
404 * 2 Core complex id
405 * 1:0 Core id
406 * Non SMT:
407 * 5:4 node id
408 * 3 Core complex id
409 * 1:0 Core id
410 */
dd08ef03
BM		 411 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id << 3) |
412 (topo_ids.core_id);
ed78467a
BM		 413 /*
414 * CPUID_Fn8000001E_ECX
415 * 31:11 Reserved
416 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
417 * 7:0 Node id (see bit decoding below)
418 * 2 Socket id
419 * 1:0 Node id
420 */
dd08ef03
BM		 421 if (nodes <= 4) {
422 *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id;
631be321
BM		 423 } else {
424 /*
425 * Node id fix up. Actual hardware supports up to 4 nodes. But with
426 * more than 32 cores, we may end up with more than 4 nodes.
427 * Node id is a combination of socket id and node id. Only requirement
428 * here is that this number should be unique accross the system.
429 * Shift the socket id to accommodate more nodes. We dont expect both
430 * socket id and node id to be big number at the same time. This is not
431 * an ideal config but we need to to support it. Max nodes we can have
432 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
433 * 5 bits for nodes. Find the left most set bit to represent the total
434 * number of nodes. find_last_bit returns last set bit(0 based). Left
435 * shift(+1) the socket id to represent all the nodes.
436 */
dd08ef03 437 nodes -= 1;
631be321 438 shift = find_last_bit(&nodes, 8);
dd08ef03
BM		 439 *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) |
440 topo_ids.node_id;
631be321 441 }
ed78467a
BM		 442 *edx = 0;
443}
444
ab8f992e
BM		 445/*
446 * Definitions of the hardcoded cache entries we expose:
447 * These are legacy cache values. If there is a need to change any
448 * of these values please use builtin_x86_defs
449 */
5e891bf8
EH		 450
451/* L1 data cache: */
ab8f992e 452static CPUCacheInfo legacy_l1d_cache = {
5f00335a 453 .type = DATA_CACHE,
7e3482f8
EH		 454 .level = 1,
455 .size = 32 * KiB,
456 .self_init = 1,
457 .line_size = 64,
458 .associativity = 8,
459 .sets = 64,
460 .partitions = 1,
461 .no_invd_sharing = true,
462};
463
5e891bf8 464/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 465static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 466 .type = DATA_CACHE,
7e3482f8
EH		 467 .level = 1,
468 .size = 64 * KiB,
469 .self_init = 1,
470 .line_size = 64,
471 .associativity = 2,
472 .sets = 512,
473 .partitions = 1,
474 .lines_per_tag = 1,
475 .no_invd_sharing = true,
476};
5e891bf8
EH		 477
478/* L1 instruction cache: */
ab8f992e 479static CPUCacheInfo legacy_l1i_cache = {
5f00335a 480 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 481 .level = 1,
482 .size = 32 * KiB,
483 .self_init = 1,
484 .line_size = 64,
485 .associativity = 8,
486 .sets = 64,
487 .partitions = 1,
488 .no_invd_sharing = true,
489};
490
5e891bf8 491/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 492static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 493 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 494 .level = 1,
495 .size = 64 * KiB,
496 .self_init = 1,
497 .line_size = 64,
498 .associativity = 2,
499 .sets = 512,
500 .partitions = 1,
501 .lines_per_tag = 1,
502 .no_invd_sharing = true,
503};
5e891bf8
EH		 504
505/* Level 2 unified cache: */
ab8f992e 506static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 507 .type = UNIFIED_CACHE,
508 .level = 2,
509 .size = 4 * MiB,
510 .self_init = 1,
511 .line_size = 64,
512 .associativity = 16,
513 .sets = 4096,
514 .partitions = 1,
515 .no_invd_sharing = true,
516};
517
5e891bf8 518/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 519static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 520 .type = UNIFIED_CACHE,
521 .level = 2,
522 .size = 2 * MiB,
523 .line_size = 64,
524 .associativity = 8,
525};
526
527
5e891bf8 528/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 529static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 530 .type = UNIFIED_CACHE,
531 .level = 2,
532 .size = 512 * KiB,
533 .line_size = 64,
534 .lines_per_tag = 1,
535 .associativity = 16,
536 .sets = 512,
537 .partitions = 1,
538};
5e891bf8 539
14c985cf 540/* Level 3 unified cache: */
ab8f992e 541static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 542 .type = UNIFIED_CACHE,
543 .level = 3,
544 .size = 16 * MiB,
545 .line_size = 64,
546 .associativity = 16,
547 .sets = 16384,
548 .partitions = 1,
549 .lines_per_tag = 1,
550 .self_init = true,
551 .inclusive = true,
552 .complex_indexing = true,
553};
5e891bf8
EH		 554
555/* TLB definitions: */
556
557#define L1_DTLB_2M_ASSOC 1
558#define L1_DTLB_2M_ENTRIES 255
559#define L1_DTLB_4K_ASSOC 1
560#define L1_DTLB_4K_ENTRIES 255
561
562#define L1_ITLB_2M_ASSOC 1
563#define L1_ITLB_2M_ENTRIES 255
564#define L1_ITLB_4K_ASSOC 1
565#define L1_ITLB_4K_ENTRIES 255
566
567#define L2_DTLB_2M_ASSOC 0 /* disabled */
568#define L2_DTLB_2M_ENTRIES 0 /* disabled */
569#define L2_DTLB_4K_ASSOC 4
570#define L2_DTLB_4K_ENTRIES 512
571
572#define L2_ITLB_2M_ASSOC 0 /* disabled */
573#define L2_ITLB_2M_ENTRIES 0 /* disabled */
574#define L2_ITLB_4K_ASSOC 4
575#define L2_ITLB_4K_ENTRIES 512
576
e37a5c7f
CP		 577/* CPUID Leaf 0x14 constants: */
578#define INTEL_PT_MAX_SUBLEAF 0x1
579/*
580 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
581 * MSR can be accessed;
582 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
583 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
584 * of Intel PT MSRs across warm reset;
585 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
586 */
587#define INTEL_PT_MINIMAL_EBX 0xf
588/*
589 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
590 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
591 * accessed;
592 * bit[01]: ToPA tables can hold any number of output entries, up to the
593 * maximum allowed by the MaskOrTableOffset field of
594 * IA32_RTIT_OUTPUT_MASK_PTRS;
595 * bit[02]: Support Single-Range Output scheme;
596 */
597#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 598/* generated packets which contain IP payloads have LIP values */
599#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 600#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
601#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
602#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
603#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
604#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 605
99b88a17
IM		 606static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
607 uint32_t vendor2, uint32_t vendor3)
608{
609 int i;
610 for (i = 0; i < 4; i++) {
611 dst[i] = vendor1 >> (8 * i);
612 dst[i + 4] = vendor2 >> (8 * i);
613 dst[i + 8] = vendor3 >> (8 * i);
614 }
615 dst[CPUID_VENDOR_SZ] = '\0';
616}
617
621626ce
EH		 618#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
619#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
620 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
621#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
622 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
623 CPUID_PSE36 | CPUID_FXSR)
624#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
625#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
626 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
627 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
628 CPUID_PAE | CPUID_SEP | CPUID_APIC)
629
630#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
631 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
632 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
633 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 634 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 635 /* partly implemented:
636 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
637 /* missing:
638 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
639#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
644 CPUID_EXT_RDRAND)
621626ce
EH		 645 /* missing:
646 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
647 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
648 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 649 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 650 CPUID_EXT_F16C */
621626ce
EH		 651
652#ifdef TARGET_X86_64
653#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
654#else
655#define TCG_EXT2_X86_64_FEATURES 0
656#endif
657
658#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
659 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
660 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
661 TCG_EXT2_X86_64_FEATURES)
662#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
663 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
664#define TCG_EXT4_FEATURES 0
fe441054 665#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 666#define TCG_KVM_FEATURES 0
667#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 668 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
669 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 670 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
671 CPUID_7_0_EBX_ERMS)
621626ce 672 /* missing:
07929f2a 673 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 674 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 675 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 676#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
677 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 678 CPUID_7_0_ECX_LA57)
95ea69fb 679#define TCG_7_0_EDX_FEATURES 0
80db491d 680#define TCG_7_1_EAX_FEATURES 0
303752a9 681#define TCG_APM_FEATURES 0
28b8e4d0 682#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 683#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
684 /* missing:
685 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 686
07585923
RH		 687typedef enum FeatureWordType {
688 CPUID_FEATURE_WORD,
689 MSR_FEATURE_WORD,
690} FeatureWordType;
691
5ef57876 692typedef struct FeatureWordInfo {
07585923 693 FeatureWordType type;
2d5312da
EH		 694 /* feature flags names are taken from "Intel Processor Identification and
695 * the CPUID Instruction" and AMD's "CPUID Specification".
696 * In cases of disagreement between feature naming conventions,
697 * aliases may be added.
698 */
ede146c2 699 const char *feat_names[64];
07585923
RH		 700 union {
701 /* If type==CPUID_FEATURE_WORD */
702 struct {
703 uint32_t eax; /* Input EAX for CPUID */
704 bool needs_ecx; /* CPUID instruction uses ECX as input */
705 uint32_t ecx; /* Input ECX value for CPUID */
706 int reg; /* output register (R_* constant) */
707 } cpuid;
708 /* If type==MSR_FEATURE_WORD */
709 struct {
710 uint32_t index;
07585923
RH		 711 } msr;
712 };
ede146c2
PB		 713 uint64_t tcg_features; /* Feature flags supported by TCG */
714 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
715 uint64_t migratable_flags; /* Feature flags known to be migratable */
0d914f39 716 /* Features that shouldn't be auto-enabled by "-cpu host" */
ede146c2 717 uint64_t no_autoenable_flags;
5ef57876
EH		 718} FeatureWordInfo;
719
720static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 721 [FEAT_1_EDX] = {
07585923 722 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 723 .feat_names = {
724 "fpu", "vme", "de", "pse",
725 "tsc", "msr", "pae", "mce",
726 "cx8", "apic", NULL, "sep",
727 "mtrr", "pge", "mca", "cmov",
728 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
729 NULL, "ds" /* Intel dts */, "acpi", "mmx",
730 "fxsr", "sse", "sse2", "ss",
731 "ht" /* Intel htt */, "tm", "ia64", "pbe",
732 },
07585923 733 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 734 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 735 },
736 [FEAT_1_ECX] = {
07585923 737 .type = CPUID_FEATURE_WORD,
2d5312da 738 .feat_names = {
16d2fcaa 739 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 740 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 741 "tm2", "ssse3", "cid", NULL,
742 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 743 NULL, "pcid", "dca", "sse4.1",
744 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 745 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 746 "avx", "f16c", "rdrand", "hypervisor",
747 },
07585923 748 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 749 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 750 },
2d5312da
EH		 751 /* Feature names that are already defined on feature_name[] but
752 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
753 * names on feat_names below. They are copied automatically
754 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
755 */
bffd67b0 756 [FEAT_8000_0001_EDX] = {
07585923 757 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 758 .feat_names = {
759 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
760 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
761 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
762 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
763 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 764 "nx", NULL, "mmxext", NULL /* mmx */,
765 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
766 NULL, "lm", "3dnowext", "3dnow",
2d5312da 767 },
07585923 768 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 769 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 770 },
771 [FEAT_8000_0001_ECX] = {
07585923 772 .type = CPUID_FEATURE_WORD,
2d5312da 773 .feat_names = {
fc7dfd20 774 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 775 "cr8legacy", "abm", "sse4a", "misalignsse",
776 "3dnowprefetch", "osvw", "ibs", "xop",
777 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 778 "fma4", "tce", NULL, "nodeid-msr",
779 NULL, "tbm", "topoext", "perfctr-core",
780 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 781 NULL, NULL, NULL, NULL,
782 },
07585923 783 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 784 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 785 /*
786 * TOPOEXT is always allowed but can't be enabled blindly by
787 * "-cpu host", as it requires consistent cache topology info
788 * to be provided so it doesn't confuse guests.
789 */
790 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 791 },
89e49c8b 792 [FEAT_C000_0001_EDX] = {
07585923 793 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 794 .feat_names = {
795 NULL, NULL, "xstore", "xstore-en",
796 NULL, NULL, "xcrypt", "xcrypt-en",
797 "ace2", "ace2-en", "phe", "phe-en",
798 "pmm", "pmm-en", NULL, NULL,
799 NULL, NULL, NULL, NULL,
800 NULL, NULL, NULL, NULL,
801 NULL, NULL, NULL, NULL,
802 NULL, NULL, NULL, NULL,
803 },
07585923 804 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 805 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 806 },
bffd67b0 807 [FEAT_KVM] = {
07585923 808 .type = CPUID_FEATURE_WORD,
2d5312da 809 .feat_names = {
fc7dfd20
EH		 810 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
811 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 812 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
b896c4b5 813 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
2d5312da
EH		 814 NULL, NULL, NULL, NULL,
815 NULL, NULL, NULL, NULL,
816 "kvmclock-stable-bit", NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 },
07585923 819 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 820 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 821 },
be777326 822 [FEAT_KVM_HINTS] = {
07585923 823 .type = CPUID_FEATURE_WORD,
be777326
WL		 824 .feat_names = {
825 "kvm-hint-dedicated", NULL, NULL, NULL,
826 NULL, NULL, NULL, NULL,
827 NULL, NULL, NULL, NULL,
828 NULL, NULL, NULL, NULL,
829 NULL, NULL, NULL, NULL,
830 NULL, NULL, NULL, NULL,
831 NULL, NULL, NULL, NULL,
832 NULL, NULL, NULL, NULL,
833 },
07585923 834 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 835 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 836 /*
837 * KVM hints aren't auto-enabled by -cpu host, they need to be
838 * explicitly enabled in the command-line.
839 */
840 .no_autoenable_flags = ~0U,
be777326 841 },
abd5fc4c
VK		 842 /*
843 * .feat_names are commented out for Hyper-V enlightenments because we
844 * don't want to have two different ways for enabling them on QEMU command
845 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
846 * enabling several feature bits simultaneously, exposing these bits
847 * individually may just confuse guests.
848 */
c35bd19a 849 [FEAT_HYPERV_EAX] = {
07585923 850 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 851 .feat_names = {
852 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
853 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
854 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
855 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
856 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
857 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 858 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
859 NULL, NULL,
2d5312da
EH		 860 NULL, NULL, NULL, NULL,
861 NULL, NULL, NULL, NULL,
862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 },
07585923 865 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 866 },
867 [FEAT_HYPERV_EBX] = {
07585923 868 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 869 .feat_names = {
870 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
871 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
872 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
873 NULL /* hv_create_port */, NULL /* hv_connect_port */,
874 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
875 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
876 NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
07585923 882 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 883 },
884 [FEAT_HYPERV_EDX] = {
07585923 885 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 886 .feat_names = {
887 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
888 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
889 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
890 NULL, NULL,
891 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 },
07585923 898 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 899 },
a2b107db
VK		 900 [FEAT_HV_RECOMM_EAX] = {
901 .type = CPUID_FEATURE_WORD,
902 .feat_names = {
903 NULL /* hv_recommend_pv_as_switch */,
904 NULL /* hv_recommend_pv_tlbflush_local */,
905 NULL /* hv_recommend_pv_tlbflush_remote */,
906 NULL /* hv_recommend_msr_apic_access */,
907 NULL /* hv_recommend_msr_reset */,
908 NULL /* hv_recommend_relaxed_timing */,
909 NULL /* hv_recommend_dma_remapping */,
910 NULL /* hv_recommend_int_remapping */,
911 NULL /* hv_recommend_x2apic_msrs */,
912 NULL /* hv_recommend_autoeoi_deprecation */,
913 NULL /* hv_recommend_pv_ipi */,
914 NULL /* hv_recommend_ex_hypercalls */,
915 NULL /* hv_hypervisor_is_nested */,
916 NULL /* hv_recommend_int_mbec */,
917 NULL /* hv_recommend_evmcs */,
918 NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
924 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
925 },
926 [FEAT_HV_NESTED_EAX] = {
927 .type = CPUID_FEATURE_WORD,
928 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
929 },
bffd67b0 930 [FEAT_SVM] = {
07585923 931 .type = CPUID_FEATURE_WORD,
2d5312da 932 .feat_names = {
fc7dfd20
EH		 933 "npt", "lbrv", "svm-lock", "nrip-save",
934 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
935 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 936 "pfthreshold", NULL, NULL, NULL,
937 NULL, NULL, NULL, NULL,
938 NULL, NULL, NULL, NULL,
939 NULL, NULL, NULL, NULL,
940 NULL, NULL, NULL, NULL,
941 },
07585923 942 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 943 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 944 },
945 [FEAT_7_0_EBX] = {
07585923 946 .type = CPUID_FEATURE_WORD,
2d5312da 947 .feat_names = {
fc7dfd20 948 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 949 "hle", "avx2", NULL, "smep",
950 "bmi2", "erms", "invpcid", "rtm",
951 NULL, NULL, "mpx", NULL,
952 "avx512f", "avx512dq", "rdseed", "adx",
953 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 954 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 955 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 956 },
07585923
RH		 957 .cpuid = {
958 .eax = 7,
959 .needs_ecx = true, .ecx = 0,
960 .reg = R_EBX,
961 },
37ce3522 962 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 963 },
f74eefe0 964 [FEAT_7_0_ECX] = {
07585923 965 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 966 .feat_names = {
967 NULL, "avx512vbmi", "umip", "pku",
67192a29 968 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 969 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
970 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 971 "la57", NULL, NULL, NULL,
2d5312da 972 NULL, NULL, "rdpid", NULL,
24261de4 973 NULL, "cldemote", NULL, "movdiri",
1c65775f 974 "movdir64b", NULL, NULL, NULL,
2d5312da 975 },
07585923
RH		 976 .cpuid = {
977 .eax = 7,
978 .needs_ecx = true, .ecx = 0,
979 .reg = R_ECX,
980 },
f74eefe0
HH		 981 .tcg_features = TCG_7_0_ECX_FEATURES,
982 },
95ea69fb 983 [FEAT_7_0_EDX] = {
07585923 984 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 985 .feat_names = {
986 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
987 NULL, NULL, NULL, NULL,
353f98c9 988 "avx512-vp2intersect", NULL, "md-clear", NULL,
95ea69fb 989 NULL, NULL, NULL, NULL,
2924ab02 990 NULL, NULL, NULL /* pconfig */, NULL,
95ea69fb 991 NULL, NULL, NULL, NULL,
0e891658 992 NULL, NULL, "spec-ctrl", "stibp",
597360c0 993 NULL, "arch-capabilities", "core-capability", "ssbd",
95ea69fb 994 },
07585923
RH		 995 .cpuid = {
996 .eax = 7,
997 .needs_ecx = true, .ecx = 0,
998 .reg = R_EDX,
999 },
95ea69fb
LK		 1000 .tcg_features = TCG_7_0_EDX_FEATURES,
1001 },
80db491d
JL		 1002 [FEAT_7_1_EAX] = {
1003 .type = CPUID_FEATURE_WORD,
1004 .feat_names = {
1005 NULL, NULL, NULL, NULL,
1006 NULL, "avx512-bf16", NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 NULL, NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL,
1010 NULL, NULL, NULL, NULL,
1011 NULL, NULL, NULL, NULL,
1012 NULL, NULL, NULL, NULL,
1013 },
1014 .cpuid = {
1015 .eax = 7,
1016 .needs_ecx = true, .ecx = 1,
1017 .reg = R_EAX,
1018 },
1019 .tcg_features = TCG_7_1_EAX_FEATURES,
1020 },
303752a9 1021 [FEAT_8000_0007_EDX] = {
07585923 1022 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1023 .feat_names = {
1024 NULL, NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL,
1026 "invtsc", NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 },
07585923 1033 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1034 .tcg_features = TCG_APM_FEATURES,
1035 .unmigratable_flags = CPUID_APM_INVTSC,
1036 },
1b3420e1 1037 [FEAT_8000_0008_EBX] = {
07585923 1038 .type = CPUID_FEATURE_WORD,
1b3420e1 1039 .feat_names = {
e900135d 1040 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 1041 NULL, NULL, NULL, NULL,
59a80a19 1042 NULL, "wbnoinvd", NULL, NULL,
143c30d4 1043 "ibpb", NULL, NULL, "amd-stibp",
1b3420e1
EH		 1044 NULL, NULL, NULL, NULL,
1045 NULL, NULL, NULL, NULL,
254790a9 1046 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1047 NULL, NULL, NULL, NULL,
1048 },
07585923 1049 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1050 .tcg_features = 0,
1051 .unmigratable_flags = 0,
1052 },
0bb0b2d2 1053 [FEAT_XSAVE] = {
07585923 1054 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1055 .feat_names = {
1056 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1057 NULL, NULL, NULL, NULL,
1058 NULL, NULL, NULL, NULL,
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 NULL, NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL,
1064 },
07585923
RH		 1065 .cpuid = {
1066 .eax = 0xd,
1067 .needs_ecx = true, .ecx = 1,
1068 .reg = R_EAX,
1069 },
c9cfe8f9 1070 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1071 },
28b8e4d0 1072 [FEAT_6_EAX] = {
07585923 1073 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1074 .feat_names = {
1075 NULL, NULL, "arat", NULL,
1076 NULL, NULL, NULL, NULL,
1077 NULL, NULL, NULL, NULL,
1078 NULL, NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, NULL, NULL,
1082 NULL, NULL, NULL, NULL,
1083 },
07585923 1084 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1085 .tcg_features = TCG_6_EAX_FEATURES,
1086 },
96193c22 1087 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1088 .type = CPUID_FEATURE_WORD,
1089 .cpuid = {
1090 .eax = 0xD,
1091 .needs_ecx = true, .ecx = 0,
1092 .reg = R_EAX,
1093 },
96193c22 1094 .tcg_features = ~0U,
6fb2fff7
EH		 1095 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1096 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1097 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1098 XSTATE_PKRU_MASK,
96193c22
EH		 1099 },
1100 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1101 .type = CPUID_FEATURE_WORD,
1102 .cpuid = {
1103 .eax = 0xD,
1104 .needs_ecx = true, .ecx = 0,
1105 .reg = R_EDX,
1106 },
96193c22
EH		 1107 .tcg_features = ~0U,
1108 },
d86f9636
RH		 1109 /*Below are MSR exposed features*/
1110 [FEAT_ARCH_CAPABILITIES] = {
1111 .type = MSR_FEATURE_WORD,
1112 .feat_names = {
1113 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 1114 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 1115 "taa-no", NULL, NULL, NULL,
d86f9636
RH		 1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 },
1122 .msr = {
1123 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 1124 },
1125 },
597360c0
XL		 1126 [FEAT_CORE_CAPABILITY] = {
1127 .type = MSR_FEATURE_WORD,
1128 .feat_names = {
1129 NULL, NULL, NULL, NULL,
1130 NULL, "split-lock-detect", NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 },
1138 .msr = {
1139 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1140 },
1141 },
ea39f9b6
LX		 1142 [FEAT_PERF_CAPABILITIES] = {
1143 .type = MSR_FEATURE_WORD,
1144 .feat_names = {
1145 NULL, NULL, NULL, NULL,
1146 NULL, NULL, NULL, NULL,
1147 NULL, NULL, NULL, NULL,
1148 NULL, "full-width-write", NULL, NULL,
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 },
1154 .msr = {
1155 .index = MSR_IA32_PERF_CAPABILITIES,
1156 },
1157 },
20a78b02
PB		 1158
1159 [FEAT_VMX_PROCBASED_CTLS] = {
1160 .type = MSR_FEATURE_WORD,
1161 .feat_names = {
1162 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1163 NULL, NULL, NULL, "vmx-hlt-exit",
1164 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1165 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1166 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1167 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1168 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1169 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1170 },
1171 .msr = {
1172 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1173 }
1174 },
1175
1176 [FEAT_VMX_SECONDARY_CTLS] = {
1177 .type = MSR_FEATURE_WORD,
1178 .feat_names = {
1179 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1180 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1181 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1182 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1183 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1184 "vmx-xsaves", NULL, NULL, NULL,
1185 NULL, NULL, NULL, NULL,
1186 NULL, NULL, NULL, NULL,
1187 },
1188 .msr = {
1189 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1190 }
1191 },
1192
1193 [FEAT_VMX_PINBASED_CTLS] = {
1194 .type = MSR_FEATURE_WORD,
1195 .feat_names = {
1196 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1197 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1198 NULL, NULL, NULL, NULL,
1199 NULL, NULL, NULL, NULL,
1200 NULL, NULL, NULL, NULL,
1201 NULL, NULL, NULL, NULL,
1202 NULL, NULL, NULL, NULL,
1203 NULL, NULL, NULL, NULL,
1204 },
1205 .msr = {
1206 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1207 }
1208 },
1209
1210 [FEAT_VMX_EXIT_CTLS] = {
1211 .type = MSR_FEATURE_WORD,
1212 /*
1213 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1214 * the LM CPUID bit.
1215 */
1216 .feat_names = {
1217 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1218 NULL, NULL, NULL, NULL,
1219 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1220 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1221 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1222 "vmx-exit-save-efer", "vmx-exit-load-efer",
1223 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1224 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1225 NULL, NULL, NULL, NULL,
1226 },
1227 .msr = {
1228 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1229 }
1230 },
1231
1232 [FEAT_VMX_ENTRY_CTLS] = {
1233 .type = MSR_FEATURE_WORD,
1234 .feat_names = {
1235 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1236 NULL, NULL, NULL, NULL,
1237 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1238 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1239 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1240 NULL, NULL, NULL, NULL,
1241 NULL, NULL, NULL, NULL,
1242 NULL, NULL, NULL, NULL,
1243 },
1244 .msr = {
1245 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1246 }
1247 },
1248
1249 [FEAT_VMX_MISC] = {
1250 .type = MSR_FEATURE_WORD,
1251 .feat_names = {
1252 NULL, NULL, NULL, NULL,
1253 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1254 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1255 NULL, NULL, NULL, NULL,
1256 NULL, NULL, NULL, NULL,
1257 NULL, NULL, NULL, NULL,
1258 NULL, NULL, NULL, NULL,
1259 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1260 },
1261 .msr = {
1262 .index = MSR_IA32_VMX_MISC,
1263 }
1264 },
1265
1266 [FEAT_VMX_EPT_VPID_CAPS] = {
1267 .type = MSR_FEATURE_WORD,
1268 .feat_names = {
1269 "vmx-ept-execonly", NULL, NULL, NULL,
1270 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1271 NULL, NULL, NULL, NULL,
1272 NULL, NULL, NULL, NULL,
1273 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1274 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1275 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1276 NULL, NULL, NULL, NULL,
1277 "vmx-invvpid", NULL, NULL, NULL,
1278 NULL, NULL, NULL, NULL,
1279 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1280 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1281 NULL, NULL, NULL, NULL,
1282 NULL, NULL, NULL, NULL,
1283 NULL, NULL, NULL, NULL,
1284 NULL, NULL, NULL, NULL,
1285 NULL, NULL, NULL, NULL,
1286 },
1287 .msr = {
1288 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1289 }
1290 },
1291
1292 [FEAT_VMX_BASIC] = {
1293 .type = MSR_FEATURE_WORD,
1294 .feat_names = {
1295 [54] = "vmx-ins-outs",
1296 [55] = "vmx-true-ctls",
1297 },
1298 .msr = {
1299 .index = MSR_IA32_VMX_BASIC,
1300 },
1301 /* Just to be safe - we don't support setting the MSEG version field. */
1302 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1303 },
1304
1305 [FEAT_VMX_VMFUNC] = {
1306 .type = MSR_FEATURE_WORD,
1307 .feat_names = {
1308 [0] = "vmx-eptp-switching",
1309 },
1310 .msr = {
1311 .index = MSR_IA32_VMX_VMFUNC,
1312 }
1313 },
1314
5ef57876
EH		 1315};
1316
99e24dbd
PB		 1317typedef struct FeatureMask {
1318 FeatureWord index;
ede146c2 1319 uint64_t mask;
99e24dbd
PB		 1320} FeatureMask;
1321
1322typedef struct FeatureDep {
1323 FeatureMask from, to;
1324} FeatureDep;
1325
1326static FeatureDep feature_dependencies[] = {
1327 {
1328 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1329 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1330 },
1331 {
1332 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1333 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1334 },
ea39f9b6
LX		 1335 {
1336 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1337 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1338 },
20a78b02
PB		 1339 {
1340 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1341 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1342 },
1343 {
1344 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1345 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1346 },
1347 {
1348 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1349 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1350 },
1351 {
1352 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1353 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1354 },
1355 {
1356 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1357 .to = { FEAT_VMX_MISC, ~0ull },
1358 },
1359 {
1360 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1361 .to = { FEAT_VMX_BASIC, ~0ull },
1362 },
1363 {
1364 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1365 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1366 },
1367 {
1368 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1369 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1370 },
1371 {
1372 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1373 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1374 },
1375 {
1376 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1377 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1378 },
1379 {
1380 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1381 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1382 },
1383 {
1384 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1385 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1386 },
1387 {
1388 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1389 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1390 },
1391 {
1392 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1393 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1394 },
1395 {
1396 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1397 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1398 },
1399 {
1400 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1401 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1402 },
1403 {
1404 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1405 .to = { FEAT_VMX_VMFUNC, ~0ull },
1406 },
730319ae
EH		 1407 {
1408 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1409 .to = { FEAT_SVM, ~0ull },
1410 },
99e24dbd
PB		 1411};
1412
8e8aba50
EH		 1413typedef struct X86RegisterInfo32 {
1414 /* Name of register */
1415 const char *name;
1416 /* QAPI enum value register */
1417 X86CPURegister32 qapi_enum;
1418} X86RegisterInfo32;
1419
1420#define REGISTER(reg) \
5d371f41 1421 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1422static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1423 REGISTER(EAX),
1424 REGISTER(ECX),
1425 REGISTER(EDX),
1426 REGISTER(EBX),
1427 REGISTER(ESP),
1428 REGISTER(EBP),
1429 REGISTER(ESI),
1430 REGISTER(EDI),
1431};
1432#undef REGISTER
1433
3f32bd21
RH		 1434typedef struct ExtSaveArea {
1435 uint32_t feature, bits;
1436 uint32_t offset, size;
1437} ExtSaveArea;
1438
1439static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1440 [XSTATE_FP_BIT] = {
1441 /* x87 FP state component is always enabled if XSAVE is supported */
1442 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1443 /* x87 state is in the legacy region of the XSAVE area */
1444 .offset = 0,
1445 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1446 },
1447 [XSTATE_SSE_BIT] = {
1448 /* SSE state component is always enabled if XSAVE is supported */
1449 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1450 /* SSE state is in the legacy region of the XSAVE area */
1451 .offset = 0,
1452 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1453 },
cfc3b074
PB		 1454 [XSTATE_YMM_BIT] =
1455 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1456 .offset = offsetof(X86XSaveArea, avx_state),
1457 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1458 [XSTATE_BNDREGS_BIT] =
1459 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1460 .offset = offsetof(X86XSaveArea, bndreg_state),
1461 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1462 [XSTATE_BNDCSR_BIT] =
1463 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1464 .offset = offsetof(X86XSaveArea, bndcsr_state),
1465 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1466 [XSTATE_OPMASK_BIT] =
1467 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1468 .offset = offsetof(X86XSaveArea, opmask_state),
1469 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1470 [XSTATE_ZMM_Hi256_BIT] =
1471 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1472 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1473 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1474 [XSTATE_Hi16_ZMM_BIT] =
1475 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1476 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1477 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1478 [XSTATE_PKRU_BIT] =
1479 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1480 .offset = offsetof(X86XSaveArea, pkru_state),
1481 .size = sizeof(XSavePKRU) },
2560f19f 1482};
8e8aba50 1483
1fda6198
EH		 1484static uint32_t xsave_area_size(uint64_t mask)
1485{
1486 int i;
e3c9022b 1487 uint64_t ret = 0;
1fda6198 1488
e3c9022b 1489 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1490 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1491 if ((mask >> i) & 1) {
1492 ret = MAX(ret, esa->offset + esa->size);
1493 }
1494 }
1495 return ret;
1496}
1497
d6dcc558
SAGDR		 1498static inline bool accel_uses_host_cpuid(void)
1499{
1500 return kvm_enabled() || hvf_enabled();
1501}
1502
96193c22
EH		 1503static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1504{
1505 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1506 cpu->env.features[FEAT_XSAVE_COMP_LO];
1507}
1508
8b4beddc
EH		 1509const char *get_register_name_32(unsigned int reg)
1510{
31ccdde2 1511 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1512 return NULL;
1513 }
8e8aba50 1514 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1515}
1516
84f1b92f
EH		 1517/*
1518 * Returns the set of feature flags that are supported and migratable by
1519 * QEMU, for a given FeatureWord.
1520 */
ede146c2 1521static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1522{
1523 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1524 uint64_t r = 0;
84f1b92f
EH		 1525 int i;
1526
ede146c2
PB		 1527 for (i = 0; i < 64; i++) {
1528 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1529
1530 /* If the feature name is known, it is implicitly considered migratable,
1531 * unless it is explicitly set in unmigratable_flags */
1532 if ((wi->migratable_flags & f) ||
1533 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1534 r |= f;
84f1b92f 1535 }
84f1b92f
EH		 1536 }
1537 return r;
1538}
1539
bb44e0d1
JK		 1540void host_cpuid(uint32_t function, uint32_t count,
1541 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1542{
a1fd24af
AL		 1543 uint32_t vec[4];
1544
1545#ifdef __x86_64__
1546 asm volatile("cpuid"
1547 : "=a"(vec[0]), "=b"(vec[1]),
1548 "=c"(vec[2]), "=d"(vec[3])
1549 : "0"(function), "c"(count) : "cc");
c1f41226 1550#elif defined(__i386__)
a1fd24af
AL		 1551 asm volatile("pusha \n\t"
1552 "cpuid \n\t"
1553 "mov %%eax, 0(%2) \n\t"
1554 "mov %%ebx, 4(%2) \n\t"
1555 "mov %%ecx, 8(%2) \n\t"
1556 "mov %%edx, 12(%2) \n\t"
1557 "popa"
1558 : : "a"(function), "c"(count), "S"(vec)
1559 : "memory", "cc");
c1f41226
EH		 1560#else
1561 abort();
a1fd24af
AL		 1562#endif
1563
bdde476a 1564 if (eax)
a1fd24af 1565 *eax = vec[0];
bdde476a 1566 if (ebx)
a1fd24af 1567 *ebx = vec[1];
bdde476a 1568 if (ecx)
a1fd24af 1569 *ecx = vec[2];
bdde476a 1570 if (edx)
a1fd24af 1571 *edx = vec[3];
bdde476a 1572}
c6dc6f63 1573
20271d48
EH		 1574void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1575{
1576 uint32_t eax, ebx, ecx, edx;
1577
1578 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1579 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1580
1581 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1582 if (family) {
1583 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1584 }
1585 if (model) {
1586 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1587 }
1588 if (stepping) {
1589 *stepping = eax & 0x0F;
1590 }
1591}
1592
d940ee9b
EH		 1593/* CPU class name definitions: */
1594
d940ee9b
EH		 1595/* Return type name for a given CPU model name
1596 * Caller is responsible for freeing the returned string.
1597 */
1598static char *x86_cpu_type_name(const char *model_name)
1599{
1600 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1601}
1602
500050d1
AF		 1603static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1604{
88703ce2
EH		 1605 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1606 return object_class_by_name(typename);
500050d1
AF		 1607}
1608
104494ea
IM		 1609static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1610{
1611 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1612 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1613 return g_strndup(class_name,
1614 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1615}
1616
dcafd1ef
EH		 1617typedef struct PropValue {
1618 const char *prop, *value;
1619} PropValue;
1620
1621typedef struct X86CPUVersionDefinition {
1622 X86CPUVersion version;
53db89d9 1623 const char *alias;
c63938df 1624 const char *note;
dcafd1ef
EH		 1625 PropValue *props;
1626} X86CPUVersionDefinition;
1627
1628/* Base definition for a CPU model */
1629typedef struct X86CPUDefinition {
c6dc6f63
AP		 1630 const char *name;
1631 uint32_t level;
90e4b0c3 1632 uint32_t xlevel;
99b88a17
IM		 1633 /* vendor is zero-terminated, 12 character ASCII string */
1634 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1635 int family;
1636 int model;
1637 int stepping;
0514ef2f 1638 FeatureWordArray features;
807e9869 1639 const char *model_id;
6aaeb054 1640 CPUCaches *cache_info;
0c1538cb
BM		 1641
1642 /* Use AMD EPYC encoding for apic id */
1643 bool use_epyc_apic_id_encoding;
1644
dcafd1ef
EH		 1645 /*
1646 * Definitions for alternative versions of CPU model.
1647 * List is terminated by item with version == 0.
1648 * If NULL, version 1 will be registered automatically.
1649 */
1650 const X86CPUVersionDefinition *versions;
1651} X86CPUDefinition;
1652
1653/* Reference to a specific CPU model version */
1654struct X86CPUModel {
1655 /* Base CPU definition */
1656 X86CPUDefinition *cpudef;
1657 /* CPU model version */
1658 X86CPUVersion version;
c63938df 1659 const char *note;
0788a56b
EH		 1660 /*
1661 * If true, this is an alias CPU model.
1662 * This matters only for "-cpu help" and query-cpu-definitions
1663 */
1664 bool is_alias;
d940ee9b 1665};
c6dc6f63 1666
dcafd1ef
EH		 1667/* Get full model name for CPU version */
1668static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1669 X86CPUVersion version)
1670{
1671 assert(version > 0);
1672 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1673}
1674
1675static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1676{
1677 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1678 static const X86CPUVersionDefinition default_version_list[] = {
1679 { 1 },
1680 { /* end of list */ }
1681 };
1682
1683 return def->versions ?: default_version_list;
1684}
1685
0c1538cb
BM		 1686bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type)
1687{
1688 X86CPUClass *xcc = X86_CPU_CLASS(object_class_by_name(cpu_type));
1689
1690 assert(xcc);
1691 if (xcc->model && xcc->model->cpudef) {
1692 return xcc->model->cpudef->use_epyc_apic_id_encoding;
1693 } else {
1694 return false;
1695 }
1696}
1697
fe52acd2 1698static CPUCaches epyc_cache_info = {
a9f27ea9 1699 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1700 .type = DATA_CACHE,
fe52acd2
BM		 1701 .level = 1,
1702 .size = 32 * KiB,
1703 .line_size = 64,
1704 .associativity = 8,
1705 .partitions = 1,
1706 .sets = 64,
1707 .lines_per_tag = 1,
1708 .self_init = 1,
1709 .no_invd_sharing = true,
1710 },
a9f27ea9 1711 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1712 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1713 .level = 1,
1714 .size = 64 * KiB,
1715 .line_size = 64,
1716 .associativity = 4,
1717 .partitions = 1,
1718 .sets = 256,
1719 .lines_per_tag = 1,
1720 .self_init = 1,
1721 .no_invd_sharing = true,
1722 },
a9f27ea9 1723 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1724 .type = UNIFIED_CACHE,
1725 .level = 2,
1726 .size = 512 * KiB,
1727 .line_size = 64,
1728 .associativity = 8,
1729 .partitions = 1,
1730 .sets = 1024,
1731 .lines_per_tag = 1,
1732 },
a9f27ea9 1733 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1734 .type = UNIFIED_CACHE,
1735 .level = 3,
1736 .size = 8 * MiB,
1737 .line_size = 64,
1738 .associativity = 16,
1739 .partitions = 1,
1740 .sets = 8192,
1741 .lines_per_tag = 1,
1742 .self_init = true,
1743 .inclusive = true,
1744 .complex_indexing = true,
1745 },
1746};
1747
143c30d4
MB		 1748static CPUCaches epyc_rome_cache_info = {
1749 .l1d_cache = &(CPUCacheInfo) {
1750 .type = DATA_CACHE,
1751 .level = 1,
1752 .size = 32 * KiB,
1753 .line_size = 64,
1754 .associativity = 8,
1755 .partitions = 1,
1756 .sets = 64,
1757 .lines_per_tag = 1,
1758 .self_init = 1,
1759 .no_invd_sharing = true,
1760 },
1761 .l1i_cache = &(CPUCacheInfo) {
1762 .type = INSTRUCTION_CACHE,
1763 .level = 1,
1764 .size = 32 * KiB,
1765 .line_size = 64,
1766 .associativity = 8,
1767 .partitions = 1,
1768 .sets = 64,
1769 .lines_per_tag = 1,
1770 .self_init = 1,
1771 .no_invd_sharing = true,
1772 },
1773 .l2_cache = &(CPUCacheInfo) {
1774 .type = UNIFIED_CACHE,
1775 .level = 2,
1776 .size = 512 * KiB,
1777 .line_size = 64,
1778 .associativity = 8,
1779 .partitions = 1,
1780 .sets = 1024,
1781 .lines_per_tag = 1,
1782 },
1783 .l3_cache = &(CPUCacheInfo) {
1784 .type = UNIFIED_CACHE,
1785 .level = 3,
1786 .size = 16 * MiB,
1787 .line_size = 64,
1788 .associativity = 16,
1789 .partitions = 1,
1790 .sets = 16384,
1791 .lines_per_tag = 1,
1792 .self_init = true,
1793 .inclusive = true,
1794 .complex_indexing = true,
1795 },
1796};
1797
0723cc8a
PB		 1798/* The following VMX features are not supported by KVM and are left out in the
1799 * CPU definitions:
1800 *
1801 * Dual-monitor support (all processors)
1802 * Entry to SMM
1803 * Deactivate dual-monitor treatment
1804 * Number of CR3-target values
1805 * Shutdown activity state
1806 * Wait-for-SIPI activity state
1807 * PAUSE-loop exiting (Westmere and newer)
1808 * EPT-violation #VE (Broadwell and newer)
1809 * Inject event with insn length=0 (Skylake and newer)
1810 * Conceal non-root operation from PT
1811 * Conceal VM exits from PT
1812 * Conceal VM entries from PT
1813 * Enable ENCLS exiting
1814 * Mode-based execute control (XS/XU)
1815 s TSC scaling (Skylake Server and newer)
1816 * GPA translation for PT (IceLake and newer)
1817 * User wait and pause
1818 * ENCLV exiting
1819 * Load IA32_RTIT_CTL
1820 * Clear IA32_RTIT_CTL
1821 * Advanced VM-exit information for EPT violations
1822 * Sub-page write permissions
1823 * PT in VMX operation
1824 */
1825
9576de75 1826static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1827 {
1828 .name = "qemu64",
3046bb5d 1829 .level = 0xd,
99b88a17 1830 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1831 .family = 6,
f8e6a11a 1832 .model = 6,
c6dc6f63 1833 .stepping = 3,
0514ef2f 1834 .features[FEAT_1_EDX] =
27861ecc 1835 PPRO_FEATURES |
c6dc6f63 1836 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1837 CPUID_PSE36,
0514ef2f 1838 .features[FEAT_1_ECX] =
6aa91e4a 1839 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1840 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1841 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1842 .features[FEAT_8000_0001_ECX] =
71195672 1843 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1844 .xlevel = 0x8000000A,
9cf2cc3d 1845 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1846 },
1847 {
1848 .name = "phenom",
1849 .level = 5,
99b88a17 1850 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1851 .family = 16,
1852 .model = 2,
1853 .stepping = 3,
b9fc20bc 1854 /* Missing: CPUID_HT */
0514ef2f 1855 .features[FEAT_1_EDX] =
27861ecc 1856 PPRO_FEATURES |
c6dc6f63 1857 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1858 CPUID_PSE36 | CPUID_VME,
0514ef2f 1859 .features[FEAT_1_ECX] =
27861ecc 1860 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1861 CPUID_EXT_POPCNT,
0514ef2f 1862 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1863 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1864 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1865 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1866 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1867 CPUID_EXT3_CR8LEG,
1868 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1869 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1870 .features[FEAT_8000_0001_ECX] =
27861ecc 1871 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1872 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1873 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1874 .features[FEAT_SVM] =
b9fc20bc 1875 CPUID_SVM_NPT,
c6dc6f63
AP		 1876 .xlevel = 0x8000001A,
1877 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1878 },
1879 {
1880 .name = "core2duo",
1881 .level = 10,
99b88a17 1882 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1883 .family = 6,
1884 .model = 15,
1885 .stepping = 11,
b9fc20bc 1886 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1887 .features[FEAT_1_EDX] =
27861ecc 1888 PPRO_FEATURES |
c6dc6f63 1889 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1890 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1891 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1892 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1893 .features[FEAT_1_ECX] =
27861ecc 1894 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1895 CPUID_EXT_CX16,
0514ef2f 1896 .features[FEAT_8000_0001_EDX] =
27861ecc 1897 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1898 .features[FEAT_8000_0001_ECX] =
27861ecc 1899 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 1900 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1901 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1902 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1903 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1904 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1905 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1906 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1907 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1908 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1909 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1910 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1911 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1912 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1913 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1914 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1915 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1916 .features[FEAT_VMX_SECONDARY_CTLS] =
1917 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 1918 .xlevel = 0x80000008,
1919 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1920 },
1921 {
1922 .name = "kvm64",
3046bb5d 1923 .level = 0xd,
99b88a17 1924 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1925 .family = 15,
1926 .model = 6,
1927 .stepping = 1,
b3a4f0b1 1928 /* Missing: CPUID_HT */
0514ef2f 1929 .features[FEAT_1_EDX] =
b3a4f0b1 1930 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1931 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1932 CPUID_PSE36,
1933 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1934 .features[FEAT_1_ECX] =
27861ecc 1935 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1936 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1937 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1938 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1939 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1940 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1941 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1942 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1943 .features[FEAT_8000_0001_ECX] =
27861ecc 1944 0,
0723cc8a
PB		 1945 /* VMX features from Cedar Mill/Prescott */
1946 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1947 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1948 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1949 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1950 VMX_PIN_BASED_NMI_EXITING,
1951 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1952 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1953 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1954 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1955 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1956 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1957 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1958 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 1959 .xlevel = 0x80000008,
1960 .model_id = "Common KVM processor"
1961 },
c6dc6f63
AP		 1962 {
1963 .name = "qemu32",
1964 .level = 4,
99b88a17 1965 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1966 .family = 6,
f8e6a11a 1967 .model = 6,
c6dc6f63 1968 .stepping = 3,
0514ef2f 1969 .features[FEAT_1_EDX] =
27861ecc 1970 PPRO_FEATURES,
0514ef2f 1971 .features[FEAT_1_ECX] =
6aa91e4a 1972 CPUID_EXT_SSE3,
58012d66 1973 .xlevel = 0x80000004,
9cf2cc3d 1974 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1975 },
eafaf1e5
AP		 1976 {
1977 .name = "kvm32",
1978 .level = 5,
99b88a17 1979 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1980 .family = 15,
1981 .model = 6,
1982 .stepping = 1,
0514ef2f 1983 .features[FEAT_1_EDX] =
b3a4f0b1 1984 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1985 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1986 .features[FEAT_1_ECX] =
27861ecc 1987 CPUID_EXT_SSE3,
0514ef2f 1988 .features[FEAT_8000_0001_ECX] =
27861ecc 1989 0,
0723cc8a
PB		 1990 /* VMX features from Yonah */
1991 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1992 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1993 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1994 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1995 VMX_PIN_BASED_NMI_EXITING,
1996 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1997 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1998 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1999 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2000 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2001 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2002 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 2003 .xlevel = 0x80000008,
2004 .model_id = "Common 32-bit KVM processor"
2005 },
c6dc6f63
AP		 2006 {
2007 .name = "coreduo",
2008 .level = 10,
99b88a17 2009 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2010 .family = 6,
2011 .model = 14,
2012 .stepping = 8,
b9fc20bc 2013 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2014 .features[FEAT_1_EDX] =
27861ecc 2015 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 2016 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2017 CPUID_SS,
2018 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 2019 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2020 .features[FEAT_1_ECX] =
e93abc14 2021 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 2022 .features[FEAT_8000_0001_EDX] =
27861ecc 2023 CPUID_EXT2_NX,
0723cc8a
PB		 2024 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2025 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2026 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2027 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2028 VMX_PIN_BASED_NMI_EXITING,
2029 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2030 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2031 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2032 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2033 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2034 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2035 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 2036 .xlevel = 0x80000008,
2037 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2038 },
2039 {
2040 .name = "486",
58012d66 2041 .level = 1,
99b88a17 2042 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2043 .family = 4,
b2a856d9 2044 .model = 8,
c6dc6f63 2045 .stepping = 0,
0514ef2f 2046 .features[FEAT_1_EDX] =
27861ecc 2047 I486_FEATURES,
c6dc6f63 2048 .xlevel = 0,
807e9869 2049 .model_id = "",
c6dc6f63
AP		 2050 },
2051 {
2052 .name = "pentium",
2053 .level = 1,
99b88a17 2054 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2055 .family = 5,
2056 .model = 4,
2057 .stepping = 3,
0514ef2f 2058 .features[FEAT_1_EDX] =
27861ecc 2059 PENTIUM_FEATURES,
c6dc6f63 2060 .xlevel = 0,
807e9869 2061 .model_id = "",
c6dc6f63
AP		 2062 },
2063 {
2064 .name = "pentium2",
2065 .level = 2,
99b88a17 2066 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2067 .family = 6,
2068 .model = 5,
2069 .stepping = 2,
0514ef2f 2070 .features[FEAT_1_EDX] =
27861ecc 2071 PENTIUM2_FEATURES,
c6dc6f63 2072 .xlevel = 0,
807e9869 2073 .model_id = "",
c6dc6f63
AP		 2074 },
2075 {
2076 .name = "pentium3",
3046bb5d 2077 .level = 3,
99b88a17 2078 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2079 .family = 6,
2080 .model = 7,
2081 .stepping = 3,
0514ef2f 2082 .features[FEAT_1_EDX] =
27861ecc 2083 PENTIUM3_FEATURES,
c6dc6f63 2084 .xlevel = 0,
807e9869 2085 .model_id = "",
c6dc6f63
AP		 2086 },
2087 {
2088 .name = "athlon",
2089 .level = 2,
99b88a17 2090 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2091 .family = 6,
2092 .model = 2,
2093 .stepping = 3,
0514ef2f 2094 .features[FEAT_1_EDX] =
27861ecc 2095 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2096 CPUID_MCA,
0514ef2f 2097 .features[FEAT_8000_0001_EDX] =
60032ac0 2098 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2099 .xlevel = 0x80000008,
9cf2cc3d 2100 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2101 },
2102 {
2103 .name = "n270",
3046bb5d 2104 .level = 10,
99b88a17 2105 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2106 .family = 6,
2107 .model = 28,
2108 .stepping = 2,
b9fc20bc 2109 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2110 .features[FEAT_1_EDX] =
27861ecc 2111 PPRO_FEATURES |
b9fc20bc
EH		 2112 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2113 CPUID_ACPI | CPUID_SS,
c6dc6f63 2114 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2115 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2116 * CPUID_EXT_XTPR */
0514ef2f 2117 .features[FEAT_1_ECX] =
27861ecc 2118 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2119 CPUID_EXT_MOVBE,
0514ef2f 2120 .features[FEAT_8000_0001_EDX] =
60032ac0 2121 CPUID_EXT2_NX,
0514ef2f 2122 .features[FEAT_8000_0001_ECX] =
27861ecc 2123 CPUID_EXT3_LAHF_LM,
3046bb5d 2124 .xlevel = 0x80000008,
c6dc6f63
AP		 2125 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2126 },
3eca4642
EH		 2127 {
2128 .name = "Conroe",
3046bb5d 2129 .level = 10,
99b88a17 2130 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2131 .family = 6,
ffce9ebb 2132 .model = 15,
3eca4642 2133 .stepping = 3,
0514ef2f 2134 .features[FEAT_1_EDX] =
b3a4f0b1 2135 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2136 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2137 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2138 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2139 CPUID_DE | CPUID_FP87,
0514ef2f 2140 .features[FEAT_1_ECX] =
27861ecc 2141 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2142 .features[FEAT_8000_0001_EDX] =
27861ecc 2143 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2144 .features[FEAT_8000_0001_ECX] =
27861ecc 2145 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2146 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2147 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2148 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2149 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2150 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2151 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2152 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2153 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2154 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2155 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2156 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2157 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2158 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2159 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2160 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2161 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2162 .features[FEAT_VMX_SECONDARY_CTLS] =
2163 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2164 .xlevel = 0x80000008,
3eca4642
EH		 2165 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2166 },
2167 {
2168 .name = "Penryn",
3046bb5d 2169 .level = 10,
99b88a17 2170 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2171 .family = 6,
ffce9ebb 2172 .model = 23,
3eca4642 2173 .stepping = 3,
0514ef2f 2174 .features[FEAT_1_EDX] =
b3a4f0b1 2175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2179 CPUID_DE | CPUID_FP87,
0514ef2f 2180 .features[FEAT_1_ECX] =
27861ecc 2181 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2182 CPUID_EXT_SSE3,
0514ef2f 2183 .features[FEAT_8000_0001_EDX] =
27861ecc 2184 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2185 .features[FEAT_8000_0001_ECX] =
27861ecc 2186 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2187 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2188 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2189 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2190 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2191 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2192 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2193 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2194 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2195 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2196 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2197 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2198 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2199 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2200 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2201 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2202 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2203 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2204 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2205 .features[FEAT_VMX_SECONDARY_CTLS] =
2206 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2207 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2208 .xlevel = 0x80000008,
3eca4642
EH		 2209 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2210 },
2211 {
2212 .name = "Nehalem",
3046bb5d 2213 .level = 11,
99b88a17 2214 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2215 .family = 6,
ffce9ebb 2216 .model = 26,
3eca4642 2217 .stepping = 3,
0514ef2f 2218 .features[FEAT_1_EDX] =
b3a4f0b1 2219 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2220 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2221 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2222 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2223 CPUID_DE | CPUID_FP87,
0514ef2f 2224 .features[FEAT_1_ECX] =
27861ecc 2225 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2226 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2227 .features[FEAT_8000_0001_EDX] =
27861ecc 2228 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2229 .features[FEAT_8000_0001_ECX] =
27861ecc 2230 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2231 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2232 MSR_VMX_BASIC_TRUE_CTLS,
2233 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2234 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2235 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2236 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2237 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2238 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2239 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2240 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2241 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2242 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2243 .features[FEAT_VMX_EXIT_CTLS] =
2244 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2245 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2246 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2247 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2248 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2249 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2250 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2251 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2252 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2253 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2254 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2255 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2256 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2257 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2258 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2259 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2260 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2261 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2262 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2263 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2264 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2265 .features[FEAT_VMX_SECONDARY_CTLS] =
2266 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2267 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2268 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2269 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2270 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2271 .xlevel = 0x80000008,
3eca4642 2272 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2273 .versions = (X86CPUVersionDefinition[]) {
2274 { .version = 1 },
2275 {
2276 .version = 2,
53db89d9 2277 .alias = "Nehalem-IBRS",
d86a7088
EH		 2278 .props = (PropValue[]) {
2279 { "spec-ctrl", "on" },
2280 { "model-id",
2281 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2282 { /* end of list */ }
2283 }
2284 },
2285 { /* end of list */ }
2286 }
3eca4642
EH		 2287 },
2288 {
2289 .name = "Westmere",
2290 .level = 11,
99b88a17 2291 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2292 .family = 6,
2293 .model = 44,
2294 .stepping = 1,
0514ef2f 2295 .features[FEAT_1_EDX] =
b3a4f0b1 2296 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2297 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2298 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2299 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2300 CPUID_DE | CPUID_FP87,
0514ef2f 2301 .features[FEAT_1_ECX] =
27861ecc 2302 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2303 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2304 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2305 .features[FEAT_8000_0001_EDX] =
27861ecc 2306 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2307 .features[FEAT_8000_0001_ECX] =
27861ecc 2308 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2309 .features[FEAT_6_EAX] =
2310 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2311 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2312 MSR_VMX_BASIC_TRUE_CTLS,
2313 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2314 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2315 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2316 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2317 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2318 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2319 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2320 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2321 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2322 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2323 .features[FEAT_VMX_EXIT_CTLS] =
2324 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2325 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2326 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2327 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2328 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2329 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2330 MSR_VMX_MISC_STORE_LMA,
2331 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2332 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2333 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2334 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2335 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2336 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2337 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2338 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2339 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2340 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2341 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2342 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2343 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2344 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2345 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2346 .features[FEAT_VMX_SECONDARY_CTLS] =
2347 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2348 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2349 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2350 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2351 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2352 .xlevel = 0x80000008,
3eca4642 2353 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2354 .versions = (X86CPUVersionDefinition[]) {
2355 { .version = 1 },
2356 {
2357 .version = 2,
53db89d9 2358 .alias = "Westmere-IBRS",
d86a7088
EH		 2359 .props = (PropValue[]) {
2360 { "spec-ctrl", "on" },
2361 { "model-id",
2362 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2363 { /* end of list */ }
2364 }
2365 },
2366 { /* end of list */ }
2367 }
3eca4642
EH		 2368 },
2369 {
2370 .name = "SandyBridge",
2371 .level = 0xd,
99b88a17 2372 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2373 .family = 6,
2374 .model = 42,
2375 .stepping = 1,
0514ef2f 2376 .features[FEAT_1_EDX] =
b3a4f0b1 2377 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2378 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2379 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2380 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2381 CPUID_DE | CPUID_FP87,
0514ef2f 2382 .features[FEAT_1_ECX] =
27861ecc 2383 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2384 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2385 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2386 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2387 CPUID_EXT_SSE3,
0514ef2f 2388 .features[FEAT_8000_0001_EDX] =
27861ecc 2389 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2390 CPUID_EXT2_SYSCALL,
0514ef2f 2391 .features[FEAT_8000_0001_ECX] =
27861ecc 2392 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2393 .features[FEAT_XSAVE] =
2394 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2395 .features[FEAT_6_EAX] =
2396 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2397 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2398 MSR_VMX_BASIC_TRUE_CTLS,
2399 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2400 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2401 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2402 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2403 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2404 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2405 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2406 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2407 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2408 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2409 .features[FEAT_VMX_EXIT_CTLS] =
2410 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2411 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2412 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2413 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2414 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2415 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2416 MSR_VMX_MISC_STORE_LMA,
2417 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2418 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2419 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2420 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2421 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2422 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2423 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2424 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2425 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2426 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2427 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2428 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2429 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2430 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2431 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2432 .features[FEAT_VMX_SECONDARY_CTLS] =
2433 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2434 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2435 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2436 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2437 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2438 .xlevel = 0x80000008,
3eca4642 2439 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2440 .versions = (X86CPUVersionDefinition[]) {
2441 { .version = 1 },
2442 {
2443 .version = 2,
53db89d9 2444 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2445 .props = (PropValue[]) {
2446 { "spec-ctrl", "on" },
2447 { "model-id",
2448 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2449 { /* end of list */ }
2450 }
2451 },
2452 { /* end of list */ }
2453 }
3eca4642 2454 },
2f9ac42a
PB		 2455 {
2456 .name = "IvyBridge",
2457 .level = 0xd,
2458 .vendor = CPUID_VENDOR_INTEL,
2459 .family = 6,
2460 .model = 58,
2461 .stepping = 9,
2462 .features[FEAT_1_EDX] =
2463 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2464 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2465 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2466 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2467 CPUID_DE | CPUID_FP87,
2468 .features[FEAT_1_ECX] =
2469 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2470 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2471 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2472 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2473 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2474 .features[FEAT_7_0_EBX] =
2475 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2476 CPUID_7_0_EBX_ERMS,
2477 .features[FEAT_8000_0001_EDX] =
2478 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2479 CPUID_EXT2_SYSCALL,
2480 .features[FEAT_8000_0001_ECX] =
2481 CPUID_EXT3_LAHF_LM,
2482 .features[FEAT_XSAVE] =
2483 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2484 .features[FEAT_6_EAX] =
2485 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2486 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2487 MSR_VMX_BASIC_TRUE_CTLS,
2488 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2489 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2490 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2491 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2492 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2493 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2494 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2495 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2496 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2497 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2498 .features[FEAT_VMX_EXIT_CTLS] =
2499 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2500 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2501 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2502 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2503 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2504 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2505 MSR_VMX_MISC_STORE_LMA,
2506 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2507 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2508 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2509 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2510 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2511 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2512 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2513 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2514 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2515 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2516 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2517 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2518 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2519 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2520 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2521 .features[FEAT_VMX_SECONDARY_CTLS] =
2522 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2523 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2524 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2525 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2526 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2527 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2528 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2529 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2530 .xlevel = 0x80000008,
2f9ac42a 2531 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2532 .versions = (X86CPUVersionDefinition[]) {
2533 { .version = 1 },
2534 {
2535 .version = 2,
53db89d9 2536 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2537 .props = (PropValue[]) {
2538 { "spec-ctrl", "on" },
2539 { "model-id",
2540 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2541 { /* end of list */ }
2542 }
2543 },
2544 { /* end of list */ }
2545 }
2f9ac42a 2546 },
ac96c413 2547 {
37507094
EH		 2548 .name = "Haswell",
2549 .level = 0xd,
99b88a17 2550 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2551 .family = 6,
2552 .model = 60,
ec56a4a7 2553 .stepping = 4,
0514ef2f 2554 .features[FEAT_1_EDX] =
b3a4f0b1 2555 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2556 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2557 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2558 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2559 CPUID_DE | CPUID_FP87,
0514ef2f 2560 .features[FEAT_1_ECX] =
27861ecc 2561 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2562 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2563 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2564 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2565 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2566 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2567 .features[FEAT_8000_0001_EDX] =
27861ecc 2568 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2569 CPUID_EXT2_SYSCALL,
0514ef2f 2570 .features[FEAT_8000_0001_ECX] =
becb6667 2571 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2572 .features[FEAT_7_0_EBX] =
27861ecc 2573 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2574 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2575 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2576 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2577 .features[FEAT_XSAVE] =
2578 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2579 .features[FEAT_6_EAX] =
2580 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2581 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2582 MSR_VMX_BASIC_TRUE_CTLS,
2583 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2584 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2585 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2586 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2587 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2588 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2589 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2590 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2591 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2592 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2593 .features[FEAT_VMX_EXIT_CTLS] =
2594 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2595 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2596 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2597 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2598 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2599 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2600 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2601 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2602 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2603 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2604 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2605 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2606 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2607 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2608 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2609 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2610 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2611 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2612 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2613 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2614 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2615 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2616 .features[FEAT_VMX_SECONDARY_CTLS] =
2617 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2618 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2619 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2620 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2621 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2622 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2623 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2624 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2625 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2626 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2627 .xlevel = 0x80000008,
37507094 2628 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2629 .versions = (X86CPUVersionDefinition[]) {
2630 { .version = 1 },
2631 {
2632 .version = 2,
53db89d9 2633 .alias = "Haswell-noTSX",
d86a7088
EH		 2634 .props = (PropValue[]) {
2635 { "hle", "off" },
2636 { "rtm", "off" },
2637 { "stepping", "1" },
2638 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2639 { /* end of list */ }
2640 },
2641 },
2642 {
2643 .version = 3,
53db89d9 2644 .alias = "Haswell-IBRS",
d86a7088
EH		 2645 .props = (PropValue[]) {
2646 /* Restore TSX features removed by -v2 above */
2647 { "hle", "on" },
2648 { "rtm", "on" },
2649 /*
2650 * Haswell and Haswell-IBRS had stepping=4 in
2651 * QEMU 4.0 and older
2652 */
2653 { "stepping", "4" },
2654 { "spec-ctrl", "on" },
2655 { "model-id",
2656 "Intel Core Processor (Haswell, IBRS)" },
2657 { /* end of list */ }
2658 }
2659 },
2660 {
2661 .version = 4,
53db89d9 2662 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2663 .props = (PropValue[]) {
2664 { "hle", "off" },
2665 { "rtm", "off" },
2666 /* spec-ctrl was already enabled by -v3 above */
2667 { "stepping", "1" },
2668 { "model-id",
2669 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2670 { /* end of list */ }
2671 }
2672 },
2673 { /* end of list */ }
2674 }
37507094 2675 },
ece01354
EH		 2676 {
2677 .name = "Broadwell",
2678 .level = 0xd,
2679 .vendor = CPUID_VENDOR_INTEL,
2680 .family = 6,
2681 .model = 61,
2682 .stepping = 2,
2683 .features[FEAT_1_EDX] =
b3a4f0b1 2684 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2685 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2686 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2687 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2688 CPUID_DE | CPUID_FP87,
2689 .features[FEAT_1_ECX] =
2690 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2691 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2692 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2693 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2694 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2695 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2696 .features[FEAT_8000_0001_EDX] =
2697 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2698 CPUID_EXT2_SYSCALL,
2699 .features[FEAT_8000_0001_ECX] =
becb6667 2700 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2701 .features[FEAT_7_0_EBX] =
2702 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2703 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2704 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2705 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2706 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2707 .features[FEAT_XSAVE] =
2708 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2709 .features[FEAT_6_EAX] =
2710 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2711 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2712 MSR_VMX_BASIC_TRUE_CTLS,
2713 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2714 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2715 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2716 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2717 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2718 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2719 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2720 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2721 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2722 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2723 .features[FEAT_VMX_EXIT_CTLS] =
2724 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2725 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2726 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2727 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2728 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2729 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2730 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2731 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2732 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2733 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2734 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2735 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2736 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2737 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2738 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2739 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2740 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2741 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2742 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2743 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2744 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2745 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2746 .features[FEAT_VMX_SECONDARY_CTLS] =
2747 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2748 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2749 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2750 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2751 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2752 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2753 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2754 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2755 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2756 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2757 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2758 .xlevel = 0x80000008,
ece01354 2759 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 2760 .versions = (X86CPUVersionDefinition[]) {
2761 { .version = 1 },
2762 {
2763 .version = 2,
53db89d9 2764 .alias = "Broadwell-noTSX",
d86a7088
EH		 2765 .props = (PropValue[]) {
2766 { "hle", "off" },
2767 { "rtm", "off" },
2768 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2769 { /* end of list */ }
2770 },
2771 },
2772 {
2773 .version = 3,
53db89d9 2774 .alias = "Broadwell-IBRS",
d86a7088
EH		 2775 .props = (PropValue[]) {
2776 /* Restore TSX features removed by -v2 above */
2777 { "hle", "on" },
2778 { "rtm", "on" },
2779 { "spec-ctrl", "on" },
2780 { "model-id",
2781 "Intel Core Processor (Broadwell, IBRS)" },
2782 { /* end of list */ }
2783 }
2784 },
2785 {
2786 .version = 4,
53db89d9 2787 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 2788 .props = (PropValue[]) {
2789 { "hle", "off" },
2790 { "rtm", "off" },
2791 /* spec-ctrl was already enabled by -v3 above */
2792 { "model-id",
2793 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2794 { /* end of list */ }
2795 }
2796 },
2797 { /* end of list */ }
2798 }
ece01354 2799 },
f6f949e9
EH		 2800 {
2801 .name = "Skylake-Client",
2802 .level = 0xd,
2803 .vendor = CPUID_VENDOR_INTEL,
2804 .family = 6,
2805 .model = 94,
2806 .stepping = 3,
2807 .features[FEAT_1_EDX] =
2808 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2809 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2810 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2811 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2812 CPUID_DE | CPUID_FP87,
2813 .features[FEAT_1_ECX] =
2814 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2815 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2816 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2817 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2818 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2819 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2820 .features[FEAT_8000_0001_EDX] =
2821 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2822 CPUID_EXT2_SYSCALL,
2823 .features[FEAT_8000_0001_ECX] =
2824 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2825 .features[FEAT_7_0_EBX] =
2826 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2827 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2828 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2829 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2830 CPUID_7_0_EBX_SMAP,
f6f949e9 2831 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2832 * including v4.1 to v4.12).
f6f949e9
EH		 2833 * KVM doesn't yet expose any XSAVES state save component,
2834 * and the only one defined in Skylake (processor tracing)
2835 * probably will block migration anyway.
2836 */
2837 .features[FEAT_XSAVE] =
2838 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2839 CPUID_XSAVE_XGETBV1,
2840 .features[FEAT_6_EAX] =
2841 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2842 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2843 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2844 MSR_VMX_BASIC_TRUE_CTLS,
2845 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2846 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2847 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2848 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2849 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2850 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2851 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2852 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2853 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2854 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2855 .features[FEAT_VMX_EXIT_CTLS] =
2856 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2857 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2858 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2859 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2860 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2861 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2862 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2863 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2864 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2865 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2866 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2867 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2868 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2869 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2870 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2871 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2872 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2873 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2874 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2875 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2876 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2877 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2878 .features[FEAT_VMX_SECONDARY_CTLS] =
2879 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2880 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2881 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2882 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2883 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2884 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2885 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2886 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 2887 .xlevel = 0x80000008,
2888 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 2889 .versions = (X86CPUVersionDefinition[]) {
2890 { .version = 1 },
2891 {
2892 .version = 2,
53db89d9 2893 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 2894 .props = (PropValue[]) {
2895 { "spec-ctrl", "on" },
2896 { "model-id",
2897 "Intel Core Processor (Skylake, IBRS)" },
2898 { /* end of list */ }
2899 }
2900 },
9ab2237f
EH		 2901 {
2902 .version = 3,
02fa60d1 2903 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 2904 .props = (PropValue[]) {
2905 { "hle", "off" },
2906 { "rtm", "off" },
673b0add
KC		 2907 { "model-id",
2908 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2909 { /* end of list */ }
2910 }
2911 },
d86a7088
EH		 2912 { /* end of list */ }
2913 }
f6f949e9 2914 },
53f9a6f4
BF		 2915 {
2916 .name = "Skylake-Server",
2917 .level = 0xd,
2918 .vendor = CPUID_VENDOR_INTEL,
2919 .family = 6,
2920 .model = 85,
2921 .stepping = 4,
2922 .features[FEAT_1_EDX] =
2923 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2927 CPUID_DE | CPUID_FP87,
2928 .features[FEAT_1_ECX] =
2929 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2930 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2931 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2932 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2933 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2934 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2935 .features[FEAT_8000_0001_EDX] =
2936 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2937 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2938 .features[FEAT_8000_0001_ECX] =
2939 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2940 .features[FEAT_7_0_EBX] =
2941 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2942 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2943 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2944 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2945 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2946 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2947 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2948 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2949 .features[FEAT_7_0_ECX] =
2950 CPUID_7_0_ECX_PKU,
53f9a6f4
BF		 2951 /* Missing: XSAVES (not supported by some Linux versions,
2952 * including v4.1 to v4.12).
2953 * KVM doesn't yet expose any XSAVES state save component,
2954 * and the only one defined in Skylake (processor tracing)
2955 * probably will block migration anyway.
2956 */
2957 .features[FEAT_XSAVE] =
2958 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2959 CPUID_XSAVE_XGETBV1,
2960 .features[FEAT_6_EAX] =
2961 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2962 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2963 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2964 MSR_VMX_BASIC_TRUE_CTLS,
2965 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2966 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2967 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2968 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2969 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2970 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2971 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2972 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2973 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2974 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2975 .features[FEAT_VMX_EXIT_CTLS] =
2976 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2977 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2978 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2979 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2980 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2981 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2982 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2983 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2984 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2985 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2986 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2987 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2988 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2989 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2990 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2991 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2992 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2993 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2994 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2995 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2996 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2997 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2998 .features[FEAT_VMX_SECONDARY_CTLS] =
2999 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3000 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3001 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3002 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3003 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3004 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3005 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3006 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3007 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3008 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 3009 .xlevel = 0x80000008,
3010 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 3011 .versions = (X86CPUVersionDefinition[]) {
3012 { .version = 1 },
3013 {
3014 .version = 2,
53db89d9 3015 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 3016 .props = (PropValue[]) {
3017 /* clflushopt was not added to Skylake-Server-IBRS */
3018 /* TODO: add -v3 including clflushopt */
3019 { "clflushopt", "off" },
3020 { "spec-ctrl", "on" },
3021 { "model-id",
3022 "Intel Xeon Processor (Skylake, IBRS)" },
3023 { /* end of list */ }
3024 }
3025 },
9ab2237f
EH		 3026 {
3027 .version = 3,
02fa60d1 3028 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 3029 .props = (PropValue[]) {
3030 { "hle", "off" },
3031 { "rtm", "off" },
673b0add
KC		 3032 { "model-id",
3033 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3034 { /* end of list */ }
3035 }
3036 },
d86a7088
EH		 3037 { /* end of list */ }
3038 }
53f9a6f4 3039 },
c7a88b52
TX		 3040 {
3041 .name = "Cascadelake-Server",
3042 .level = 0xd,
3043 .vendor = CPUID_VENDOR_INTEL,
3044 .family = 6,
3045 .model = 85,
b0a19803 3046 .stepping = 6,
c7a88b52
TX		 3047 .features[FEAT_1_EDX] =
3048 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3049 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3050 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3051 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3052 CPUID_DE | CPUID_FP87,
3053 .features[FEAT_1_ECX] =
3054 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3055 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3056 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3057 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3058 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3059 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3060 .features[FEAT_8000_0001_EDX] =
3061 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3062 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3063 .features[FEAT_8000_0001_ECX] =
3064 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3065 .features[FEAT_7_0_EBX] =
3066 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3067 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3068 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3069 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3070 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3071 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3072 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3073 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3074 .features[FEAT_7_0_ECX] =
bb4928c7 3075 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3076 CPUID_7_0_ECX_AVX512VNNI,
3077 .features[FEAT_7_0_EDX] =
3078 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3079 /* Missing: XSAVES (not supported by some Linux versions,
3080 * including v4.1 to v4.12).
3081 * KVM doesn't yet expose any XSAVES state save component,
3082 * and the only one defined in Skylake (processor tracing)
3083 * probably will block migration anyway.
3084 */
3085 .features[FEAT_XSAVE] =
3086 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3087 CPUID_XSAVE_XGETBV1,
3088 .features[FEAT_6_EAX] =
3089 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3090 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3091 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3092 MSR_VMX_BASIC_TRUE_CTLS,
3093 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3094 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3095 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3096 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3097 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3098 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3099 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3100 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3101 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3102 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3103 .features[FEAT_VMX_EXIT_CTLS] =
3104 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3105 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3106 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3107 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3108 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3109 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3110 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3111 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3112 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3113 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3114 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3115 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3116 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3117 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3118 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3119 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3120 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3121 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3122 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3123 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3124 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3125 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3126 .features[FEAT_VMX_SECONDARY_CTLS] =
3127 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3128 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3129 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3130 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3131 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3132 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3133 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3134 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3135 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3136 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3137 .xlevel = 0x80000008,
3138 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3139 .versions = (X86CPUVersionDefinition[]) {
3140 { .version = 1 },
3141 { .version = 2,
47f0d11d 3142 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3143 .props = (PropValue[]) {
3144 { "arch-capabilities", "on" },
3145 { "rdctl-no", "on" },
3146 { "ibrs-all", "on" },
3147 { "skip-l1dfl-vmentry", "on" },
3148 { "mds-no", "on" },
3149 { /* end of list */ }
3150 },
3151 },
9ab2237f 3152 { .version = 3,
02fa60d1 3153 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3154 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3155 .props = (PropValue[]) {
3156 { "hle", "off" },
3157 { "rtm", "off" },
3158 { /* end of list */ }
3159 },
3160 },
fd63c6d1
EH		 3161 { /* end of list */ }
3162 }
c7a88b52 3163 },
22a866b6
CZ		 3164 {
3165 .name = "Cooperlake",
3166 .level = 0xd,
3167 .vendor = CPUID_VENDOR_INTEL,
3168 .family = 6,
3169 .model = 85,
3170 .stepping = 10,
3171 .features[FEAT_1_EDX] =
3172 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3173 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3174 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3175 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3176 CPUID_DE | CPUID_FP87,
3177 .features[FEAT_1_ECX] =
3178 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3179 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3180 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3181 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3182 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3183 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3184 .features[FEAT_8000_0001_EDX] =
3185 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3186 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3187 .features[FEAT_8000_0001_ECX] =
3188 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3189 .features[FEAT_7_0_EBX] =
3190 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3191 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3192 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3193 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3194 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3195 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3196 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3197 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3198 .features[FEAT_7_0_ECX] =
3199 CPUID_7_0_ECX_PKU |
3200 CPUID_7_0_ECX_AVX512VNNI,
3201 .features[FEAT_7_0_EDX] =
3202 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3203 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3204 .features[FEAT_ARCH_CAPABILITIES] =
3205 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3206 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3207 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6
CZ		 3208 .features[FEAT_7_1_EAX] =
3209 CPUID_7_1_EAX_AVX512_BF16,
3210 /*
3211 * Missing: XSAVES (not supported by some Linux versions,
3212 * including v4.1 to v4.12).
3213 * KVM doesn't yet expose any XSAVES state save component,
3214 * and the only one defined in Skylake (processor tracing)
3215 * probably will block migration anyway.
3216 */
3217 .features[FEAT_XSAVE] =
3218 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3219 CPUID_XSAVE_XGETBV1,
3220 .features[FEAT_6_EAX] =
3221 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3222 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3223 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3224 MSR_VMX_BASIC_TRUE_CTLS,
3225 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3226 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3227 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3228 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3229 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3230 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3231 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3232 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3233 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3234 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3235 .features[FEAT_VMX_EXIT_CTLS] =
3236 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3237 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3238 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3239 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3240 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3241 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3242 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3243 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3244 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3245 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3246 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3247 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3248 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3249 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3250 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3251 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3252 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3253 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3254 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3255 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3256 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3257 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3258 .features[FEAT_VMX_SECONDARY_CTLS] =
3259 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3260 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3261 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3262 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3263 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3264 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3265 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3266 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3267 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3268 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3269 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3270 .xlevel = 0x80000008,
3271 .model_id = "Intel Xeon Processor (Cooperlake)",
3272 },
8a11c62d
RH		 3273 {
3274 .name = "Icelake-Client",
3275 .level = 0xd,
3276 .vendor = CPUID_VENDOR_INTEL,
3277 .family = 6,
3278 .model = 126,
3279 .stepping = 0,
3280 .features[FEAT_1_EDX] =
3281 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3282 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3283 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3284 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3285 CPUID_DE | CPUID_FP87,
3286 .features[FEAT_1_ECX] =
3287 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3288 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3289 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3290 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3291 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3292 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3293 .features[FEAT_8000_0001_EDX] =
3294 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3295 CPUID_EXT2_SYSCALL,
3296 .features[FEAT_8000_0001_ECX] =
3297 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3298 .features[FEAT_8000_0008_EBX] =
3299 CPUID_8000_0008_EBX_WBNOINVD,
3300 .features[FEAT_7_0_EBX] =
3301 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3302 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3303 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3304 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 3305 CPUID_7_0_EBX_SMAP,
8a11c62d 3306 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3307 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3308 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3309 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3310 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3311 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3312 .features[FEAT_7_0_EDX] =
3313 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3314 /* Missing: XSAVES (not supported by some Linux versions,
3315 * including v4.1 to v4.12).
3316 * KVM doesn't yet expose any XSAVES state save component,
3317 * and the only one defined in Skylake (processor tracing)
3318 * probably will block migration anyway.
3319 */
3320 .features[FEAT_XSAVE] =
3321 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3322 CPUID_XSAVE_XGETBV1,
3323 .features[FEAT_6_EAX] =
3324 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3325 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3326 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3327 MSR_VMX_BASIC_TRUE_CTLS,
3328 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3329 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3330 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3331 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3332 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3333 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3334 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3335 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3336 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3337 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3338 .features[FEAT_VMX_EXIT_CTLS] =
3339 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3340 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3341 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3342 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3343 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3344 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3345 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3346 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3347 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3348 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3349 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3350 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3351 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3352 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3353 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3354 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3355 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3356 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3357 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3358 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3359 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3360 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3361 .features[FEAT_VMX_SECONDARY_CTLS] =
3362 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3363 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3364 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3365 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3366 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3367 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3368 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3369 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8a11c62d
RH		 3370 .xlevel = 0x80000008,
3371 .model_id = "Intel Core Processor (Icelake)",
9ab2237f
EH		 3372 .versions = (X86CPUVersionDefinition[]) {
3373 { .version = 1 },
3374 {
3375 .version = 2,
47f0d11d 3376 .note = "no TSX",
02fa60d1 3377 .alias = "Icelake-Client-noTSX",
9ab2237f
EH		 3378 .props = (PropValue[]) {
3379 { "hle", "off" },
3380 { "rtm", "off" },
3381 { /* end of list */ }
3382 },
3383 },
3384 { /* end of list */ }
3385 }
8a11c62d
RH		 3386 },
3387 {
3388 .name = "Icelake-Server",
3389 .level = 0xd,
3390 .vendor = CPUID_VENDOR_INTEL,
3391 .family = 6,
3392 .model = 134,
3393 .stepping = 0,
3394 .features[FEAT_1_EDX] =
3395 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3396 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3397 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3398 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3399 CPUID_DE | CPUID_FP87,
3400 .features[FEAT_1_ECX] =
3401 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3402 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3403 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3404 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3405 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3406 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3407 .features[FEAT_8000_0001_EDX] =
3408 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3409 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3410 .features[FEAT_8000_0001_ECX] =
3411 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3412 .features[FEAT_8000_0008_EBX] =
3413 CPUID_8000_0008_EBX_WBNOINVD,
3414 .features[FEAT_7_0_EBX] =
3415 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3416 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3417 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3418 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3419 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3420 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3421 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3422 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3423 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3424 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3425 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3426 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3427 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3428 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3429 .features[FEAT_7_0_EDX] =
76e5a4d5 3430 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
8a11c62d
RH		 3431 /* Missing: XSAVES (not supported by some Linux versions,
3432 * including v4.1 to v4.12).
3433 * KVM doesn't yet expose any XSAVES state save component,
3434 * and the only one defined in Skylake (processor tracing)
3435 * probably will block migration anyway.
3436 */
3437 .features[FEAT_XSAVE] =
3438 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3439 CPUID_XSAVE_XGETBV1,
3440 .features[FEAT_6_EAX] =
3441 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3442 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3443 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3444 MSR_VMX_BASIC_TRUE_CTLS,
3445 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3446 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3447 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3448 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3449 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3450 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3451 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3452 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3453 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3454 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3455 .features[FEAT_VMX_EXIT_CTLS] =
3456 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3457 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3458 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3459 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3460 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3461 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3462 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3463 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3464 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3465 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3466 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3467 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3468 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3469 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3470 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3471 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3472 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3473 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3474 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3475 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3476 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3477 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3478 .features[FEAT_VMX_SECONDARY_CTLS] =
3479 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3480 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3481 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3482 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3483 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3484 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3485 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3486 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3487 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3488 .xlevel = 0x80000008,
3489 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3490 .versions = (X86CPUVersionDefinition[]) {
3491 { .version = 1 },
3492 {
3493 .version = 2,
47f0d11d 3494 .note = "no TSX",
02fa60d1 3495 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3496 .props = (PropValue[]) {
3497 { "hle", "off" },
3498 { "rtm", "off" },
3499 { /* end of list */ }
3500 },
3501 },
d965dc35
XL		 3502 {
3503 .version = 3,
3504 .props = (PropValue[]) {
3505 { "arch-capabilities", "on" },
3506 { "rdctl-no", "on" },
3507 { "ibrs-all", "on" },
3508 { "skip-l1dfl-vmentry", "on" },
3509 { "mds-no", "on" },
3510 { "pschange-mc-no", "on" },
3511 { "taa-no", "on" },
3512 { /* end of list */ }
3513 },
3514 },
9ab2237f
EH		 3515 { /* end of list */ }
3516 }
8a11c62d 3517 },
8b44d860
TX		 3518 {
3519 .name = "Denverton",
3520 .level = 21,
3521 .vendor = CPUID_VENDOR_INTEL,
3522 .family = 6,
3523 .model = 95,
3524 .stepping = 1,
3525 .features[FEAT_1_EDX] =
3526 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3527 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3528 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3529 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3530 CPUID_SSE | CPUID_SSE2,
3531 .features[FEAT_1_ECX] =
3532 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3533 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3534 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3535 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3536 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3537 .features[FEAT_8000_0001_EDX] =
3538 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3539 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3540 .features[FEAT_8000_0001_ECX] =
3541 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3542 .features[FEAT_7_0_EBX] =
3543 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3544 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3545 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3546 .features[FEAT_7_0_EDX] =
3547 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3548 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3549 /*
3550 * Missing: XSAVES (not supported by some Linux versions,
3551 * including v4.1 to v4.12).
3552 * KVM doesn't yet expose any XSAVES state save component,
3553 * and the only one defined in Skylake (processor tracing)
3554 * probably will block migration anyway.
3555 */
3556 .features[FEAT_XSAVE] =
3557 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3558 .features[FEAT_6_EAX] =
3559 CPUID_6_EAX_ARAT,
3560 .features[FEAT_ARCH_CAPABILITIES] =
3561 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3562 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3563 MSR_VMX_BASIC_TRUE_CTLS,
3564 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3565 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3566 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3567 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3568 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3569 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3570 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3571 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3572 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3573 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3574 .features[FEAT_VMX_EXIT_CTLS] =
3575 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3576 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3577 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3578 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3579 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3580 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3581 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3582 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3583 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3584 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3585 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3586 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3587 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3588 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3589 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3590 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3591 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3592 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3593 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3594 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3595 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3596 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3597 .features[FEAT_VMX_SECONDARY_CTLS] =
3598 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3599 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3600 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3601 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3602 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3603 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3604 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3605 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3606 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3607 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3608 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3609 .xlevel = 0x80000008,
3610 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3611 .versions = (X86CPUVersionDefinition[]) {
3612 { .version = 1 },
3613 {
3614 .version = 2,
47f0d11d 3615 .note = "no MPX, no MONITOR",
ab0c942c
TX		 3616 .props = (PropValue[]) {
3617 { "monitor", "off" },
3618 { "mpx", "off" },
3619 { /* end of list */ },
3620 },
3621 },
3622 { /* end of list */ },
3623 },
8b44d860 3624 },
0b18874b 3625 {
ff656fcd 3626 .name = "Snowridge",
0b18874b
PL		 3627 .level = 27,
3628 .vendor = CPUID_VENDOR_INTEL,
3629 .family = 6,
3630 .model = 134,
3631 .stepping = 1,
3632 .features[FEAT_1_EDX] =
3633 /* missing: CPUID_PN CPUID_IA64 */
3634 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3635 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3636 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3637 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3638 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3639 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3640 CPUID_MMX |
3641 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3642 .features[FEAT_1_ECX] =
3643 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3644 CPUID_EXT_SSSE3 |
3645 CPUID_EXT_CX16 |
3646 CPUID_EXT_SSE41 |
3647 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3648 CPUID_EXT_POPCNT |
3649 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3650 CPUID_EXT_RDRAND,
3651 .features[FEAT_8000_0001_EDX] =
3652 CPUID_EXT2_SYSCALL |
3653 CPUID_EXT2_NX |
3654 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3655 CPUID_EXT2_LM,
3656 .features[FEAT_8000_0001_ECX] =
3657 CPUID_EXT3_LAHF_LM |
3658 CPUID_EXT3_3DNOWPREFETCH,
3659 .features[FEAT_7_0_EBX] =
3660 CPUID_7_0_EBX_FSGSBASE |
3661 CPUID_7_0_EBX_SMEP |
3662 CPUID_7_0_EBX_ERMS |
3663 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3664 CPUID_7_0_EBX_RDSEED |
3665 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3666 CPUID_7_0_EBX_CLWB |
3667 CPUID_7_0_EBX_SHA_NI,
3668 .features[FEAT_7_0_ECX] =
3669 CPUID_7_0_ECX_UMIP |
3670 /* missing bit 5 */
3671 CPUID_7_0_ECX_GFNI |
3672 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3673 CPUID_7_0_ECX_MOVDIR64B,
3674 .features[FEAT_7_0_EDX] =
3675 CPUID_7_0_EDX_SPEC_CTRL |
3676 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3677 CPUID_7_0_EDX_CORE_CAPABILITY,
3678 .features[FEAT_CORE_CAPABILITY] =
3679 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3680 /*
3681 * Missing: XSAVES (not supported by some Linux versions,
3682 * including v4.1 to v4.12).
3683 * KVM doesn't yet expose any XSAVES state save component,
3684 * and the only one defined in Skylake (processor tracing)
3685 * probably will block migration anyway.
3686 */
3687 .features[FEAT_XSAVE] =
3688 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3689 CPUID_XSAVE_XGETBV1,
3690 .features[FEAT_6_EAX] =
3691 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3692 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3693 MSR_VMX_BASIC_TRUE_CTLS,
3694 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3695 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3696 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3697 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3698 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3699 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3700 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3701 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3702 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3703 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3704 .features[FEAT_VMX_EXIT_CTLS] =
3705 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3706 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3707 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3708 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3709 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3710 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3711 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3712 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3713 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3714 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3715 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3716 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3717 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3718 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3719 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3720 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3721 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3722 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3723 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3724 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3725 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3726 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3727 .features[FEAT_VMX_SECONDARY_CTLS] =
3728 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3729 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3730 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3731 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3732 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3733 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3734 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3735 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3736 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3737 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3738 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 3739 .xlevel = 0x80000008,
3740 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 3741 .versions = (X86CPUVersionDefinition[]) {
3742 { .version = 1 },
3743 {
3744 .version = 2,
3745 .props = (PropValue[]) {
3746 { "mpx", "off" },
3747 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3748 { /* end of list */ },
3749 },
3750 },
3751 { /* end of list */ },
3752 },
0b18874b 3753 },
a1849515
BF		 3754 {
3755 .name = "KnightsMill",
3756 .level = 0xd,
3757 .vendor = CPUID_VENDOR_INTEL,
3758 .family = 6,
3759 .model = 133,
3760 .stepping = 0,
3761 .features[FEAT_1_EDX] =
3762 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3763 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3764 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3765 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3766 CPUID_PSE | CPUID_DE | CPUID_FP87,
3767 .features[FEAT_1_ECX] =
3768 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3769 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3770 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3771 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3772 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3773 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3774 .features[FEAT_8000_0001_EDX] =
3775 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3776 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3777 .features[FEAT_8000_0001_ECX] =
3778 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3779 .features[FEAT_7_0_EBX] =
3780 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3781 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3782 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3783 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3784 CPUID_7_0_EBX_AVX512ER,
3785 .features[FEAT_7_0_ECX] =
3786 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3787 .features[FEAT_7_0_EDX] =
3788 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3789 .features[FEAT_XSAVE] =
3790 CPUID_XSAVE_XSAVEOPT,
3791 .features[FEAT_6_EAX] =
3792 CPUID_6_EAX_ARAT,
3793 .xlevel = 0x80000008,
3794 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3795 },
3eca4642
EH		 3796 {
3797 .name = "Opteron_G1",
3798 .level = 5,
99b88a17 3799 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3800 .family = 15,
3801 .model = 6,
3802 .stepping = 1,
0514ef2f 3803 .features[FEAT_1_EDX] =
b3a4f0b1 3804 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3805 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3806 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3807 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3808 CPUID_DE | CPUID_FP87,
0514ef2f 3809 .features[FEAT_1_ECX] =
27861ecc 3810 CPUID_EXT_SSE3,
0514ef2f 3811 .features[FEAT_8000_0001_EDX] =
2a923a29 3812 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 3813 .xlevel = 0x80000008,
3814 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3815 },
3816 {
3817 .name = "Opteron_G2",
3818 .level = 5,
99b88a17 3819 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3820 .family = 15,
3821 .model = 6,
3822 .stepping = 1,
0514ef2f 3823 .features[FEAT_1_EDX] =
b3a4f0b1 3824 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3825 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3826 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3827 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3828 CPUID_DE | CPUID_FP87,
0514ef2f 3829 .features[FEAT_1_ECX] =
27861ecc 3830 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 3831 .features[FEAT_8000_0001_EDX] =
2a923a29 3832 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 3833 .features[FEAT_8000_0001_ECX] =
27861ecc 3834 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3835 .xlevel = 0x80000008,
3836 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3837 },
3838 {
3839 .name = "Opteron_G3",
3840 .level = 5,
99b88a17 3841 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 3842 .family = 16,
3843 .model = 2,
3844 .stepping = 3,
0514ef2f 3845 .features[FEAT_1_EDX] =
b3a4f0b1 3846 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3850 CPUID_DE | CPUID_FP87,
0514ef2f 3851 .features[FEAT_1_ECX] =
27861ecc 3852 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 3853 CPUID_EXT_SSE3,
0514ef2f 3854 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 3855 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3856 CPUID_EXT2_RDTSCP,
0514ef2f 3857 .features[FEAT_8000_0001_ECX] =
27861ecc 3858 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 3859 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3860 .xlevel = 0x80000008,
3861 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3862 },
3863 {
3864 .name = "Opteron_G4",
3865 .level = 0xd,
99b88a17 3866 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3867 .family = 21,
3868 .model = 1,
3869 .stepping = 2,
0514ef2f 3870 .features[FEAT_1_EDX] =
b3a4f0b1 3871 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3872 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3873 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3874 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3875 CPUID_DE | CPUID_FP87,
0514ef2f 3876 .features[FEAT_1_ECX] =
27861ecc 3877 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 3878 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3879 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3880 CPUID_EXT_SSE3,
0514ef2f 3881 .features[FEAT_8000_0001_EDX] =
2a923a29 3882 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3883 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3884 .features[FEAT_8000_0001_ECX] =
27861ecc 3885 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3886 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3887 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3888 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3889 .features[FEAT_SVM] =
3890 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3891 /* no xsaveopt! */
3eca4642
EH		 3892 .xlevel = 0x8000001A,
3893 .model_id = "AMD Opteron 62xx class CPU",
3894 },
021941b9
AP		 3895 {
3896 .name = "Opteron_G5",
3897 .level = 0xd,
99b88a17 3898 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 3899 .family = 21,
3900 .model = 2,
3901 .stepping = 0,
0514ef2f 3902 .features[FEAT_1_EDX] =
b3a4f0b1 3903 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3904 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3905 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3906 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3907 CPUID_DE | CPUID_FP87,
0514ef2f 3908 .features[FEAT_1_ECX] =
27861ecc 3909 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 3910 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3911 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3912 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 3913 .features[FEAT_8000_0001_EDX] =
2a923a29 3914 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3915 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3916 .features[FEAT_8000_0001_ECX] =
27861ecc 3917 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3918 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3919 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3920 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3921 .features[FEAT_SVM] =
3922 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3923 /* no xsaveopt! */
021941b9
AP		 3924 .xlevel = 0x8000001A,
3925 .model_id = "AMD Opteron 63xx class CPU",
3926 },
2e2efc7d
BS		 3927 {
3928 .name = "EPYC",
3929 .level = 0xd,
3930 .vendor = CPUID_VENDOR_AMD,
3931 .family = 23,
3932 .model = 1,
3933 .stepping = 2,
3934 .features[FEAT_1_EDX] =
3935 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3936 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3937 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3938 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3939 CPUID_VME | CPUID_FP87,
3940 .features[FEAT_1_ECX] =
3941 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3942 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3943 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3944 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3945 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3946 .features[FEAT_8000_0001_EDX] =
3947 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3948 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3949 CPUID_EXT2_SYSCALL,
3950 .features[FEAT_8000_0001_ECX] =
3951 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3952 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 3953 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3954 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 3955 .features[FEAT_7_0_EBX] =
3956 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3957 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3958 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3959 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 3960 .features[FEAT_XSAVE] =
3961 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3962 CPUID_XSAVE_XGETBV1,
3963 .features[FEAT_6_EAX] =
3964 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 3965 .features[FEAT_SVM] =
3966 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 3967 .xlevel = 0x8000001E,
2e2efc7d 3968 .model_id = "AMD EPYC Processor",
fe52acd2 3969 .cache_info = &epyc_cache_info,
247b18c5 3970 .use_epyc_apic_id_encoding = 1,
d86a7088
EH		 3971 .versions = (X86CPUVersionDefinition[]) {
3972 { .version = 1 },
3973 {
3974 .version = 2,
53db89d9 3975 .alias = "EPYC-IBPB",
d86a7088
EH		 3976 .props = (PropValue[]) {
3977 { "ibpb", "on" },
3978 { "model-id",
3979 "AMD EPYC Processor (with IBPB)" },
3980 { /* end of list */ }
3981 }
3982 },
a16e8dbc
MB		 3983 {
3984 .version = 3,
3985 .props = (PropValue[]) {
3986 { "ibpb", "on" },
3987 { "perfctr-core", "on" },
3988 { "clzero", "on" },
3989 { "xsaveerptr", "on" },
3990 { "xsaves", "on" },
3991 { "model-id",
3992 "AMD EPYC Processor" },
3993 { /* end of list */ }
3994 }
3995 },
d86a7088
EH		 3996 { /* end of list */ }
3997 }
2e2efc7d 3998 },
8d031cec
PW		 3999 {
4000 .name = "Dhyana",
4001 .level = 0xd,
4002 .vendor = CPUID_VENDOR_HYGON,
4003 .family = 24,
4004 .model = 0,
4005 .stepping = 1,
4006 .features[FEAT_1_EDX] =
4007 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4008 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4009 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4010 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4011 CPUID_VME | CPUID_FP87,
4012 .features[FEAT_1_ECX] =
4013 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4014 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4015 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4016 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4017 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4018 .features[FEAT_8000_0001_EDX] =
4019 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4020 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4021 CPUID_EXT2_SYSCALL,
4022 .features[FEAT_8000_0001_ECX] =
4023 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4024 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4025 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4026 CPUID_EXT3_TOPOEXT,
4027 .features[FEAT_8000_0008_EBX] =
4028 CPUID_8000_0008_EBX_IBPB,
4029 .features[FEAT_7_0_EBX] =
4030 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4031 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4032 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4033 /*
4034 * Missing: XSAVES (not supported by some Linux versions,
4035 * including v4.1 to v4.12).
4036 * KVM doesn't yet expose any XSAVES state save component.
4037 */
4038 .features[FEAT_XSAVE] =
4039 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4040 CPUID_XSAVE_XGETBV1,
4041 .features[FEAT_6_EAX] =
4042 CPUID_6_EAX_ARAT,
4043 .features[FEAT_SVM] =
4044 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4045 .xlevel = 0x8000001E,
4046 .model_id = "Hygon Dhyana Processor",
4047 .cache_info = &epyc_cache_info,
4048 },
143c30d4
MB		 4049 {
4050 .name = "EPYC-Rome",
4051 .level = 0xd,
4052 .vendor = CPUID_VENDOR_AMD,
4053 .family = 23,
4054 .model = 49,
4055 .stepping = 0,
4056 .features[FEAT_1_EDX] =
4057 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4058 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4059 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4060 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4061 CPUID_VME | CPUID_FP87,
4062 .features[FEAT_1_ECX] =
4063 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4064 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4065 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4066 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4067 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4068 .features[FEAT_8000_0001_EDX] =
4069 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4070 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4071 CPUID_EXT2_SYSCALL,
4072 .features[FEAT_8000_0001_ECX] =
4073 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4074 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4075 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4076 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4077 .features[FEAT_8000_0008_EBX] =
4078 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4079 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4080 CPUID_8000_0008_EBX_STIBP,
4081 .features[FEAT_7_0_EBX] =
4082 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4083 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4084 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4085 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4086 .features[FEAT_7_0_ECX] =
4087 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4088 .features[FEAT_XSAVE] =
4089 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4090 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4091 .features[FEAT_6_EAX] =
4092 CPUID_6_EAX_ARAT,
4093 .features[FEAT_SVM] =
4094 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4095 .xlevel = 0x8000001E,
4096 .model_id = "AMD EPYC-Rome Processor",
4097 .cache_info = &epyc_rome_cache_info,
247b18c5 4098 .use_epyc_apic_id_encoding = 1,
143c30d4 4099 },
c6dc6f63
AP		 4100};
4101
5114e842
EH		 4102/* KVM-specific features that are automatically added/removed
4103 * from all CPU models when KVM is enabled.
4104 */
4105static PropValue kvm_default_props[] = {
4106 { "kvmclock", "on" },
4107 { "kvm-nopiodelay", "on" },
4108 { "kvm-asyncpf", "on" },
4109 { "kvm-steal-time", "on" },
4110 { "kvm-pv-eoi", "on" },
4111 { "kvmclock-stable-bit", "on" },
4112 { "x2apic", "on" },
4113 { "acpi", "off" },
4114 { "monitor", "off" },
4115 { "svm", "off" },
4116 { NULL, NULL },
4117};
4118
04d99c3c
EH		 4119/* TCG-specific defaults that override all CPU models when using TCG
4120 */
4121static PropValue tcg_default_props[] = {
4122 { "vme", "off" },
4123 { NULL, NULL },
4124};
4125
4126
ad183928
EH		 4127/*
4128 * We resolve CPU model aliases using -v1 when using "-machine
4129 * none", but this is just for compatibility while libvirt isn't
4130 * adapted to resolve CPU model versions before creating VMs.
4131 * See "Runnability guarantee of CPU models" at * qemu-deprecated.texi.
4132 */
4133X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4134
4135void x86_cpu_set_default_version(X86CPUVersion version)
4136{
4137 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4138 assert(version != CPU_VERSION_AUTO);
4139 default_cpu_version = version;
4140}
4141
dcafd1ef
EH		 4142static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4143{
4144 int v = 0;
4145 const X86CPUVersionDefinition *vdef =
4146 x86_cpu_def_get_versions(model->cpudef);
4147 while (vdef->version) {
4148 v = vdef->version;
4149 vdef++;
4150 }
4151 return v;
4152}
4153
4154/* Return the actual version being used for a specific CPU model */
4155static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4156{
4157 X86CPUVersion v = model->version;
0788a56b
EH		 4158 if (v == CPU_VERSION_AUTO) {
4159 v = default_cpu_version;
4160 }
dcafd1ef
EH		 4161 if (v == CPU_VERSION_LATEST) {
4162 return x86_cpu_model_last_version(model);
4163 }
4164 return v;
4165}
4166
5114e842
EH		 4167void x86_cpu_change_kvm_default(const char *prop, const char *value)
4168{
4169 PropValue *pv;
4170 for (pv = kvm_default_props; pv->prop; pv++) {
4171 if (!strcmp(pv->prop, prop)) {
4172 pv->value = value;
4173 break;
4174 }
4175 }
4176
4177 /* It is valid to call this function only for properties that
4178 * are already present in the kvm_default_props table.
4179 */
4180 assert(pv->prop);
4181}
4182
ede146c2 4183static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4d1b279b
EH		 4184 bool migratable_only);
4185
40bfe48f
HZ		 4186static bool lmce_supported(void)
4187{
c62f2630 4188 uint64_t mce_cap = 0;
40bfe48f 4189
c62f2630 4190#ifdef CONFIG_KVM
40bfe48f
HZ		 4191 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4192 return false;
4193 }
c62f2630 4194#endif
40bfe48f
HZ		 4195
4196 return !!(mce_cap & MCG_LMCE_P);
4197}
4198
7d8050b5
EH		 4199#define CPUID_MODEL_ID_SZ 48
4200
4201/**
4202 * cpu_x86_fill_model_id:
4203 * Get CPUID model ID string from host CPU.
4204 *
4205 * @str should have at least CPUID_MODEL_ID_SZ bytes
4206 *
4207 * The function does NOT add a null terminator to the string
4208 * automatically.
4209 */
c6dc6f63
AP		 4210static int cpu_x86_fill_model_id(char *str)
4211{
4212 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4213 int i;
4214
4215 for (i = 0; i < 3; i++) {
4216 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4217 memcpy(str + i * 16 + 0, &eax, 4);
4218 memcpy(str + i * 16 + 4, &ebx, 4);
4219 memcpy(str + i * 16 + 8, &ecx, 4);
4220 memcpy(str + i * 16 + 12, &edx, 4);
4221 }
4222 return 0;
4223}
4224
c62f2630 4225static Property max_x86_cpu_properties[] = {
120eee7d 4226 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4227 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4228 DEFINE_PROP_END_OF_LIST()
4229};
4230
c62f2630 4231static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4232{
84f1b92f 4233 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4234 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4235
f48c8837 4236 xcc->ordering = 9;
6e746f30 4237
ee465a3e 4238 xcc->model_description =
c62f2630 4239 "Enables all features supported by the accelerator in the current host";
d940ee9b 4240
4f67d30b 4241 device_class_set_props(dc, max_x86_cpu_properties);
d940ee9b
EH		 4242}
4243
c62f2630 4244static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4245{
4246 X86CPU *cpu = X86_CPU(obj);
4247 CPUX86State *env = &cpu->env;
4248 KVMState *s = kvm_state;
d940ee9b 4249
4d1b279b
EH		 4250 /* We can't fill the features array here because we don't know yet if
4251 * "migratable" is true or false.
4252 */
44bd8e53 4253 cpu->max_features = true;
4d1b279b 4254
d6dcc558 4255 if (accel_uses_host_cpuid()) {
bd182022
EH		 4256 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4257 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4258 int family, model, stepping;
0bacd8b3 4259
bd182022 4260 host_vendor_fms(vendor, &family, &model, &stepping);
bd182022 4261 cpu_x86_fill_model_id(model_id);
0bacd8b3 4262
5325cc34
MA		 4263 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
4264 object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
4265 object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
4266 object_property_set_int(OBJECT(cpu), "stepping", stepping,
bd182022 4267 &error_abort);
5325cc34 4268 object_property_set_str(OBJECT(cpu), "model-id", model_id,
bd182022 4269 &error_abort);
0bacd8b3 4270
d6dcc558
SAGDR		 4271 if (kvm_enabled()) {
4272 env->cpuid_min_level =
4273 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4274 env->cpuid_min_xlevel =
4275 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4276 env->cpuid_min_xlevel2 =
4277 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4278 } else {
4279 env->cpuid_min_level =
4280 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4281 env->cpuid_min_xlevel =
4282 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4283 env->cpuid_min_xlevel2 =
4284 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4285 }
40bfe48f
HZ		 4286
4287 if (lmce_supported()) {
5325cc34 4288 object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
40bfe48f 4289 }
6900d1cc 4290 } else {
5325cc34
MA		 4291 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4292 &error_abort);
4293 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4294 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4295 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
4296 object_property_set_str(OBJECT(cpu), "model-id",
6900d1cc 4297 "QEMU TCG CPU version " QEMU_HW_VERSION,
5325cc34 4298 &error_abort);
e4356010 4299 }
2a573259 4300
5325cc34 4301 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
c6dc6f63
AP		 4302}
4303
c62f2630
EH		 4304static const TypeInfo max_x86_cpu_type_info = {
4305 .name = X86_CPU_TYPE_NAME("max"),
4306 .parent = TYPE_X86_CPU,
4307 .instance_init = max_x86_cpu_initfn,
4308 .class_init = max_x86_cpu_class_init,
4309};
4310
d6dcc558 4311#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 4312static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4313{
4314 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4315
d6dcc558 4316 xcc->host_cpuid_required = true;
c62f2630
EH		 4317 xcc->ordering = 8;
4318
02693cc4
GK		 4319#if defined(CONFIG_KVM)
4320 xcc->model_description =
4321 "KVM processor with all supported host features ";
4322#elif defined(CONFIG_HVF)
4323 xcc->model_description =
4324 "HVF processor with all supported host features ";
4325#endif
c62f2630
EH		 4326}
4327
d940ee9b
EH		 4328static const TypeInfo host_x86_cpu_type_info = {
4329 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 4330 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 4331 .class_init = host_x86_cpu_class_init,
4332};
4333
4334#endif
4335
07585923
RH		 4336static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4337{
4338 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4339
4340 switch (f->type) {
4341 case CPUID_FEATURE_WORD:
4342 {
4343 const char *reg = get_register_name_32(f->cpuid.reg);
4344 assert(reg);
4345 return g_strdup_printf("CPUID.%02XH:%s",
4346 f->cpuid.eax, reg);
4347 }
4348 case MSR_FEATURE_WORD:
4349 return g_strdup_printf("MSR(%02XH)",
4350 f->msr.index);
4351 }
4352
4353 return NULL;
4354}
4355
245edd0c 4356static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4357{
245edd0c
PB		 4358 FeatureWord w;
4359
4360 for (w = 0; w < FEATURE_WORDS; w++) {
4361 if (cpu->filtered_features[w]) {
4362 return true;
4363 }
4364 }
4365
4366 return false;
4367}
4368
ede146c2 4369static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4370 const char *verbose_prefix)
4371{
4372 CPUX86State *env = &cpu->env;
8459e396 4373 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4374 int i;
4375
245edd0c
PB		 4376 if (!cpu->force_features) {
4377 env->features[w] &= ~mask;
4378 }
4379 cpu->filtered_features[w] |= mask;
4380
4381 if (!verbose_prefix) {
4382 return;
4383 }
4384
ede146c2
PB		 4385 for (i = 0; i < 64; ++i) {
4386 if ((1ULL << i) & mask) {
88703ce2 4387 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4388 warn_report("%s: %s%s%s [bit %d]",
4389 verbose_prefix,
07585923 4390 feat_word_str,
8297be80
AF		 4391 f->feat_names[i] ? "." : "",
4392 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4393 }
857aee33 4394 }
c6dc6f63
AP		 4395}
4396
d7bce999
EB		 4397static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4398 const char *name, void *opaque,
4399 Error **errp)
95b8519d
AF		 4400{
4401 X86CPU *cpu = X86_CPU(obj);
4402 CPUX86State *env = &cpu->env;
4403 int64_t value;
4404
4405 value = (env->cpuid_version >> 8) & 0xf;
4406 if (value == 0xf) {
4407 value += (env->cpuid_version >> 20) & 0xff;
4408 }
51e72bc1 4409 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4410}
4411
d7bce999
EB		 4412static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4413 const char *name, void *opaque,
4414 Error **errp)
ed5e1ec3 4415{
71ad61d3
AF		 4416 X86CPU *cpu = X86_CPU(obj);
4417 CPUX86State *env = &cpu->env;
4418 const int64_t min = 0;
4419 const int64_t max = 0xff + 0xf;
4420 int64_t value;
4421
668f62ec 4422 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 4423 return;
4424 }
4425 if (value < min || value > max) {
c6bd8c70
MA		 4426 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4427 name ? name : "null", value, min, max);
71ad61d3
AF		 4428 return;
4429 }
4430
ed5e1ec3 4431 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4432 if (value > 0x0f) {
4433 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4434 } else {
71ad61d3 4435 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4436 }
4437}
4438
d7bce999
EB		 4439static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4440 const char *name, void *opaque,
4441 Error **errp)
67e30c83
AF		 4442{
4443 X86CPU *cpu = X86_CPU(obj);
4444 CPUX86State *env = &cpu->env;
4445 int64_t value;
4446
4447 value = (env->cpuid_version >> 4) & 0xf;
4448 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4449 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4450}
4451
d7bce999
EB		 4452static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4453 const char *name, void *opaque,
4454 Error **errp)
b0704cbd 4455{
c5291a4f
AF		 4456 X86CPU *cpu = X86_CPU(obj);
4457 CPUX86State *env = &cpu->env;
4458 const int64_t min = 0;
4459 const int64_t max = 0xff;
4460 int64_t value;
4461
668f62ec 4462 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 4463 return;
4464 }
4465 if (value < min || value > max) {
c6bd8c70
MA		 4466 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4467 name ? name : "null", value, min, max);
c5291a4f
AF		 4468 return;
4469 }
4470
b0704cbd 4471 env->cpuid_version &= ~0xf00f0;
c5291a4f 4472 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4473}
4474
35112e41 4475static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4476 const char *name, void *opaque,
35112e41
AF		 4477 Error **errp)
4478{
4479 X86CPU *cpu = X86_CPU(obj);
4480 CPUX86State *env = &cpu->env;
4481 int64_t value;
4482
4483 value = env->cpuid_version & 0xf;
51e72bc1 4484 visit_type_int(v, name, &value, errp);
35112e41
AF		 4485}
4486
036e2222 4487static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4488 const char *name, void *opaque,
036e2222 4489 Error **errp)
38c3dc46 4490{
036e2222
AF		 4491 X86CPU *cpu = X86_CPU(obj);
4492 CPUX86State *env = &cpu->env;
4493 const int64_t min = 0;
4494 const int64_t max = 0xf;
4495 int64_t value;
4496
668f62ec 4497 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 4498 return;
4499 }
4500 if (value < min || value > max) {
c6bd8c70
MA		 4501 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4502 name ? name : "null", value, min, max);
036e2222
AF		 4503 return;
4504 }
4505
38c3dc46 4506 env->cpuid_version &= ~0xf;
036e2222 4507 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4508}
4509
d480e1af
AF		 4510static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4511{
4512 X86CPU *cpu = X86_CPU(obj);
4513 CPUX86State *env = &cpu->env;
4514 char *value;
d480e1af 4515
e42a92ae 4516 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4517 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4518 env->cpuid_vendor3);
d480e1af
AF		 4519 return value;
4520}
4521
4522static void x86_cpuid_set_vendor(Object *obj, const char *value,
4523 Error **errp)
4524{
4525 X86CPU *cpu = X86_CPU(obj);
4526 CPUX86State *env = &cpu->env;
4527 int i;
4528
9df694ee 4529 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4530 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4531 return;
4532 }
4533
4534 env->cpuid_vendor1 = 0;
4535 env->cpuid_vendor2 = 0;
4536 env->cpuid_vendor3 = 0;
4537 for (i = 0; i < 4; i++) {
4538 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4539 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4540 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4541 }
d480e1af
AF		 4542}
4543
63e886eb
AF		 4544static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4545{
4546 X86CPU *cpu = X86_CPU(obj);
4547 CPUX86State *env = &cpu->env;
4548 char *value;
4549 int i;
4550
4551 value = g_malloc(48 + 1);
4552 for (i = 0; i < 48; i++) {
4553 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4554 }
4555 value[48] = '\0';
4556 return value;
4557}
4558
938d4c25
AF		 4559static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4560 Error **errp)
dcce6675 4561{
938d4c25
AF		 4562 X86CPU *cpu = X86_CPU(obj);
4563 CPUX86State *env = &cpu->env;
dcce6675
AF		 4564 int c, len, i;
4565
4566 if (model_id == NULL) {
4567 model_id = "";
4568 }
4569 len = strlen(model_id);
d0a6acf4 4570 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4571 for (i = 0; i < 48; i++) {
4572 if (i >= len) {
4573 c = '\0';
4574 } else {
4575 c = (uint8_t)model_id[i];
4576 }
4577 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4578 }
4579}
4580
d7bce999
EB		 4581static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4582 void *opaque, Error **errp)
89e48965
AF		 4583{
4584 X86CPU *cpu = X86_CPU(obj);
4585 int64_t value;
4586
4587 value = cpu->env.tsc_khz * 1000;
51e72bc1 4588 visit_type_int(v, name, &value, errp);
89e48965
AF		 4589}
4590
d7bce999
EB		 4591static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4592 void *opaque, Error **errp)
89e48965
AF		 4593{
4594 X86CPU *cpu = X86_CPU(obj);
4595 const int64_t min = 0;
2e84849a 4596 const int64_t max = INT64_MAX;
89e48965
AF		 4597 int64_t value;
4598
668f62ec 4599 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 4600 return;
4601 }
4602 if (value < min || value > max) {
c6bd8c70
MA		 4603 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4604 name ? name : "null", value, min, max);
89e48965
AF		 4605 return;
4606 }
4607
36f96c4b 4608 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 4609}
4610
7e5292b5 4611/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 4612static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4613 const char *name, void *opaque,
4614 Error **errp)
8e8aba50 4615{
ede146c2 4616 uint64_t *array = (uint64_t *)opaque;
8e8aba50 4617 FeatureWord w;
8e8aba50
EH		 4618 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4619 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4620 X86CPUFeatureWordInfoList *list = NULL;
4621
4622 for (w = 0; w < FEATURE_WORDS; w++) {
4623 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 4624 /*
4625 * We didn't have MSR features when "feature-words" was
4626 * introduced. Therefore skipped other type entries.
4627 */
4628 if (wi->type != CPUID_FEATURE_WORD) {
4629 continue;
4630 }
8e8aba50 4631 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 4632 qwi->cpuid_input_eax = wi->cpuid.eax;
4633 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4634 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4635 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 4636 qwi->features = array[w];
8e8aba50
EH		 4637
4638 /* List will be in reverse order, but order shouldn't matter */
4639 list_entries[w].next = list;
4640 list_entries[w].value = &word_infos[w];
4641 list = &list_entries[w];
4642 }
4643
6b62d961 4644 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 4645}
4646
72ac2e87
IM		 4647/* Convert all '_' in a feature string option name to '-', to make feature
4648 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4649 */
4650static inline void feat2prop(char *s)
4651{
4652 while ((s = strchr(s, '_'))) {
4653 *s = '-';
4654 }
4655}
4656
b54c9377
EH		 4657/* Return the feature property name for a feature flag bit */
4658static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4659{
ede146c2 4660 const char *name;
b54c9377
EH		 4661 /* XSAVE components are automatically enabled by other features,
4662 * so return the original feature name instead
4663 */
4664 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4665 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4666
4667 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4668 x86_ext_save_areas[comp].bits) {
4669 w = x86_ext_save_areas[comp].feature;
4670 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4671 }
4672 }
4673
ede146c2 4674 assert(bitnr < 64);
b54c9377 4675 assert(w < FEATURE_WORDS);
ede146c2
PB		 4676 name = feature_word_info[w].feat_names[bitnr];
4677 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4678 return name;
b54c9377
EH		 4679}
4680
dc15c051
IM		 4681/* Compatibily hack to maintain legacy +-feat semantic,
4682 * where +-feat overwrites any feature set by
4683 * feat=on|feat even if the later is parsed after +-feat
4684 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4685 */
2fae0d96 4686static GList *plus_features, *minus_features;
dc15c051 4687
83a00f60
EH		 4688static gint compare_string(gconstpointer a, gconstpointer b)
4689{
4690 return g_strcmp0(a, b);
4691}
4692
8f961357
EH		 4693/* Parse "+feature,-feature,feature=foo" CPU feature string
4694 */
62a48a2a 4695static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 4696 Error **errp)
8f961357 4697{
8f961357 4698 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 4699 static bool cpu_globals_initialized;
83a00f60 4700 bool ambiguous = false;
62a48a2a
IM		 4701
4702 if (cpu_globals_initialized) {
4703 return;
4704 }
4705 cpu_globals_initialized = true;
8f961357 4706
f6750e95
EH		 4707 if (!features) {
4708 return;
4709 }
4710
4711 for (featurestr = strtok(features, ",");
685479bd 4712 featurestr;
f6750e95
EH		 4713 featurestr = strtok(NULL, ",")) {
4714 const char *name;
4715 const char *val = NULL;
4716 char *eq = NULL;
cf2887c9 4717 char num[32];
62a48a2a 4718 GlobalProperty *prop;
c6dc6f63 4719
f6750e95 4720 /* Compatibility syntax: */
c6dc6f63 4721 if (featurestr[0] == '+') {
2fae0d96
EH		 4722 plus_features = g_list_append(plus_features,
4723 g_strdup(featurestr + 1));
f6750e95 4724 continue;
c6dc6f63 4725 } else if (featurestr[0] == '-') {
2fae0d96
EH		 4726 minus_features = g_list_append(minus_features,
4727 g_strdup(featurestr + 1));
f6750e95
EH		 4728 continue;
4729 }
4730
4731 eq = strchr(featurestr, '=');
4732 if (eq) {
4733 *eq++ = 0;
4734 val = eq;
c6dc6f63 4735 } else {
f6750e95 4736 val = "on";
a91987c2 4737 }
f6750e95
EH		 4738
4739 feat2prop(featurestr);
4740 name = featurestr;
4741
83a00f60 4742 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 4743 warn_report("Ambiguous CPU model string. "
4744 "Don't mix both \"+%s\" and \"%s=%s\"",
4745 name, name, val);
83a00f60
EH		 4746 ambiguous = true;
4747 }
4748 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 4749 warn_report("Ambiguous CPU model string. "
4750 "Don't mix both \"-%s\" and \"%s=%s\"",
4751 name, name, val);
83a00f60
EH		 4752 ambiguous = true;
4753 }
4754
f6750e95
EH		 4755 /* Special case: */
4756 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 4757 int ret;
f46bfdbf 4758 uint64_t tsc_freq;
f6750e95 4759
f17fd4fd 4760 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 4761 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 4762 error_setg(errp, "bad numerical value %s", val);
4763 return;
4764 }
4765 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4766 val = num;
4767 name = "tsc-frequency";
c6dc6f63 4768 }
f6750e95 4769
62a48a2a
IM		 4770 prop = g_new0(typeof(*prop), 1);
4771 prop->driver = typename;
4772 prop->property = g_strdup(name);
4773 prop->value = g_strdup(val);
62a48a2a 4774 qdev_prop_register_global(prop);
f6750e95
EH		 4775 }
4776
83a00f60 4777 if (ambiguous) {
3dc6f869
AF		 4778 warn_report("Compatibility of ambiguous CPU model "
4779 "strings won't be kept on future QEMU versions");
83a00f60 4780 }
c6dc6f63
AP		 4781}
4782
b8d834a0 4783static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
245edd0c 4784static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 4785
5a853fc5
EH		 4786/* Build a list with the name of all features on a feature word array */
4787static void x86_cpu_list_feature_names(FeatureWordArray features,
4788 strList **feat_names)
4789{
4790 FeatureWord w;
4791 strList **next = feat_names;
4792
4793 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 4794 uint64_t filtered = features[w];
5a853fc5 4795 int i;
ede146c2
PB		 4796 for (i = 0; i < 64; i++) {
4797 if (filtered & (1ULL << i)) {
5a853fc5
EH		 4798 strList *new = g_new0(strList, 1);
4799 new->value = g_strdup(x86_cpu_feature_name(w, i));
4800 *next = new;
4801 next = &new->next;
4802 }
4803 }
4804 }
4805}
4806
506174bf
EH		 4807static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4808 const char *name, void *opaque,
4809 Error **errp)
4810{
4811 X86CPU *xc = X86_CPU(obj);
4812 strList *result = NULL;
4813
4814 x86_cpu_list_feature_names(xc->filtered_features, &result);
4815 visit_type_strList(v, "unavailable-features", &result, errp);
4816}
4817
b54c9377
EH		 4818/* Check for missing features that may prevent the CPU class from
4819 * running using the current machine and accelerator.
4820 */
4821static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4822 strList **missing_feats)
4823{
4824 X86CPU *xc;
b54c9377
EH		 4825 Error *err = NULL;
4826 strList **next = missing_feats;
4827
d6dcc558 4828 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 4829 strList *new = g_new0(strList, 1);
3c254ab8 4830 new->value = g_strdup("kvm");
b54c9377
EH		 4831 *missing_feats = new;
4832 return;
4833 }
4834
3c75e12e 4835 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
b54c9377 4836
b8d834a0 4837 x86_cpu_expand_features(xc, &err);
b54c9377 4838 if (err) {
b8d834a0 4839 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 4840 * but in case it does, just report the model as not
4841 * runnable at all using the "type" property.
4842 */
4843 strList *new = g_new0(strList, 1);
4844 new->value = g_strdup("type");
4845 *next = new;
4846 next = &new->next;
4847 }
4848
245edd0c 4849 x86_cpu_filter_features(xc, false);
b54c9377 4850
5a853fc5 4851 x86_cpu_list_feature_names(xc->filtered_features, next);
b54c9377
EH		 4852
4853 object_unref(OBJECT(xc));
4854}
4855
8c3329e5 4856/* Print all cpuid feature names in featureset
c6dc6f63 4857 */
0442428a 4858static void listflags(GList *features)
0856579c 4859{
cc643b1e
DB		 4860 size_t len = 0;
4861 GList *tmp;
4862
4863 for (tmp = features; tmp; tmp = tmp->next) {
4864 const char *name = tmp->data;
4865 if ((len + strlen(name) + 1) >= 75) {
0442428a 4866 qemu_printf("\n");
cc643b1e 4867 len = 0;
c6dc6f63 4868 }
0442428a 4869 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 4870 len += strlen(name) + 1;
8c3329e5 4871 }
0442428a 4872 qemu_printf("\n");
c6dc6f63
AP		 4873}
4874
f48c8837 4875/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 4876static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4877{
4878 ObjectClass *class_a = (ObjectClass *)a;
4879 ObjectClass *class_b = (ObjectClass *)b;
4880 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4881 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 4882 int ret;
ee465a3e 4883
f48c8837 4884 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 4885 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 4886 } else {
88703ce2
EH		 4887 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4888 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 4889 ret = strcmp(name_a, name_b);
ee465a3e 4890 }
c7dbff4b 4891 return ret;
ee465a3e
EH		 4892}
4893
4894static GSList *get_sorted_cpu_model_list(void)
4895{
4896 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4897 list = g_slist_sort(list, x86_cpu_list_compare);
4898 return list;
4899}
4900
164e779c
EH		 4901static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4902{
3c75e12e 4903 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 4904 char *r = object_property_get_str(obj, "model-id", &error_abort);
4905 object_unref(obj);
4906 return r;
4907}
4908
0788a56b
EH		 4909static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4910{
4911 X86CPUVersion version;
4912
4913 if (!cc->model || !cc->model->is_alias) {
4914 return NULL;
4915 }
4916 version = x86_cpu_model_resolve_version(cc->model);
4917 if (version <= 0) {
4918 return NULL;
4919 }
4920 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4921}
4922
ee465a3e
EH		 4923static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4924{
4925 ObjectClass *oc = data;
4926 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 4927 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4928 g_autofree char *desc = g_strdup(cc->model_description);
4929 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 4930 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 4931
0788a56b
EH		 4932 if (!desc && alias_of) {
4933 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4934 desc = g_strdup("(alias configured by machine type)");
4935 } else {
4936 desc = g_strdup_printf("(alias of %s)", alias_of);
4937 }
4938 }
c63938df
TX		 4939 if (!desc && cc->model && cc->model->note) {
4940 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4941 }
164e779c 4942 if (!desc) {
c63938df 4943 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 4944 }
4945
c63938df 4946 qemu_printf("x86 %-20s %-58s\n", name, desc);
ee465a3e
EH		 4947}
4948
4949/* list available CPU models and flags */
0442428a 4950void x86_cpu_list(void)
c6dc6f63 4951{
cc643b1e 4952 int i, j;
ee465a3e 4953 GSList *list;
cc643b1e 4954 GList *names = NULL;
c6dc6f63 4955
0442428a 4956 qemu_printf("Available CPUs:\n");
ee465a3e 4957 list = get_sorted_cpu_model_list();
0442428a 4958 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 4959 g_slist_free(list);
21ad7789 4960
cc643b1e 4961 names = NULL;
3af60be2
JK		 4962 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4963 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 4964 for (j = 0; j < 64; j++) {
cc643b1e
DB		 4965 if (fw->feat_names[j]) {
4966 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4967 }
4968 }
3af60be2 4969 }
cc643b1e
DB		 4970
4971 names = g_list_sort(names, (GCompareFunc)strcmp);
4972
0442428a
MA		 4973 qemu_printf("\nRecognized CPUID flags:\n");
4974 listflags(names);
4975 qemu_printf("\n");
cc643b1e 4976 g_list_free(names);
c6dc6f63
AP		 4977}
4978
ee465a3e
EH		 4979static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4980{
4981 ObjectClass *oc = data;
4982 X86CPUClass *cc = X86_CPU_CLASS(oc);
4983 CpuDefinitionInfoList **cpu_list = user_data;
4984 CpuDefinitionInfoList *entry;
4985 CpuDefinitionInfo *info;
4986
4987 info = g_malloc0(sizeof(*info));
4988 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 4989 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4990 info->has_unavailable_features = true;
8ed877b7 4991 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 4992 info->migration_safe = cc->migration_safe;
4993 info->has_migration_safe = true;
5adbed30 4994 info->q_static = cc->static_model;
0788a56b
EH		 4995 /*
4996 * Old machine types won't report aliases, so that alias translation
4997 * doesn't break compatibility with previous QEMU versions.
4998 */
4999 if (default_cpu_version != CPU_VERSION_LEGACY) {
5000 info->alias_of = x86_cpu_class_get_alias_of(cc);
5001 info->has_alias_of = !!info->alias_of;
5002 }
ee465a3e
EH		 5003
5004 entry = g_malloc0(sizeof(*entry));
5005 entry->value = info;
5006 entry->next = *cpu_list;
5007 *cpu_list = entry;
5008}
5009
25a9d6ca 5010CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 5011{
5012 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 5013 GSList *list = get_sorted_cpu_model_list();
5014 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5015 g_slist_free(list);
e3966126
AL		 5016 return cpu_list;
5017}
5018
ede146c2 5019static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
84f1b92f 5020 bool migratable_only)
27418adf
EH		 5021{
5022 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 5023 uint64_t r = 0;
27418adf 5024
fefb41bf 5025 if (kvm_enabled()) {
07585923
RH		 5026 switch (wi->type) {
5027 case CPUID_FEATURE_WORD:
5028 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5029 wi->cpuid.ecx,
5030 wi->cpuid.reg);
5031 break;
5032 case MSR_FEATURE_WORD:
d86f9636
RH		 5033 r = kvm_arch_get_supported_msr_feature(kvm_state,
5034 wi->msr.index);
07585923
RH		 5035 break;
5036 }
d6dcc558 5037 } else if (hvf_enabled()) {
07585923
RH		 5038 if (wi->type != CPUID_FEATURE_WORD) {
5039 return 0;
5040 }
5041 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5042 wi->cpuid.ecx,
5043 wi->cpuid.reg);
fefb41bf 5044 } else if (tcg_enabled()) {
84f1b92f 5045 r = wi->tcg_features;
fefb41bf
EH		 5046 } else {
5047 return ~0;
5048 }
84f1b92f
EH		 5049 if (migratable_only) {
5050 r &= x86_cpu_get_migratable_flags(w);
5051 }
5052 return r;
27418adf
EH		 5053}
5054
5114e842
EH		 5055static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5056{
5057 PropValue *pv;
5058 for (pv = props; pv->prop; pv++) {
5059 if (!pv->value) {
5060 continue;
5061 }
5325cc34 5062 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 5063 &error_abort);
5064 }
5065}
5066
dcafd1ef
EH		 5067/* Apply properties for the CPU model version specified in model */
5068static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5069{
5070 const X86CPUVersionDefinition *vdef;
5071 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5072
5073 if (version == CPU_VERSION_LEGACY) {
5074 return;
5075 }
5076
5077 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5078 PropValue *p;
5079
5080 for (p = vdef->props; p && p->prop; p++) {
5325cc34 5081 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 5082 &error_abort);
5083 }
5084
5085 if (vdef->version == version) {
5086 break;
5087 }
5088 }
5089
5090 /*
5091 * If we reached the end of the list, version number was invalid
5092 */
5093 assert(vdef->version == version);
5094}
5095
f99fd7ca 5096/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 5097 */
49e2fa85 5098static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 5099{
dcafd1ef 5100 X86CPUDefinition *def = model->cpudef;
61dcd775 5101 CPUX86State *env = &cpu->env;
74f54bc4
EH		 5102 const char *vendor;
5103 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 5104 FeatureWord w;
c6dc6f63 5105
f99fd7ca
EH		 5106 /*NOTE: any property set by this function should be returned by
5107 * x86_cpu_static_props(), so static expansion of
5108 * query-cpu-model-expansion is always complete.
5109 */
5110
c39c0edf 5111 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 5112 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 5113 &error_abort);
5325cc34 5114 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 5115 &error_abort);
5116
5325cc34
MA		 5117 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5118 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5119 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 5120 &error_abort);
5325cc34 5121 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 5122 &error_abort);
e1c224b4
EH		 5123 for (w = 0; w < FEATURE_WORDS; w++) {
5124 env->features[w] = def->features[w];
5125 }
82beb536 5126
a9f27ea9
EH		 5127 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5128 cpu->legacy_cache = !def->cache_info;
ab8f992e 5129
9576de75 5130 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 5131 /* TODO: in-kernel irqchip for hvf */
82beb536 5132 if (kvm_enabled()) {
492a4c94
LT		 5133 if (!kvm_irqchip_in_kernel()) {
5134 x86_cpu_change_kvm_default("x2apic", "off");
5135 }
5136
5114e842 5137 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 5138 } else if (tcg_enabled()) {
5139 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 5140 }
5fcca9ff 5141
82beb536 5142 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5143
5144 /* sysenter isn't supported in compatibility mode on AMD,
5145 * syscall isn't supported in compatibility mode on Intel.
5146 * Normally we advertise the actual CPU vendor, but you can
5147 * override this using the 'vendor' property if you want to use
5148 * KVM's sysenter/syscall emulation in compatibility mode and
5149 * when doing cross vendor migration
5150 */
74f54bc4 5151 vendor = def->vendor;
d6dcc558 5152 if (accel_uses_host_cpuid()) {
7c08db30
EH		 5153 uint32_t ebx = 0, ecx = 0, edx = 0;
5154 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5155 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5156 vendor = host_vendor;
5157 }
5158
5325cc34 5159 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
7c08db30 5160
dcafd1ef 5161 x86_cpu_apply_version_props(cpu, model);
c6dc6f63
AP		 5162}
5163
96f75b59 5164#ifndef CONFIG_USER_ONLY
f99fd7ca 5165/* Return a QDict containing keys for all properties that can be included
dcafd1ef 5166 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
f99fd7ca
EH		 5167 * must be included in the dictionary.
5168 */
5169static QDict *x86_cpu_static_props(void)
5170{
5171 FeatureWord w;
5172 int i;
5173 static const char *props[] = {
5174 "min-level",
5175 "min-xlevel",
5176 "family",
5177 "model",
5178 "stepping",
5179 "model-id",
5180 "vendor",
5181 "lmce",
5182 NULL,
5183 };
5184 static QDict *d;
5185
5186 if (d) {
5187 return d;
5188 }
5189
5190 d = qdict_new();
5191 for (i = 0; props[i]; i++) {
0f9afc2a 5192 qdict_put_null(d, props[i]);
f99fd7ca
EH		 5193 }
5194
5195 for (w = 0; w < FEATURE_WORDS; w++) {
5196 FeatureWordInfo *fi = &feature_word_info[w];
5197 int bit;
ede146c2 5198 for (bit = 0; bit < 64; bit++) {
f99fd7ca
EH		 5199 if (!fi->feat_names[bit]) {
5200 continue;
5201 }
0f9afc2a 5202 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 5203 }
5204 }
5205
5206 return d;
5207}
5208
5209/* Add an entry to @props dict, with the value for property. */
5210static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5211{
5212 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5213 &error_abort);
5214
5215 qdict_put_obj(props, prop, value);
5216}
5217
5218/* Convert CPU model data from X86CPU object to a property dictionary
5219 * that can recreate exactly the same CPU model.
5220 */
5221static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5222{
5223 QDict *sprops = x86_cpu_static_props();
5224 const QDictEntry *e;
5225
5226 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5227 const char *prop = qdict_entry_key(e);
5228 x86_cpu_expand_prop(cpu, props, prop);
5229 }
5230}
5231
b8097deb
EH		 5232/* Convert CPU model data from X86CPU object to a property dictionary
5233 * that can recreate exactly the same CPU model, including every
5234 * writeable QOM property.
5235 */
5236static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5237{
5238 ObjectPropertyIterator iter;
5239 ObjectProperty *prop;
5240
5241 object_property_iter_init(&iter, OBJECT(cpu));
5242 while ((prop = object_property_iter_next(&iter))) {
5243 /* skip read-only or write-only properties */
5244 if (!prop->get || !prop->set) {
5245 continue;
5246 }
5247
5248 /* "hotplugged" is the only property that is configurable
5249 * on the command-line but will be set differently on CPUs
5250 * created using "-cpu ... -smp ..." and by CPUs created
5251 * on the fly by x86_cpu_from_model() for querying. Skip it.
5252 */
5253 if (!strcmp(prop->name, "hotplugged")) {
5254 continue;
5255 }
5256 x86_cpu_expand_prop(cpu, props, prop->name);
5257 }
5258}
5259
f99fd7ca
EH		 5260static void object_apply_props(Object *obj, QDict *props, Error **errp)
5261{
5262 const QDictEntry *prop;
f99fd7ca
EH		 5263
5264 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
778a2dc5 5265 if (!object_property_set_qobject(obj, qdict_entry_key(prop),
992861fb 5266 qdict_entry_value(prop), errp)) {
f99fd7ca
EH		 5267 break;
5268 }
5269 }
f99fd7ca
EH		 5270}
5271
5272/* Create X86CPU object according to model+props specification */
5273static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5274{
5275 X86CPU *xc = NULL;
5276 X86CPUClass *xcc;
5277 Error *err = NULL;
5278
5279 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5280 if (xcc == NULL) {
5281 error_setg(&err, "CPU model '%s' not found", model);
5282 goto out;
5283 }
5284
3c75e12e 5285 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
f99fd7ca
EH		 5286 if (props) {
5287 object_apply_props(OBJECT(xc), props, &err);
5288 if (err) {
5289 goto out;
5290 }
5291 }
5292
5293 x86_cpu_expand_features(xc, &err);
5294 if (err) {
5295 goto out;
5296 }
5297
5298out:
5299 if (err) {
5300 error_propagate(errp, err);
5301 object_unref(OBJECT(xc));
5302 xc = NULL;
5303 }
5304 return xc;
5305}
5306
5307CpuModelExpansionInfo *
96f75b59 5308qmp_query_cpu_model_expansion(CpuModelExpansionType type,
f99fd7ca
EH		 5309 CpuModelInfo *model,
5310 Error **errp)
5311{
5312 X86CPU *xc = NULL;
5313 Error *err = NULL;
5314 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5315 QDict *props = NULL;
5316 const char *base_name;
5317
5318 xc = x86_cpu_from_model(model->name,
5319 model->has_props ?
7dc847eb 5320 qobject_to(QDict, model->props) :
f99fd7ca
EH		 5321 NULL, &err);
5322 if (err) {
5323 goto out;
5324 }
5325
b8097deb 5326 props = qdict_new();
e38bf612
EH		 5327 ret->model = g_new0(CpuModelInfo, 1);
5328 ret->model->props = QOBJECT(props);
5329 ret->model->has_props = true;
f99fd7ca
EH		 5330
5331 switch (type) {
5332 case CPU_MODEL_EXPANSION_TYPE_STATIC:
5333 /* Static expansion will be based on "base" only */
5334 base_name = "base";
b8097deb 5335 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 5336 break;
5337 case CPU_MODEL_EXPANSION_TYPE_FULL:
5338 /* As we don't return every single property, full expansion needs
5339 * to keep the original model name+props, and add extra
5340 * properties on top of that.
5341 */
5342 base_name = model->name;
b8097deb 5343 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 5344 break;
5345 default:
df68a7f3 5346 error_setg(&err, "Unsupported expansion type");
f99fd7ca
EH		 5347 goto out;
5348 }
5349
f99fd7ca
EH		 5350 x86_cpu_to_dict(xc, props);
5351
f99fd7ca 5352 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 5353
5354out:
5355 object_unref(OBJECT(xc));
5356 if (err) {
5357 error_propagate(errp, err);
5358 qapi_free_CpuModelExpansionInfo(ret);
5359 ret = NULL;
5360 }
5361 return ret;
5362}
96f75b59 5363#endif /* !CONFIG_USER_ONLY */
f99fd7ca 5364
00fcd100
AB		 5365static gchar *x86_gdb_arch_name(CPUState *cs)
5366{
5367#ifdef TARGET_X86_64
5368 return g_strdup("i386:x86-64");
5369#else
5370 return g_strdup("i386");
5371#endif
5372}
5373
d940ee9b
EH		 5374static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5375{
dcafd1ef 5376 X86CPUModel *model = data;
d940ee9b
EH		 5377 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5378
dcafd1ef 5379 xcc->model = model;
bd72159d 5380 xcc->migration_safe = true;
d940ee9b
EH		 5381}
5382
dcafd1ef 5383static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5384{
88703ce2 5385 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5386 TypeInfo ti = {
5387 .name = typename,
5388 .parent = TYPE_X86_CPU,
5389 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5390 .class_data = model,
d940ee9b
EH		 5391 };
5392
dcafd1ef 5393 type_register(&ti);
dcafd1ef
EH		 5394}
5395
5396static void x86_register_cpudef_types(X86CPUDefinition *def)
5397{
5398 X86CPUModel *m;
5399 const X86CPUVersionDefinition *vdef;
dcafd1ef 5400
2a923a29
EH		 5401 /* AMD aliases are handled at runtime based on CPUID vendor, so
5402 * they shouldn't be set on the CPU model table.
5403 */
5404 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5405 /* catch mistakes instead of silently truncating model_id when too long */
5406 assert(def->model_id && strlen(def->model_id) <= 48);
5407
dcafd1ef
EH		 5408 /* Unversioned model: */
5409 m = g_new0(X86CPUModel, 1);
5410 m->cpudef = def;
0788a56b
EH		 5411 m->version = CPU_VERSION_AUTO;
5412 m->is_alias = true;
dcafd1ef
EH		 5413 x86_register_cpu_model_type(def->name, m);
5414
5415 /* Versioned models: */
5416
5417 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5418 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5419 g_autofree char *name =
5420 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5421 m->cpudef = def;
5422 m->version = vdef->version;
c63938df 5423 m->note = vdef->note;
dcafd1ef 5424 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5425
5426 if (vdef->alias) {
5427 X86CPUModel *am = g_new0(X86CPUModel, 1);
5428 am->cpudef = def;
5429 am->version = vdef->version;
0788a56b 5430 am->is_alias = true;
53db89d9
EH		 5431 x86_register_cpu_model_type(vdef->alias, am);
5432 }
dcafd1ef 5433 }
2a923a29 5434
d940ee9b
EH		 5435}
5436
c6dc6f63 5437#if !defined(CONFIG_USER_ONLY)
c6dc6f63 5438
0e26b7b8
BS		 5439void cpu_clear_apic_feature(CPUX86State *env)
5440{
0514ef2f 5441 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 5442}
5443
c6dc6f63
AP		 5444#endif /* !CONFIG_USER_ONLY */
5445
c6dc6f63
AP		 5446void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5447 uint32_t *eax, uint32_t *ebx,
5448 uint32_t *ecx, uint32_t *edx)
5449{
6aa9e42f
RH		 5450 X86CPU *cpu = env_archcpu(env);
5451 CPUState *cs = env_cpu(env);
d65af288 5452 uint32_t die_offset;
4ed3d478 5453 uint32_t limit;
1ce36bfe 5454 uint32_t signature[3];
f20dec0b
BM		 5455 X86CPUTopoInfo topo_info;
5456
dd08ef03 5457 topo_info.nodes_per_pkg = env->nr_nodes;
f20dec0b
BM		 5458 topo_info.dies_per_pkg = env->nr_dies;
5459 topo_info.cores_per_die = cs->nr_cores;
5460 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5461
4ed3d478
DB		 5462 /* Calculate & apply limits for different index ranges */
5463 if (index >= 0xC0000000) {
5464 limit = env->cpuid_xlevel2;
5465 } else if (index >= 0x80000000) {
5466 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5467 } else if (index >= 0x40000000) {
5468 limit = 0x40000001;
c6dc6f63 5469 } else {
4ed3d478
DB		 5470 limit = env->cpuid_level;
5471 }
5472
5473 if (index > limit) {
5474 /* Intel documentation states that invalid EAX input will
5475 * return the same information as EAX=cpuid_level
5476 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5477 */
5478 index = env->cpuid_level;
c6dc6f63
AP		 5479 }
5480
5481 switch(index) {
5482 case 0:
5483 *eax = env->cpuid_level;
5eb2f7a4
EH		 5484 *ebx = env->cpuid_vendor1;
5485 *edx = env->cpuid_vendor2;
5486 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5487 break;
5488 case 1:
5489 *eax = env->cpuid_version;
7e72a45c
EH		 5490 *ebx = (cpu->apic_id << 24) |
5491 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5492 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5493 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5494 *ecx |= CPUID_EXT_OSXSAVE;
5495 }
0514ef2f 5496 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5497 if (cs->nr_cores * cs->nr_threads > 1) {
5498 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5499 *edx |= CPUID_HT;
c6dc6f63 5500 }
ea39f9b6
LX		 5501 if (!cpu->enable_pmu) {
5502 *ecx &= ~CPUID_EXT_PDCM;
5503 }
c6dc6f63
AP		 5504 break;
5505 case 2:
5506 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 5507 if (cpu->cache_info_passthrough) {
5508 host_cpuid(index, 0, eax, ebx, ecx, edx);
5509 break;
5510 }
5e891bf8 5511 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5512 *ebx = 0;
14c985cf
LM		 5513 if (!cpu->enable_l3_cache) {
5514 *ecx = 0;
5515 } else {
a9f27ea9 5516 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5517 }
a9f27ea9
EH		 5518 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5519 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5520 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5521 break;
5522 case 4:
5523 /* cache info: needed for Core compatibility */
787aaf57
BC		 5524 if (cpu->cache_info_passthrough) {
5525 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 5526 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 5527 *eax &= ~0xFC000000;
7e3482f8
EH		 5528 if ((*eax & 31) && cs->nr_cores > 1) {
5529 *eax |= (cs->nr_cores - 1) << 26;
5530 }
c6dc6f63 5531 } else {
2f7a21c4 5532 *eax = 0;
76c2975a 5533 switch (count) {
c6dc6f63 5534 case 0: /* L1 dcache info */
a9f27ea9
EH		 5535 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5536 1, cs->nr_cores,
7e3482f8 5537 eax, ebx, ecx, edx);
c6dc6f63
AP		 5538 break;
5539 case 1: /* L1 icache info */
a9f27ea9
EH		 5540 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5541 1, cs->nr_cores,
7e3482f8 5542 eax, ebx, ecx, edx);
c6dc6f63
AP		 5543 break;
5544 case 2: /* L2 cache info */
a9f27ea9
EH		 5545 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5546 cs->nr_threads, cs->nr_cores,
7e3482f8 5547 eax, ebx, ecx, edx);
c6dc6f63 5548 break;
14c985cf 5549 case 3: /* L3 cache info */
f20dec0b 5550 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5551 if (cpu->enable_l3_cache) {
a9f27ea9 5552 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5553 (1 << die_offset), cs->nr_cores,
7e3482f8 5554 eax, ebx, ecx, edx);
14c985cf
LM		 5555 break;
5556 }
7e3482f8 5557 /* fall through */
c6dc6f63 5558 default: /* end of info */
7e3482f8 5559 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5560 break;
76c2975a
PB		 5561 }
5562 }
c6dc6f63
AP		 5563 break;
5564 case 5:
2266d443
MT		 5565 /* MONITOR/MWAIT Leaf */
5566 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5567 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5568 *ecx = cpu->mwait.ecx; /* flags */
5569 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5570 break;
5571 case 6:
5572 /* Thermal and Power Leaf */
28b8e4d0 5573 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5574 *ebx = 0;
5575 *ecx = 0;
5576 *edx = 0;
5577 break;
f7911686 5578 case 7:
13526728
EH		 5579 /* Structured Extended Feature Flags Enumeration Leaf */
5580 if (count == 0) {
80db491d
JL		 5581 /* Maximum ECX value for sub-leaves */
5582 *eax = env->cpuid_level_func7;
0514ef2f 5583 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5584 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5585 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5586 *ecx |= CPUID_7_0_ECX_OSPKE;
5587 }
95ea69fb 5588 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
80db491d
JL		 5589 } else if (count == 1) {
5590 *eax = env->features[FEAT_7_1_EAX];
5591 *ebx = 0;
5592 *ecx = 0;
5593 *edx = 0;
f7911686
YW		 5594 } else {
5595 *eax = 0;
5596 *ebx = 0;
5597 *ecx = 0;
5598 *edx = 0;
5599 }
5600 break;
c6dc6f63
AP		 5601 case 9:
5602 /* Direct Cache Access Information Leaf */
5603 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5604 *ebx = 0;
5605 *ecx = 0;
5606 *edx = 0;
5607 break;
5608 case 0xA:
5609 /* Architectural Performance Monitoring Leaf */
9337e3b6 5610 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 5611 KVMState *s = cs->kvm_state;
a0fa8208
GN		 5612
5613 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5614 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5615 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5616 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 5617 } else if (hvf_enabled() && cpu->enable_pmu) {
5618 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5619 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5620 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5621 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 5622 } else {
5623 *eax = 0;
5624 *ebx = 0;
5625 *ecx = 0;
5626 *edx = 0;
5627 }
c6dc6f63 5628 break;
5232d00a
RK		 5629 case 0xB:
5630 /* Extended Topology Enumeration Leaf */
5631 if (!cpu->enable_cpuid_0xb) {
5632 *eax = *ebx = *ecx = *edx = 0;
5633 break;
5634 }
5635
5636 *ecx = count & 0xff;
5637 *edx = cpu->apic_id;
5638
5639 switch (count) {
5640 case 0:
f20dec0b 5641 *eax = apicid_core_offset(&topo_info);
eab60fb9 5642 *ebx = cs->nr_threads;
5232d00a
RK		 5643 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5644 break;
5645 case 1:
7b225762 5646 *eax = env->pkg_offset;
eab60fb9 5647 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5648 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5649 break;
5650 default:
5651 *eax = 0;
5652 *ebx = 0;
5653 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5654 }
5655
a94e1428
LX		 5656 assert(!(*eax & ~0x1f));
5657 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5658 break;
5659 case 0x1F:
5660 /* V2 Extended Topology Enumeration Leaf */
5661 if (env->nr_dies < 2) {
5662 *eax = *ebx = *ecx = *edx = 0;
5663 break;
5664 }
5665
5666 *ecx = count & 0xff;
5667 *edx = cpu->apic_id;
5668 switch (count) {
5669 case 0:
f20dec0b 5670 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 5671 *ebx = cs->nr_threads;
5672 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5673 break;
5674 case 1:
f20dec0b 5675 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 5676 *ebx = cs->nr_cores * cs->nr_threads;
5677 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5678 break;
5679 case 2:
7b225762 5680 *eax = env->pkg_offset;
a94e1428
LX		 5681 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5682 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5683 break;
5684 default:
5685 *eax = 0;
5686 *ebx = 0;
5687 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5688 }
5232d00a
RK		 5689 assert(!(*eax & ~0x1f));
5690 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5691 break;
2560f19f 5692 case 0xD: {
51e49430 5693 /* Processor Extended State */
2560f19f
PB		 5694 *eax = 0;
5695 *ebx = 0;
5696 *ecx = 0;
5697 *edx = 0;
19dc85db 5698 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 5699 break;
5700 }
4928cd6d 5701
2560f19f 5702 if (count == 0) {
96193c22
EH		 5703 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5704 *eax = env->features[FEAT_XSAVE_COMP_LO];
5705 *edx = env->features[FEAT_XSAVE_COMP_HI];
76ecd7a5
BS		 5706 /*
5707 * The initial value of xcr0 and ebx == 0, On host without kvm
5708 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5709 * even through guest update xcr0, this will crash some legacy guest
5710 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5711 */
5712 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
2560f19f 5713 } else if (count == 1) {
0bb0b2d2 5714 *eax = env->features[FEAT_XSAVE];
f4f1110e 5715 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 5716 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5717 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 5718 *eax = esa->size;
5719 *ebx = esa->offset;
2560f19f 5720 }
51e49430
SY		 5721 }
5722 break;
2560f19f 5723 }
e37a5c7f
CP		 5724 case 0x14: {
5725 /* Intel Processor Trace Enumeration */
5726 *eax = 0;
5727 *ebx = 0;
5728 *ecx = 0;
5729 *edx = 0;
5730 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5731 !kvm_enabled()) {
5732 break;
5733 }
5734
5735 if (count == 0) {
5736 *eax = INTEL_PT_MAX_SUBLEAF;
5737 *ebx = INTEL_PT_MINIMAL_EBX;
5738 *ecx = INTEL_PT_MINIMAL_ECX;
5739 } else if (count == 1) {
5740 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5741 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5742 }
5743 break;
5744 }
1ce36bfe
DB		 5745 case 0x40000000:
5746 /*
5747 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5748 * set here, but we restrict to TCG none the less.
5749 */
5750 if (tcg_enabled() && cpu->expose_tcg) {
5751 memcpy(signature, "TCGTCGTCGTCG", 12);
5752 *eax = 0x40000001;
5753 *ebx = signature[0];
5754 *ecx = signature[1];
5755 *edx = signature[2];
5756 } else {
5757 *eax = 0;
5758 *ebx = 0;
5759 *ecx = 0;
5760 *edx = 0;
5761 }
5762 break;
5763 case 0x40000001:
5764 *eax = 0;
5765 *ebx = 0;
5766 *ecx = 0;
5767 *edx = 0;
5768 break;
c6dc6f63
AP		 5769 case 0x80000000:
5770 *eax = env->cpuid_xlevel;
5771 *ebx = env->cpuid_vendor1;
5772 *edx = env->cpuid_vendor2;
5773 *ecx = env->cpuid_vendor3;
5774 break;
5775 case 0x80000001:
5776 *eax = env->cpuid_version;
5777 *ebx = 0;
0514ef2f
EH		 5778 *ecx = env->features[FEAT_8000_0001_ECX];
5779 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 5780
5781 /* The Linux kernel checks for the CMPLegacy bit and
5782 * discards multiple thread information if it is set.
cb8d4c8f 5783 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 5784 */
ce3960eb 5785 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 5786 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5787 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5788 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 5789 *ecx |= 1 << 1; /* CmpLegacy bit */
5790 }
5791 }
c6dc6f63
AP		 5792 break;
5793 case 0x80000002:
5794 case 0x80000003:
5795 case 0x80000004:
5796 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5797 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5798 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5799 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5800 break;
5801 case 0x80000005:
5802 /* cache info (L1 cache) */
787aaf57
BC		 5803 if (cpu->cache_info_passthrough) {
5804 host_cpuid(index, 0, eax, ebx, ecx, edx);
5805 break;
5806 }
78ee6bd0 5807 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 5808 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 5809 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 5810 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5811 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5812 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 5813 break;
5814 case 0x80000006:
5815 /* cache info (L2 cache) */
787aaf57
BC		 5816 if (cpu->cache_info_passthrough) {
5817 host_cpuid(index, 0, eax, ebx, ecx, edx);
5818 break;
5819 }
78ee6bd0
PMD		 5820 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5821 (L2_DTLB_2M_ENTRIES << 16) |
5822 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 5823 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 5824 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5825 (L2_DTLB_4K_ENTRIES << 16) |
5826 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 5827 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5828 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5829 cpu->enable_l3_cache ?
5830 env->cache_info_amd.l3_cache : NULL,
5831 ecx, edx);
c6dc6f63 5832 break;
303752a9
MT		 5833 case 0x80000007:
5834 *eax = 0;
5835 *ebx = 0;
5836 *ecx = 0;
5837 *edx = env->features[FEAT_8000_0007_EDX];
5838 break;
c6dc6f63
AP		 5839 case 0x80000008:
5840 /* virtual & phys address size in low 2 bytes. */
0514ef2f 5841 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 5842 /* 64 bit processor */
5843 *eax = cpu->phys_bits; /* configurable physical bits */
5844 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5845 *eax |= 0x00003900; /* 57 bits virtual */
5846 } else {
5847 *eax |= 0x00003000; /* 48 bits virtual */
5848 }
c6dc6f63 5849 } else {
af45907a 5850 *eax = cpu->phys_bits;
c6dc6f63 5851 }
1b3420e1 5852 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 5853 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 5854 /*
5855 * Bits 15:12 is "The number of bits in the initial
5856 * Core::X86::Apic::ApicId[ApicId] value that indicate
5857 * thread ID within a package". This is already stored at
5858 * CPUX86State::pkg_offset.
5859 * Bits 7:0 is "The number of threads in the package is NC+1"
5860 */
5861 *ecx = (env->pkg_offset << 12) |
5862 ((cs->nr_cores * cs->nr_threads) - 1);
5863 } else {
5864 *ecx = 0;
c6dc6f63 5865 }
cac9edfc 5866 *edx = 0;
c6dc6f63
AP		 5867 break;
5868 case 0x8000000A:
0514ef2f 5869 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 5870 *eax = 0x00000001; /* SVM Revision */
5871 *ebx = 0x00000010; /* nr of ASIDs */
5872 *ecx = 0;
0514ef2f 5873 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 5874 } else {
5875 *eax = 0;
5876 *ebx = 0;
5877 *ecx = 0;
5878 *edx = 0;
5879 }
c6dc6f63 5880 break;
8f4202fb
BM		 5881 case 0x8000001D:
5882 *eax = 0;
a4e0b436
SL		 5883 if (cpu->cache_info_passthrough) {
5884 host_cpuid(index, count, eax, ebx, ecx, edx);
5885 break;
5886 }
8f4202fb
BM		 5887 switch (count) {
5888 case 0: /* L1 dcache info */
dd08ef03
BM		 5889 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5890 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5891 break;
5892 case 1: /* L1 icache info */
dd08ef03
BM		 5893 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5894 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5895 break;
5896 case 2: /* L2 cache info */
dd08ef03
BM		 5897 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5898 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5899 break;
5900 case 3: /* L3 cache info */
dd08ef03
BM		 5901 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5902 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5903 break;
5904 default: /* end of info */
5905 *eax = *ebx = *ecx = *edx = 0;
5906 break;
5907 }
5908 break;
ed78467a
BM		 5909 case 0x8000001E:
5910 assert(cpu->core_id <= 255);
dd08ef03 5911 encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx);
ed78467a 5912 break;
b3baa152
BW		 5913 case 0xC0000000:
5914 *eax = env->cpuid_xlevel2;
5915 *ebx = 0;
5916 *ecx = 0;
5917 *edx = 0;
5918 break;
5919 case 0xC0000001:
5920 /* Support for VIA CPU's CPUID instruction */
5921 *eax = env->cpuid_version;
5922 *ebx = 0;
5923 *ecx = 0;
0514ef2f 5924 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 5925 break;
5926 case 0xC0000002:
5927 case 0xC0000003:
5928 case 0xC0000004:
5929 /* Reserved for the future, and now filled with zero */
5930 *eax = 0;
5931 *ebx = 0;
5932 *ecx = 0;
5933 *edx = 0;
5934 break;
6cb8f2a6
BS		 5935 case 0x8000001F:
5936 *eax = sev_enabled() ? 0x2 : 0;
5937 *ebx = sev_get_cbit_position();
5938 *ebx |= sev_get_reduced_phys_bits() << 6;
5939 *ecx = 0;
5940 *edx = 0;
5941 break;
c6dc6f63
AP		 5942 default:
5943 /* reserved values: zero */
5944 *eax = 0;
5945 *ebx = 0;
5946 *ecx = 0;
5947 *edx = 0;
5948 break;
5949 }
5950}
5fd2087a 5951
781c67ca 5952static void x86_cpu_reset(DeviceState *dev)
5fd2087a 5953{
781c67ca 5954 CPUState *s = CPU(dev);
5fd2087a
AF		 5955 X86CPU *cpu = X86_CPU(s);
5956 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5957 CPUX86State *env = &cpu->env;
a114d25d
RH		 5958 target_ulong cr4;
5959 uint64_t xcr0;
c1958aea
AF		 5960 int i;
5961
781c67ca 5962 xcc->parent_reset(dev);
5fd2087a 5963
5e992a8e 5964 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 5965
c1958aea
AF		 5966 env->old_exception = -1;
5967
5968 /* init to reset state */
5969
c1958aea
AF		 5970 env->hflags2 |= HF2_GIF_MASK;
5971
5972 cpu_x86_update_cr0(env, 0x60000010);
5973 env->a20_mask = ~0x0;
5974 env->smbase = 0x30000;
e13713db 5975 env->msr_smi_count = 0;
c1958aea
AF		 5976
5977 env->idt.limit = 0xffff;
5978 env->gdt.limit = 0xffff;
5979 env->ldt.limit = 0xffff;
5980 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5981 env->tr.limit = 0xffff;
5982 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5983
5984 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5985 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5986 DESC_R_MASK | DESC_A_MASK);
5987 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5988 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5989 DESC_A_MASK);
5990 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5991 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5992 DESC_A_MASK);
5993 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5994 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5995 DESC_A_MASK);
5996 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5997 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5998 DESC_A_MASK);
5999 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6000 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6001 DESC_A_MASK);
6002
6003 env->eip = 0xfff0;
6004 env->regs[R_EDX] = env->cpuid_version;
6005
6006 env->eflags = 0x2;
6007
6008 /* FPU init */
6009 for (i = 0; i < 8; i++) {
6010 env->fptags[i] = 1;
6011 }
5bde1407 6012 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 6013
6014 env->mxcsr = 0x1f80;
a114d25d
RH		 6015 /* All units are in INIT state. */
6016 env->xstate_bv = 0;
c1958aea
AF		 6017
6018 env->pat = 0x0007040600070406ULL;
6019 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 6020 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6021 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6022 }
c1958aea
AF		 6023
6024 memset(env->dr, 0, sizeof(env->dr));
6025 env->dr[6] = DR6_FIXED_1;
6026 env->dr[7] = DR7_FIXED_1;
b3310ab3 6027 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 6028 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 6029
a114d25d 6030 cr4 = 0;
cfc3b074 6031 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 6032
6033#ifdef CONFIG_USER_ONLY
6034 /* Enable all the features for user-mode. */
6035 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 6036 xcr0 |= XSTATE_SSE_MASK;
a114d25d 6037 }
0f70ed47
PB		 6038 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6039 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 6040 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 6041 xcr0 |= 1ull << i;
6042 }
a114d25d 6043 }
0f70ed47 6044
a114d25d
RH		 6045 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6046 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6047 }
07929f2a
RH		 6048 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6049 cr4 |= CR4_FSGSBASE_MASK;
6050 }
a114d25d
RH		 6051#endif
6052
6053 env->xcr0 = xcr0;
6054 cpu_x86_update_cr4(env, cr4);
0522604b 6055
9db2efd9
AW		 6056 /*
6057 * SDM 11.11.5 requires:
6058 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6059 * - IA32_MTRR_PHYSMASKn.V = 0
6060 * All other bits are undefined. For simplification, zero it all.
6061 */
6062 env->mtrr_deftype = 0;
6063 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6064 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6065
b7394c83 6066 env->interrupt_injected = -1;
fd13f23b
LA		 6067 env->exception_nr = -1;
6068 env->exception_pending = 0;
6069 env->exception_injected = 0;
6070 env->exception_has_payload = false;
6071 env->exception_payload = 0;
b7394c83 6072 env->nmi_injected = false;
dd673288
IM		 6073#if !defined(CONFIG_USER_ONLY)
6074 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 6075 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 6076
259186a7 6077 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 6078
6079 if (kvm_enabled()) {
6080 kvm_arch_reset_vcpu(cpu);
6081 }
d6dcc558
SAGDR		 6082 else if (hvf_enabled()) {
6083 hvf_reset_vcpu(s);
6084 }
dd673288 6085#endif
5fd2087a
AF		 6086}
6087
dd673288
IM		 6088#ifndef CONFIG_USER_ONLY
6089bool cpu_is_bsp(X86CPU *cpu)
6090{
02e51483 6091 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 6092}
65dee380
IM		 6093
6094/* TODO: remove me, when reset over QOM tree is implemented */
6095static void x86_cpu_machine_reset_cb(void *opaque)
6096{
6097 X86CPU *cpu = opaque;
6098 cpu_reset(CPU(cpu));
6099}
dd673288
IM		 6100#endif
6101
de024815
AF		 6102static void mce_init(X86CPU *cpu)
6103{
6104 CPUX86State *cenv = &cpu->env;
6105 unsigned int bank;
6106
6107 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 6108 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 6109 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 6110 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6111 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 6112 cenv->mcg_ctl = ~(uint64_t)0;
6113 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6114 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6115 }
6116 }
6117}
6118
bdeec802 6119#ifndef CONFIG_USER_ONLY
2f114315 6120APICCommonClass *apic_get_class(void)
bdeec802 6121{
bdeec802
IM		 6122 const char *apic_type = "apic";
6123
d6dcc558 6124 /* TODO: in-kernel irqchip for hvf */
15eafc2e 6125 if (kvm_apic_in_kernel()) {
bdeec802
IM		 6126 apic_type = "kvm-apic";
6127 } else if (xen_enabled()) {
6128 apic_type = "xen-apic";
6129 }
6130
2f114315
RK		 6131 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6132}
6133
6134static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6135{
6136 APICCommonState *apic;
6137 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6138
3c75e12e 6139 cpu->apic_state = DEVICE(object_new_with_class(apic_class));
bdeec802 6140
6816b1b3 6141 object_property_add_child(OBJECT(cpu), "lapic",
d2623129 6142 OBJECT(cpu->apic_state));
67e55caa 6143 object_unref(OBJECT(cpu->apic_state));
6816b1b3 6144
33d7a288 6145 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 6146 /* TODO: convert to link<> */
02e51483 6147 apic = APIC_COMMON(cpu->apic_state);
60671e58 6148 apic->cpu = cpu;
8d42d2d3 6149 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 6150}
6151
6152static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6153{
8d42d2d3
CF		 6154 APICCommonState *apic;
6155 static bool apic_mmio_map_once;
6156
02e51483 6157 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 6158 return;
6159 }
ce189ab2 6160 qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
8d42d2d3
CF		 6161
6162 /* Map APIC MMIO area */
6163 apic = APIC_COMMON(cpu->apic_state);
6164 if (!apic_mmio_map_once) {
6165 memory_region_add_subregion_overlap(get_system_memory(),
6166 apic->apicbase &
6167 MSR_IA32_APICBASE_BASE,
6168 &apic->io_memory,
6169 0x1000);
6170 apic_mmio_map_once = true;
6171 }
bdeec802 6172}
f809c605
PB		 6173
6174static void x86_cpu_machine_done(Notifier *n, void *unused)
6175{
6176 X86CPU *cpu = container_of(n, X86CPU, machine_done);
6177 MemoryRegion *smram =
6178 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6179
6180 if (smram) {
6181 cpu->smram = g_new(MemoryRegion, 1);
6182 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3fb79344 6183 smram, 0, 4 * GiB);
f8c45c65 6184 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 6185 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6186 }
6187}
d3c64d6a
IM		 6188#else
6189static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6190{
6191}
bdeec802
IM		 6192#endif
6193
11f6fee5
DDAG		 6194/* Note: Only safe for use on x86(-64) hosts */
6195static uint32_t x86_host_phys_bits(void)
6196{
6197 uint32_t eax;
6198 uint32_t host_phys_bits;
6199
6200 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6201 if (eax >= 0x80000008) {
6202 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6203 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6204 * at 23:16 that can specify a maximum physical address bits for
6205 * the guest that can override this value; but I've not seen
6206 * anything with that set.
6207 */
6208 host_phys_bits = eax & 0xff;
6209 } else {
6210 /* It's an odd 64 bit machine that doesn't have the leaf for
6211 * physical address bits; fall back to 36 that's most older
6212 * Intel.
6213 */
6214 host_phys_bits = 36;
6215 }
6216
6217 return host_phys_bits;
6218}
e48638fd 6219
c39c0edf
EH		 6220static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6221{
6222 if (*min < value) {
6223 *min = value;
6224 }
6225}
6226
6227/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6228static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6229{
6230 CPUX86State *env = &cpu->env;
6231 FeatureWordInfo *fi = &feature_word_info[w];
07585923 6232 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 6233 uint32_t region = eax & 0xF0000000;
6234
07585923 6235 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 6236 if (!env->features[w]) {
6237 return;
6238 }
6239
6240 switch (region) {
6241 case 0x00000000:
6242 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6243 break;
6244 case 0x80000000:
6245 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6246 break;
6247 case 0xC0000000:
6248 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6249 break;
6250 }
80db491d
JL		 6251
6252 if (eax == 7) {
6253 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6254 fi->cpuid.ecx);
6255 }
c39c0edf
EH		 6256}
6257
2ca8a8be
EH		 6258/* Calculate XSAVE components based on the configured CPU feature flags */
6259static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6260{
6261 CPUX86State *env = &cpu->env;
6262 int i;
96193c22 6263 uint64_t mask;
2ca8a8be
EH		 6264
6265 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6266 return;
6267 }
6268
e3c9022b
EH		 6269 mask = 0;
6270 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 6271 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6272 if (env->features[esa->feature] & esa->bits) {
96193c22 6273 mask |= (1ULL << i);
2ca8a8be
EH		 6274 }
6275 }
6276
96193c22
EH		 6277 env->features[FEAT_XSAVE_COMP_LO] = mask;
6278 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 6279}
6280
b8d834a0
EH		 6281/***** Steps involved on loading and filtering CPUID data
6282 *
6283 * When initializing and realizing a CPU object, the steps
6284 * involved in setting up CPUID data are:
6285 *
6286 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 6287 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 6288 * transparent, as it is done automatically by instance_init.
6289 * No code should need to look at X86CPUDefinition structs
6290 * outside instance_init.
6291 *
6292 * 2) CPU expansion. This is done by realize before CPUID
6293 * filtering, and will make sure host/accelerator data is
6294 * loaded for CPU models that depend on host capabilities
6295 * (e.g. "host"). Done by x86_cpu_expand_features().
6296 *
6297 * 3) CPUID filtering. This initializes extra data related to
6298 * CPUID, and checks if the host supports all capabilities
6299 * required by the CPU. Runnability of a CPU model is
6300 * determined at this step. Done by x86_cpu_filter_features().
6301 *
6302 * Some operations don't require all steps to be performed.
6303 * More precisely:
6304 *
6305 * - CPU instance creation (instance_init) will run only CPU
6306 * model loading. CPU expansion can't run at instance_init-time
6307 * because host/accelerator data may be not available yet.
6308 * - CPU realization will perform both CPU model expansion and CPUID
6309 * filtering, and return an error in case one of them fails.
6310 * - query-cpu-definitions needs to run all 3 steps. It needs
6311 * to run CPUID filtering, as the 'unavailable-features'
6312 * field is set based on the filtering results.
6313 * - The query-cpu-model-expansion QMP command only needs to run
6314 * CPU model loading and CPU expansion. It should not filter
6315 * any CPUID data based on host capabilities.
6316 */
6317
6318/* Expand CPU configuration data, based on configured features
6319 * and host/accelerator capabilities when appropriate.
6320 */
6321static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 6322{
b34d12d1 6323 CPUX86State *env = &cpu->env;
dc15c051 6324 FeatureWord w;
99e24dbd 6325 int i;
2fae0d96 6326 GList *l;
9886e834 6327
99e24dbd
PB		 6328 for (l = plus_features; l; l = l->next) {
6329 const char *prop = l->data;
992861fb
MA		 6330 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6331 return;
99e24dbd
PB		 6332 }
6333 }
6334
6335 for (l = minus_features; l; l = l->next) {
6336 const char *prop = l->data;
992861fb
MA		 6337 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6338 return;
99e24dbd
PB		 6339 }
6340 }
6341
d4a606b3
EH		 6342 /*TODO: Now cpu->max_features doesn't overwrite features
6343 * set using QOM properties, and we can convert
dc15c051
IM		 6344 * plus_features & minus_features to global properties
6345 * inside x86_cpu_parse_featurestr() too.
6346 */
44bd8e53 6347 if (cpu->max_features) {
dc15c051 6348 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 6349 /* Override only features that weren't set explicitly
6350 * by the user.
6351 */
6352 env->features[w] |=
6353 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 6354 ~env->user_features[w] &
0d914f39 6355 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 6356 }
6357 }
6358
99e24dbd
PB		 6359 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6360 FeatureDep *d = &feature_dependencies[i];
6361 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 6362 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 6363
99e24dbd
PB		 6364 /* Not an error unless the dependent feature was added explicitly. */
6365 mark_unavailable_features(cpu, d->to.index,
6366 unavailable_features & env->user_features[d->to.index],
6367 "This feature depends on other features that were not requested");
6368
6369 env->user_features[d->to.index] |= unavailable_features;
6370 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 6371 }
dc15c051
IM		 6372 }
6373
aec661de
EH		 6374 if (!kvm_enabled() || !cpu->expose_kvm) {
6375 env->features[FEAT_KVM] = 0;
6376 }
6377
2ca8a8be 6378 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 6379
6380 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6381 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6382 if (cpu->full_cpuid_auto_level) {
6383 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6384 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6385 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6386 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 6387 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 6388 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6389 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6390 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 6391 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 6392 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6393 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6394 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 6395
6396 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 6397 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6398 if (cpu->intel_pt_auto_level) {
6399 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6400 } else if (cpu->env.cpuid_min_level < 0x14) {
6401 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6402 CPUID_7_0_EBX_INTEL_PT,
6403 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,level=0x14\"");
6404 }
f24c3a79
LK		 6405 }
6406
a94e1428
LX		 6407 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6408 if (env->nr_dies > 1) {
6409 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6410 }
6411
0c3d7c00
EH		 6412 /* SVM requires CPUID[0x8000000A] */
6413 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6414 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6415 }
6cb8f2a6
BS		 6416
6417 /* SEV requires CPUID[0x8000001F] */
6418 if (sev_enabled()) {
6419 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6420 }
c39c0edf
EH		 6421 }
6422
6423 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 6424 if (env->cpuid_level_func7 == UINT32_MAX) {
6425 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6426 }
c39c0edf
EH		 6427 if (env->cpuid_level == UINT32_MAX) {
6428 env->cpuid_level = env->cpuid_min_level;
6429 }
6430 if (env->cpuid_xlevel == UINT32_MAX) {
6431 env->cpuid_xlevel = env->cpuid_min_xlevel;
6432 }
6433 if (env->cpuid_xlevel2 == UINT32_MAX) {
6434 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 6435 }
41f3d4d6
EH		 6436}
6437
b8d834a0
EH		 6438/*
6439 * Finishes initialization of CPUID data, filters CPU feature
6440 * words based on host availability of each feature.
6441 *
6442 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6443 */
245edd0c 6444static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 6445{
6446 CPUX86State *env = &cpu->env;
6447 FeatureWord w;
245edd0c
PB		 6448 const char *prefix = NULL;
6449
6450 if (verbose) {
6451 prefix = accel_uses_host_cpuid()
6452 ? "host doesn't support requested feature"
6453 : "TCG doesn't support requested feature";
6454 }
b8d834a0
EH		 6455
6456 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 6457 uint64_t host_feat =
b8d834a0 6458 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6459 uint64_t requested_features = env->features[w];
6460 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6461 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6462 }
6463
e37a5c7f
CP		 6464 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6465 kvm_enabled()) {
6466 KVMState *s = CPU(cpu)->kvm_state;
6467 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6468 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6469 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6470 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6471 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6472
6473 if (!eax_0 ||
6474 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6475 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6476 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6477 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6478 INTEL_PT_ADDR_RANGES_NUM) ||
6479 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 6480 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6481 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 6482 /*
6483 * Processor Trace capabilities aren't configurable, so if the
6484 * host can't emulate the capabilities we report on
6485 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6486 */
245edd0c 6487 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6488 }
6489 }
b8d834a0
EH		 6490}
6491
41f3d4d6
EH		 6492static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6493{
6494 CPUState *cs = CPU(dev);
6495 X86CPU *cpu = X86_CPU(dev);
6496 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6497 CPUX86State *env = &cpu->env;
6498 Error *local_err = NULL;
6499 static bool ht_warned;
6500
2266d443
MT		 6501 if (xcc->host_cpuid_required) {
6502 if (!accel_uses_host_cpuid()) {
88703ce2 6503 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
2266d443 6504 error_setg(&local_err, "CPU model '%s' requires KVM", name);
2266d443
MT		 6505 goto out;
6506 }
be02cda3 6507 }
2266d443 6508
be02cda3 6509 if (cpu->max_features && accel_uses_host_cpuid()) {
2266d443
MT		 6510 if (enable_cpu_pm) {
6511 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6512 &cpu->mwait.ecx, &cpu->mwait.edx);
6513 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6514 }
32c87d70
PB		 6515 if (kvm_enabled() && cpu->ucode_rev == 0) {
6516 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6517 MSR_IA32_UCODE_REV);
6518 }
41f3d4d6
EH		 6519 }
6520
4e45aff3
PB		 6521 if (cpu->ucode_rev == 0) {
6522 /* The default is the same as KVM's. */
6523 if (IS_AMD_CPU(env)) {
6524 cpu->ucode_rev = 0x01000065;
6525 } else {
6526 cpu->ucode_rev = 0x100000000ULL;
6527 }
6528 }
6529
2266d443
MT		 6530 /* mwait extended info: needed for Core compatibility */
6531 /* We always wake on interrupt even if host does not have the capability */
6532 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6533
41f3d4d6
EH		 6534 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6535 error_setg(errp, "apic-id property was not initialized properly");
6536 return;
6537 }
6538
b8d834a0 6539 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6540 if (local_err) {
6541 goto out;
6542 }
6543
245edd0c
PB		 6544 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6545
6546 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6547 error_setg(&local_err,
6548 accel_uses_host_cpuid() ?
6549 "Host doesn't support requested features" :
6550 "TCG doesn't support requested features");
6551 goto out;
9997cf7b
EH		 6552 }
6553
9b15cd9e
IM		 6554 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6555 * CPUID[1].EDX.
6556 */
e48638fd 6557 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 6558 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6559 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 6560 & CPUID_EXT2_AMD_ALIASES);
6561 }
6562
11f6fee5
DDAG		 6563 /* For 64bit systems think about the number of physical bits to present.
6564 * ideally this should be the same as the host; anything other than matching
6565 * the host can cause incorrect guest behaviour.
6566 * QEMU used to pick the magic value of 40 bits that corresponds to
6567 * consumer AMD devices but nothing else.
6568 */
af45907a 6569 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 6570 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 6571 uint32_t host_phys_bits = x86_host_phys_bits();
6572 static bool warned;
6573
11f6fee5
DDAG		 6574 /* Print a warning if the user set it to a value that's not the
6575 * host value.
6576 */
6577 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6578 !warned) {
3dc6f869
AF		 6579 warn_report("Host physical bits (%u)"
6580 " does not match phys-bits property (%u)",
6581 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 6582 warned = true;
6583 }
6584
fea30652
EH		 6585 if (cpu->host_phys_bits) {
6586 /* The user asked for us to use the host physical bits */
6587 cpu->phys_bits = host_phys_bits;
6588 if (cpu->host_phys_bits_limit &&
6589 cpu->phys_bits > cpu->host_phys_bits_limit) {
6590 cpu->phys_bits = cpu->host_phys_bits_limit;
6591 }
6592 }
6593
11f6fee5
DDAG		 6594 if (cpu->phys_bits &&
6595 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6596 cpu->phys_bits < 32)) {
af45907a
DDAG		 6597 error_setg(errp, "phys-bits should be between 32 and %u "
6598 " (but is %u)",
6599 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6600 return;
6601 }
6602 } else {
11f6fee5 6603 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 6604 error_setg(errp, "TCG only supports phys-bits=%u",
6605 TCG_PHYS_ADDR_BITS);
6606 return;
6607 }
6608 }
11f6fee5
DDAG		 6609 /* 0 means it was not explicitly set by the user (or by machine
6610 * compat_props or by the host code above). In this case, the default
6611 * is the value used by TCG (40).
6612 */
6613 if (cpu->phys_bits == 0) {
6614 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6615 }
af45907a
DDAG		 6616 } else {
6617 /* For 32 bit systems don't use the user set value, but keep
6618 * phys_bits consistent with what we tell the guest.
6619 */
6620 if (cpu->phys_bits != 0) {
6621 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6622 return;
6623 }
fefb41bf 6624
af45907a
DDAG		 6625 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6626 cpu->phys_bits = 36;
6627 } else {
6628 cpu->phys_bits = 32;
6629 }
6630 }
a9f27ea9
EH		 6631
6632 /* Cache information initialization */
6633 if (!cpu->legacy_cache) {
dcafd1ef 6634 if (!xcc->model || !xcc->model->cpudef->cache_info) {
88703ce2 6635 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 6636 error_setg(errp,
6637 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 6638 return;
6639 }
6640 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
dcafd1ef 6641 *xcc->model->cpudef->cache_info;
a9f27ea9
EH		 6642 } else {
6643 /* Build legacy cache information */
6644 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6645 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6646 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6647 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6648
6649 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6650 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6651 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6652 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6653
6654 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6655 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6656 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6657 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6658 }
6659
6660
ce5b1bbf
LV		 6661 cpu_exec_realizefn(cs, &local_err);
6662 if (local_err != NULL) {
6663 error_propagate(errp, local_err);
6664 return;
6665 }
42ecabaa 6666
65dee380 6667#ifndef CONFIG_USER_ONLY
0e11fc69 6668 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 6669 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 6670
0e11fc69 6671 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 6672 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 6673 if (local_err != NULL) {
4dc1f449 6674 goto out;
bdeec802
IM		 6675 }
6676 }
65dee380
IM		 6677#endif
6678
7a059953 6679 mce_init(cpu);
2001d0cd
PB		 6680
6681#ifndef CONFIG_USER_ONLY
6682 if (tcg_enabled()) {
f809c605 6683 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 6684 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 6685
6686 /* Outer container... */
6687 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 6688 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 6689
6690 /* ... with two regions inside: normal system memory with low
6691 * priority, and...
6692 */
6693 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6694 get_system_memory(), 0, ~0ull);
6695 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6696 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 6697
6698 cs->num_ases = 2;
80ceb07a
PX		 6699 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6700 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 6701
6702 /* ... SMRAM with higher priority, linked from /machine/smram. */
6703 cpu->machine_done.notify = x86_cpu_machine_done;
6704 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 6705 }
6706#endif
6707
14a10fc3 6708 qemu_init_vcpu(cs);
d3c64d6a 6709
6b2942f9
BM		 6710 /*
6711 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6712 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6713 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 6714 * users a warning.
6715 *
6716 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6717 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6718 */
0765691e
MA		 6719 if (IS_AMD_CPU(env) &&
6720 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6721 cs->nr_threads > 1 && !ht_warned) {
6722 warn_report("This family of AMD CPU doesn't support "
6723 "hyperthreading(%d)",
6724 cs->nr_threads);
6725 error_printf("Please configure -smp options properly"
6726 " or try enabling topoext feature.\n");
6727 ht_warned = true;
e48638fd
WH		 6728 }
6729
d3c64d6a
IM		 6730 x86_cpu_apic_realize(cpu, &local_err);
6731 if (local_err != NULL) {
6732 goto out;
6733 }
14a10fc3 6734 cpu_reset(cs);
2b6f294c 6735
4dc1f449 6736 xcc->parent_realize(dev, &local_err);
2001d0cd 6737
4dc1f449
IM		 6738out:
6739 if (local_err != NULL) {
6740 error_propagate(errp, local_err);
6741 return;
6742 }
7a059953
AF		 6743}
6744
b69c3c21 6745static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 6746{
6747 X86CPU *cpu = X86_CPU(dev);
7bbc124e 6748 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 6749
6750#ifndef CONFIG_USER_ONLY
6751 cpu_remove_sync(CPU(dev));
6752 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6753#endif
6754
6755 if (cpu->apic_state) {
6756 object_unparent(OBJECT(cpu->apic_state));
6757 cpu->apic_state = NULL;
6758 }
7bbc124e 6759
b69c3c21 6760 xcc->parent_unrealize(dev);
c884776e
IM		 6761}
6762
38e5c119 6763typedef struct BitProperty {
a7b0ffac 6764 FeatureWord w;
ede146c2 6765 uint64_t mask;
38e5c119
EH		 6766} BitProperty;
6767
d7bce999
EB		 6768static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6769 void *opaque, Error **errp)
38e5c119 6770{
a7b0ffac 6771 X86CPU *cpu = X86_CPU(obj);
38e5c119 6772 BitProperty *fp = opaque;
ede146c2 6773 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 6774 bool value = (f & fp->mask) == fp->mask;
51e72bc1 6775 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 6776}
6777
d7bce999
EB		 6778static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6779 void *opaque, Error **errp)
38e5c119
EH		 6780{
6781 DeviceState *dev = DEVICE(obj);
a7b0ffac 6782 X86CPU *cpu = X86_CPU(obj);
38e5c119 6783 BitProperty *fp = opaque;
38e5c119
EH		 6784 bool value;
6785
6786 if (dev->realized) {
6787 qdev_prop_set_after_realize(dev, name, errp);
6788 return;
6789 }
6790
668f62ec 6791 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 6792 return;
6793 }
6794
6795 if (value) {
a7b0ffac 6796 cpu->env.features[fp->w] |= fp->mask;
38e5c119 6797 } else {
a7b0ffac 6798 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 6799 }
d4a606b3 6800 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 6801}
6802
6803static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6804 void *opaque)
6805{
6806 BitProperty *prop = opaque;
6807 g_free(prop);
6808}
6809
6810/* Register a boolean property to get/set a single bit in a uint32_t field.
6811 *
6812 * The same property name can be registered multiple times to make it affect
6813 * multiple bits in the same FeatureWord. In that case, the getter will return
6814 * true only if all bits are set.
6815 */
6816static void x86_cpu_register_bit_prop(X86CPU *cpu,
6817 const char *prop_name,
a7b0ffac 6818 FeatureWord w,
38e5c119
EH		 6819 int bitnr)
6820{
6821 BitProperty *fp;
6822 ObjectProperty *op;
ede146c2 6823 uint64_t mask = (1ULL << bitnr);
38e5c119
EH		 6824
6825 op = object_property_find(OBJECT(cpu), prop_name, NULL);
6826 if (op) {
6827 fp = op->opaque;
a7b0ffac 6828 assert(fp->w == w);
38e5c119
EH		 6829 fp->mask |= mask;
6830 } else {
6831 fp = g_new0(BitProperty, 1);
a7b0ffac 6832 fp->w = w;
38e5c119
EH		 6833 fp->mask = mask;
6834 object_property_add(OBJECT(cpu), prop_name, "bool",
6835 x86_cpu_get_bit_prop,
6836 x86_cpu_set_bit_prop,
d2623129 6837 x86_cpu_release_bit_prop, fp);
38e5c119
EH		 6838 }
6839}
6840
6841static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6842 FeatureWord w,
6843 int bitnr)
6844{
38e5c119 6845 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 6846 const char *name = fi->feat_names[bitnr];
38e5c119 6847
16d2fcaa 6848 if (!name) {
38e5c119
EH		 6849 return;
6850 }
6851
fc7dfd20
EH		 6852 /* Property names should use "-" instead of "_".
6853 * Old names containing underscores are registered as aliases
6854 * using object_property_add_alias()
6855 */
16d2fcaa
EH		 6856 assert(!strchr(name, '_'));
6857 /* aliases don't use "|" delimiters anymore, they are registered
6858 * manually using object_property_add_alias() */
6859 assert(!strchr(name, '|'));
a7b0ffac 6860 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 6861}
6862
b75c9900 6863#if !defined(CONFIG_USER_ONLY)
d187e08d
AN		 6864static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6865{
6866 X86CPU *cpu = X86_CPU(cs);
6867 CPUX86State *env = &cpu->env;
6868 GuestPanicInformation *panic_info = NULL;
6869
5e953812 6870 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 6871 panic_info = g_malloc0(sizeof(GuestPanicInformation));
6872
e8ed97a6 6873 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 6874
5e953812 6875 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 6876 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6877 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6878 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6879 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6880 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 6881 }
6882
6883 return panic_info;
6884}
6885static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6886 const char *name, void *opaque,
6887 Error **errp)
6888{
6889 CPUState *cs = CPU(obj);
6890 GuestPanicInformation *panic_info;
6891
6892 if (!cs->crash_occurred) {
6893 error_setg(errp, "No crash occured");
6894 return;
6895 }
6896
6897 panic_info = x86_cpu_get_crash_info(cs);
6898 if (panic_info == NULL) {
6899 error_setg(errp, "No crash information");
6900 return;
6901 }
6902
6903 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6904 errp);
6905 qapi_free_GuestPanicInformation(panic_info);
6906}
b75c9900 6907#endif /* !CONFIG_USER_ONLY */
d187e08d 6908
de024815
AF		 6909static void x86_cpu_initfn(Object *obj)
6910{
6911 X86CPU *cpu = X86_CPU(obj);
d940ee9b 6912 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 6913 CPUX86State *env = &cpu->env;
38e5c119 6914 FeatureWord w;
de024815 6915
c26ae610 6916 env->nr_dies = 1;
c24a41bb 6917 env->nr_nodes = 1;
7506ed90 6918 cpu_set_cpustate_pointers(cpu);
71ad61d3
AF		 6919
6920 object_property_add(obj, "family", "int",
95b8519d 6921 x86_cpuid_version_get_family,
d2623129 6922 x86_cpuid_version_set_family, NULL, NULL);
c5291a4f 6923 object_property_add(obj, "model", "int",
67e30c83 6924 x86_cpuid_version_get_model,
d2623129 6925 x86_cpuid_version_set_model, NULL, NULL);
036e2222 6926 object_property_add(obj, "stepping", "int",
35112e41 6927 x86_cpuid_version_get_stepping,
d2623129 6928 x86_cpuid_version_set_stepping, NULL, NULL);
d480e1af
AF		 6929 object_property_add_str(obj, "vendor",
6930 x86_cpuid_get_vendor,
d2623129 6931 x86_cpuid_set_vendor);
938d4c25 6932 object_property_add_str(obj, "model-id",
63e886eb 6933 x86_cpuid_get_model_id,
d2623129 6934 x86_cpuid_set_model_id);
89e48965
AF		 6935 object_property_add(obj, "tsc-frequency", "int",
6936 x86_cpuid_get_tsc_freq,
d2623129 6937 x86_cpuid_set_tsc_freq, NULL, NULL);
8e8aba50
EH		 6938 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6939 x86_cpu_get_feature_words,
d2623129 6940 NULL, NULL, (void *)env->features);
7e5292b5
EH		 6941 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6942 x86_cpu_get_feature_words,
d2623129 6943 NULL, NULL, (void *)cpu->filtered_features);
506174bf
EH		 6944 /*
6945 * The "unavailable-features" property has the same semantics as
6946 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6947 * QMP command: they list the features that would have prevented the
6948 * CPU from running if the "enforce" flag was set.
6949 */
6950 object_property_add(obj, "unavailable-features", "strList",
6951 x86_cpu_get_unavailable_features,
d2623129 6952 NULL, NULL, NULL);
71ad61d3 6953
b75c9900 6954#if !defined(CONFIG_USER_ONLY)
d187e08d 6955 object_property_add(obj, "crash-information", "GuestPanicInformation",
d2623129 6956 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
b75c9900 6957#endif
d187e08d 6958
38e5c119
EH		 6959 for (w = 0; w < FEATURE_WORDS; w++) {
6960 int bitnr;
6961
ede146c2 6962 for (bitnr = 0; bitnr < 64; bitnr++) {
38e5c119
EH		 6963 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6964 }
6965 }
6966
d2623129
MA		 6967 object_property_add_alias(obj, "sse3", obj, "pni");
6968 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6969 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6970 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6971 object_property_add_alias(obj, "xd", obj, "nx");
6972 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6973 object_property_add_alias(obj, "i64", obj, "lm");
6974
6975 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6976 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6977 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6978 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6979 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6980 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6981 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6982 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6983 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6984 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6985 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
6986 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6987 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6988 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6989 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6990 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6991 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6992 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6993 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6994 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6995 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6996 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 6997
dcafd1ef 6998 if (xcc->model) {
49e2fa85 6999 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 7000 }
de024815
AF		 7001}
7002
997395d3
IM		 7003static int64_t x86_cpu_get_arch_id(CPUState *cs)
7004{
7005 X86CPU *cpu = X86_CPU(cs);
997395d3 7006
7e72a45c 7007 return cpu->apic_id;
997395d3
IM		 7008}
7009
444d5590
AF		 7010static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7011{
7012 X86CPU *cpu = X86_CPU(cs);
7013
7014 return cpu->env.cr[0] & CR0_PG_MASK;
7015}
7016
f45748f1
AF		 7017static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7018{
7019 X86CPU *cpu = X86_CPU(cs);
7020
7021 cpu->env.eip = value;
7022}
7023
bdf7ae5b
AF		 7024static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
7025{
7026 X86CPU *cpu = X86_CPU(cs);
7027
7028 cpu->env.eip = tb->pc - tb->cs_base;
7029}
7030
92d5f1a4 7031int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 7032{
7033 X86CPU *cpu = X86_CPU(cs);
7034 CPUX86State *env = &cpu->env;
7035
92d5f1a4
PB		 7036#if !defined(CONFIG_USER_ONLY)
7037 if (interrupt_request & CPU_INTERRUPT_POLL) {
7038 return CPU_INTERRUPT_POLL;
7039 }
7040#endif
7041 if (interrupt_request & CPU_INTERRUPT_SIPI) {
7042 return CPU_INTERRUPT_SIPI;
7043 }
7044
7045 if (env->hflags2 & HF2_GIF_MASK) {
7046 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7047 !(env->hflags & HF_SMM_MASK)) {
7048 return CPU_INTERRUPT_SMI;
7049 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7050 !(env->hflags2 & HF2_NMI_MASK)) {
7051 return CPU_INTERRUPT_NMI;
7052 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7053 return CPU_INTERRUPT_MCE;
7054 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7055 (((env->hflags2 & HF2_VINTR_MASK) &&
7056 (env->hflags2 & HF2_HIF_MASK)) ||
7057 (!(env->hflags2 & HF2_VINTR_MASK) &&
7058 (env->eflags & IF_MASK &&
7059 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7060 return CPU_INTERRUPT_HARD;
7061#if !defined(CONFIG_USER_ONLY)
7062 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
7063 (env->eflags & IF_MASK) &&
7064 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
7065 return CPU_INTERRUPT_VIRQ;
7066#endif
7067 }
7068 }
7069
7070 return 0;
7071}
7072
7073static bool x86_cpu_has_work(CPUState *cs)
7074{
7075 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 7076}
7077
f50f3dd5
RH		 7078static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7079{
7080 X86CPU *cpu = X86_CPU(cs);
7081 CPUX86State *env = &cpu->env;
7082
7083 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7084 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7085 : bfd_mach_i386_i8086);
7086 info->print_insn = print_insn_i386;
b666d2a4
RH		 7087
7088 info->cap_arch = CS_ARCH_X86;
7089 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7090 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7091 : CS_MODE_16);
15fa1a0a
RH		 7092 info->cap_insn_unit = 1;
7093 info->cap_insn_split = 8;
f50f3dd5
RH		 7094}
7095
35b1b927
TW		 7096void x86_update_hflags(CPUX86State *env)
7097{
7098 uint32_t hflags;
7099#define HFLAG_COPY_MASK \
7100 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7101 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7102 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7103 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7104
7105 hflags = env->hflags & HFLAG_COPY_MASK;
7106 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7107 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7108 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7109 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7110 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7111
7112 if (env->cr[4] & CR4_OSFXSR_MASK) {
7113 hflags |= HF_OSFXSR_MASK;
7114 }
7115
7116 if (env->efer & MSR_EFER_LMA) {
7117 hflags |= HF_LMA_MASK;
7118 }
7119
7120 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7121 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7122 } else {
7123 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7124 (DESC_B_SHIFT - HF_CS32_SHIFT);
7125 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7126 (DESC_B_SHIFT - HF_SS32_SHIFT);
7127 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7128 !(hflags & HF_CS32_MASK)) {
7129 hflags |= HF_ADDSEG_MASK;
7130 } else {
7131 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7132 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7133 }
7134 }
7135 env->hflags = hflags;
7136}
7137
9337e3b6 7138static Property x86_cpu_properties[] = {
2da00e31
IM		 7139#ifdef CONFIG_USER_ONLY
7140 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7141 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 7142 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7143 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 7144 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 7145 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 7146#else
7147 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 7148 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7149 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 7150 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 7151 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 7152#endif
15f8b142 7153 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 7154 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2d384d7c 7155
915aee93
RK		 7156 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7157 HYPERV_SPINLOCK_NEVER_RETRY),
2d384d7c
VK		 7158 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7159 HYPERV_FEAT_RELAXED, 0),
7160 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7161 HYPERV_FEAT_VAPIC, 0),
7162 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7163 HYPERV_FEAT_TIME, 0),
7164 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7165 HYPERV_FEAT_CRASH, 0),
7166 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7167 HYPERV_FEAT_RESET, 0),
7168 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7169 HYPERV_FEAT_VPINDEX, 0),
7170 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7171 HYPERV_FEAT_RUNTIME, 0),
7172 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7173 HYPERV_FEAT_SYNIC, 0),
7174 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7175 HYPERV_FEAT_STIMER, 0),
7176 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7177 HYPERV_FEAT_FREQUENCIES, 0),
7178 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7179 HYPERV_FEAT_REENLIGHTENMENT, 0),
7180 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7181 HYPERV_FEAT_TLBFLUSH, 0),
7182 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7183 HYPERV_FEAT_EVMCS, 0),
7184 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7185 HYPERV_FEAT_IPI, 0),
128531d9
VK		 7186 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7187 HYPERV_FEAT_STIMER_DIRECT, 0),
30d6ff66
VK		 7188 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7189 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
e48ddcc6 7190 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
2d384d7c 7191
15e41345 7192 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 7193 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 7194 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 7195 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 7196 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 7197 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 7198 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 7199 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 7200 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7201 UINT32_MAX),
c39c0edf
EH		 7202 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7203 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7204 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7205 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7206 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7207 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 7208 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 7209 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 7210 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 7211 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 7212 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 7213 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 7214 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7215 false),
0b564e6f 7216 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 7217 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 7218 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7219 true),
ab8f992e 7220 /*
a9f27ea9
EH		 7221 * lecacy_cache defaults to true unless the CPU model provides its
7222 * own cache information (see x86_cpu_load_def()).
ab8f992e 7223 */
a9f27ea9 7224 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 7225
7226 /*
7227 * From "Requirements for Implementing the Microsoft
7228 * Hypervisor Interface":
7229 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7230 *
7231 * "Starting with Windows Server 2012 and Windows 8, if
7232 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7233 * the hypervisor imposes no specific limit to the number of VPs.
7234 * In this case, Windows Server 2012 guest VMs may use more than
7235 * 64 VPs, up to the maximum supported number of processors applicable
7236 * to the specific Windows version being used."
7237 */
7238 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 7239 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7240 false),
f24c3a79
LK		 7241 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7242 true),
9337e3b6
EH		 7243 DEFINE_PROP_END_OF_LIST()
7244};
7245
5fd2087a
AF		 7246static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7247{
7248 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7249 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 7250 DeviceClass *dc = DEVICE_CLASS(oc);
7251
bf853881
PMD		 7252 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7253 &xcc->parent_realize);
7254 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7255 &xcc->parent_unrealize);
4f67d30b 7256 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 7257
781c67ca 7258 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
91b1df8c 7259 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 7260
500050d1 7261 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 7262 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 7263 cc->has_work = x86_cpu_has_work;
79c664f6 7264#ifdef CONFIG_TCG
97a8ea5a 7265 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 7266 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 7267#endif
878096ee 7268 cc->dump_state = x86_cpu_dump_state;
f45748f1 7269 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 7270 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 7271 cc->gdb_read_register = x86_cpu_gdb_read_register;
7272 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 7273 cc->get_arch_id = x86_cpu_get_arch_id;
7274 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5d004421 7275#ifndef CONFIG_USER_ONLY
f8c45c65 7276 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 7277 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
56f99750 7278 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
b75c9900 7279 cc->get_crash_info = x86_cpu_get_crash_info;
c72bf468
JF		 7280 cc->write_elf64_note = x86_cpu_write_elf64_note;
7281 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7282 cc->write_elf32_note = x86_cpu_write_elf32_note;
7283 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 7284 cc->vmsd = &vmstate_x86_cpu;
c72bf468 7285#endif
00fcd100
AB		 7286 cc->gdb_arch_name = x86_gdb_arch_name;
7287#ifdef TARGET_X86_64
b8158192 7288 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 7289 cc->gdb_num_core_regs = 66;
00fcd100 7290#else
b8158192 7291 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 7292 cc->gdb_num_core_regs = 50;
00fcd100 7293#endif
79c664f6 7294#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 7295 cc->debug_excp_handler = breakpoint_handler;
7296#endif
374e0cd4
RH		 7297 cc->cpu_exec_enter = x86_cpu_exec_enter;
7298 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 7299#ifdef CONFIG_TCG
55c3ceef 7300 cc->tcg_initialize = tcg_x86_init;
5d004421 7301 cc->tlb_fill = x86_cpu_tlb_fill;
74d7fc7f 7302#endif
f50f3dd5 7303 cc->disas_set_info = x86_disas_set_info;
4c315c27 7304
e90f2a8c 7305 dc->user_creatable = true;
5fd2087a
AF		 7306}
7307
7308static const TypeInfo x86_cpu_type_info = {
7309 .name = TYPE_X86_CPU,
7310 .parent = TYPE_CPU,
7311 .instance_size = sizeof(X86CPU),
de024815 7312 .instance_init = x86_cpu_initfn,
d940ee9b 7313 .abstract = true,
5fd2087a
AF		 7314 .class_size = sizeof(X86CPUClass),
7315 .class_init = x86_cpu_common_class_init,
7316};
7317
5adbed30
EH		 7318
7319/* "base" CPU model, used by query-cpu-model-expansion */
7320static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7321{
7322 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7323
7324 xcc->static_model = true;
7325 xcc->migration_safe = true;
7326 xcc->model_description = "base CPU model type with no features enabled";
7327 xcc->ordering = 8;
7328}
7329
7330static const TypeInfo x86_base_cpu_type_info = {
7331 .name = X86_CPU_TYPE_NAME("base"),
7332 .parent = TYPE_X86_CPU,
7333 .class_init = x86_cpu_base_class_init,
7334};
7335
5fd2087a
AF		 7336static void x86_cpu_register_types(void)
7337{
d940ee9b
EH		 7338 int i;
7339
5fd2087a 7340 type_register_static(&x86_cpu_type_info);
d940ee9b 7341 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 7342 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 7343 }
c62f2630 7344 type_register_static(&max_x86_cpu_type_info);
5adbed30 7345 type_register_static(&x86_base_cpu_type_info);
d6dcc558 7346#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 7347 type_register_static(&host_x86_cpu_type_info);
7348#endif
5fd2087a
AF		 7349}
7350
7351type_init(x86_cpu_register_types)
Empty description
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