[qemu.git] / hw / timer / etraxfs_timer.c

/*
 * QEMU ETRAX Timers
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"

#define D(x)

#define RW_TMR0_DIV   0x00
#define R_TMR0_DATA   0x04
#define RW_TMR0_CTRL  0x08
#define RW_TMR1_DIV   0x10
#define R_TMR1_DATA   0x14
#define RW_TMR1_CTRL  0x18
#define R_TIME        0x38
#define RW_WD_CTRL    0x40
#define R_WD_STAT     0x44
#define RW_INTR_MASK  0x48
#define RW_ACK_INTR   0x4c
#define R_INTR        0x50
#define R_MASKED_INTR 0x54

#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
#define ETRAX_TIMER(obj) \
    OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)

typedef struct ETRAXTimerState {
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    qemu_irq irq;
    qemu_irq nmi;

    QEMUBH *bh_t0;
    QEMUBH *bh_t1;
    QEMUBH *bh_wd;
    ptimer_state *ptimer_t0;
    ptimer_state *ptimer_t1;
    ptimer_state *ptimer_wd;

    int wd_hits;

    /* Control registers.  */
    uint32_t rw_tmr0_div;
    uint32_t r_tmr0_data;
    uint32_t rw_tmr0_ctrl;

    uint32_t rw_tmr1_div;
    uint32_t r_tmr1_data;
    uint32_t rw_tmr1_ctrl;

    uint32_t rw_wd_ctrl;

    uint32_t rw_intr_mask;
    uint32_t rw_ack_intr;
    uint32_t r_intr;
    uint32_t r_masked_intr;
} ETRAXTimerState;

static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
    ETRAXTimerState *t = opaque;
    uint32_t r = 0;

    switch (addr) {
    case R_TMR0_DATA:
        r = ptimer_get_count(t->ptimer_t0);
        break;
    case R_TMR1_DATA:
        r = ptimer_get_count(t->ptimer_t1);
        break;
    case R_TIME:
        r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
        break;
    case RW_INTR_MASK:
        r = t->rw_intr_mask;
        break;
    case R_MASKED_INTR:
        r = t->r_intr & t->rw_intr_mask;
        break;
    default:
        D(printf ("%s %x\n", __func__, addr));
        break;
    }
    return r;
}

static void update_ctrl(ETRAXTimerState *t, int tnum)
{
    unsigned int op;
    unsigned int freq;
    unsigned int freq_hz;
    unsigned int div;
    uint32_t ctrl;

    ptimer_state *timer;

    if (tnum == 0) {
        ctrl = t->rw_tmr0_ctrl;
        div = t->rw_tmr0_div;
        timer = t->ptimer_t0;
    } else {
        ctrl = t->rw_tmr1_ctrl;
        div = t->rw_tmr1_div;
        timer = t->ptimer_t1;
    }


    op = ctrl & 3;
    freq = ctrl >> 2;
    freq_hz = 32000000;

    switch (freq)
    {
    case 0:
    case 1:
        D(printf ("extern or disabled timer clock?\n"));
        break;
    case 4: freq_hz =  29493000; break;
    case 5: freq_hz =  32000000; break;
    case 6: freq_hz =  32768000; break;
    case 7: freq_hz = 100000000; break;
    default:
        abort();
        break;
    }

    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
    ptimer_set_freq(timer, freq_hz);
    ptimer_set_limit(timer, div, 0);

    switch (op)
    {
        case 0:
            /* Load.  */
            ptimer_set_limit(timer, div, 1);
            break;
        case 1:
            /* Hold.  */
            ptimer_stop(timer);
            break;
        case 2:
            /* Run.  */
            ptimer_run(timer, 0);
            break;
        default:
            abort();
            break;
    }
}

static void timer_update_irq(ETRAXTimerState *t)
{
    t->r_intr &= ~(t->rw_ack_intr);
    t->r_masked_intr = t->r_intr & t->rw_intr_mask;

    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
    qemu_set_irq(t->irq, !!t->r_masked_intr);
}

static void timer0_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    t->r_intr |= 1;
    timer_update_irq(t);
}

static void timer1_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    t->r_intr |= 2;
    timer_update_irq(t);
}

static void watchdog_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    if (t->wd_hits == 0) {
        /* real hw gives a single tick before reseting but we are
           a bit friendlier to compensate for our slower execution.  */
        ptimer_set_count(t->ptimer_wd, 10);
        ptimer_run(t->ptimer_wd, 1);
        qemu_irq_raise(t->nmi);
    }
    else
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

    t->wd_hits++;
}

static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
{
    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
    unsigned int wd_key = t->rw_wd_ctrl >> 9;
    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
    unsigned int new_cmd = (value >> 8) & 1;

    /* If the watchdog is enabled, they written key must match the
       complement of the previous.  */
    wd_key = ~wd_key & ((1 << 7) - 1);

    if (wd_en && wd_key != new_key)
        return;

    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
         wd_en, new_key, wd_key, new_cmd, wd_cnt));

    if (t->wd_hits)
        qemu_irq_lower(t->nmi);

    t->wd_hits = 0;

    ptimer_set_freq(t->ptimer_wd, 760);
    if (wd_cnt == 0)
        wd_cnt = 256;
    ptimer_set_count(t->ptimer_wd, wd_cnt);
    if (new_cmd)
        ptimer_run(t->ptimer_wd, 1);
    else
        ptimer_stop(t->ptimer_wd);

    t->rw_wd_ctrl = value;
}

static void
timer_write(void *opaque, hwaddr addr,
            uint64_t val64, unsigned int size)
{
    ETRAXTimerState *t = opaque;
    uint32_t value = val64;

    switch (addr)
    {
        case RW_TMR0_DIV:
            t->rw_tmr0_div = value;
            break;
        case RW_TMR0_CTRL:
            D(printf ("RW_TMR0_CTRL=%x\n", value));
            t->rw_tmr0_ctrl = value;
            update_ctrl(t, 0);
            break;
        case RW_TMR1_DIV:
            t->rw_tmr1_div = value;
            break;
        case RW_TMR1_CTRL:
            D(printf ("RW_TMR1_CTRL=%x\n", value));
            t->rw_tmr1_ctrl = value;
            update_ctrl(t, 1);
            break;
        case RW_INTR_MASK:
            D(printf ("RW_INTR_MASK=%x\n", value));
            t->rw_intr_mask = value;
            timer_update_irq(t);
            break;
        case RW_WD_CTRL:
            timer_watchdog_update(t, value);
            break;
        case RW_ACK_INTR:
            t->rw_ack_intr = value;
            timer_update_irq(t);
            t->rw_ack_intr = 0;
            break;
        default:
            printf ("%s " TARGET_FMT_plx " %x\n",
                __func__, addr, value);
            break;
    }
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static void etraxfs_timer_reset(void *opaque)
{
    ETRAXTimerState *t = opaque;

    ptimer_stop(t->ptimer_t0);
    ptimer_stop(t->ptimer_t1);
    ptimer_stop(t->ptimer_wd);
    t->rw_wd_ctrl = 0;
    t->r_intr = 0;
    t->rw_intr_mask = 0;
    qemu_irq_lower(t->irq);
}

static int etraxfs_timer_init(SysBusDevice *dev)
{
    ETRAXTimerState *t = ETRAX_TIMER(dev);

    t->bh_t0 = qemu_bh_new(timer0_hit, t);
    t->bh_t1 = qemu_bh_new(timer1_hit, t);
    t->bh_wd = qemu_bh_new(watchdog_hit, t);
    t->ptimer_t0 = ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT);
    t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT);
    t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT);

    sysbus_init_irq(dev, &t->irq);
    sysbus_init_irq(dev, &t->nmi);

    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
                          "etraxfs-timer", 0x5c);
    sysbus_init_mmio(dev, &t->mmio);
    qemu_register_reset(etraxfs_timer_reset, t);
    return 0;
}

static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

    sdc->init = etraxfs_timer_init;
}

static const TypeInfo etraxfs_timer_info = {
    .name          = TYPE_ETRAX_FS_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ETRAXTimerState),
    .class_init    = etraxfs_timer_class_init,
};

static void etraxfs_timer_register_types(void)
{
    type_register_static(&etraxfs_timer_info);
}

type_init(etraxfs_timer_register_types)
Commit	Line	Data
83fa1010	1	/*
e62b5b13	2	* QEMU ETRAX Timers
83fa1010 TS	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
282bc81e	24	#include "qemu/osdep.h"
83c9f4ca	25	#include "hw/sysbus.h"
9c17d615	26	#include "sysemu/sysemu.h"
1de7afc9	27	#include "qemu/timer.h"
83c9f4ca	28	#include "hw/ptimer.h"
83fa1010	29
bbaf29c7 EI	30	#define D(x)
bbaf29c7 EI	31
ca87d03b EI	32	#define RW_TMR0_DIV 0x00
	33	#define R_TMR0_DATA 0x04
	34	#define RW_TMR0_CTRL 0x08
	35	#define RW_TMR1_DIV 0x10
	36	#define R_TMR1_DATA 0x14
	37	#define RW_TMR1_CTRL 0x18
	38	#define R_TIME 0x38
	39	#define RW_WD_CTRL 0x40
5439779e	40	#define R_WD_STAT 0x44
ca87d03b EI	41	#define RW_INTR_MASK 0x48
	42	#define RW_ACK_INTR 0x4c
	43	#define R_INTR 0x50
	44	#define R_MASKED_INTR 0x54
83fa1010	45
5880ce52 AF	46	#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
	47	#define ETRAX_TIMER(obj) \
	48	OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
	49
3c9a8a8c	50	typedef struct ETRAXTimerState {
5880ce52 AF	51	SysBusDevice parent_obj;
5880ce52 AF	52
b8e5da2c	53	MemoryRegion mmio;
3b1fd90e EI	54	qemu_irq irq;
3b1fd90e EI	55	qemu_irq nmi;
84ceea57 EI	56
	57	QEMUBH *bh_t0;
	58	QEMUBH *bh_t1;
	59	QEMUBH *bh_wd;
	60	ptimer_state *ptimer_t0;
	61	ptimer_state *ptimer_t1;
	62	ptimer_state *ptimer_wd;
84ceea57 EI	63
	64	int wd_hits;
	65
	66	/* Control registers. */
	67	uint32_t rw_tmr0_div;
	68	uint32_t r_tmr0_data;
	69	uint32_t rw_tmr0_ctrl;
	70
	71	uint32_t rw_tmr1_div;
	72	uint32_t r_tmr1_data;
	73	uint32_t rw_tmr1_ctrl;
	74
	75	uint32_t rw_wd_ctrl;
	76
	77	uint32_t rw_intr_mask;
	78	uint32_t rw_ack_intr;
	79	uint32_t r_intr;
	80	uint32_t r_masked_intr;
3c9a8a8c	81	} ETRAXTimerState;
83fa1010	82
b8e5da2c	83	static uint64_t
a8170e5e	84	timer_read(void *opaque, hwaddr addr, unsigned int size)
83fa1010	85	{
3c9a8a8c	86	ETRAXTimerState *t = opaque;
84ceea57 EI	87	uint32_t r = 0;
	88
	89	switch (addr) {
	90	case R_TMR0_DATA:
	91	r = ptimer_get_count(t->ptimer_t0);
	92	break;
	93	case R_TMR1_DATA:
	94	r = ptimer_get_count(t->ptimer_t1);
	95	break;
	96	case R_TIME:
bc72ad67	97	r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
84ceea57 EI	98	break;
	99	case RW_INTR_MASK:
	100	r = t->rw_intr_mask;
	101	break;
	102	case R_MASKED_INTR:
	103	r = t->r_intr & t->rw_intr_mask;
	104	break;
	105	default:
	106	D(printf ("%s %x\n", __func__, addr));
	107	break;
	108	}
	109	return r;
83fa1010 TS	110	}
83fa1010 TS	111
3c9a8a8c	112	static void update_ctrl(ETRAXTimerState *t, int tnum)
83fa1010	113	{
84ceea57 EI	114	unsigned int op;
	115	unsigned int freq;
	116	unsigned int freq_hz;
	117	unsigned int div;
	118	uint32_t ctrl;
	119
	120	ptimer_state *timer;
	121
	122	if (tnum == 0) {
	123	ctrl = t->rw_tmr0_ctrl;
	124	div = t->rw_tmr0_div;
	125	timer = t->ptimer_t0;
	126	} else {
	127	ctrl = t->rw_tmr1_ctrl;
	128	div = t->rw_tmr1_div;
	129	timer = t->ptimer_t1;
	130	}
	131
	132
	133	op = ctrl & 3;
	134	freq = ctrl >> 2;
	135	freq_hz = 32000000;
	136
	137	switch (freq)
	138	{
	139	case 0:
	140	case 1:
	141	D(printf ("extern or disabled timer clock?\n"));
	142	break;
	143	case 4: freq_hz = 29493000; break;
	144	case 5: freq_hz = 32000000; break;
	145	case 6: freq_hz = 32768000; break;
	146	case 7: freq_hz = 100000000; break;
	147	default:
	148	abort();
	149	break;
	150	}
	151
	152	D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
84ceea57 EI	153	ptimer_set_freq(timer, freq_hz);
	154	ptimer_set_limit(timer, div, 0);
	155
	156	switch (op)
	157	{
	158	case 0:
	159	/* Load. */
	160	ptimer_set_limit(timer, div, 1);
	161	break;
	162	case 1:
	163	/* Hold. */
	164	ptimer_stop(timer);
	165	break;
	166	case 2:
	167	/* Run. */
	168	ptimer_run(timer, 0);
	169	break;
	170	default:
	171	abort();
	172	break;
	173	}
83fa1010 TS	174	}
83fa1010 TS	175
3c9a8a8c	176	static void timer_update_irq(ETRAXTimerState *t)
83fa1010	177	{
84ceea57 EI	178	t->r_intr &= ~(t->rw_ack_intr);
84ceea57 EI	179	t->r_masked_intr = t->r_intr & t->rw_intr_mask;
60237223	180
84ceea57	181	D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
3b1fd90e	182	qemu_set_irq(t->irq, !!t->r_masked_intr);
83fa1010 TS	183	}
83fa1010 TS	184
5439779e	185	static void timer0_hit(void *opaque)
60237223	186	{
3c9a8a8c	187	ETRAXTimerState *t = opaque;
84ceea57 EI	188	t->r_intr \|= 1;
84ceea57 EI	189	timer_update_irq(t);
60237223 EI	190	}
60237223 EI	191
5439779e EI	192	static void timer1_hit(void *opaque)
5439779e EI	193	{
3c9a8a8c	194	ETRAXTimerState *t = opaque;
84ceea57 EI	195	t->r_intr \|= 2;
84ceea57 EI	196	timer_update_irq(t);
5439779e EI	197	}
	198
	199	static void watchdog_hit(void *opaque)
	200	{
3c9a8a8c	201	ETRAXTimerState *t = opaque;
84ceea57 EI	202	if (t->wd_hits == 0) {
	203	/* real hw gives a single tick before reseting but we are
	204	a bit friendlier to compensate for our slower execution. */
	205	ptimer_set_count(t->ptimer_wd, 10);
	206	ptimer_run(t->ptimer_wd, 1);
3b1fd90e	207	qemu_irq_raise(t->nmi);
84ceea57 EI	208	}
84ceea57 EI	209	else
cf83f140	210	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
84ceea57 EI	211
84ceea57 EI	212	t->wd_hits++;
5439779e EI	213	}
5439779e EI	214
3c9a8a8c	215	static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
5439779e	216	{
84ceea57 EI	217	unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
	218	unsigned int wd_key = t->rw_wd_ctrl >> 9;
	219	unsigned int wd_cnt = t->rw_wd_ctrl & 511;
	220	unsigned int new_key = value >> 9 & ((1 << 7) - 1);
	221	unsigned int new_cmd = (value >> 8) & 1;
5439779e	222
84ceea57 EI	223	/* If the watchdog is enabled, they written key must match the
	224	complement of the previous. */
	225	wd_key = ~wd_key & ((1 << 7) - 1);
5439779e	226
84ceea57 EI	227	if (wd_en && wd_key != new_key)
84ceea57 EI	228	return;
5439779e	229
84ceea57 EI	230	D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
84ceea57 EI	231	wd_en, new_key, wd_key, new_cmd, wd_cnt));
5439779e	232
84ceea57	233	if (t->wd_hits)
3b1fd90e	234	qemu_irq_lower(t->nmi);
5ef98b47	235
84ceea57	236	t->wd_hits = 0;
5ef98b47	237
84ceea57 EI	238	ptimer_set_freq(t->ptimer_wd, 760);
	239	if (wd_cnt == 0)
	240	wd_cnt = 256;
	241	ptimer_set_count(t->ptimer_wd, wd_cnt);
	242	if (new_cmd)
	243	ptimer_run(t->ptimer_wd, 1);
	244	else
	245	ptimer_stop(t->ptimer_wd);
5439779e	246
84ceea57	247	t->rw_wd_ctrl = value;
5439779e EI	248	}
5439779e EI	249
83fa1010	250	static void
a8170e5e	251	timer_write(void *opaque, hwaddr addr,
b8e5da2c	252	uint64_t val64, unsigned int size)
83fa1010	253	{
3c9a8a8c	254	ETRAXTimerState *t = opaque;
b8e5da2c	255	uint32_t value = val64;
84ceea57 EI	256
	257	switch (addr)
	258	{
	259	case RW_TMR0_DIV:
	260	t->rw_tmr0_div = value;
	261	break;
	262	case RW_TMR0_CTRL:
	263	D(printf ("RW_TMR0_CTRL=%x\n", value));
	264	t->rw_tmr0_ctrl = value;
	265	update_ctrl(t, 0);
	266	break;
	267	case RW_TMR1_DIV:
	268	t->rw_tmr1_div = value;
	269	break;
	270	case RW_TMR1_CTRL:
	271	D(printf ("RW_TMR1_CTRL=%x\n", value));
	272	t->rw_tmr1_ctrl = value;
	273	update_ctrl(t, 1);
	274	break;
	275	case RW_INTR_MASK:
	276	D(printf ("RW_INTR_MASK=%x\n", value));
	277	t->rw_intr_mask = value;
	278	timer_update_irq(t);
	279	break;
	280	case RW_WD_CTRL:
	281	timer_watchdog_update(t, value);
	282	break;
	283	case RW_ACK_INTR:
	284	t->rw_ack_intr = value;
	285	timer_update_irq(t);
	286	t->rw_ack_intr = 0;
	287	break;
	288	default:
	289	printf ("%s " TARGET_FMT_plx " %x\n",
	290	__func__, addr, value);
	291	break;
	292	}
83fa1010 TS	293	}
83fa1010 TS	294
b8e5da2c EI	295	static const MemoryRegionOps timer_ops = {
	296	.read = timer_read,
	297	.write = timer_write,
	298	.endianness = DEVICE_LITTLE_ENDIAN,
	299	.valid = {
	300	.min_access_size = 4,
	301	.max_access_size = 4
	302	}
83fa1010 TS	303	};
83fa1010 TS	304
5439779e EI	305	static void etraxfs_timer_reset(void *opaque)
5439779e EI	306	{
3c9a8a8c	307	ETRAXTimerState *t = opaque;
84ceea57 EI	308
	309	ptimer_stop(t->ptimer_t0);
	310	ptimer_stop(t->ptimer_t1);
	311	ptimer_stop(t->ptimer_wd);
	312	t->rw_wd_ctrl = 0;
	313	t->r_intr = 0;
	314	t->rw_intr_mask = 0;
3b1fd90e	315	qemu_irq_lower(t->irq);
5439779e EI	316	}
5439779e EI	317
81a322d4	318	static int etraxfs_timer_init(SysBusDevice *dev)
83fa1010	319	{
5880ce52	320	ETRAXTimerState *t = ETRAX_TIMER(dev);
83fa1010	321
84ceea57 EI	322	t->bh_t0 = qemu_bh_new(timer0_hit, t);
	323	t->bh_t1 = qemu_bh_new(timer1_hit, t);
	324	t->bh_wd = qemu_bh_new(watchdog_hit, t);
e7ea81c3 DO	325	t->ptimer_t0 = ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT);
	326	t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT);
	327	t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT);
3b1fd90e EI	328
	329	sysbus_init_irq(dev, &t->irq);
	330	sysbus_init_irq(dev, &t->nmi);
83fa1010	331
853dca12 PB	332	memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
853dca12 PB	333	"etraxfs-timer", 0x5c);
750ecd44	334	sysbus_init_mmio(dev, &t->mmio);
a08d4367	335	qemu_register_reset(etraxfs_timer_reset, t);
81a322d4	336	return 0;
83fa1010	337	}
3b1fd90e	338
999e12bb AL	339	static void etraxfs_timer_class_init(ObjectClass klass, void data)
	340	{
	341	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	342
	343	sdc->init = etraxfs_timer_init;
	344	}
	345
8c43a6f0	346	static const TypeInfo etraxfs_timer_info = {
5880ce52	347	.name = TYPE_ETRAX_FS_TIMER,
39bffca2	348	.parent = TYPE_SYS_BUS_DEVICE,
3c9a8a8c	349	.instance_size = sizeof(ETRAXTimerState),
39bffca2	350	.class_init = etraxfs_timer_class_init,
999e12bb AL	351	};
999e12bb AL	352
83f7d43a	353	static void etraxfs_timer_register_types(void)
3b1fd90e	354	{
39bffca2	355	type_register_static(&etraxfs_timer_info);
3b1fd90e EI	356	}
3b1fd90e EI	357
83f7d43a	358	type_init(etraxfs_timer_register_types)