[qemu.git] / hw / timer / etraxfs_timer.c

/*
 * QEMU ETRAX Timers
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"

#define D(x)

#define RW_TMR0_DIV   0x00
#define R_TMR0_DATA   0x04
#define RW_TMR0_CTRL  0x08
#define RW_TMR1_DIV   0x10
#define R_TMR1_DATA   0x14
#define RW_TMR1_CTRL  0x18
#define R_TIME        0x38
#define RW_WD_CTRL    0x40
#define R_WD_STAT     0x44
#define RW_INTR_MASK  0x48
#define RW_ACK_INTR   0x4c
#define R_INTR        0x50
#define R_MASKED_INTR 0x54

#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
#define ETRAX_TIMER(obj) \
    OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)

typedef struct ETRAXTimerState {
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    qemu_irq irq;
    qemu_irq nmi;

    QEMUBH *bh_t0;
    QEMUBH *bh_t1;
    QEMUBH *bh_wd;
    ptimer_state *ptimer_t0;
    ptimer_state *ptimer_t1;
    ptimer_state *ptimer_wd;

    int wd_hits;

    /* Control registers.  */
    uint32_t rw_tmr0_div;
    uint32_t r_tmr0_data;
    uint32_t rw_tmr0_ctrl;

    uint32_t rw_tmr1_div;
    uint32_t r_tmr1_data;
    uint32_t rw_tmr1_ctrl;

    uint32_t rw_wd_ctrl;

    uint32_t rw_intr_mask;
    uint32_t rw_ack_intr;
    uint32_t r_intr;
    uint32_t r_masked_intr;
} ETRAXTimerState;

static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
    ETRAXTimerState *t = opaque;
    uint32_t r = 0;

    switch (addr) {
    case R_TMR0_DATA:
        r = ptimer_get_count(t->ptimer_t0);
        break;
    case R_TMR1_DATA:
        r = ptimer_get_count(t->ptimer_t1);
        break;
    case R_TIME:
        r = qemu_get_clock_ns(vm_clock) / 10;
        break;
    case RW_INTR_MASK:
        r = t->rw_intr_mask;
        break;
    case R_MASKED_INTR:
        r = t->r_intr & t->rw_intr_mask;
        break;
    default:
        D(printf ("%s %x\n", __func__, addr));
        break;
    }
    return r;
}

static void update_ctrl(ETRAXTimerState *t, int tnum)
{
    unsigned int op;
    unsigned int freq;
    unsigned int freq_hz;
    unsigned int div;
    uint32_t ctrl;

    ptimer_state *timer;

    if (tnum == 0) {
        ctrl = t->rw_tmr0_ctrl;
        div = t->rw_tmr0_div;
        timer = t->ptimer_t0;
    } else {
        ctrl = t->rw_tmr1_ctrl;
        div = t->rw_tmr1_div;
        timer = t->ptimer_t1;
    }


    op = ctrl & 3;
    freq = ctrl >> 2;
    freq_hz = 32000000;

    switch (freq)
    {
    case 0:
    case 1:
        D(printf ("extern or disabled timer clock?\n"));
        break;
    case 4: freq_hz =  29493000; break;
    case 5: freq_hz =  32000000; break;
    case 6: freq_hz =  32768000; break;
    case 7: freq_hz = 100000000; break;
    default:
        abort();
        break;
    }

    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
    ptimer_set_freq(timer, freq_hz);
    ptimer_set_limit(timer, div, 0);

    switch (op)
    {
        case 0:
            /* Load.  */
            ptimer_set_limit(timer, div, 1);
            break;
        case 1:
            /* Hold.  */
            ptimer_stop(timer);
            break;
        case 2:
            /* Run.  */
            ptimer_run(timer, 0);
            break;
        default:
            abort();
            break;
    }
}

static void timer_update_irq(ETRAXTimerState *t)
{
    t->r_intr &= ~(t->rw_ack_intr);
    t->r_masked_intr = t->r_intr & t->rw_intr_mask;

    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
    qemu_set_irq(t->irq, !!t->r_masked_intr);
}

static void timer0_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    t->r_intr |= 1;
    timer_update_irq(t);
}

static void timer1_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    t->r_intr |= 2;
    timer_update_irq(t);
}

static void watchdog_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    if (t->wd_hits == 0) {
        /* real hw gives a single tick before reseting but we are
           a bit friendlier to compensate for our slower execution.  */
        ptimer_set_count(t->ptimer_wd, 10);
        ptimer_run(t->ptimer_wd, 1);
        qemu_irq_raise(t->nmi);
    }
    else
        qemu_system_reset_request();

    t->wd_hits++;
}

static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
{
    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
    unsigned int wd_key = t->rw_wd_ctrl >> 9;
    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
    unsigned int new_cmd = (value >> 8) & 1;

    /* If the watchdog is enabled, they written key must match the
       complement of the previous.  */
    wd_key = ~wd_key & ((1 << 7) - 1);

    if (wd_en && wd_key != new_key)
        return;

    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
         wd_en, new_key, wd_key, new_cmd, wd_cnt));

    if (t->wd_hits)
        qemu_irq_lower(t->nmi);

    t->wd_hits = 0;

    ptimer_set_freq(t->ptimer_wd, 760);
    if (wd_cnt == 0)
        wd_cnt = 256;
    ptimer_set_count(t->ptimer_wd, wd_cnt);
    if (new_cmd)
        ptimer_run(t->ptimer_wd, 1);
    else
        ptimer_stop(t->ptimer_wd);

    t->rw_wd_ctrl = value;
}

static void
timer_write(void *opaque, hwaddr addr,
            uint64_t val64, unsigned int size)
{
    ETRAXTimerState *t = opaque;
    uint32_t value = val64;

    switch (addr)
    {
        case RW_TMR0_DIV:
            t->rw_tmr0_div = value;
            break;
        case RW_TMR0_CTRL:
            D(printf ("RW_TMR0_CTRL=%x\n", value));
            t->rw_tmr0_ctrl = value;
            update_ctrl(t, 0);
            break;
        case RW_TMR1_DIV:
            t->rw_tmr1_div = value;
            break;
        case RW_TMR1_CTRL:
            D(printf ("RW_TMR1_CTRL=%x\n", value));
            t->rw_tmr1_ctrl = value;
            update_ctrl(t, 1);
            break;
        case RW_INTR_MASK:
            D(printf ("RW_INTR_MASK=%x\n", value));
            t->rw_intr_mask = value;
            timer_update_irq(t);
            break;
        case RW_WD_CTRL:
            timer_watchdog_update(t, value);
            break;
        case RW_ACK_INTR:
            t->rw_ack_intr = value;
            timer_update_irq(t);
            t->rw_ack_intr = 0;
            break;
        default:
            printf ("%s " TARGET_FMT_plx " %x\n",
                __func__, addr, value);
            break;
    }
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static void etraxfs_timer_reset(void *opaque)
{
    ETRAXTimerState *t = opaque;

    ptimer_stop(t->ptimer_t0);
    ptimer_stop(t->ptimer_t1);
    ptimer_stop(t->ptimer_wd);
    t->rw_wd_ctrl = 0;
    t->r_intr = 0;
    t->rw_intr_mask = 0;
    qemu_irq_lower(t->irq);
}

static int etraxfs_timer_init(SysBusDevice *dev)
{
    ETRAXTimerState *t = ETRAX_TIMER(dev);

    t->bh_t0 = qemu_bh_new(timer0_hit, t);
    t->bh_t1 = qemu_bh_new(timer1_hit, t);
    t->bh_wd = qemu_bh_new(watchdog_hit, t);
    t->ptimer_t0 = ptimer_init(t->bh_t0);
    t->ptimer_t1 = ptimer_init(t->bh_t1);
    t->ptimer_wd = ptimer_init(t->bh_wd);

    sysbus_init_irq(dev, &t->irq);
    sysbus_init_irq(dev, &t->nmi);

    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
                          "etraxfs-timer", 0x5c);
    sysbus_init_mmio(dev, &t->mmio);
    qemu_register_reset(etraxfs_timer_reset, t);
    return 0;
}

static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

    sdc->init = etraxfs_timer_init;
}

static const TypeInfo etraxfs_timer_info = {
    .name          = TYPE_ETRAX_FS_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ETRAXTimerState),
    .class_init    = etraxfs_timer_class_init,
};

static void etraxfs_timer_register_types(void)
{
    type_register_static(&etraxfs_timer_info);
}

type_init(etraxfs_timer_register_types)
Commit	Line	Data
83fa1010	1	/*
e62b5b13	2	* QEMU ETRAX Timers
83fa1010 TS	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
83c9f4ca	24	#include "hw/sysbus.h"
9c17d615	25	#include "sysemu/sysemu.h"
1de7afc9	26	#include "qemu/timer.h"
83c9f4ca	27	#include "hw/ptimer.h"
83fa1010	28
bbaf29c7 EI	29	#define D(x)
bbaf29c7 EI	30
ca87d03b EI	31	#define RW_TMR0_DIV 0x00
	32	#define R_TMR0_DATA 0x04
	33	#define RW_TMR0_CTRL 0x08
	34	#define RW_TMR1_DIV 0x10
	35	#define R_TMR1_DATA 0x14
	36	#define RW_TMR1_CTRL 0x18
	37	#define R_TIME 0x38
	38	#define RW_WD_CTRL 0x40
5439779e	39	#define R_WD_STAT 0x44
ca87d03b EI	40	#define RW_INTR_MASK 0x48
	41	#define RW_ACK_INTR 0x4c
	42	#define R_INTR 0x50
	43	#define R_MASKED_INTR 0x54
83fa1010	44
5880ce52 AF	45	#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
	46	#define ETRAX_TIMER(obj) \
	47	OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
	48
3c9a8a8c	49	typedef struct ETRAXTimerState {
5880ce52 AF	50	SysBusDevice parent_obj;
5880ce52 AF	51
b8e5da2c	52	MemoryRegion mmio;
3b1fd90e EI	53	qemu_irq irq;
3b1fd90e EI	54	qemu_irq nmi;
84ceea57 EI	55
	56	QEMUBH *bh_t0;
	57	QEMUBH *bh_t1;
	58	QEMUBH *bh_wd;
	59	ptimer_state *ptimer_t0;
	60	ptimer_state *ptimer_t1;
	61	ptimer_state *ptimer_wd;
84ceea57 EI	62
	63	int wd_hits;
	64
	65	/* Control registers. */
	66	uint32_t rw_tmr0_div;
	67	uint32_t r_tmr0_data;
	68	uint32_t rw_tmr0_ctrl;
	69
	70	uint32_t rw_tmr1_div;
	71	uint32_t r_tmr1_data;
	72	uint32_t rw_tmr1_ctrl;
	73
	74	uint32_t rw_wd_ctrl;
	75
	76	uint32_t rw_intr_mask;
	77	uint32_t rw_ack_intr;
	78	uint32_t r_intr;
	79	uint32_t r_masked_intr;
3c9a8a8c	80	} ETRAXTimerState;
83fa1010	81
b8e5da2c	82	static uint64_t
a8170e5e	83	timer_read(void *opaque, hwaddr addr, unsigned int size)
83fa1010	84	{
3c9a8a8c	85	ETRAXTimerState *t = opaque;
84ceea57 EI	86	uint32_t r = 0;
	87
	88	switch (addr) {
	89	case R_TMR0_DATA:
	90	r = ptimer_get_count(t->ptimer_t0);
	91	break;
	92	case R_TMR1_DATA:
	93	r = ptimer_get_count(t->ptimer_t1);
	94	break;
	95	case R_TIME:
74475455	96	r = qemu_get_clock_ns(vm_clock) / 10;
84ceea57 EI	97	break;
	98	case RW_INTR_MASK:
	99	r = t->rw_intr_mask;
	100	break;
	101	case R_MASKED_INTR:
	102	r = t->r_intr & t->rw_intr_mask;
	103	break;
	104	default:
	105	D(printf ("%s %x\n", __func__, addr));
	106	break;
	107	}
	108	return r;
83fa1010 TS	109	}
83fa1010 TS	110
3c9a8a8c	111	static void update_ctrl(ETRAXTimerState *t, int tnum)
83fa1010	112	{
84ceea57 EI	113	unsigned int op;
	114	unsigned int freq;
	115	unsigned int freq_hz;
	116	unsigned int div;
	117	uint32_t ctrl;
	118
	119	ptimer_state *timer;
	120
	121	if (tnum == 0) {
	122	ctrl = t->rw_tmr0_ctrl;
	123	div = t->rw_tmr0_div;
	124	timer = t->ptimer_t0;
	125	} else {
	126	ctrl = t->rw_tmr1_ctrl;
	127	div = t->rw_tmr1_div;
	128	timer = t->ptimer_t1;
	129	}
	130
	131
	132	op = ctrl & 3;
	133	freq = ctrl >> 2;
	134	freq_hz = 32000000;
	135
	136	switch (freq)
	137	{
	138	case 0:
	139	case 1:
	140	D(printf ("extern or disabled timer clock?\n"));
	141	break;
	142	case 4: freq_hz = 29493000; break;
	143	case 5: freq_hz = 32000000; break;
	144	case 6: freq_hz = 32768000; break;
	145	case 7: freq_hz = 100000000; break;
	146	default:
	147	abort();
	148	break;
	149	}
	150
	151	D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
84ceea57 EI	152	ptimer_set_freq(timer, freq_hz);
	153	ptimer_set_limit(timer, div, 0);
	154
	155	switch (op)
	156	{
	157	case 0:
	158	/* Load. */
	159	ptimer_set_limit(timer, div, 1);
	160	break;
	161	case 1:
	162	/* Hold. */
	163	ptimer_stop(timer);
	164	break;
	165	case 2:
	166	/* Run. */
	167	ptimer_run(timer, 0);
	168	break;
	169	default:
	170	abort();
	171	break;
	172	}
83fa1010 TS	173	}
83fa1010 TS	174
3c9a8a8c	175	static void timer_update_irq(ETRAXTimerState *t)
83fa1010	176	{
84ceea57 EI	177	t->r_intr &= ~(t->rw_ack_intr);
84ceea57 EI	178	t->r_masked_intr = t->r_intr & t->rw_intr_mask;
60237223	179
84ceea57	180	D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
3b1fd90e	181	qemu_set_irq(t->irq, !!t->r_masked_intr);
83fa1010 TS	182	}
83fa1010 TS	183
5439779e	184	static void timer0_hit(void *opaque)
60237223	185	{
3c9a8a8c	186	ETRAXTimerState *t = opaque;
84ceea57 EI	187	t->r_intr \|= 1;
84ceea57 EI	188	timer_update_irq(t);
60237223 EI	189	}
60237223 EI	190
5439779e EI	191	static void timer1_hit(void *opaque)
5439779e EI	192	{
3c9a8a8c	193	ETRAXTimerState *t = opaque;
84ceea57 EI	194	t->r_intr \|= 2;
84ceea57 EI	195	timer_update_irq(t);
5439779e EI	196	}
	197
	198	static void watchdog_hit(void *opaque)
	199	{
3c9a8a8c	200	ETRAXTimerState *t = opaque;
84ceea57 EI	201	if (t->wd_hits == 0) {
	202	/* real hw gives a single tick before reseting but we are
	203	a bit friendlier to compensate for our slower execution. */
	204	ptimer_set_count(t->ptimer_wd, 10);
	205	ptimer_run(t->ptimer_wd, 1);
3b1fd90e	206	qemu_irq_raise(t->nmi);
84ceea57 EI	207	}
	208	else
	209	qemu_system_reset_request();
	210
	211	t->wd_hits++;
5439779e EI	212	}
5439779e EI	213
3c9a8a8c	214	static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
5439779e	215	{
84ceea57 EI	216	unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
	217	unsigned int wd_key = t->rw_wd_ctrl >> 9;
	218	unsigned int wd_cnt = t->rw_wd_ctrl & 511;
	219	unsigned int new_key = value >> 9 & ((1 << 7) - 1);
	220	unsigned int new_cmd = (value >> 8) & 1;
5439779e	221
84ceea57 EI	222	/* If the watchdog is enabled, they written key must match the
	223	complement of the previous. */
	224	wd_key = ~wd_key & ((1 << 7) - 1);
5439779e	225
84ceea57 EI	226	if (wd_en && wd_key != new_key)
84ceea57 EI	227	return;
5439779e	228
84ceea57 EI	229	D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
84ceea57 EI	230	wd_en, new_key, wd_key, new_cmd, wd_cnt));
5439779e	231
84ceea57	232	if (t->wd_hits)
3b1fd90e	233	qemu_irq_lower(t->nmi);
5ef98b47	234
84ceea57	235	t->wd_hits = 0;
5ef98b47	236
84ceea57 EI	237	ptimer_set_freq(t->ptimer_wd, 760);
	238	if (wd_cnt == 0)
	239	wd_cnt = 256;
	240	ptimer_set_count(t->ptimer_wd, wd_cnt);
	241	if (new_cmd)
	242	ptimer_run(t->ptimer_wd, 1);
	243	else
	244	ptimer_stop(t->ptimer_wd);
5439779e	245
84ceea57	246	t->rw_wd_ctrl = value;
5439779e EI	247	}
5439779e EI	248
83fa1010	249	static void
a8170e5e	250	timer_write(void *opaque, hwaddr addr,
b8e5da2c	251	uint64_t val64, unsigned int size)
83fa1010	252	{
3c9a8a8c	253	ETRAXTimerState *t = opaque;
b8e5da2c	254	uint32_t value = val64;
84ceea57 EI	255
	256	switch (addr)
	257	{
	258	case RW_TMR0_DIV:
	259	t->rw_tmr0_div = value;
	260	break;
	261	case RW_TMR0_CTRL:
	262	D(printf ("RW_TMR0_CTRL=%x\n", value));
	263	t->rw_tmr0_ctrl = value;
	264	update_ctrl(t, 0);
	265	break;
	266	case RW_TMR1_DIV:
	267	t->rw_tmr1_div = value;
	268	break;
	269	case RW_TMR1_CTRL:
	270	D(printf ("RW_TMR1_CTRL=%x\n", value));
	271	t->rw_tmr1_ctrl = value;
	272	update_ctrl(t, 1);
	273	break;
	274	case RW_INTR_MASK:
	275	D(printf ("RW_INTR_MASK=%x\n", value));
	276	t->rw_intr_mask = value;
	277	timer_update_irq(t);
	278	break;
	279	case RW_WD_CTRL:
	280	timer_watchdog_update(t, value);
	281	break;
	282	case RW_ACK_INTR:
	283	t->rw_ack_intr = value;
	284	timer_update_irq(t);
	285	t->rw_ack_intr = 0;
	286	break;
	287	default:
	288	printf ("%s " TARGET_FMT_plx " %x\n",
	289	__func__, addr, value);
	290	break;
	291	}
83fa1010 TS	292	}
83fa1010 TS	293
b8e5da2c EI	294	static const MemoryRegionOps timer_ops = {
	295	.read = timer_read,
	296	.write = timer_write,
	297	.endianness = DEVICE_LITTLE_ENDIAN,
	298	.valid = {
	299	.min_access_size = 4,
	300	.max_access_size = 4
	301	}
83fa1010 TS	302	};
83fa1010 TS	303
5439779e EI	304	static void etraxfs_timer_reset(void *opaque)
5439779e EI	305	{
3c9a8a8c	306	ETRAXTimerState *t = opaque;
84ceea57 EI	307
	308	ptimer_stop(t->ptimer_t0);
	309	ptimer_stop(t->ptimer_t1);
	310	ptimer_stop(t->ptimer_wd);
	311	t->rw_wd_ctrl = 0;
	312	t->r_intr = 0;
	313	t->rw_intr_mask = 0;
3b1fd90e	314	qemu_irq_lower(t->irq);
5439779e EI	315	}
5439779e EI	316
81a322d4	317	static int etraxfs_timer_init(SysBusDevice *dev)
83fa1010	318	{
5880ce52	319	ETRAXTimerState *t = ETRAX_TIMER(dev);
83fa1010	320
84ceea57 EI	321	t->bh_t0 = qemu_bh_new(timer0_hit, t);
	322	t->bh_t1 = qemu_bh_new(timer1_hit, t);
	323	t->bh_wd = qemu_bh_new(watchdog_hit, t);
	324	t->ptimer_t0 = ptimer_init(t->bh_t0);
	325	t->ptimer_t1 = ptimer_init(t->bh_t1);
	326	t->ptimer_wd = ptimer_init(t->bh_wd);
3b1fd90e EI	327
	328	sysbus_init_irq(dev, &t->irq);
	329	sysbus_init_irq(dev, &t->nmi);
83fa1010	330
853dca12 PB	331	memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
853dca12 PB	332	"etraxfs-timer", 0x5c);
750ecd44	333	sysbus_init_mmio(dev, &t->mmio);
a08d4367	334	qemu_register_reset(etraxfs_timer_reset, t);
81a322d4	335	return 0;
83fa1010	336	}
3b1fd90e	337
999e12bb AL	338	static void etraxfs_timer_class_init(ObjectClass klass, void data)
	339	{
	340	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	341
	342	sdc->init = etraxfs_timer_init;
	343	}
	344
8c43a6f0	345	static const TypeInfo etraxfs_timer_info = {
5880ce52	346	.name = TYPE_ETRAX_FS_TIMER,
39bffca2	347	.parent = TYPE_SYS_BUS_DEVICE,
3c9a8a8c	348	.instance_size = sizeof(ETRAXTimerState),
39bffca2	349	.class_init = etraxfs_timer_class_init,
999e12bb AL	350	};
999e12bb AL	351
83f7d43a	352	static void etraxfs_timer_register_types(void)
3b1fd90e	353	{
39bffca2	354	type_register_static(&etraxfs_timer_info);
3b1fd90e EI	355	}
3b1fd90e EI	356
83f7d43a	357	type_init(etraxfs_timer_register_types)