[qemu.git] / hw / timer / etraxfs_timer.c

/*
 * QEMU ETRAX Timers
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"

#define D(x)

#define RW_TMR0_DIV   0x00
#define R_TMR0_DATA   0x04
#define RW_TMR0_CTRL  0x08
#define RW_TMR1_DIV   0x10
#define R_TMR1_DATA   0x14
#define RW_TMR1_CTRL  0x18
#define R_TIME        0x38
#define RW_WD_CTRL    0x40
#define R_WD_STAT     0x44
#define RW_INTR_MASK  0x48
#define RW_ACK_INTR   0x4c
#define R_INTR        0x50
#define R_MASKED_INTR 0x54

struct etrax_timer {
    SysBusDevice busdev;
    MemoryRegion mmio;
    qemu_irq irq;
    qemu_irq nmi;

    QEMUBH *bh_t0;
    QEMUBH *bh_t1;
    QEMUBH *bh_wd;
    ptimer_state *ptimer_t0;
    ptimer_state *ptimer_t1;
    ptimer_state *ptimer_wd;

    int wd_hits;

    /* Control registers.  */
    uint32_t rw_tmr0_div;
    uint32_t r_tmr0_data;
    uint32_t rw_tmr0_ctrl;

    uint32_t rw_tmr1_div;
    uint32_t r_tmr1_data;
    uint32_t rw_tmr1_ctrl;

    uint32_t rw_wd_ctrl;

    uint32_t rw_intr_mask;
    uint32_t rw_ack_intr;
    uint32_t r_intr;
    uint32_t r_masked_intr;
};

static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
    struct etrax_timer *t = opaque;
    uint32_t r = 0;

    switch (addr) {
    case R_TMR0_DATA:
        r = ptimer_get_count(t->ptimer_t0);
        break;
    case R_TMR1_DATA:
        r = ptimer_get_count(t->ptimer_t1);
        break;
    case R_TIME:
        r = qemu_get_clock_ns(vm_clock) / 10;
        break;
    case RW_INTR_MASK:
        r = t->rw_intr_mask;
        break;
    case R_MASKED_INTR:
        r = t->r_intr & t->rw_intr_mask;
        break;
    default:
        D(printf ("%s %x\n", __func__, addr));
        break;
    }
    return r;
}

static void update_ctrl(struct etrax_timer *t, int tnum)
{
    unsigned int op;
    unsigned int freq;
    unsigned int freq_hz;
    unsigned int div;
    uint32_t ctrl;

    ptimer_state *timer;

    if (tnum == 0) {
        ctrl = t->rw_tmr0_ctrl;
        div = t->rw_tmr0_div;
        timer = t->ptimer_t0;
    } else {
        ctrl = t->rw_tmr1_ctrl;
        div = t->rw_tmr1_div;
        timer = t->ptimer_t1;
    }


    op = ctrl & 3;
    freq = ctrl >> 2;
    freq_hz = 32000000;

    switch (freq)
    {
    case 0:
    case 1:
        D(printf ("extern or disabled timer clock?\n"));
        break;
    case 4: freq_hz =  29493000; break;
    case 5: freq_hz =  32000000; break;
    case 6: freq_hz =  32768000; break;
    case 7: freq_hz = 100000000; break;
    default:
        abort();
        break;
    }

    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
    ptimer_set_freq(timer, freq_hz);
    ptimer_set_limit(timer, div, 0);

    switch (op)
    {
        case 0:
            /* Load.  */
            ptimer_set_limit(timer, div, 1);
            break;
        case 1:
            /* Hold.  */
            ptimer_stop(timer);
            break;
        case 2:
            /* Run.  */
            ptimer_run(timer, 0);
            break;
        default:
            abort();
            break;
    }
}

static void timer_update_irq(struct etrax_timer *t)
{
    t->r_intr &= ~(t->rw_ack_intr);
    t->r_masked_intr = t->r_intr & t->rw_intr_mask;

    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
    qemu_set_irq(t->irq, !!t->r_masked_intr);
}

static void timer0_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    t->r_intr |= 1;
    timer_update_irq(t);
}

static void timer1_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    t->r_intr |= 2;
    timer_update_irq(t);
}

static void watchdog_hit(void *opaque)
{
    struct etrax_timer *t = opaque;
    if (t->wd_hits == 0) {
        /* real hw gives a single tick before reseting but we are
           a bit friendlier to compensate for our slower execution.  */
        ptimer_set_count(t->ptimer_wd, 10);
        ptimer_run(t->ptimer_wd, 1);
        qemu_irq_raise(t->nmi);
    }
    else
        qemu_system_reset_request();

    t->wd_hits++;
}

static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
{
    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
    unsigned int wd_key = t->rw_wd_ctrl >> 9;
    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
    unsigned int new_cmd = (value >> 8) & 1;

    /* If the watchdog is enabled, they written key must match the
       complement of the previous.  */
    wd_key = ~wd_key & ((1 << 7) - 1);

    if (wd_en && wd_key != new_key)
        return;

    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
         wd_en, new_key, wd_key, new_cmd, wd_cnt));

    if (t->wd_hits)
        qemu_irq_lower(t->nmi);

    t->wd_hits = 0;

    ptimer_set_freq(t->ptimer_wd, 760);
    if (wd_cnt == 0)
        wd_cnt = 256;
    ptimer_set_count(t->ptimer_wd, wd_cnt);
    if (new_cmd)
        ptimer_run(t->ptimer_wd, 1);
    else
        ptimer_stop(t->ptimer_wd);

    t->rw_wd_ctrl = value;
}

static void
timer_write(void *opaque, hwaddr addr,
            uint64_t val64, unsigned int size)
{
    struct etrax_timer *t = opaque;
    uint32_t value = val64;

    switch (addr)
    {
        case RW_TMR0_DIV:
            t->rw_tmr0_div = value;
            break;
        case RW_TMR0_CTRL:
            D(printf ("RW_TMR0_CTRL=%x\n", value));
            t->rw_tmr0_ctrl = value;
            update_ctrl(t, 0);
            break;
        case RW_TMR1_DIV:
            t->rw_tmr1_div = value;
            break;
        case RW_TMR1_CTRL:
            D(printf ("RW_TMR1_CTRL=%x\n", value));
            t->rw_tmr1_ctrl = value;
            update_ctrl(t, 1);
            break;
        case RW_INTR_MASK:
            D(printf ("RW_INTR_MASK=%x\n", value));
            t->rw_intr_mask = value;
            timer_update_irq(t);
            break;
        case RW_WD_CTRL:
            timer_watchdog_update(t, value);
            break;
        case RW_ACK_INTR:
            t->rw_ack_intr = value;
            timer_update_irq(t);
            t->rw_ack_intr = 0;
            break;
        default:
            printf ("%s " TARGET_FMT_plx " %x\n",
                __func__, addr, value);
            break;
    }
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static void etraxfs_timer_reset(void *opaque)
{
    struct etrax_timer *t = opaque;

    ptimer_stop(t->ptimer_t0);
    ptimer_stop(t->ptimer_t1);
    ptimer_stop(t->ptimer_wd);
    t->rw_wd_ctrl = 0;
    t->r_intr = 0;
    t->rw_intr_mask = 0;
    qemu_irq_lower(t->irq);
}

static int etraxfs_timer_init(SysBusDevice *dev)
{
    struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);

    t->bh_t0 = qemu_bh_new(timer0_hit, t);
    t->bh_t1 = qemu_bh_new(timer1_hit, t);
    t->bh_wd = qemu_bh_new(watchdog_hit, t);
    t->ptimer_t0 = ptimer_init(t->bh_t0);
    t->ptimer_t1 = ptimer_init(t->bh_t1);
    t->ptimer_wd = ptimer_init(t->bh_wd);

    sysbus_init_irq(dev, &t->irq);
    sysbus_init_irq(dev, &t->nmi);

    memory_region_init_io(&t->mmio, NULL, &timer_ops, t, "etraxfs-timer", 0x5c);
    sysbus_init_mmio(dev, &t->mmio);
    qemu_register_reset(etraxfs_timer_reset, t);
    return 0;
}

static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

    sdc->init = etraxfs_timer_init;
}

static const TypeInfo etraxfs_timer_info = {
    .name          = "etraxfs,timer",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof (struct etrax_timer),
    .class_init    = etraxfs_timer_class_init,
};

static void etraxfs_timer_register_types(void)
{
    type_register_static(&etraxfs_timer_info);
}

type_init(etraxfs_timer_register_types)
Commit	Line	Data
83fa1010	1	/*
e62b5b13	2	* QEMU ETRAX Timers
83fa1010 TS	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
83c9f4ca	24	#include "hw/sysbus.h"
9c17d615	25	#include "sysemu/sysemu.h"
1de7afc9	26	#include "qemu/timer.h"
83c9f4ca	27	#include "hw/ptimer.h"
83fa1010	28
bbaf29c7 EI	29	#define D(x)
bbaf29c7 EI	30
ca87d03b EI	31	#define RW_TMR0_DIV 0x00
	32	#define R_TMR0_DATA 0x04
	33	#define RW_TMR0_CTRL 0x08
	34	#define RW_TMR1_DIV 0x10
	35	#define R_TMR1_DATA 0x14
	36	#define RW_TMR1_CTRL 0x18
	37	#define R_TIME 0x38
	38	#define RW_WD_CTRL 0x40
5439779e	39	#define R_WD_STAT 0x44
ca87d03b EI	40	#define RW_INTR_MASK 0x48
	41	#define RW_ACK_INTR 0x4c
	42	#define R_INTR 0x50
	43	#define R_MASKED_INTR 0x54
83fa1010	44
3b1fd90e EI	45	struct etrax_timer {
3b1fd90e EI	46	SysBusDevice busdev;
b8e5da2c	47	MemoryRegion mmio;
3b1fd90e EI	48	qemu_irq irq;
3b1fd90e EI	49	qemu_irq nmi;
84ceea57 EI	50
	51	QEMUBH *bh_t0;
	52	QEMUBH *bh_t1;
	53	QEMUBH *bh_wd;
	54	ptimer_state *ptimer_t0;
	55	ptimer_state *ptimer_t1;
	56	ptimer_state *ptimer_wd;
84ceea57 EI	57
	58	int wd_hits;
	59
	60	/* Control registers. */
	61	uint32_t rw_tmr0_div;
	62	uint32_t r_tmr0_data;
	63	uint32_t rw_tmr0_ctrl;
	64
	65	uint32_t rw_tmr1_div;
	66	uint32_t r_tmr1_data;
	67	uint32_t rw_tmr1_ctrl;
	68
	69	uint32_t rw_wd_ctrl;
	70
	71	uint32_t rw_intr_mask;
	72	uint32_t rw_ack_intr;
	73	uint32_t r_intr;
	74	uint32_t r_masked_intr;
83fa1010 TS	75	};
83fa1010 TS	76
b8e5da2c	77	static uint64_t
a8170e5e	78	timer_read(void *opaque, hwaddr addr, unsigned int size)
83fa1010	79	{
3b1fd90e	80	struct etrax_timer *t = opaque;
84ceea57 EI	81	uint32_t r = 0;
	82
	83	switch (addr) {
	84	case R_TMR0_DATA:
	85	r = ptimer_get_count(t->ptimer_t0);
	86	break;
	87	case R_TMR1_DATA:
	88	r = ptimer_get_count(t->ptimer_t1);
	89	break;
	90	case R_TIME:
74475455	91	r = qemu_get_clock_ns(vm_clock) / 10;
84ceea57 EI	92	break;
	93	case RW_INTR_MASK:
	94	r = t->rw_intr_mask;
	95	break;
	96	case R_MASKED_INTR:
	97	r = t->r_intr & t->rw_intr_mask;
	98	break;
	99	default:
	100	D(printf ("%s %x\n", __func__, addr));
	101	break;
	102	}
	103	return r;
83fa1010 TS	104	}
83fa1010 TS	105
3b1fd90e	106	static void update_ctrl(struct etrax_timer *t, int tnum)
83fa1010	107	{
84ceea57 EI	108	unsigned int op;
	109	unsigned int freq;
	110	unsigned int freq_hz;
	111	unsigned int div;
	112	uint32_t ctrl;
	113
	114	ptimer_state *timer;
	115
	116	if (tnum == 0) {
	117	ctrl = t->rw_tmr0_ctrl;
	118	div = t->rw_tmr0_div;
	119	timer = t->ptimer_t0;
	120	} else {
	121	ctrl = t->rw_tmr1_ctrl;
	122	div = t->rw_tmr1_div;
	123	timer = t->ptimer_t1;
	124	}
	125
	126
	127	op = ctrl & 3;
	128	freq = ctrl >> 2;
	129	freq_hz = 32000000;
	130
	131	switch (freq)
	132	{
	133	case 0:
	134	case 1:
	135	D(printf ("extern or disabled timer clock?\n"));
	136	break;
	137	case 4: freq_hz = 29493000; break;
	138	case 5: freq_hz = 32000000; break;
	139	case 6: freq_hz = 32768000; break;
	140	case 7: freq_hz = 100000000; break;
	141	default:
	142	abort();
	143	break;
	144	}
	145
	146	D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
84ceea57 EI	147	ptimer_set_freq(timer, freq_hz);
	148	ptimer_set_limit(timer, div, 0);
	149
	150	switch (op)
	151	{
	152	case 0:
	153	/* Load. */
	154	ptimer_set_limit(timer, div, 1);
	155	break;
	156	case 1:
	157	/* Hold. */
	158	ptimer_stop(timer);
	159	break;
	160	case 2:
	161	/* Run. */
	162	ptimer_run(timer, 0);
	163	break;
	164	default:
	165	abort();
	166	break;
	167	}
83fa1010 TS	168	}
83fa1010 TS	169
3b1fd90e	170	static void timer_update_irq(struct etrax_timer *t)
83fa1010	171	{
84ceea57 EI	172	t->r_intr &= ~(t->rw_ack_intr);
84ceea57 EI	173	t->r_masked_intr = t->r_intr & t->rw_intr_mask;
60237223	174
84ceea57	175	D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
3b1fd90e	176	qemu_set_irq(t->irq, !!t->r_masked_intr);
83fa1010 TS	177	}
83fa1010 TS	178
5439779e	179	static void timer0_hit(void *opaque)
60237223	180	{
3b1fd90e	181	struct etrax_timer *t = opaque;
84ceea57 EI	182	t->r_intr \|= 1;
84ceea57 EI	183	timer_update_irq(t);
60237223 EI	184	}
60237223 EI	185
5439779e EI	186	static void timer1_hit(void *opaque)
5439779e EI	187	{
3b1fd90e	188	struct etrax_timer *t = opaque;
84ceea57 EI	189	t->r_intr \|= 2;
84ceea57 EI	190	timer_update_irq(t);
5439779e EI	191	}
	192
	193	static void watchdog_hit(void *opaque)
	194	{
3b1fd90e	195	struct etrax_timer *t = opaque;
84ceea57 EI	196	if (t->wd_hits == 0) {
	197	/* real hw gives a single tick before reseting but we are
	198	a bit friendlier to compensate for our slower execution. */
	199	ptimer_set_count(t->ptimer_wd, 10);
	200	ptimer_run(t->ptimer_wd, 1);
3b1fd90e	201	qemu_irq_raise(t->nmi);
84ceea57 EI	202	}
	203	else
	204	qemu_system_reset_request();
	205
	206	t->wd_hits++;
5439779e EI	207	}
5439779e EI	208
3b1fd90e	209	static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
5439779e	210	{
84ceea57 EI	211	unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
	212	unsigned int wd_key = t->rw_wd_ctrl >> 9;
	213	unsigned int wd_cnt = t->rw_wd_ctrl & 511;
	214	unsigned int new_key = value >> 9 & ((1 << 7) - 1);
	215	unsigned int new_cmd = (value >> 8) & 1;
5439779e	216
84ceea57 EI	217	/* If the watchdog is enabled, they written key must match the
	218	complement of the previous. */
	219	wd_key = ~wd_key & ((1 << 7) - 1);
5439779e	220
84ceea57 EI	221	if (wd_en && wd_key != new_key)
84ceea57 EI	222	return;
5439779e	223
84ceea57 EI	224	D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
84ceea57 EI	225	wd_en, new_key, wd_key, new_cmd, wd_cnt));
5439779e	226
84ceea57	227	if (t->wd_hits)
3b1fd90e	228	qemu_irq_lower(t->nmi);
5ef98b47	229
84ceea57	230	t->wd_hits = 0;
5ef98b47	231
84ceea57 EI	232	ptimer_set_freq(t->ptimer_wd, 760);
	233	if (wd_cnt == 0)
	234	wd_cnt = 256;
	235	ptimer_set_count(t->ptimer_wd, wd_cnt);
	236	if (new_cmd)
	237	ptimer_run(t->ptimer_wd, 1);
	238	else
	239	ptimer_stop(t->ptimer_wd);
5439779e	240
84ceea57	241	t->rw_wd_ctrl = value;
5439779e EI	242	}
5439779e EI	243
83fa1010	244	static void
a8170e5e	245	timer_write(void *opaque, hwaddr addr,
b8e5da2c	246	uint64_t val64, unsigned int size)
83fa1010	247	{
3b1fd90e	248	struct etrax_timer *t = opaque;
b8e5da2c	249	uint32_t value = val64;
84ceea57 EI	250
	251	switch (addr)
	252	{
	253	case RW_TMR0_DIV:
	254	t->rw_tmr0_div = value;
	255	break;
	256	case RW_TMR0_CTRL:
	257	D(printf ("RW_TMR0_CTRL=%x\n", value));
	258	t->rw_tmr0_ctrl = value;
	259	update_ctrl(t, 0);
	260	break;
	261	case RW_TMR1_DIV:
	262	t->rw_tmr1_div = value;
	263	break;
	264	case RW_TMR1_CTRL:
	265	D(printf ("RW_TMR1_CTRL=%x\n", value));
	266	t->rw_tmr1_ctrl = value;
	267	update_ctrl(t, 1);
	268	break;
	269	case RW_INTR_MASK:
	270	D(printf ("RW_INTR_MASK=%x\n", value));
	271	t->rw_intr_mask = value;
	272	timer_update_irq(t);
	273	break;
	274	case RW_WD_CTRL:
	275	timer_watchdog_update(t, value);
	276	break;
	277	case RW_ACK_INTR:
	278	t->rw_ack_intr = value;
	279	timer_update_irq(t);
	280	t->rw_ack_intr = 0;
	281	break;
	282	default:
	283	printf ("%s " TARGET_FMT_plx " %x\n",
	284	__func__, addr, value);
	285	break;
	286	}
83fa1010 TS	287	}
83fa1010 TS	288
b8e5da2c EI	289	static const MemoryRegionOps timer_ops = {
	290	.read = timer_read,
	291	.write = timer_write,
	292	.endianness = DEVICE_LITTLE_ENDIAN,
	293	.valid = {
	294	.min_access_size = 4,
	295	.max_access_size = 4
	296	}
83fa1010 TS	297	};
83fa1010 TS	298
5439779e EI	299	static void etraxfs_timer_reset(void *opaque)
5439779e EI	300	{
3b1fd90e	301	struct etrax_timer *t = opaque;
84ceea57 EI	302
	303	ptimer_stop(t->ptimer_t0);
	304	ptimer_stop(t->ptimer_t1);
	305	ptimer_stop(t->ptimer_wd);
	306	t->rw_wd_ctrl = 0;
	307	t->r_intr = 0;
	308	t->rw_intr_mask = 0;
3b1fd90e	309	qemu_irq_lower(t->irq);
5439779e EI	310	}
5439779e EI	311
81a322d4	312	static int etraxfs_timer_init(SysBusDevice *dev)
83fa1010	313	{
3b1fd90e	314	struct etrax_timer t = FROM_SYSBUS(typeof (t), dev);
83fa1010	315
84ceea57 EI	316	t->bh_t0 = qemu_bh_new(timer0_hit, t);
	317	t->bh_t1 = qemu_bh_new(timer1_hit, t);
	318	t->bh_wd = qemu_bh_new(watchdog_hit, t);
	319	t->ptimer_t0 = ptimer_init(t->bh_t0);
	320	t->ptimer_t1 = ptimer_init(t->bh_t1);
	321	t->ptimer_wd = ptimer_init(t->bh_wd);
3b1fd90e EI	322
	323	sysbus_init_irq(dev, &t->irq);
	324	sysbus_init_irq(dev, &t->nmi);
83fa1010	325
2c9b15ca	326	memory_region_init_io(&t->mmio, NULL, &timer_ops, t, "etraxfs-timer", 0x5c);
750ecd44	327	sysbus_init_mmio(dev, &t->mmio);
a08d4367	328	qemu_register_reset(etraxfs_timer_reset, t);
81a322d4	329	return 0;
83fa1010	330	}
3b1fd90e	331
999e12bb AL	332	static void etraxfs_timer_class_init(ObjectClass klass, void data)
	333	{
	334	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	335
	336	sdc->init = etraxfs_timer_init;
	337	}
	338
8c43a6f0	339	static const TypeInfo etraxfs_timer_info = {
39bffca2 AL	340	.name = "etraxfs,timer",
	341	.parent = TYPE_SYS_BUS_DEVICE,
	342	.instance_size = sizeof (struct etrax_timer),
	343	.class_init = etraxfs_timer_class_init,
999e12bb AL	344	};
999e12bb AL	345
83f7d43a	346	static void etraxfs_timer_register_types(void)
3b1fd90e	347	{
39bffca2	348	type_register_static(&etraxfs_timer_info);
3b1fd90e EI	349	}
3b1fd90e EI	350
83f7d43a	351	type_init(etraxfs_timer_register_types)