]>
Commit | Line | Data |
---|---|---|
1ad2134f PB |
1 | #ifndef CPU_COMMON_H |
2 | #define CPU_COMMON_H 1 | |
3 | ||
07f35073 | 4 | /* CPU interfaces that are target independent. */ |
1ad2134f | 5 | |
ce927ed9 | 6 | #ifndef CONFIG_USER_ONLY |
022c62cb | 7 | #include "exec/hwaddr.h" |
ce927ed9 | 8 | #endif |
37b76cfd PB |
9 | |
10 | #ifndef NEED_CPU_H | |
022c62cb | 11 | #include "exec/poison.h" |
37b76cfd PB |
12 | #endif |
13 | ||
1de7afc9 PB |
14 | #include "qemu/bswap.h" |
15 | #include "qemu/queue.h" | |
fba0a593 PM |
16 | #include "qemu/fprintf-fn.h" |
17 | #include "qemu/typedefs.h" | |
1ad2134f | 18 | |
92a31361 AF |
19 | /** |
20 | * CPUListState: | |
21 | * @cpu_fprintf: Print function. | |
22 | * @file: File to print to using @cpu_fprint. | |
23 | * | |
24 | * State commonly used for iterating over CPU models. | |
25 | */ | |
26 | typedef struct CPUListState { | |
27 | fprintf_function cpu_fprintf; | |
28 | FILE *file; | |
29 | } CPUListState; | |
30 | ||
55e94093 LA |
31 | typedef enum MMUAccessType { |
32 | MMU_DATA_LOAD = 0, | |
33 | MMU_DATA_STORE = 1, | |
34 | MMU_INST_FETCH = 2 | |
35 | } MMUAccessType; | |
36 | ||
b3755a91 PB |
37 | #if !defined(CONFIG_USER_ONLY) |
38 | ||
dd310534 AG |
39 | enum device_endian { |
40 | DEVICE_NATIVE_ENDIAN, | |
41 | DEVICE_BIG_ENDIAN, | |
42 | DEVICE_LITTLE_ENDIAN, | |
43 | }; | |
44 | ||
1ad2134f | 45 | /* address in the RAM (different from a physical address) */ |
4be403c8 | 46 | #if defined(CONFIG_XEN_BACKEND) |
f15fbc4b AP |
47 | typedef uint64_t ram_addr_t; |
48 | # define RAM_ADDR_MAX UINT64_MAX | |
49 | # define RAM_ADDR_FMT "%" PRIx64 | |
50 | #else | |
53576999 SW |
51 | typedef uintptr_t ram_addr_t; |
52 | # define RAM_ADDR_MAX UINTPTR_MAX | |
53 | # define RAM_ADDR_FMT "%" PRIxPTR | |
f15fbc4b | 54 | #endif |
1ad2134f | 55 | |
96d0e26c | 56 | extern ram_addr_t ram_size; |
87a45cfe | 57 | ram_addr_t get_current_ram_size(void); |
96d0e26c | 58 | |
1ad2134f PB |
59 | /* memory API */ |
60 | ||
a8170e5e AK |
61 | typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); |
62 | typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); | |
1ad2134f | 63 | |
cd19cfa2 | 64 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); |
1ad2134f | 65 | /* This should not be used by devices. */ |
1b5ec234 | 66 | MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); |
c5705a77 | 67 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev); |
20cfe881 | 68 | void qemu_ram_unset_idstr(ram_addr_t addr); |
1ad2134f | 69 | |
a8170e5e | 70 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
1ad2134f | 71 | int len, int is_write); |
a8170e5e | 72 | static inline void cpu_physical_memory_read(hwaddr addr, |
3bad9814 | 73 | void *buf, int len) |
1ad2134f PB |
74 | { |
75 | cpu_physical_memory_rw(addr, buf, len, 0); | |
76 | } | |
a8170e5e | 77 | static inline void cpu_physical_memory_write(hwaddr addr, |
3bad9814 | 78 | const void *buf, int len) |
1ad2134f | 79 | { |
3bad9814 | 80 | cpu_physical_memory_rw(addr, (void *)buf, len, 1); |
1ad2134f | 81 | } |
a8170e5e AK |
82 | void *cpu_physical_memory_map(hwaddr addr, |
83 | hwaddr *plen, | |
1ad2134f | 84 | int is_write); |
a8170e5e AK |
85 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
86 | int is_write, hwaddr access_len); | |
e95205e1 FZ |
87 | void cpu_register_map_client(QEMUBH *bh); |
88 | void cpu_unregister_map_client(QEMUBH *bh); | |
1ad2134f | 89 | |
a8170e5e | 90 | bool cpu_physical_memory_is_io(hwaddr phys_addr); |
76f35538 | 91 | |
6842a08e BS |
92 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
93 | * This usually implies that write operations are side-effect free. This allows | |
94 | * batching which can make a major impact on performance when using | |
95 | * virtualization. | |
96 | */ | |
6842a08e BS |
97 | void qemu_flush_coalesced_mmio_buffer(void); |
98 | ||
2c17449b | 99 | uint32_t ldub_phys(AddressSpace *as, hwaddr addr); |
41701aa4 EI |
100 | uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr); |
101 | uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr); | |
fdfba1a2 EI |
102 | uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr); |
103 | uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr); | |
2c17449b EI |
104 | uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr); |
105 | uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr); | |
db3be60d | 106 | void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
5ce5944d EI |
107 | void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
108 | void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
ab1da857 EI |
109 | void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
110 | void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
f606604f EI |
111 | void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val); |
112 | void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val); | |
c227f099 | 113 | |
21673cde | 114 | #ifdef NEED_CPU_H |
41701aa4 | 115 | uint32_t lduw_phys(AddressSpace *as, hwaddr addr); |
fdfba1a2 | 116 | uint32_t ldl_phys(AddressSpace *as, hwaddr addr); |
2c17449b | 117 | uint64_t ldq_phys(AddressSpace *as, hwaddr addr); |
2198a121 | 118 | void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val); |
5ce5944d | 119 | void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
ab1da857 | 120 | void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
f606604f | 121 | void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val); |
21673cde BS |
122 | #endif |
123 | ||
2a221651 | 124 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, |
1ad2134f | 125 | const uint8_t *buf, int len); |
582b55a9 | 126 | void cpu_flush_icache_range(hwaddr start, int len); |
1ad2134f | 127 | |
0e0df1e2 | 128 | extern struct MemoryRegion io_mem_rom; |
0e0df1e2 | 129 | extern struct MemoryRegion io_mem_notdirty; |
1ad2134f | 130 | |
e3807054 | 131 | typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr, |
bd2fa51f MH |
132 | ram_addr_t offset, ram_addr_t length, void *opaque); |
133 | ||
e3807054 | 134 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); |
bd2fa51f | 135 | |
b3755a91 PB |
136 | #endif |
137 | ||
1ad2134f | 138 | #endif /* !CPU_COMMON_H */ |