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1ad2134f PB |
1 | #ifndef CPU_COMMON_H |
2 | #define CPU_COMMON_H 1 | |
3 | ||
4 | /* CPU interfaces that are target indpendent. */ | |
5 | ||
477ba620 | 6 | #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__) |
1ad2134f PB |
7 | #define WORDS_ALIGNED |
8 | #endif | |
9 | ||
37b76cfd PB |
10 | #ifdef TARGET_PHYS_ADDR_BITS |
11 | #include "targphys.h" | |
12 | #endif | |
13 | ||
14 | #ifndef NEED_CPU_H | |
15 | #include "poison.h" | |
16 | #endif | |
17 | ||
1ad2134f | 18 | #include "bswap.h" |
f6f3fbca | 19 | #include "qemu-queue.h" |
1ad2134f | 20 | |
b3755a91 PB |
21 | #if !defined(CONFIG_USER_ONLY) |
22 | ||
1ad2134f | 23 | /* address in the RAM (different from a physical address) */ |
c227f099 | 24 | typedef unsigned long ram_addr_t; |
1ad2134f PB |
25 | |
26 | /* memory API */ | |
27 | ||
c227f099 AL |
28 | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
29 | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); | |
1ad2134f | 30 | |
c227f099 AL |
31 | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr, |
32 | ram_addr_t size, | |
33 | ram_addr_t phys_offset, | |
34 | ram_addr_t region_offset); | |
35 | static inline void cpu_register_physical_memory(target_phys_addr_t start_addr, | |
36 | ram_addr_t size, | |
37 | ram_addr_t phys_offset) | |
1ad2134f PB |
38 | { |
39 | cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0); | |
40 | } | |
41 | ||
c227f099 | 42 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); |
84b89d78 CM |
43 | ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name, |
44 | ram_addr_t size, void *host); | |
1724f049 | 45 | ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size); |
c227f099 | 46 | void qemu_ram_free(ram_addr_t addr); |
1ad2134f | 47 | /* This should only be used for ram local to a device. */ |
c227f099 | 48 | void *qemu_get_ram_ptr(ram_addr_t addr); |
b2e0a138 MT |
49 | /* Same but slower, to use for migration, where the order of |
50 | * RAMBlocks must not change. */ | |
51 | void *qemu_safe_ram_ptr(ram_addr_t addr); | |
1ad2134f | 52 | /* This should not be used by devices. */ |
e890261f MT |
53 | int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); |
54 | ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); | |
1ad2134f | 55 | |
d60efc6b BS |
56 | int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
57 | CPUWriteMemoryFunc * const *mem_write, | |
1ad2134f PB |
58 | void *opaque); |
59 | void cpu_unregister_io_memory(int table_address); | |
60 | ||
c227f099 | 61 | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, |
1ad2134f | 62 | int len, int is_write); |
c227f099 | 63 | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
1ad2134f PB |
64 | uint8_t *buf, int len) |
65 | { | |
66 | cpu_physical_memory_rw(addr, buf, len, 0); | |
67 | } | |
c227f099 | 68 | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
1ad2134f PB |
69 | const uint8_t *buf, int len) |
70 | { | |
71 | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1); | |
72 | } | |
c227f099 AL |
73 | void *cpu_physical_memory_map(target_phys_addr_t addr, |
74 | target_phys_addr_t *plen, | |
1ad2134f | 75 | int is_write); |
c227f099 AL |
76 | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
77 | int is_write, target_phys_addr_t access_len); | |
1ad2134f PB |
78 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); |
79 | void cpu_unregister_map_client(void *cookie); | |
80 | ||
f6f3fbca MT |
81 | struct CPUPhysMemoryClient; |
82 | typedef struct CPUPhysMemoryClient CPUPhysMemoryClient; | |
83 | struct CPUPhysMemoryClient { | |
84 | void (*set_memory)(struct CPUPhysMemoryClient *client, | |
85 | target_phys_addr_t start_addr, | |
86 | ram_addr_t size, | |
87 | ram_addr_t phys_offset); | |
88 | int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client, | |
89 | target_phys_addr_t start_addr, | |
90 | target_phys_addr_t end_addr); | |
91 | int (*migration_log)(struct CPUPhysMemoryClient *client, | |
92 | int enable); | |
93 | QLIST_ENTRY(CPUPhysMemoryClient) list; | |
94 | }; | |
95 | ||
96 | void cpu_register_phys_memory_client(CPUPhysMemoryClient *); | |
97 | void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *); | |
98 | ||
6842a08e BS |
99 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
100 | * This usually implies that write operations are side-effect free. This allows | |
101 | * batching which can make a major impact on performance when using | |
102 | * virtualization. | |
103 | */ | |
104 | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
105 | ||
106 | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size); | |
107 | ||
108 | void qemu_flush_coalesced_mmio_buffer(void); | |
109 | ||
c227f099 AL |
110 | uint32_t ldub_phys(target_phys_addr_t addr); |
111 | uint32_t lduw_phys(target_phys_addr_t addr); | |
112 | uint32_t ldl_phys(target_phys_addr_t addr); | |
113 | uint64_t ldq_phys(target_phys_addr_t addr); | |
114 | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val); | |
115 | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val); | |
116 | void stb_phys(target_phys_addr_t addr, uint32_t val); | |
117 | void stw_phys(target_phys_addr_t addr, uint32_t val); | |
118 | void stl_phys(target_phys_addr_t addr, uint32_t val); | |
119 | void stq_phys(target_phys_addr_t addr, uint64_t val); | |
120 | ||
121 | void cpu_physical_memory_write_rom(target_phys_addr_t addr, | |
1ad2134f PB |
122 | const uint8_t *buf, int len); |
123 | ||
124 | #define IO_MEM_SHIFT 3 | |
125 | ||
126 | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ | |
127 | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ | |
128 | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) | |
129 | #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT) | |
130 | ||
131 | /* Acts like a ROM when read and like a device when written. */ | |
132 | #define IO_MEM_ROMD (1) | |
133 | #define IO_MEM_SUBPAGE (2) | |
1ad2134f | 134 | |
b3755a91 PB |
135 | #endif |
136 | ||
1ad2134f | 137 | #endif /* !CPU_COMMON_H */ |