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Commit | Line | Data |
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1ad2134f PB |
1 | #ifndef CPU_COMMON_H |
2 | #define CPU_COMMON_H 1 | |
3 | ||
07f35073 | 4 | /* CPU interfaces that are target independent. */ |
1ad2134f | 5 | |
ce927ed9 | 6 | #ifndef CONFIG_USER_ONLY |
022c62cb | 7 | #include "exec/hwaddr.h" |
ce927ed9 | 8 | #endif |
37b76cfd PB |
9 | |
10 | #ifndef NEED_CPU_H | |
022c62cb | 11 | #include "exec/poison.h" |
37b76cfd PB |
12 | #endif |
13 | ||
1de7afc9 PB |
14 | #include "qemu/bswap.h" |
15 | #include "qemu/queue.h" | |
1ad2134f | 16 | |
92a31361 AF |
17 | /** |
18 | * CPUListState: | |
19 | * @cpu_fprintf: Print function. | |
20 | * @file: File to print to using @cpu_fprint. | |
21 | * | |
22 | * State commonly used for iterating over CPU models. | |
23 | */ | |
24 | typedef struct CPUListState { | |
25 | fprintf_function cpu_fprintf; | |
26 | FILE *file; | |
27 | } CPUListState; | |
28 | ||
b3755a91 PB |
29 | #if !defined(CONFIG_USER_ONLY) |
30 | ||
dd310534 AG |
31 | enum device_endian { |
32 | DEVICE_NATIVE_ENDIAN, | |
33 | DEVICE_BIG_ENDIAN, | |
34 | DEVICE_LITTLE_ENDIAN, | |
35 | }; | |
36 | ||
1ad2134f | 37 | /* address in the RAM (different from a physical address) */ |
4be403c8 | 38 | #if defined(CONFIG_XEN_BACKEND) |
f15fbc4b AP |
39 | typedef uint64_t ram_addr_t; |
40 | # define RAM_ADDR_MAX UINT64_MAX | |
41 | # define RAM_ADDR_FMT "%" PRIx64 | |
42 | #else | |
53576999 SW |
43 | typedef uintptr_t ram_addr_t; |
44 | # define RAM_ADDR_MAX UINTPTR_MAX | |
45 | # define RAM_ADDR_FMT "%" PRIxPTR | |
f15fbc4b | 46 | #endif |
1ad2134f PB |
47 | |
48 | /* memory API */ | |
49 | ||
a8170e5e AK |
50 | typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); |
51 | typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); | |
1ad2134f | 52 | |
cd19cfa2 | 53 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); |
1ad2134f | 54 | /* This should not be used by devices. */ |
1b5ec234 | 55 | MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); |
c5705a77 | 56 | void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev); |
1ad2134f | 57 | |
a8170e5e | 58 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, |
1ad2134f | 59 | int len, int is_write); |
a8170e5e | 60 | static inline void cpu_physical_memory_read(hwaddr addr, |
3bad9814 | 61 | void *buf, int len) |
1ad2134f PB |
62 | { |
63 | cpu_physical_memory_rw(addr, buf, len, 0); | |
64 | } | |
a8170e5e | 65 | static inline void cpu_physical_memory_write(hwaddr addr, |
3bad9814 | 66 | const void *buf, int len) |
1ad2134f | 67 | { |
3bad9814 | 68 | cpu_physical_memory_rw(addr, (void *)buf, len, 1); |
1ad2134f | 69 | } |
a8170e5e AK |
70 | void *cpu_physical_memory_map(hwaddr addr, |
71 | hwaddr *plen, | |
1ad2134f | 72 | int is_write); |
a8170e5e AK |
73 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, |
74 | int is_write, hwaddr access_len); | |
1ad2134f | 75 | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); |
1ad2134f | 76 | |
a8170e5e | 77 | bool cpu_physical_memory_is_io(hwaddr phys_addr); |
76f35538 | 78 | |
6842a08e BS |
79 | /* Coalesced MMIO regions are areas where write operations can be reordered. |
80 | * This usually implies that write operations are side-effect free. This allows | |
81 | * batching which can make a major impact on performance when using | |
82 | * virtualization. | |
83 | */ | |
6842a08e BS |
84 | void qemu_flush_coalesced_mmio_buffer(void); |
85 | ||
2c17449b | 86 | uint32_t ldub_phys(AddressSpace *as, hwaddr addr); |
41701aa4 EI |
87 | uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr); |
88 | uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr); | |
fdfba1a2 EI |
89 | uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr); |
90 | uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr); | |
2c17449b EI |
91 | uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr); |
92 | uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr); | |
a8170e5e AK |
93 | void stb_phys(hwaddr addr, uint32_t val); |
94 | void stw_le_phys(hwaddr addr, uint32_t val); | |
95 | void stw_be_phys(hwaddr addr, uint32_t val); | |
ab1da857 EI |
96 | void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
97 | void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); | |
f606604f EI |
98 | void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val); |
99 | void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val); | |
c227f099 | 100 | |
21673cde | 101 | #ifdef NEED_CPU_H |
41701aa4 | 102 | uint32_t lduw_phys(AddressSpace *as, hwaddr addr); |
fdfba1a2 | 103 | uint32_t ldl_phys(AddressSpace *as, hwaddr addr); |
2c17449b | 104 | uint64_t ldq_phys(AddressSpace *as, hwaddr addr); |
a8170e5e | 105 | void stl_phys_notdirty(hwaddr addr, uint32_t val); |
a8170e5e | 106 | void stw_phys(hwaddr addr, uint32_t val); |
ab1da857 | 107 | void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val); |
f606604f | 108 | void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val); |
21673cde BS |
109 | #endif |
110 | ||
a8170e5e | 111 | void cpu_physical_memory_write_rom(hwaddr addr, |
1ad2134f | 112 | const uint8_t *buf, int len); |
582b55a9 | 113 | void cpu_flush_icache_range(hwaddr start, int len); |
1ad2134f | 114 | |
0e0df1e2 | 115 | extern struct MemoryRegion io_mem_rom; |
0e0df1e2 | 116 | extern struct MemoryRegion io_mem_notdirty; |
1ad2134f | 117 | |
bd2fa51f MH |
118 | typedef void (RAMBlockIterFunc)(void *host_addr, |
119 | ram_addr_t offset, ram_addr_t length, void *opaque); | |
120 | ||
121 | void qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); | |
122 | ||
b3755a91 PB |
123 | #endif |
124 | ||
1ad2134f | 125 | #endif /* !CPU_COMMON_H */ |