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megasas: Fixup MSI-X handling
[qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
9c17d615 23#include "sysemu/dma.h"
4be74634 24#include "sysemu/block-backend.h"
4522b69c 25#include "hw/pci/msi.h"
83c9f4ca 26#include "hw/pci/msix.h"
1de7afc9 27#include "qemu/iov.h"
0d09e41a
PB		 28#include "hw/scsi/scsi.h"
29#include "block/scsi.h"
e8f943c3
HR		 30#include "trace.h"
31
47b43a1f 32#include "mfi.h"
e8f943c3 33
e23d0498
HR		 34#define MEGASAS_VERSION_GEN1 "1.70"
35#define MEGASAS_VERSION_GEN2 "1.80"
e8f943c3
HR		 36#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
37#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
e23d0498 38#define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
e8f943c3
HR		 39#define MEGASAS_MAX_SGE 128 /* Firmware limit */
40#define MEGASAS_DEFAULT_SGE 80
41#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
42#define MEGASAS_MAX_ARRAYS 128
43
fb654157 44#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 45#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
46#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
47
e8f943c3
HR		 48#define MEGASAS_FLAG_USE_JBOD 0
49#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
4522b69c
HR		 50#define MEGASAS_FLAG_USE_MSI 1
51#define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI)
52#define MEGASAS_FLAG_USE_MSIX 2
e8f943c3 53#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
4522b69c 54#define MEGASAS_FLAG_USE_QUEUE64 3
e8f943c3
HR		 55#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
56
a97ad268 57static const char *mfi_frame_desc[] = {
e8f943c3
HR		 58 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
59 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
60
61typedef struct MegasasCmd {
62 uint32_t index;
63 uint16_t flags;
64 uint16_t count;
65 uint64_t context;
66
a8170e5e
AK		 67 hwaddr pa;
68 hwaddr pa_size;
e8f943c3
HR		 69 union mfi_frame *frame;
70 SCSIRequest *req;
71 QEMUSGList qsg;
72 void *iov_buf;
73 size_t iov_size;
74 size_t iov_offset;
75 struct MegasasState *state;
76} MegasasCmd;
77
78typedef struct MegasasState {
52190c1e
AF		 79 /*< private >*/
80 PCIDevice parent_obj;
81 /*< public >*/
82
e8f943c3
HR		 83 MemoryRegion mmio_io;
84 MemoryRegion port_io;
85 MemoryRegion queue_io;
86 uint32_t frame_hi;
87
88 int fw_state;
89 uint32_t fw_sge;
90 uint32_t fw_cmds;
91 uint32_t flags;
92 int fw_luns;
93 int intr_mask;
94 int doorbell;
95 int busy;
e23d0498
HR		 96 int diag;
97 int adp_reset;
e8f943c3
HR		 98
99 MegasasCmd *event_cmd;
100 int event_locale;
101 int event_class;
102 int event_count;
103 int shutdown_event;
104 int boot_event;
105
76b523db 106 uint64_t sas_addr;
fb654157 107 char *hba_serial;
76b523db 108
e8f943c3
HR		 109 uint64_t reply_queue_pa;
110 void *reply_queue;
111 int reply_queue_len;
112 int reply_queue_head;
113 int reply_queue_tail;
114 uint64_t consumer_pa;
115 uint64_t producer_pa;
116
117 MegasasCmd frames[MEGASAS_MAX_FRAMES];
6df5718b 118 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 119 SCSIBus bus;
120} MegasasState;
121
e23d0498
HR		 122typedef struct MegasasBaseClass {
123 PCIDeviceClass parent_class;
124 const char *product_name;
125 const char *product_version;
126 int mmio_bar;
127 int ioport_bar;
128 int osts;
129} MegasasBaseClass;
130
131#define TYPE_MEGASAS_BASE "megasas-base"
132#define TYPE_MEGASAS_GEN1 "megasas"
133#define TYPE_MEGASAS_GEN2 "megasas-gen2"
c79e16ae
PC		 134
135#define MEGASAS(obj) \
e23d0498
HR		 136 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
137
138#define MEGASAS_DEVICE_CLASS(oc) \
139 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
140#define MEGASAS_DEVICE_GET_CLASS(oc) \
141 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
c79e16ae 142
e8f943c3
HR		 143#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
144
145static bool megasas_intr_enabled(MegasasState *s)
146{
147 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
148 MEGASAS_INTR_DISABLED_MASK) {
149 return true;
150 }
151 return false;
152}
153
154static bool megasas_use_queue64(MegasasState *s)
155{
156 return s->flags & MEGASAS_MASK_USE_QUEUE64;
157}
158
4522b69c
HR		 159static bool megasas_use_msi(MegasasState *s)
160{
161 return s->flags & MEGASAS_MASK_USE_MSI;
162}
163
e8f943c3
HR		 164static bool megasas_use_msix(MegasasState *s)
165{
166 return s->flags & MEGASAS_MASK_USE_MSIX;
167}
168
169static bool megasas_is_jbod(MegasasState *s)
170{
171 return s->flags & MEGASAS_MASK_USE_JBOD;
172}
173
174static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
175{
db3be60d
EI		 176 stb_phys(&address_space_memory,
177 frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 178}
179
180static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
181{
db3be60d
EI		 182 stb_phys(&address_space_memory,
183 frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 184}
185
186/*
187 * Context is considered opaque, but the HBA firmware is running
188 * in little endian mode. So convert it to little endian, too.
189 */
190static uint64_t megasas_frame_get_context(unsigned long frame)
191{
2c17449b
EI		 192 return ldq_le_phys(&address_space_memory,
193 frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 194}
195
196static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
197{
198 return cmd->flags & MFI_FRAME_IEEE_SGL;
199}
200
201static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
202{
203 return cmd->flags & MFI_FRAME_SGL64;
204}
205
206static bool megasas_frame_is_sense64(MegasasCmd *cmd)
207{
208 return cmd->flags & MFI_FRAME_SENSE64;
209}
210
211static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
212 union mfi_sgl *sgl)
213{
214 uint64_t addr;
215
216 if (megasas_frame_is_ieee_sgl(cmd)) {
217 addr = le64_to_cpu(sgl->sg_skinny->addr);
218 } else if (megasas_frame_is_sgl64(cmd)) {
219 addr = le64_to_cpu(sgl->sg64->addr);
220 } else {
221 addr = le32_to_cpu(sgl->sg32->addr);
222 }
223 return addr;
224}
225
226static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
227 union mfi_sgl *sgl)
228{
229 uint32_t len;
230
231 if (megasas_frame_is_ieee_sgl(cmd)) {
232 len = le32_to_cpu(sgl->sg_skinny->len);
233 } else if (megasas_frame_is_sgl64(cmd)) {
234 len = le32_to_cpu(sgl->sg64->len);
235 } else {
236 len = le32_to_cpu(sgl->sg32->len);
237 }
238 return len;
239}
240
241static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
242 union mfi_sgl *sgl)
243{
244 uint8_t *next = (uint8_t *)sgl;
245
246 if (megasas_frame_is_ieee_sgl(cmd)) {
247 next += sizeof(struct mfi_sg_skinny);
248 } else if (megasas_frame_is_sgl64(cmd)) {
249 next += sizeof(struct mfi_sg64);
250 } else {
251 next += sizeof(struct mfi_sg32);
252 }
253
254 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
255 return NULL;
256 }
257 return (union mfi_sgl *)next;
258}
259
260static void megasas_soft_reset(MegasasState *s);
261
262static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
263{
264 int i;
265 int iov_count = 0;
266 size_t iov_size = 0;
267
268 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
269 iov_count = cmd->frame->header.sge_count;
270 if (iov_count > MEGASAS_MAX_SGE) {
271 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
272 MEGASAS_MAX_SGE);
273 return iov_count;
274 }
52190c1e 275 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 276 for (i = 0; i < iov_count; i++) {
277 dma_addr_t iov_pa, iov_size_p;
278
279 if (!sgl) {
280 trace_megasas_iovec_sgl_underflow(cmd->index, i);
281 goto unmap;
282 }
283 iov_pa = megasas_sgl_get_addr(cmd, sgl);
284 iov_size_p = megasas_sgl_get_len(cmd, sgl);
285 if (!iov_pa || !iov_size_p) {
286 trace_megasas_iovec_sgl_invalid(cmd->index, i,
287 iov_pa, iov_size_p);
288 goto unmap;
289 }
290 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
291 sgl = megasas_sgl_next(cmd, sgl);
292 iov_size += (size_t)iov_size_p;
293 }
294 if (cmd->iov_size > iov_size) {
295 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
296 } else if (cmd->iov_size < iov_size) {
297 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
298 }
299 cmd->iov_offset = 0;
300 return 0;
301unmap:
302 qemu_sglist_destroy(&cmd->qsg);
303 return iov_count - i;
304}
305
306static void megasas_unmap_sgl(MegasasCmd *cmd)
307{
308 qemu_sglist_destroy(&cmd->qsg);
309 cmd->iov_offset = 0;
310}
311
312/*
313 * passthrough sense and io sense are at the same offset
314 */
315static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
316 uint8_t sense_len)
317{
1016b239 318 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 319 uint32_t pa_hi = 0, pa_lo;
a8170e5e 320 hwaddr pa;
e8f943c3
HR		 321
322 if (sense_len > cmd->frame->header.sense_len) {
323 sense_len = cmd->frame->header.sense_len;
324 }
325 if (sense_len) {
326 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
327 if (megasas_frame_is_sense64(cmd)) {
328 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
329 }
330 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 331 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 332 cmd->frame->header.sense_len = sense_len;
333 }
334 return sense_len;
335}
336
337static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
338{
339 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
340 uint8_t sense_len = 18;
341
342 memset(sense_buf, 0, sense_len);
343 sense_buf[0] = 0xf0;
344 sense_buf[2] = sense.key;
345 sense_buf[7] = 10;
346 sense_buf[12] = sense.asc;
347 sense_buf[13] = sense.ascq;
348 megasas_build_sense(cmd, sense_buf, sense_len);
349}
350
351static void megasas_copy_sense(MegasasCmd *cmd)
352{
353 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
354 uint8_t sense_len;
355
356 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
357 SCSI_SENSE_BUF_SIZE);
358 megasas_build_sense(cmd, sense_buf, sense_len);
359}
360
361/*
362 * Format an INQUIRY CDB
363 */
364static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
365{
366 memset(cdb, 0, 6);
367 cdb[0] = INQUIRY;
368 if (pg > 0) {
369 cdb[1] = 0x1;
370 cdb[2] = pg;
371 }
372 cdb[3] = (len >> 8) & 0xff;
373 cdb[4] = (len & 0xff);
374 return len;
375}
376
377/*
378 * Encode lba and len into a READ_16/WRITE_16 CDB
379 */
380static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
381 uint32_t len, bool is_write)
382{
383 memset(cdb, 0x0, 16);
384 if (is_write) {
385 cdb[0] = WRITE_16;
386 } else {
387 cdb[0] = READ_16;
388 }
389 cdb[2] = (lba >> 56) & 0xff;
390 cdb[3] = (lba >> 48) & 0xff;
391 cdb[4] = (lba >> 40) & 0xff;
392 cdb[5] = (lba >> 32) & 0xff;
393 cdb[6] = (lba >> 24) & 0xff;
394 cdb[7] = (lba >> 16) & 0xff;
395 cdb[8] = (lba >> 8) & 0xff;
396 cdb[9] = (lba) & 0xff;
397 cdb[10] = (len >> 24) & 0xff;
398 cdb[11] = (len >> 16) & 0xff;
399 cdb[12] = (len >> 8) & 0xff;
400 cdb[13] = (len) & 0xff;
401}
402
403/*
404 * Utility functions
405 */
406static uint64_t megasas_fw_time(void)
407{
408 struct tm curtime;
409 uint64_t bcd_time;
410
411 qemu_get_timedate(&curtime, 0);
412 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
413 ((uint64_t)curtime.tm_min & 0xff) << 40 |
414 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
415 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
416 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
417 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
418
419 return bcd_time;
420}
421
76b523db
HR		 422/*
423 * Default disk sata address
424 * 0x1221 is the magic number as
425 * present in real hardware,
426 * so use it here, too.
427 */
428static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 429{
76b523db
HR		 430 uint64_t addr = (0x1221ULL << 48);
431 return addr & (id << 24);
e8f943c3
HR		 432}
433
434/*
435 * Frame handling
436 */
437static int megasas_next_index(MegasasState *s, int index, int limit)
438{
439 index++;
440 if (index == limit) {
441 index = 0;
442 }
443 return index;
444}
445
446static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 447 hwaddr frame)
e8f943c3
HR		 448{
449 MegasasCmd *cmd = NULL;
450 int num = 0, index;
451
452 index = s->reply_queue_head;
453
454 while (num < s->fw_cmds) {
455 if (s->frames[index].pa && s->frames[index].pa == frame) {
456 cmd = &s->frames[index];
457 break;
458 }
459 index = megasas_next_index(s, index, s->fw_cmds);
460 num++;
461 }
462
463 return cmd;
464}
465
6df5718b 466static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
e8f943c3 467{
6df5718b 468 PCIDevice *p = PCI_DEVICE(s);
e8f943c3 469
6df5718b
HR		 470 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
471 cmd->frame = NULL;
472 cmd->pa = 0;
473 clear_bit(cmd->index, s->frame_map);
e8f943c3
HR		 474}
475
6df5718b
HR		 476/*
477 * This absolutely needs to be locked if
478 * qemu ever goes multithreaded.
479 */
e8f943c3 480static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 481 hwaddr frame, uint64_t context, int count)
e8f943c3 482{
1016b239 483 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 484 MegasasCmd *cmd = NULL;
485 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 486 hwaddr frame_size_p = frame_size;
6df5718b 487 unsigned long index;
e8f943c3 488
6df5718b
HR		 489 index = 0;
490 while (index < s->fw_cmds) {
491 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
492 if (!s->frames[index].pa)
493 break;
494 /* Busy frame found */
495 trace_megasas_qf_mapped(index);
496 }
497 if (index >= s->fw_cmds) {
498 /* All frames busy */
499 trace_megasas_qf_busy(frame);
e8f943c3
HR		 500 return NULL;
501 }
6df5718b
HR		 502 cmd = &s->frames[index];
503 set_bit(index, s->frame_map);
504 trace_megasas_qf_new(index, frame);
505
506 cmd->pa = frame;
507 /* Map all possible frames */
508 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
509 if (frame_size_p != frame_size) {
510 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
511 if (cmd->frame) {
512 megasas_unmap_frame(s, cmd);
e8f943c3 513 }
6df5718b
HR		 514 s->event_count++;
515 return NULL;
516 }
517 cmd->pa_size = frame_size_p;
518 cmd->context = context;
519 if (!megasas_use_queue64(s)) {
520 cmd->context &= (uint64_t)0xFFFFFFFF;
e8f943c3
HR		 521 }
522 cmd->count = count;
523 s->busy++;
524
aaf2a859
HR		 525 if (s->consumer_pa) {
526 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
527 s->consumer_pa);
528 }
e8f943c3 529 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
aaf2a859 530 s->reply_queue_head, s->reply_queue_tail, s->busy);
e8f943c3
HR		 531
532 return cmd;
533}
534
535static void megasas_complete_frame(MegasasState *s, uint64_t context)
536{
52190c1e 537 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 538 int tail, queue_offset;
539
540 /* Decrement busy count */
541 s->busy--;
e8f943c3
HR		 542 if (s->reply_queue_pa) {
543 /*
544 * Put command on the reply queue.
545 * Context is opaque, but emulation is running in
546 * little endian. So convert it.
547 */
e8f943c3 548 if (megasas_use_queue64(s)) {
7957ee71 549 queue_offset = s->reply_queue_head * sizeof(uint64_t);
f606604f
EI		 550 stq_le_phys(&address_space_memory,
551 s->reply_queue_pa + queue_offset, context);
e8f943c3 552 } else {
7957ee71 553 queue_offset = s->reply_queue_head * sizeof(uint32_t);
ab1da857
EI		 554 stl_le_phys(&address_space_memory,
555 s->reply_queue_pa + queue_offset, context);
e8f943c3 556 }
aaf2a859
HR		 557 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
558 s->consumer_pa);
559 trace_megasas_qf_complete(context, s->reply_queue_head,
7957ee71 560 s->reply_queue_tail, s->busy);
e8f943c3
HR		 561 }
562
563 if (megasas_intr_enabled(s)) {
7957ee71
HR		 564 /* Update reply queue pointer */
565 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
566 s->consumer_pa);
567 tail = s->reply_queue_head;
568 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
569 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
570 s->busy);
571 stl_le_phys(&address_space_memory,
572 s->producer_pa, s->reply_queue_head);
e8f943c3 573 /* Notify HBA */
7957ee71
HR		 574 if (msix_enabled(pci_dev)) {
575 trace_megasas_msix_raise(0);
576 msix_notify(pci_dev, 0);
577 } else if (msi_enabled(pci_dev)) {
578 trace_megasas_msi_raise(0);
579 msi_notify(pci_dev, 0);
580 } else {
581 s->doorbell++;
582 if (s->doorbell == 1) {
e8f943c3 583 trace_megasas_irq_raise();
9e64f8a3 584 pci_irq_assert(pci_dev);
e8f943c3
HR		 585 }
586 }
587 } else {
588 trace_megasas_qf_complete_noirq(context);
589 }
590}
591
592static void megasas_reset_frames(MegasasState *s)
593{
594 int i;
595 MegasasCmd *cmd;
596
597 for (i = 0; i < s->fw_cmds; i++) {
598 cmd = &s->frames[i];
599 if (cmd->pa) {
6df5718b 600 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 601 }
602 }
6df5718b 603 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 604}
605
606static void megasas_abort_command(MegasasCmd *cmd)
607{
608 if (cmd->req) {
e2b06058 609 scsi_req_cancel(cmd->req);
e8f943c3
HR		 610 cmd->req = NULL;
611 }
612}
613
614static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
615{
1016b239 616 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 617 uint32_t pa_hi, pa_lo;
96f8f23a
HR		 618 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
619 struct mfi_init_qinfo *initq = NULL;
e8f943c3
HR		 620 uint32_t flags;
621 int ret = MFI_STAT_OK;
622
96f8f23a
HR		 623 if (s->reply_queue_pa) {
624 trace_megasas_initq_mapped(s->reply_queue_pa);
625 goto out;
626 }
e8f943c3
HR		 627 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
628 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
629 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
630 trace_megasas_init_firmware((uint64_t)iq_pa);
1016b239 631 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 632 if (!initq || initq_size != sizeof(*initq)) {
633 trace_megasas_initq_map_failed(cmd->index);
634 s->event_count++;
635 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
636 goto out;
637 }
638 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
639 if (s->reply_queue_len > s->fw_cmds) {
640 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
641 s->event_count++;
642 ret = MFI_STAT_INVALID_PARAMETER;
643 goto out;
644 }
645 pa_lo = le32_to_cpu(initq->rq_addr_lo);
646 pa_hi = le32_to_cpu(initq->rq_addr_hi);
647 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
648 pa_lo = le32_to_cpu(initq->ci_addr_lo);
649 pa_hi = le32_to_cpu(initq->ci_addr_hi);
650 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
651 pa_lo = le32_to_cpu(initq->pi_addr_lo);
652 pa_hi = le32_to_cpu(initq->pi_addr_hi);
653 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
fdfba1a2
EI		 654 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
655 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
e8f943c3
HR		 656 flags = le32_to_cpu(initq->flags);
657 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
658 s->flags |= MEGASAS_MASK_USE_QUEUE64;
659 }
660 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
661 s->reply_queue_len, s->reply_queue_head,
662 s->reply_queue_tail, flags);
663 megasas_reset_frames(s);
664 s->fw_state = MFI_FWSTATE_OPERATIONAL;
665out:
666 if (initq) {
1016b239 667 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 668 }
669 return ret;
670}
671
672static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
673{
674 dma_addr_t iov_pa, iov_size;
675
676 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
677 if (!cmd->frame->header.sge_count) {
678 trace_megasas_dcmd_zero_sge(cmd->index);
679 cmd->iov_size = 0;
680 return 0;
681 } else if (cmd->frame->header.sge_count > 1) {
682 trace_megasas_dcmd_invalid_sge(cmd->index,
683 cmd->frame->header.sge_count);
684 cmd->iov_size = 0;
685 return -1;
686 }
687 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
688 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 689 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 690 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
691 cmd->iov_size = iov_size;
692 return cmd->iov_size;
693}
694
695static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
696{
697 trace_megasas_finish_dcmd(cmd->index, iov_size);
698
699 if (cmd->frame->header.sge_count) {
700 qemu_sglist_destroy(&cmd->qsg);
701 }
702 if (iov_size > cmd->iov_size) {
703 if (megasas_frame_is_ieee_sgl(cmd)) {
704 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
705 } else if (megasas_frame_is_sgl64(cmd)) {
706 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
707 } else {
708 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
709 }
710 }
711 cmd->iov_size = 0;
e8f943c3
HR		 712}
713
714static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
715{
52190c1e 716 PCIDevice *pci_dev = PCI_DEVICE(s);
e23d0498
HR		 717 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
718 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 719 struct mfi_ctrl_info info;
720 size_t dcmd_size = sizeof(info);
721 BusChild *kid;
3f2cd4dd 722 int num_pd_disks = 0;
e8f943c3
HR		 723
724 memset(&info, 0x0, cmd->iov_size);
725 if (cmd->iov_size < dcmd_size) {
726 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
727 dcmd_size);
728 return MFI_STAT_INVALID_PARAMETER;
729 }
730
e23d0498
HR		 731 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
732 info.pci.device = cpu_to_le16(pci_class->device_id);
733 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
734 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
e8f943c3 735
76b523db
HR		 736 /*
737 * For some reason the firmware supports
738 * only up to 8 device ports.
739 * Despite supporting a far larger number
740 * of devices for the physical devices.
741 * So just display the first 8 devices
742 * in the device port list, independent
743 * of how many logical devices are actually
744 * present.
745 */
746 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 747 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 748 info.device.port_count = 8;
749 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
750 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd 751 uint16_t pd_id;
76b523db 752
3f2cd4dd
HR		 753 if (num_pd_disks < 8) {
754 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
755 info.device.port_addr[num_pd_disks] =
756 cpu_to_le64(megasas_get_sata_addr(pd_id));
76b523db 757 }
3f2cd4dd 758 num_pd_disks++;
76b523db 759 }
e8f943c3 760
e23d0498 761 memcpy(info.product_name, base_class->product_name, 24);
fb654157 762 snprintf(info.serial_number, 32, "%s", s->hba_serial);
e8f943c3
HR		 763 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION);
764 memcpy(info.image_component[0].name, "APP", 3);
e23d0498
HR		 765 snprintf(info.image_component[0].version, 10, "%s-QEMU",
766 base_class->product_version);
5a7733b0
OH		 767 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
768 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 769 info.image_component_count = 1;
52190c1e 770 if (pci_dev->has_rom) {
e8f943c3
HR		 771 uint8_t biosver[32];
772 uint8_t *ptr;
773
52190c1e 774 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 775 memcpy(biosver, ptr + 0x41, 31);
e8f943c3
HR		 776 memcpy(info.image_component[1].name, "BIOS", 4);
777 memcpy(info.image_component[1].version, biosver,
778 strlen((const char *)biosver));
779 info.image_component_count++;
780 }
781 info.current_fw_time = cpu_to_le32(megasas_fw_time());
782 info.max_arms = 32;
783 info.max_spans = 8;
784 info.max_arrays = MEGASAS_MAX_ARRAYS;
3f2cd4dd 785 info.max_lds = MFI_MAX_LD;
e8f943c3
HR		 786 info.max_cmds = cpu_to_le16(s->fw_cmds);
787 info.max_sg_elements = cpu_to_le16(s->fw_sge);
788 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
3f2cd4dd
HR		 789 if (!megasas_is_jbod(s))
790 info.lds_present = cpu_to_le16(num_pd_disks);
791 info.pd_present = cpu_to_le16(num_pd_disks);
792 info.pd_disks_present = cpu_to_le16(num_pd_disks);
e8f943c3
HR		 793 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
794 MFI_INFO_HW_MEM |
795 MFI_INFO_HW_FLASH);
796 info.memory_size = cpu_to_le16(512);
797 info.nvram_size = cpu_to_le16(32);
798 info.flash_size = cpu_to_le16(16);
799 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
800 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
801 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
802 MFI_INFO_AOPS_MIXED_ARRAY);
803 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
804 MFI_INFO_LDOPS_ACCESS_POLICY |
805 MFI_INFO_LDOPS_IO_POLICY |
806 MFI_INFO_LDOPS_WRITE_POLICY |
807 MFI_INFO_LDOPS_READ_POLICY);
808 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
809 info.stripe_sz_ops.min = 3;
810 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1;
811 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
812 info.properties.intr_throttle_cnt = cpu_to_le16(16);
813 info.properties.intr_throttle_timeout = cpu_to_le16(50);
814 info.properties.rebuild_rate = 30;
815 info.properties.patrol_read_rate = 30;
816 info.properties.bgi_rate = 30;
817 info.properties.cc_rate = 30;
818 info.properties.recon_rate = 30;
819 info.properties.cache_flush_interval = 4;
820 info.properties.spinup_drv_cnt = 2;
821 info.properties.spinup_delay = 6;
822 info.properties.ecc_bucket_size = 15;
823 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
824 info.properties.expose_encl_devices = 1;
825 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
826 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
827 MFI_INFO_PDOPS_FORCE_OFFLINE);
828 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
829 MFI_INFO_PDMIX_SATA |
830 MFI_INFO_PDMIX_LD);
831
832 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
833 return MFI_STAT_OK;
834}
835
836static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
837{
838 struct mfi_defaults info;
839 size_t dcmd_size = sizeof(struct mfi_defaults);
840
841 memset(&info, 0x0, dcmd_size);
842 if (cmd->iov_size < dcmd_size) {
843 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
844 dcmd_size);
845 return MFI_STAT_INVALID_PARAMETER;
846 }
847
76b523db 848 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 849 info.stripe_size = 3;
850 info.flush_time = 4;
851 info.background_rate = 30;
852 info.allow_mix_in_enclosure = 1;
853 info.allow_mix_in_ld = 1;
854 info.direct_pd_mapping = 1;
855 /* Enable for BIOS support */
856 info.bios_enumerate_lds = 1;
857 info.disable_ctrl_r = 1;
858 info.expose_enclosure_devices = 1;
859 info.disable_preboot_cli = 1;
860 info.cluster_disable = 1;
861
862 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
863 return MFI_STAT_OK;
864}
865
866static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
867{
868 struct mfi_bios_data info;
869 size_t dcmd_size = sizeof(info);
870
871 memset(&info, 0x0, dcmd_size);
872 if (cmd->iov_size < dcmd_size) {
873 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
874 dcmd_size);
875 return MFI_STAT_INVALID_PARAMETER;
876 }
877 info.continue_on_error = 1;
878 info.verbose = 1;
879 if (megasas_is_jbod(s)) {
880 info.expose_all_drives = 1;
881 }
882
883 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
884 return MFI_STAT_OK;
885}
886
887static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
888{
889 uint64_t fw_time;
890 size_t dcmd_size = sizeof(fw_time);
891
892 fw_time = cpu_to_le64(megasas_fw_time());
893
894 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
895 return MFI_STAT_OK;
896}
897
898static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
899{
900 uint64_t fw_time;
901
902 /* This is a dummy; setting of firmware time is not allowed */
903 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
904
905 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
906 fw_time = cpu_to_le64(megasas_fw_time());
907 return MFI_STAT_OK;
908}
909
910static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
911{
912 struct mfi_evt_log_state info;
913 size_t dcmd_size = sizeof(info);
914
915 memset(&info, 0, dcmd_size);
916
917 info.newest_seq_num = cpu_to_le32(s->event_count);
918 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
919 info.boot_seq_num = cpu_to_le32(s->boot_event);
920
921 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
922 return MFI_STAT_OK;
923}
924
925static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
926{
927 union mfi_evt event;
928
929 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
930 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
931 sizeof(struct mfi_evt_detail));
932 return MFI_STAT_INVALID_PARAMETER;
933 }
934 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
935 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
936 s->event_locale = event.members.locale;
937 s->event_class = event.members.class;
938 s->event_cmd = cmd;
939 /* Decrease busy count; event frame doesn't count here */
940 s->busy--;
941 cmd->iov_size = sizeof(struct mfi_evt_detail);
942 return MFI_STAT_INVALID_STATUS;
943}
944
945static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
946{
947 struct mfi_pd_list info;
948 size_t dcmd_size = sizeof(info);
949 BusChild *kid;
950 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
e8f943c3
HR		 951
952 memset(&info, 0, dcmd_size);
953 offset = 8;
954 dcmd_limit = offset + sizeof(struct mfi_pd_address);
955 if (cmd->iov_size < dcmd_limit) {
956 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
957 dcmd_limit);
958 return MFI_STAT_INVALID_PARAMETER;
959 }
960
961 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
3f2cd4dd
HR		 962 if (max_pd_disks > MFI_MAX_SYS_PDS) {
963 max_pd_disks = MFI_MAX_SYS_PDS;
e8f943c3 964 }
e8f943c3
HR		 965 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
966 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd
HR		 967 uint16_t pd_id;
968
969 if (num_pd_disks >= max_pd_disks)
970 break;
e8f943c3 971
3f2cd4dd
HR		 972 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
973 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 974 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
975 info.addr[num_pd_disks].encl_index = 0;
3f2cd4dd 976 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
e8f943c3
HR		 977 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
978 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
979 info.addr[num_pd_disks].sas_addr[0] =
3f2cd4dd 980 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 981 num_pd_disks++;
982 offset += sizeof(struct mfi_pd_address);
983 }
984 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
985 max_pd_disks, offset);
986
987 info.size = cpu_to_le32(offset);
988 info.count = cpu_to_le32(num_pd_disks);
989
990 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
991 return MFI_STAT_OK;
992}
993
994static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
995{
996 uint16_t flags;
997
998 /* mbox0 contains flags */
999 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1000 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1001 if (flags == MR_PD_QUERY_TYPE_ALL ||
1002 megasas_is_jbod(s)) {
1003 return megasas_dcmd_pd_get_list(s, cmd);
1004 }
1005
1006 return MFI_STAT_OK;
1007}
1008
1009static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1010 MegasasCmd *cmd)
1011{
1012 struct mfi_pd_info *info = cmd->iov_buf;
1013 size_t dcmd_size = sizeof(struct mfi_pd_info);
e8f943c3 1014 uint64_t pd_size;
3f2cd4dd 1015 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1016 uint8_t cmdbuf[6];
1017 SCSIRequest *req;
1018 size_t len, resid;
1019
1020 if (!cmd->iov_buf) {
1021 cmd->iov_buf = g_malloc(dcmd_size);
1022 memset(cmd->iov_buf, 0, dcmd_size);
1023 info = cmd->iov_buf;
1024 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1025 info->vpd_page83[0] = 0x7f;
1026 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1027 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1028 if (!req) {
1029 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1030 "PD get info std inquiry");
1031 g_free(cmd->iov_buf);
1032 cmd->iov_buf = NULL;
1033 return MFI_STAT_FLASH_ALLOC_FAIL;
1034 }
1035 trace_megasas_dcmd_internal_submit(cmd->index,
1036 "PD get info std inquiry", lun);
1037 len = scsi_req_enqueue(req);
1038 if (len > 0) {
1039 cmd->iov_size = len;
1040 scsi_req_continue(req);
1041 }
1042 return MFI_STAT_INVALID_STATUS;
1043 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1044 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1045 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1046 if (!req) {
1047 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1048 "PD get info vpd inquiry");
1049 return MFI_STAT_FLASH_ALLOC_FAIL;
1050 }
1051 trace_megasas_dcmd_internal_submit(cmd->index,
1052 "PD get info vpd inquiry", lun);
1053 len = scsi_req_enqueue(req);
1054 if (len > 0) {
1055 cmd->iov_size = len;
1056 scsi_req_continue(req);
1057 }
1058 return MFI_STAT_INVALID_STATUS;
1059 }
1060 /* Finished, set FW state */
1061 if ((info->inquiry_data[0] >> 5) == 0) {
1062 if (megasas_is_jbod(cmd->state)) {
1063 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1064 } else {
1065 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1066 }
1067 } else {
1068 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1069 }
1070
3f2cd4dd 1071 info->ref.v.device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 1072 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1073 MFI_PD_DDF_TYPE_INTF_SAS);
4be74634 1074 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1075 info->raw_size = cpu_to_le64(pd_size);
1076 info->non_coerced_size = cpu_to_le64(pd_size);
1077 info->coerced_size = cpu_to_le64(pd_size);
1078 info->encl_device_id = 0xFFFF;
1079 info->slot_number = (sdev->id & 0xFF);
1080 info->path_info.count = 1;
1081 info->path_info.sas_addr[0] =
3f2cd4dd 1082 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 1083 info->connected_port_bitmap = 0x1;
1084 info->device_speed = 1;
1085 info->link_speed = 1;
1086 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1087 g_free(cmd->iov_buf);
1088 cmd->iov_size = dcmd_size - resid;
1089 cmd->iov_buf = NULL;
1090 return MFI_STAT_OK;
1091}
1092
1093static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1094{
1095 size_t dcmd_size = sizeof(struct mfi_pd_info);
1096 uint16_t pd_id;
3f2cd4dd 1097 uint8_t target_id, lun_id;
e8f943c3
HR		 1098 SCSIDevice *sdev = NULL;
1099 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1100
1101 if (cmd->iov_size < dcmd_size) {
1102 return MFI_STAT_INVALID_PARAMETER;
1103 }
1104
1105 /* mbox0 has the ID */
1106 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
3f2cd4dd
HR		 1107 target_id = (pd_id >> 8) & 0xFF;
1108 lun_id = pd_id & 0xFF;
1109 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
e8f943c3
HR		 1110 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1111
1112 if (sdev) {
1113 /* Submit inquiry */
1114 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1115 }
1116
1117 return retval;
1118}
1119
1120static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1121{
1122 struct mfi_ld_list info;
1123 size_t dcmd_size = sizeof(info), resid;
3f2cd4dd 1124 uint32_t num_ld_disks = 0, max_ld_disks;
e8f943c3
HR		 1125 uint64_t ld_size;
1126 BusChild *kid;
1127
1128 memset(&info, 0, dcmd_size);
e74a4315 1129 if (cmd->iov_size > dcmd_size) {
e8f943c3
HR		 1130 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1131 dcmd_size);
1132 return MFI_STAT_INVALID_PARAMETER;
1133 }
1134
3f2cd4dd 1135 max_ld_disks = (cmd->iov_size - 8) / 16;
e8f943c3
HR		 1136 if (megasas_is_jbod(s)) {
1137 max_ld_disks = 0;
1138 }
3f2cd4dd
HR		 1139 if (max_ld_disks > MFI_MAX_LD) {
1140 max_ld_disks = MFI_MAX_LD;
1141 }
e8f943c3
HR		 1142 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1143 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
e8f943c3
HR		 1144
1145 if (num_ld_disks >= max_ld_disks) {
1146 break;
1147 }
1148 /* Logical device size is in blocks */
4be74634 1149 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1150 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1151 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1152 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1153 num_ld_disks++;
1154 }
1155 info.ld_count = cpu_to_le32(num_ld_disks);
1156 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1157
1158 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1159 cmd->iov_size = dcmd_size - resid;
1160 return MFI_STAT_OK;
1161}
1162
34bb4d02
HR		 1163static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1164{
1165 uint16_t flags;
d97ae368
HR		 1166 struct mfi_ld_targetid_list info;
1167 size_t dcmd_size = sizeof(info), resid;
1168 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1169 BusChild *kid;
34bb4d02
HR		 1170
1171 /* mbox0 contains flags */
1172 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1173 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
d97ae368
HR		 1174 if (flags != MR_LD_QUERY_TYPE_ALL &&
1175 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1176 max_ld_disks = 0;
1177 }
1178
1179 memset(&info, 0, dcmd_size);
1180 if (cmd->iov_size < 12) {
1181 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1182 dcmd_size);
1183 return MFI_STAT_INVALID_PARAMETER;
1184 }
1185 dcmd_size = sizeof(uint32_t) * 2 + 3;
3f2cd4dd 1186 max_ld_disks = cmd->iov_size - dcmd_size;
d97ae368
HR		 1187 if (megasas_is_jbod(s)) {
1188 max_ld_disks = 0;
34bb4d02 1189 }
3f2cd4dd
HR		 1190 if (max_ld_disks > MFI_MAX_LD) {
1191 max_ld_disks = MFI_MAX_LD;
1192 }
d97ae368
HR		 1193 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1194 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
34bb4d02 1195
d97ae368
HR		 1196 if (num_ld_disks >= max_ld_disks) {
1197 break;
1198 }
1199 info.targetid[num_ld_disks] = sdev->lun;
1200 num_ld_disks++;
1201 dcmd_size++;
1202 }
1203 info.ld_count = cpu_to_le32(num_ld_disks);
1204 info.size = dcmd_size;
1205 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1206
1207 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1208 cmd->iov_size = dcmd_size - resid;
34bb4d02
HR		 1209 return MFI_STAT_OK;
1210}
1211
e8f943c3
HR		 1212static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1213 MegasasCmd *cmd)
1214{
1215 struct mfi_ld_info *info = cmd->iov_buf;
1216 size_t dcmd_size = sizeof(struct mfi_ld_info);
1217 uint8_t cdb[6];
1218 SCSIRequest *req;
1219 ssize_t len, resid;
3f2cd4dd 1220 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1221 uint64_t ld_size;
1222
1223 if (!cmd->iov_buf) {
1224 cmd->iov_buf = g_malloc(dcmd_size);
1225 memset(cmd->iov_buf, 0x0, dcmd_size);
1226 info = cmd->iov_buf;
1227 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1228 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1229 if (!req) {
1230 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1231 "LD get info vpd inquiry");
1232 g_free(cmd->iov_buf);
1233 cmd->iov_buf = NULL;
1234 return MFI_STAT_FLASH_ALLOC_FAIL;
1235 }
1236 trace_megasas_dcmd_internal_submit(cmd->index,
1237 "LD get info vpd inquiry", lun);
1238 len = scsi_req_enqueue(req);
1239 if (len > 0) {
1240 cmd->iov_size = len;
1241 scsi_req_continue(req);
1242 }
1243 return MFI_STAT_INVALID_STATUS;
1244 }
1245
1246 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1247 info->ld_config.properties.ld.v.target_id = lun;
1248 info->ld_config.params.stripe_size = 3;
1249 info->ld_config.params.num_drives = 1;
1250 info->ld_config.params.is_consistent = 1;
1251 /* Logical device size is in blocks */
4be74634 1252 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1253 info->size = cpu_to_le64(ld_size);
1254 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1255 info->ld_config.span[0].start_block = 0;
1256 info->ld_config.span[0].num_blocks = info->size;
1257 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1258
1259 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1260 g_free(cmd->iov_buf);
1261 cmd->iov_size = dcmd_size - resid;
1262 cmd->iov_buf = NULL;
1263 return MFI_STAT_OK;
1264}
1265
1266static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1267{
1268 struct mfi_ld_info info;
1269 size_t dcmd_size = sizeof(info);
1270 uint16_t ld_id;
1271 uint32_t max_ld_disks = s->fw_luns;
1272 SCSIDevice *sdev = NULL;
1273 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1274
1275 if (cmd->iov_size < dcmd_size) {
1276 return MFI_STAT_INVALID_PARAMETER;
1277 }
1278
1279 /* mbox0 has the ID */
1280 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1281 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1282
1283 if (megasas_is_jbod(s)) {
1284 return MFI_STAT_DEVICE_NOT_FOUND;
1285 }
1286
1287 if (ld_id < max_ld_disks) {
1288 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1289 }
1290
1291 if (sdev) {
1292 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1293 }
1294
1295 return retval;
1296}
1297
1298static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1299{
1300 uint8_t data[4096];
1301 struct mfi_config_data *info;
1302 int num_pd_disks = 0, array_offset, ld_offset;
1303 BusChild *kid;
1304
1305 if (cmd->iov_size > 4096) {
1306 return MFI_STAT_INVALID_PARAMETER;
1307 }
1308
1309 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1310 num_pd_disks++;
1311 }
1312 info = (struct mfi_config_data *)&data;
1313 /*
1314 * Array mapping:
1315 * - One array per SCSI device
1316 * - One logical drive per SCSI device
1317 * spanning the entire device
1318 */
1319 info->array_count = num_pd_disks;
1320 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1321 info->log_drv_count = num_pd_disks;
1322 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1323 info->spares_count = 0;
1324 info->spares_size = sizeof(struct mfi_spare);
1325 info->size = sizeof(struct mfi_config_data) + info->array_size +
1326 info->log_drv_size;
1327 if (info->size > 4096) {
1328 return MFI_STAT_INVALID_PARAMETER;
1329 }
1330
1331 array_offset = sizeof(struct mfi_config_data);
1332 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1333
1334 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1335 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd 1336 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
e8f943c3
HR		 1337 struct mfi_array *array;
1338 struct mfi_ld_config *ld;
1339 uint64_t pd_size;
1340 int i;
1341
1342 array = (struct mfi_array *)(data + array_offset);
4be74634 1343 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1344 array->size = cpu_to_le64(pd_size);
1345 array->num_drives = 1;
1346 array->array_ref = cpu_to_le16(sdev_id);
1347 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1348 array->pd[0].ref.v.seq_num = 0;
1349 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1350 array->pd[0].encl.pd = 0xFF;
1351 array->pd[0].encl.slot = (sdev->id & 0xFF);
1352 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1353 array->pd[i].ref.v.device_id = 0xFFFF;
1354 array->pd[i].ref.v.seq_num = 0;
1355 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1356 array->pd[i].encl.pd = 0xFF;
1357 array->pd[i].encl.slot = 0xFF;
1358 }
1359 array_offset += sizeof(struct mfi_array);
1360 ld = (struct mfi_ld_config *)(data + ld_offset);
1361 memset(ld, 0, sizeof(struct mfi_ld_config));
3f2cd4dd 1362 ld->properties.ld.v.target_id = sdev->id;
e8f943c3
HR		 1363 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1364 MR_LD_CACHE_READ_ADAPTIVE;
1365 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1366 MR_LD_CACHE_READ_ADAPTIVE;
1367 ld->params.state = MFI_LD_STATE_OPTIMAL;
1368 ld->params.stripe_size = 3;
1369 ld->params.num_drives = 1;
1370 ld->params.span_depth = 1;
1371 ld->params.is_consistent = 1;
1372 ld->span[0].start_block = 0;
1373 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1374 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1375 ld_offset += sizeof(struct mfi_ld_config);
1376 }
1377
1378 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1379 return MFI_STAT_OK;
1380}
1381
1382static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1383{
1384 struct mfi_ctrl_props info;
1385 size_t dcmd_size = sizeof(info);
1386
1387 memset(&info, 0x0, dcmd_size);
1388 if (cmd->iov_size < dcmd_size) {
1389 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1390 dcmd_size);
1391 return MFI_STAT_INVALID_PARAMETER;
1392 }
1393 info.pred_fail_poll_interval = cpu_to_le16(300);
1394 info.intr_throttle_cnt = cpu_to_le16(16);
1395 info.intr_throttle_timeout = cpu_to_le16(50);
1396 info.rebuild_rate = 30;
1397 info.patrol_read_rate = 30;
1398 info.bgi_rate = 30;
1399 info.cc_rate = 30;
1400 info.recon_rate = 30;
1401 info.cache_flush_interval = 4;
1402 info.spinup_drv_cnt = 2;
1403 info.spinup_delay = 6;
1404 info.ecc_bucket_size = 15;
1405 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1406 info.expose_encl_devices = 1;
1407
1408 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1409 return MFI_STAT_OK;
1410}
1411
1412static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1413{
4be74634 1414 blk_drain_all();
e8f943c3
HR		 1415 return MFI_STAT_OK;
1416}
1417
1418static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1419{
1420 s->fw_state = MFI_FWSTATE_READY;
1421 return MFI_STAT_OK;
1422}
1423
200b6966 1424/* Some implementations use CLUSTER RESET LD to simulate a device reset */
e8f943c3
HR		 1425static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1426{
200b6966
HR		 1427 uint16_t target_id;
1428 int i;
1429
1430 /* mbox0 contains the device index */
1431 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1432 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1433 for (i = 0; i < s->fw_cmds; i++) {
1434 MegasasCmd *tmp_cmd = &s->frames[i];
1435 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1436 SCSIDevice *d = tmp_cmd->req->dev;
1437 qdev_reset_all(&d->qdev);
1438 }
1439 }
1440 return MFI_STAT_OK;
e8f943c3
HR		 1441}
1442
1443static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1444{
10d6530c
HR		 1445 struct mfi_ctrl_props info;
1446 size_t dcmd_size = sizeof(info);
1447
1448 if (cmd->iov_size < dcmd_size) {
1449 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1450 dcmd_size);
1451 return MFI_STAT_INVALID_PARAMETER;
1452 }
1453 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg);
1454 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1455 return MFI_STAT_OK;
1456}
1457
1458static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1459{
1460 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1461 return MFI_STAT_OK;
1462}
1463
1464static const struct dcmd_cmd_tbl_t {
1465 int opcode;
1466 const char *desc;
1467 int (*func)(MegasasState *s, MegasasCmd *cmd);
1468} dcmd_cmd_tbl[] = {
1469 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1470 megasas_dcmd_dummy },
1471 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1472 megasas_ctrl_get_info },
1473 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1474 megasas_dcmd_get_properties },
1475 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1476 megasas_dcmd_set_properties },
1477 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1478 megasas_dcmd_dummy },
1479 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1480 megasas_dcmd_dummy },
1481 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1482 megasas_dcmd_dummy },
1483 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1484 megasas_dcmd_dummy },
1485 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1486 megasas_dcmd_dummy },
1487 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1488 megasas_event_info },
1489 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1490 megasas_dcmd_dummy },
1491 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1492 megasas_event_wait },
1493 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1494 megasas_ctrl_shutdown },
1495 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1496 megasas_dcmd_dummy },
1497 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1498 megasas_dcmd_get_fw_time },
1499 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1500 megasas_dcmd_set_fw_time },
1501 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1502 megasas_dcmd_get_bios_info },
1503 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1504 megasas_dcmd_dummy },
1505 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1506 megasas_mfc_get_defaults },
1507 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1508 megasas_dcmd_dummy },
1509 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1510 megasas_cache_flush },
1511 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1512 megasas_dcmd_pd_get_list },
1513 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1514 megasas_dcmd_pd_list_query },
1515 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1516 megasas_dcmd_pd_get_info },
1517 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1518 megasas_dcmd_dummy },
1519 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1520 megasas_dcmd_dummy },
1521 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1522 megasas_dcmd_dummy },
1523 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1524 megasas_dcmd_dummy },
1525 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1526 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1527 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1528 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1529 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1530 megasas_dcmd_ld_get_info },
1531 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1532 megasas_dcmd_dummy },
1533 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1534 megasas_dcmd_dummy },
1535 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1536 megasas_dcmd_dummy },
1537 { MFI_DCMD_CFG_READ, "CFG_READ",
1538 megasas_dcmd_cfg_read },
1539 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1540 megasas_dcmd_dummy },
1541 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1542 megasas_dcmd_dummy },
1543 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1544 megasas_dcmd_dummy },
1545 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1546 megasas_dcmd_dummy },
1547 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1548 megasas_dcmd_dummy },
1549 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1550 megasas_dcmd_dummy },
1551 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1552 megasas_dcmd_dummy },
1553 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1554 megasas_dcmd_dummy },
1555 { MFI_DCMD_CLUSTER, "CLUSTER",
1556 megasas_dcmd_dummy },
1557 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1558 megasas_dcmd_dummy },
1559 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1560 megasas_cluster_reset_ld },
1561 { -1, NULL, NULL }
1562};
1563
1564static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1565{
1566 int opcode, len;
1567 int retval = 0;
1568 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1569
1570 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1571 trace_megasas_handle_dcmd(cmd->index, opcode);
1572 len = megasas_map_dcmd(s, cmd);
1573 if (len < 0) {
1574 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1575 }
1576 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1577 cmdptr++;
1578 }
1579 if (cmdptr->opcode == -1) {
1580 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1581 retval = megasas_dcmd_dummy(s, cmd);
1582 } else {
1583 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1584 retval = cmdptr->func(s, cmd);
1585 }
1586 if (retval != MFI_STAT_INVALID_STATUS) {
1587 megasas_finish_dcmd(cmd, len);
1588 }
1589 return retval;
1590}
1591
1592static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1593 SCSIRequest *req)
1594{
1595 int opcode;
1596 int retval = MFI_STAT_OK;
1597 int lun = req->lun;
1598
1599 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1600 scsi_req_unref(req);
1601 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1602 switch (opcode) {
1603 case MFI_DCMD_PD_GET_INFO:
1604 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1605 break;
1606 case MFI_DCMD_LD_GET_INFO:
1607 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1608 break;
1609 default:
1610 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1611 retval = MFI_STAT_INVALID_DCMD;
1612 break;
1613 }
1614 if (retval != MFI_STAT_INVALID_STATUS) {
1615 megasas_finish_dcmd(cmd, cmd->iov_size);
1616 }
1617 return retval;
1618}
1619
1620static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1621{
1622 int len;
1623
1624 len = scsi_req_enqueue(cmd->req);
1625 if (len < 0) {
1626 len = -len;
1627 }
1628 if (len > 0) {
1629 if (len > cmd->iov_size) {
1630 if (is_write) {
1631 trace_megasas_iov_write_overflow(cmd->index, len,
1632 cmd->iov_size);
1633 } else {
1634 trace_megasas_iov_read_overflow(cmd->index, len,
1635 cmd->iov_size);
1636 }
1637 }
1638 if (len < cmd->iov_size) {
1639 if (is_write) {
1640 trace_megasas_iov_write_underflow(cmd->index, len,
1641 cmd->iov_size);
1642 } else {
1643 trace_megasas_iov_read_underflow(cmd->index, len,
1644 cmd->iov_size);
1645 }
1646 cmd->iov_size = len;
1647 }
1648 scsi_req_continue(cmd->req);
1649 }
1650 return len;
1651}
1652
1653static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1654 bool is_logical)
1655{
1656 uint8_t *cdb;
e8f943c3
HR		 1657 bool is_write;
1658 struct SCSIDevice *sdev = NULL;
1659
1660 cdb = cmd->frame->pass.cdb;
1661
3f2cd4dd
HR		 1662 if (is_logical) {
1663 if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1664 cmd->frame->header.lun_id != 0) {
1665 trace_megasas_scsi_target_not_present(
1666 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1667 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1668 return MFI_STAT_DEVICE_NOT_FOUND;
1669 }
e8f943c3 1670 }
3f2cd4dd
HR		 1671 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1672 cmd->frame->header.lun_id);
1673
e8f943c3
HR		 1674 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1675 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1676 is_logical, cmd->frame->header.target_id,
1677 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1678
1679 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1680 trace_megasas_scsi_target_not_present(
1681 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1682 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1683 return MFI_STAT_DEVICE_NOT_FOUND;
1684 }
1685
1686 if (cmd->frame->header.cdb_len > 16) {
1687 trace_megasas_scsi_invalid_cdb_len(
1688 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1689 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1690 cmd->frame->header.cdb_len);
1691 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1692 cmd->frame->header.scsi_status = CHECK_CONDITION;
1693 s->event_count++;
1694 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1695 }
1696
1697 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1698 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1699 cmd->frame->header.scsi_status = CHECK_CONDITION;
1700 s->event_count++;
1701 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1702 }
1703
1704 cmd->req = scsi_req_new(sdev, cmd->index,
1705 cmd->frame->header.lun_id, cdb, cmd);
1706 if (!cmd->req) {
1707 trace_megasas_scsi_req_alloc_failed(
1708 mfi_frame_desc[cmd->frame->header.frame_cmd],
1709 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1710 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1711 cmd->frame->header.scsi_status = BUSY;
1712 s->event_count++;
1713 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1714 }
1715
1716 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
aaf2a859 1717 if (cmd->iov_size) {
e8f943c3 1718 if (is_write) {
aaf2a859 1719 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
e8f943c3 1720 } else {
aaf2a859 1721 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
e8f943c3
HR		 1722 }
1723 } else {
1724 trace_megasas_scsi_nodata(cmd->index);
1725 }
aaf2a859 1726 megasas_enqueue_req(cmd, is_write);
e8f943c3
HR		 1727 return MFI_STAT_INVALID_STATUS;
1728}
1729
1730static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1731{
1732 uint32_t lba_count, lba_start_hi, lba_start_lo;
1733 uint64_t lba_start;
1734 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1735 uint8_t cdb[16];
1736 int len;
1737 struct SCSIDevice *sdev = NULL;
1738
1739 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1740 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1741 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1742 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1743
3f2cd4dd
HR		 1744 if (cmd->frame->header.target_id < MFI_MAX_LD &&
1745 cmd->frame->header.lun_id == 0) {
e8f943c3
HR		 1746 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1747 cmd->frame->header.lun_id);
1748 }
1749
1750 trace_megasas_handle_io(cmd->index,
1751 mfi_frame_desc[cmd->frame->header.frame_cmd],
1752 cmd->frame->header.target_id,
1753 cmd->frame->header.lun_id,
1754 (unsigned long)lba_start, (unsigned long)lba_count);
1755 if (!sdev) {
1756 trace_megasas_io_target_not_present(cmd->index,
1757 mfi_frame_desc[cmd->frame->header.frame_cmd],
1758 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1759 return MFI_STAT_DEVICE_NOT_FOUND;
1760 }
1761
1762 if (cmd->frame->header.cdb_len > 16) {
1763 trace_megasas_scsi_invalid_cdb_len(
1764 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1765 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1766 cmd->frame->header.cdb_len);
1767 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1768 cmd->frame->header.scsi_status = CHECK_CONDITION;
1769 s->event_count++;
1770 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1771 }
1772
1773 cmd->iov_size = lba_count * sdev->blocksize;
1774 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1775 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1776 cmd->frame->header.scsi_status = CHECK_CONDITION;
1777 s->event_count++;
1778 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1779 }
1780
1781 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1782 cmd->req = scsi_req_new(sdev, cmd->index,
1783 cmd->frame->header.lun_id, cdb, cmd);
1784 if (!cmd->req) {
1785 trace_megasas_scsi_req_alloc_failed(
1786 mfi_frame_desc[cmd->frame->header.frame_cmd],
1787 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1788 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1789 cmd->frame->header.scsi_status = BUSY;
1790 s->event_count++;
1791 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1792 }
1793 len = megasas_enqueue_req(cmd, is_write);
1794 if (len > 0) {
1795 if (is_write) {
1796 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1797 } else {
1798 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1799 }
1800 }
1801 return MFI_STAT_INVALID_STATUS;
1802}
1803
1804static int megasas_finish_internal_command(MegasasCmd *cmd,
1805 SCSIRequest *req, size_t resid)
1806{
1807 int retval = MFI_STAT_INVALID_CMD;
1808
1809 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1810 cmd->iov_size -= resid;
1811 retval = megasas_finish_internal_dcmd(cmd, req);
1812 }
1813 return retval;
1814}
1815
1816static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1817{
1818 MegasasCmd *cmd = req->hba_private;
1819
1820 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1821 return NULL;
1822 } else {
1823 return &cmd->qsg;
1824 }
1825}
1826
1827static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1828{
1829 MegasasCmd *cmd = req->hba_private;
1830 uint8_t *buf;
1831 uint32_t opcode;
1832
1833 trace_megasas_io_complete(cmd->index, len);
1834
1835 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1836 scsi_req_continue(req);
1837 return;
1838 }
1839
1840 buf = scsi_req_get_buf(req);
1841 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1842 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1843 struct mfi_pd_info *info = cmd->iov_buf;
1844
1845 if (info->inquiry_data[0] == 0x7f) {
1846 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1847 memcpy(info->inquiry_data, buf, len);
1848 } else if (info->vpd_page83[0] == 0x7f) {
1849 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1850 memcpy(info->vpd_page83, buf, len);
1851 }
1852 scsi_req_continue(req);
1853 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1854 struct mfi_ld_info *info = cmd->iov_buf;
1855
1856 if (cmd->iov_buf) {
1857 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1858 scsi_req_continue(req);
1859 }
1860 }
1861}
1862
1863static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1864 size_t resid)
1865{
1866 MegasasCmd *cmd = req->hba_private;
1867 uint8_t cmd_status = MFI_STAT_OK;
1868
1869 trace_megasas_command_complete(cmd->index, status, resid);
1870
1871 if (cmd->req != req) {
1872 /*
1873 * Internal command complete
1874 */
1875 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1876 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1877 return;
1878 }
1879 } else {
1880 req->status = status;
1881 trace_megasas_scsi_complete(cmd->index, req->status,
1882 cmd->iov_size, req->cmd.xfer);
1883 if (req->status != GOOD) {
1884 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1885 }
1886 if (req->status == CHECK_CONDITION) {
1887 megasas_copy_sense(cmd);
1888 }
1889
1890 megasas_unmap_sgl(cmd);
1891 cmd->frame->header.scsi_status = req->status;
1892 scsi_req_unref(cmd->req);
1893 cmd->req = NULL;
1894 }
1895 cmd->frame->header.cmd_status = cmd_status;
6df5718b 1896 megasas_unmap_frame(cmd->state, cmd);
e8f943c3
HR		 1897 megasas_complete_frame(cmd->state, cmd->context);
1898}
1899
1900static void megasas_command_cancel(SCSIRequest *req)
1901{
1902 MegasasCmd *cmd = req->hba_private;
1903
1904 if (cmd) {
1905 megasas_abort_command(cmd);
1906 } else {
1907 scsi_req_unref(req);
1908 }
1909}
1910
1911static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1912{
1913 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1914 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1915 MegasasCmd *abort_cmd;
1916
1917 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1918 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1919 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1920
1921 abort_cmd = megasas_lookup_frame(s, abort_addr);
1922 if (!abort_cmd) {
1923 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1924 s->event_count++;
1925 return MFI_STAT_OK;
1926 }
1927 if (!megasas_use_queue64(s)) {
1928 abort_ctx &= (uint64_t)0xFFFFFFFF;
1929 }
1930 if (abort_cmd->context != abort_ctx) {
1931 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1932 abort_cmd->context);
1933 s->event_count++;
1934 return MFI_STAT_ABORT_NOT_POSSIBLE;
1935 }
1936 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1937 megasas_abort_command(abort_cmd);
1938 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1939 s->event_cmd = NULL;
1940 }
1941 s->event_count++;
1942 return MFI_STAT_OK;
1943}
1944
1945static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1946 uint32_t frame_count)
1947{
1948 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1949 uint64_t frame_context;
1950 MegasasCmd *cmd;
1951
1952 /*
1953 * Always read 64bit context, top bits will be
1954 * masked out if required in megasas_enqueue_frame()
1955 */
1956 frame_context = megasas_frame_get_context(frame_addr);
1957
1958 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1959 if (!cmd) {
1960 /* reply queue full */
1961 trace_megasas_frame_busy(frame_addr);
1962 megasas_frame_set_scsi_status(frame_addr, BUSY);
1963 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1964 megasas_complete_frame(s, frame_context);
1965 s->event_count++;
1966 return;
1967 }
1968 switch (cmd->frame->header.frame_cmd) {
1969 case MFI_CMD_INIT:
1970 frame_status = megasas_init_firmware(s, cmd);
1971 break;
1972 case MFI_CMD_DCMD:
1973 frame_status = megasas_handle_dcmd(s, cmd);
1974 break;
1975 case MFI_CMD_ABORT:
1976 frame_status = megasas_handle_abort(s, cmd);
1977 break;
1978 case MFI_CMD_PD_SCSI_IO:
1979 frame_status = megasas_handle_scsi(s, cmd, 0);
1980 break;
1981 case MFI_CMD_LD_SCSI_IO:
1982 frame_status = megasas_handle_scsi(s, cmd, 1);
1983 break;
1984 case MFI_CMD_LD_READ:
1985 case MFI_CMD_LD_WRITE:
1986 frame_status = megasas_handle_io(s, cmd);
1987 break;
1988 default:
1989 trace_megasas_unhandled_frame_cmd(cmd->index,
1990 cmd->frame->header.frame_cmd);
1991 s->event_count++;
1992 break;
1993 }
1994 if (frame_status != MFI_STAT_INVALID_STATUS) {
1995 if (cmd->frame) {
1996 cmd->frame->header.cmd_status = frame_status;
1997 } else {
1998 megasas_frame_set_cmd_status(frame_addr, frame_status);
1999 }
6df5718b 2000 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 2001 megasas_complete_frame(s, cmd->context);
2002 }
2003}
2004
a8170e5e 2005static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2006 unsigned size)
2007{
2008 MegasasState *s = opaque;
e23d0498
HR		 2009 PCIDevice *pci_dev = PCI_DEVICE(s);
2010 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2011 uint32_t retval = 0;
2012
2013 switch (addr) {
2014 case MFI_IDB:
2015 retval = 0;
77bb6b17 2016 trace_megasas_mmio_readl("MFI_IDB", retval);
e8f943c3
HR		 2017 break;
2018 case MFI_OMSG0:
2019 case MFI_OSP0:
e23d0498 2020 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
e8f943c3
HR		 2021 (s->fw_state & MFI_FWSTATE_MASK) |
2022 ((s->fw_sge & 0xff) << 16) |
2023 (s->fw_cmds & 0xFFFF);
77bb6b17
HR		 2024 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2025 retval);
e8f943c3
HR		 2026 break;
2027 case MFI_OSTS:
2028 if (megasas_intr_enabled(s) && s->doorbell) {
e23d0498 2029 retval = base_class->osts;
e8f943c3 2030 }
77bb6b17 2031 trace_megasas_mmio_readl("MFI_OSTS", retval);
e8f943c3
HR		 2032 break;
2033 case MFI_OMSK:
2034 retval = s->intr_mask;
77bb6b17 2035 trace_megasas_mmio_readl("MFI_OMSK", retval);
e8f943c3
HR		 2036 break;
2037 case MFI_ODCR0:
7957ee71 2038 retval = s->doorbell ? 1 : 0;
77bb6b17 2039 trace_megasas_mmio_readl("MFI_ODCR0", retval);
e8f943c3 2040 break;
e23d0498
HR		 2041 case MFI_DIAG:
2042 retval = s->diag;
77bb6b17 2043 trace_megasas_mmio_readl("MFI_DIAG", retval);
e23d0498
HR		 2044 break;
2045 case MFI_OSP1:
2046 retval = 15;
77bb6b17 2047 trace_megasas_mmio_readl("MFI_OSP1", retval);
e23d0498 2048 break;
e8f943c3
HR		 2049 default:
2050 trace_megasas_mmio_invalid_readl(addr);
2051 break;
2052 }
e8f943c3
HR		 2053 return retval;
2054}
2055
e23d0498
HR		 2056static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2057
a8170e5e 2058static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2059 uint64_t val, unsigned size)
2060{
2061 MegasasState *s = opaque;
52190c1e 2062 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 2063 uint64_t frame_addr;
2064 uint32_t frame_count;
2065 int i;
2066
e8f943c3
HR		 2067 switch (addr) {
2068 case MFI_IDB:
77bb6b17 2069 trace_megasas_mmio_writel("MFI_IDB", val);
e8f943c3
HR		 2070 if (val & MFI_FWINIT_ABORT) {
2071 /* Abort all pending cmds */
2072 for (i = 0; i < s->fw_cmds; i++) {
2073 megasas_abort_command(&s->frames[i]);
2074 }
2075 }
2076 if (val & MFI_FWINIT_READY) {
2077 /* move to FW READY */
2078 megasas_soft_reset(s);
2079 }
2080 if (val & MFI_FWINIT_MFIMODE) {
2081 /* discard MFIs */
2082 }
e23d0498
HR		 2083 if (val & MFI_FWINIT_STOP_ADP) {
2084 /* Terminal error, stop processing */
2085 s->fw_state = MFI_FWSTATE_FAULT;
2086 }
e8f943c3
HR		 2087 break;
2088 case MFI_OMSK:
77bb6b17 2089 trace_megasas_mmio_writel("MFI_OMSK", val);
e8f943c3 2090 s->intr_mask = val;
4522b69c
HR		 2091 if (!megasas_intr_enabled(s) &&
2092 !msi_enabled(pci_dev) &&
2093 !msix_enabled(pci_dev)) {
e8f943c3 2094 trace_megasas_irq_lower();
9e64f8a3 2095 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2096 }
2097 if (megasas_intr_enabled(s)) {
4522b69c
HR		 2098 if (msix_enabled(pci_dev)) {
2099 trace_megasas_msix_enabled(0);
2100 } else if (msi_enabled(pci_dev)) {
2101 trace_megasas_msi_enabled(0);
2102 } else {
2103 trace_megasas_intr_enabled();
2104 }
e8f943c3
HR		 2105 } else {
2106 trace_megasas_intr_disabled();
e23d0498 2107 megasas_soft_reset(s);
e8f943c3
HR		 2108 }
2109 break;
2110 case MFI_ODCR0:
77bb6b17 2111 trace_megasas_mmio_writel("MFI_ODCR0", val);
e8f943c3 2112 s->doorbell = 0;
7957ee71
HR		 2113 if (megasas_intr_enabled(s)) {
2114 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
e8f943c3 2115 trace_megasas_irq_lower();
9e64f8a3 2116 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2117 }
2118 }
2119 break;
2120 case MFI_IQPH:
77bb6b17 2121 trace_megasas_mmio_writel("MFI_IQPH", val);
e8f943c3
HR		 2122 /* Received high 32 bits of a 64 bit MFI frame address */
2123 s->frame_hi = val;
2124 break;
2125 case MFI_IQPL:
77bb6b17 2126 trace_megasas_mmio_writel("MFI_IQPL", val);
e8f943c3 2127 /* Received low 32 bits of a 64 bit MFI frame address */
e23d0498 2128 /* Fallthrough */
e8f943c3 2129 case MFI_IQP:
77bb6b17
HR		 2130 if (addr == MFI_IQP) {
2131 trace_megasas_mmio_writel("MFI_IQP", val);
2132 /* Received 64 bit MFI frame address */
2133 s->frame_hi = 0;
2134 }
e8f943c3
HR		 2135 frame_addr = (val & ~0x1F);
2136 /* Add possible 64 bit offset */
2137 frame_addr |= ((uint64_t)s->frame_hi << 32);
2138 s->frame_hi = 0;
2139 frame_count = (val >> 1) & 0xF;
2140 megasas_handle_frame(s, frame_addr, frame_count);
2141 break;
e23d0498 2142 case MFI_SEQ:
77bb6b17 2143 trace_megasas_mmio_writel("MFI_SEQ", val);
e23d0498
HR		 2144 /* Magic sequence to start ADP reset */
2145 if (adp_reset_seq[s->adp_reset] == val) {
2146 s->adp_reset++;
2147 } else {
2148 s->adp_reset = 0;
2149 s->diag = 0;
2150 }
2151 if (s->adp_reset == 6) {
2152 s->diag = MFI_DIAG_WRITE_ENABLE;
2153 }
2154 break;
2155 case MFI_DIAG:
77bb6b17 2156 trace_megasas_mmio_writel("MFI_DIAG", val);
e23d0498
HR		 2157 /* ADP reset */
2158 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2159 (val & MFI_DIAG_RESET_ADP)) {
2160 s->diag |= MFI_DIAG_RESET_ADP;
2161 megasas_soft_reset(s);
2162 s->adp_reset = 0;
2163 s->diag = 0;
2164 }
2165 break;
e8f943c3
HR		 2166 default:
2167 trace_megasas_mmio_invalid_writel(addr, val);
2168 break;
2169 }
2170}
2171
2172static const MemoryRegionOps megasas_mmio_ops = {
2173 .read = megasas_mmio_read,
2174 .write = megasas_mmio_write,
2175 .endianness = DEVICE_LITTLE_ENDIAN,
2176 .impl = {
2177 .min_access_size = 8,
2178 .max_access_size = 8,
2179 }
2180};
2181
a8170e5e 2182static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2183 unsigned size)
2184{
2185 return megasas_mmio_read(opaque, addr & 0xff, size);
2186}
2187
a8170e5e 2188static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2189 uint64_t val, unsigned size)
2190{
2191 megasas_mmio_write(opaque, addr & 0xff, val, size);
2192}
2193
2194static const MemoryRegionOps megasas_port_ops = {
2195 .read = megasas_port_read,
2196 .write = megasas_port_write,
2197 .endianness = DEVICE_LITTLE_ENDIAN,
2198 .impl = {
2199 .min_access_size = 4,
2200 .max_access_size = 4,
2201 }
2202};
2203
a8170e5e 2204static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2205 unsigned size)
2206{
2207 return 0;
2208}
2209
2210static const MemoryRegionOps megasas_queue_ops = {
2211 .read = megasas_queue_read,
2212 .endianness = DEVICE_LITTLE_ENDIAN,
2213 .impl = {
2214 .min_access_size = 8,
2215 .max_access_size = 8,
2216 }
2217};
2218
2219static void megasas_soft_reset(MegasasState *s)
2220{
2221 int i;
2222 MegasasCmd *cmd;
2223
8d72db68 2224 trace_megasas_reset(s->fw_state);
e8f943c3
HR		 2225 for (i = 0; i < s->fw_cmds; i++) {
2226 cmd = &s->frames[i];
2227 megasas_abort_command(cmd);
2228 }
8d72db68
HR		 2229 if (s->fw_state == MFI_FWSTATE_READY) {
2230 BusChild *kid;
2231
2232 /*
2233 * The EFI firmware doesn't handle UA,
2234 * so we need to clear the Power On/Reset UA
2235 * after the initial reset.
2236 */
2237 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2238 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
2239
2240 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2241 scsi_device_unit_attention_reported(sdev);
2242 }
2243 }
e8f943c3
HR		 2244 megasas_reset_frames(s);
2245 s->reply_queue_len = s->fw_cmds;
2246 s->reply_queue_pa = 0;
2247 s->consumer_pa = 0;
2248 s->producer_pa = 0;
2249 s->fw_state = MFI_FWSTATE_READY;
2250 s->doorbell = 0;
2251 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2252 s->frame_hi = 0;
2253 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2254 s->event_count++;
2255 s->boot_event = s->event_count;
2256}
2257
2258static void megasas_scsi_reset(DeviceState *dev)
2259{
c79e16ae 2260 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2261
2262 megasas_soft_reset(s);
2263}
2264
e23d0498 2265static const VMStateDescription vmstate_megasas_gen1 = {
e8f943c3
HR		 2266 .name = "megasas",
2267 .version_id = 0,
2268 .minimum_version_id = 0,
d49805ae 2269 .fields = (VMStateField[]) {
52190c1e 2270 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2271 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2272
2273 VMSTATE_INT32(fw_state, MegasasState),
2274 VMSTATE_INT32(intr_mask, MegasasState),
2275 VMSTATE_INT32(doorbell, MegasasState),
2276 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2277 VMSTATE_UINT64(consumer_pa, MegasasState),
2278 VMSTATE_UINT64(producer_pa, MegasasState),
2279 VMSTATE_END_OF_LIST()
2280 }
2281};
2282
e23d0498
HR		 2283static const VMStateDescription vmstate_megasas_gen2 = {
2284 .name = "megasas-gen2",
2285 .version_id = 0,
2286 .minimum_version_id = 0,
2287 .minimum_version_id_old = 0,
2288 .fields = (VMStateField[]) {
2289 VMSTATE_PCIE_DEVICE(parent_obj, MegasasState),
2290 VMSTATE_MSIX(parent_obj, MegasasState),
2291
2292 VMSTATE_INT32(fw_state, MegasasState),
2293 VMSTATE_INT32(intr_mask, MegasasState),
2294 VMSTATE_INT32(doorbell, MegasasState),
2295 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2296 VMSTATE_UINT64(consumer_pa, MegasasState),
2297 VMSTATE_UINT64(producer_pa, MegasasState),
2298 VMSTATE_END_OF_LIST()
2299 }
2300};
2301
18fc611b 2302static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2303{
c79e16ae 2304 MegasasState *s = MEGASAS(d);
e8f943c3 2305
4522b69c
HR		 2306 if (megasas_use_msix(s)) {
2307 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2308 }
2309 if (megasas_use_msi(s)) {
2310 msi_uninit(d);
2311 }
e8f943c3
HR		 2312}
2313
2314static const struct SCSIBusInfo megasas_scsi_info = {
2315 .tcq = true,
2316 .max_target = MFI_MAX_LD,
2317 .max_lun = 255,
2318
2319 .transfer_data = megasas_xfer_complete,
2320 .get_sg_list = megasas_get_sg_list,
2321 .complete = megasas_command_complete,
2322 .cancel = megasas_command_cancel,
2323};
2324
2325static int megasas_scsi_init(PCIDevice *dev)
2326{
22d6aa03 2327 DeviceState *d = DEVICE(dev);
c79e16ae 2328 MegasasState *s = MEGASAS(dev);
e23d0498 2329 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2330 uint8_t *pci_conf;
2331 int i, bar_type;
caad4eb3 2332 Error *err = NULL;
e8f943c3 2333
52190c1e 2334 pci_conf = dev->config;
e8f943c3
HR		 2335
2336 /* PCI latency timer = 0 */
2337 pci_conf[PCI_LATENCY_TIMER] = 0;
2338 /* Interrupt pin 1 */
2339 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2340
29776739 2341 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2342 "megasas-mmio", 0x4000);
29776739 2343 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2344 "megasas-io", 256);
29776739 2345 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2346 "megasas-queue", 0x40000);
2347
4522b69c
HR		 2348 if (megasas_use_msi(s) &&
2349 msi_init(dev, 0x50, 1, true, false)) {
2350 s->flags &= ~MEGASAS_MASK_USE_MSI;
2351 }
e8f943c3 2352 if (megasas_use_msix(s) &&
e23d0498
HR		 2353 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2354 &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) {
e8f943c3
HR		 2355 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2356 }
e23d0498
HR		 2357 if (pci_is_express(dev)) {
2358 pcie_endpoint_cap_init(dev, 0xa0);
2359 }
e8f943c3
HR		 2360
2361 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
e23d0498
HR		 2362 pci_register_bar(dev, b->ioport_bar,
2363 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2364 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
52190c1e 2365 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2366
2367 if (megasas_use_msix(s)) {
52190c1e 2368 msix_vector_use(dev, 0);
e8f943c3
HR		 2369 }
2370
8d72db68 2371 s->fw_state = MFI_FWSTATE_READY;
76b523db
HR		 2372 if (!s->sas_addr) {
2373 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2374 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2375 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2376 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2377 s->sas_addr |= PCI_FUNC(dev->devfn);
2378 }
fb654157 2379 if (!s->hba_serial) {
23335f62 2380 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2381 }
e8f943c3
HR		 2382 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2383 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2384 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2385 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2386 } else {
2387 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2388 }
2389 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2390 s->fw_cmds = MEGASAS_MAX_FRAMES;
2391 }
2392 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3 2393 megasas_is_jbod(s) ? "jbod" : "raid");
3f2cd4dd
HR		 2394
2395 if (megasas_is_jbod(s)) {
2396 s->fw_luns = MFI_MAX_SYS_PDS;
2397 } else {
2398 s->fw_luns = MFI_MAX_LD;
2399 }
e8f943c3
HR		 2400 s->producer_pa = 0;
2401 s->consumer_pa = 0;
2402 for (i = 0; i < s->fw_cmds; i++) {
2403 s->frames[i].index = i;
2404 s->frames[i].context = -1;
2405 s->frames[i].pa = 0;
2406 s->frames[i].state = s;
2407 }
2408
b1187b51
AF		 2409 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2410 &megasas_scsi_info, NULL);
22d6aa03 2411 if (!d->hotplugged) {
caad4eb3
AF		 2412 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2413 if (err != NULL) {
2414 error_free(err);
2415 return -1;
2416 }
22d6aa03 2417 }
e8f943c3
HR		 2418 return 0;
2419}
2420
4522b69c
HR		 2421static void
2422megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
2423{
2424 pci_default_write_config(pci, addr, val, len);
2425 msi_write_config(pci, addr, val, len);
2426}
2427
e23d0498 2428static Property megasas_properties_gen1[] = {
e8f943c3
HR		 2429 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2430 MEGASAS_DEFAULT_SGE),
2431 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2432 MEGASAS_DEFAULT_FRAMES),
fb654157 2433 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2434 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
4522b69c
HR		 2435 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2436 MEGASAS_FLAG_USE_MSI, false),
e8f943c3
HR		 2437 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2438 MEGASAS_FLAG_USE_MSIX, false),
e8f943c3
HR		 2439 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2440 MEGASAS_FLAG_USE_JBOD, false),
2441 DEFINE_PROP_END_OF_LIST(),
2442};
2443
e23d0498
HR		 2444static Property megasas_properties_gen2[] = {
2445 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2446 MEGASAS_DEFAULT_SGE),
2447 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2448 MEGASAS_GEN2_DEFAULT_FRAMES),
2449 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2450 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2451 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2452 MEGASAS_FLAG_USE_MSI, true),
2453 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2454 MEGASAS_FLAG_USE_MSIX, true),
2455 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2456 MEGASAS_FLAG_USE_JBOD, false),
2457 DEFINE_PROP_END_OF_LIST(),
2458};
2459
2460typedef struct MegasasInfo {
2461 const char *name;
2462 const char *desc;
2463 const char *product_name;
2464 const char *product_version;
2465 uint16_t device_id;
2466 uint16_t subsystem_id;
2467 int ioport_bar;
2468 int mmio_bar;
2469 bool is_express;
2470 int osts;
2471 const VMStateDescription *vmsd;
2472 Property *props;
2473} MegasasInfo;
2474
2475static struct MegasasInfo megasas_devices[] = {
2476 {
2477 .name = TYPE_MEGASAS_GEN1,
2478 .desc = "LSI MegaRAID SAS 1078",
2479 .product_name = "LSI MegaRAID SAS 8708EM2",
2480 .product_version = MEGASAS_VERSION_GEN1,
2481 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2482 .subsystem_id = 0x1013,
2483 .ioport_bar = 2,
2484 .mmio_bar = 0,
2485 .osts = MFI_1078_RM | 1,
2486 .is_express = false,
2487 .vmsd = &vmstate_megasas_gen1,
2488 .props = megasas_properties_gen1,
2489 },{
2490 .name = TYPE_MEGASAS_GEN2,
2491 .desc = "LSI MegaRAID SAS 2108",
2492 .product_name = "LSI MegaRAID SAS 9260-8i",
2493 .product_version = MEGASAS_VERSION_GEN2,
2494 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2495 .subsystem_id = 0x9261,
2496 .ioport_bar = 0,
2497 .mmio_bar = 1,
2498 .osts = MFI_GEN2_RM,
2499 .is_express = true,
2500 .vmsd = &vmstate_megasas_gen2,
2501 .props = megasas_properties_gen2,
2502 }
2503};
2504
e8f943c3
HR		 2505static void megasas_class_init(ObjectClass *oc, void *data)
2506{
2507 DeviceClass *dc = DEVICE_CLASS(oc);
2508 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
e23d0498
HR		 2509 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2510 const MegasasInfo *info = data;
e8f943c3
HR		 2511
2512 pc->init = megasas_scsi_init;
2513 pc->exit = megasas_scsi_uninit;
2514 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2515 pc->device_id = info->device_id;
e8f943c3 2516 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2517 pc->subsystem_id = info->subsystem_id;
e8f943c3 2518 pc->class_id = PCI_CLASS_STORAGE_RAID;
e23d0498
HR		 2519 pc->is_express = info->is_express;
2520 e->mmio_bar = info->mmio_bar;
2521 e->ioport_bar = info->ioport_bar;
2522 e->osts = info->osts;
2523 e->product_name = info->product_name;
2524 e->product_version = info->product_version;
2525 dc->props = info->props;
e8f943c3 2526 dc->reset = megasas_scsi_reset;
e23d0498 2527 dc->vmsd = info->vmsd;
125ee0ed 2528 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e23d0498 2529 dc->desc = info->desc;
4522b69c 2530 pc->config_write = megasas_write_config;
e8f943c3
HR		 2531}
2532
2533static const TypeInfo megasas_info = {
e23d0498 2534 .name = TYPE_MEGASAS_BASE,
e8f943c3
HR		 2535 .parent = TYPE_PCI_DEVICE,
2536 .instance_size = sizeof(MegasasState),
e23d0498
HR		 2537 .class_size = sizeof(MegasasBaseClass),
2538 .abstract = true,
e8f943c3
HR		 2539};
2540
2541static void megasas_register_types(void)
2542{
e23d0498
HR		 2543 int i;
2544
e8f943c3 2545 type_register_static(&megasas_info);
e23d0498
HR		 2546 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2547 const MegasasInfo *info = &megasas_devices[i];
2548 TypeInfo type_info = {};
2549
2550 type_info.name = info->name;
2551 type_info.parent = TYPE_MEGASAS_BASE;
2552 type_info.class_data = (void *)info;
2553 type_info.class_init = megasas_class_init;
2554
2555 type_register(&type_info);
2556 }
e8f943c3
HR		 2557}
2558
2559type_init(megasas_register_types)
Empty description
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