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megasas: Rework frame queueing algorithm
[qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
9c17d615 23#include "sysemu/dma.h"
4be74634 24#include "sysemu/block-backend.h"
4522b69c 25#include "hw/pci/msi.h"
83c9f4ca 26#include "hw/pci/msix.h"
1de7afc9 27#include "qemu/iov.h"
0d09e41a
PB		 28#include "hw/scsi/scsi.h"
29#include "block/scsi.h"
e8f943c3
HR		 30#include "trace.h"
31
47b43a1f 32#include "mfi.h"
e8f943c3 33
e23d0498
HR		 34#define MEGASAS_VERSION_GEN1 "1.70"
35#define MEGASAS_VERSION_GEN2 "1.80"
e8f943c3
HR		 36#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
37#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
e23d0498 38#define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
e8f943c3
HR		 39#define MEGASAS_MAX_SGE 128 /* Firmware limit */
40#define MEGASAS_DEFAULT_SGE 80
41#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
42#define MEGASAS_MAX_ARRAYS 128
43
fb654157 44#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 45#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
46#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
47
e8f943c3
HR		 48#define MEGASAS_FLAG_USE_JBOD 0
49#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
4522b69c
HR		 50#define MEGASAS_FLAG_USE_MSI 1
51#define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI)
52#define MEGASAS_FLAG_USE_MSIX 2
e8f943c3 53#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
4522b69c 54#define MEGASAS_FLAG_USE_QUEUE64 3
e8f943c3
HR		 55#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
56
a97ad268 57static const char *mfi_frame_desc[] = {
e8f943c3
HR		 58 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
59 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
60
61typedef struct MegasasCmd {
62 uint32_t index;
63 uint16_t flags;
64 uint16_t count;
65 uint64_t context;
66
a8170e5e
AK		 67 hwaddr pa;
68 hwaddr pa_size;
e8f943c3
HR		 69 union mfi_frame *frame;
70 SCSIRequest *req;
71 QEMUSGList qsg;
72 void *iov_buf;
73 size_t iov_size;
74 size_t iov_offset;
75 struct MegasasState *state;
76} MegasasCmd;
77
78typedef struct MegasasState {
52190c1e
AF		 79 /*< private >*/
80 PCIDevice parent_obj;
81 /*< public >*/
82
e8f943c3
HR		 83 MemoryRegion mmio_io;
84 MemoryRegion port_io;
85 MemoryRegion queue_io;
86 uint32_t frame_hi;
87
88 int fw_state;
89 uint32_t fw_sge;
90 uint32_t fw_cmds;
91 uint32_t flags;
92 int fw_luns;
93 int intr_mask;
94 int doorbell;
95 int busy;
e23d0498
HR		 96 int diag;
97 int adp_reset;
e8f943c3
HR		 98
99 MegasasCmd *event_cmd;
100 int event_locale;
101 int event_class;
102 int event_count;
103 int shutdown_event;
104 int boot_event;
105
76b523db 106 uint64_t sas_addr;
fb654157 107 char *hba_serial;
76b523db 108
e8f943c3
HR		 109 uint64_t reply_queue_pa;
110 void *reply_queue;
111 int reply_queue_len;
112 int reply_queue_head;
113 int reply_queue_tail;
114 uint64_t consumer_pa;
115 uint64_t producer_pa;
116
117 MegasasCmd frames[MEGASAS_MAX_FRAMES];
6df5718b 118 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 119 SCSIBus bus;
120} MegasasState;
121
e23d0498
HR		 122typedef struct MegasasBaseClass {
123 PCIDeviceClass parent_class;
124 const char *product_name;
125 const char *product_version;
126 int mmio_bar;
127 int ioport_bar;
128 int osts;
129} MegasasBaseClass;
130
131#define TYPE_MEGASAS_BASE "megasas-base"
132#define TYPE_MEGASAS_GEN1 "megasas"
133#define TYPE_MEGASAS_GEN2 "megasas-gen2"
c79e16ae
PC		 134
135#define MEGASAS(obj) \
e23d0498
HR		 136 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
137
138#define MEGASAS_DEVICE_CLASS(oc) \
139 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
140#define MEGASAS_DEVICE_GET_CLASS(oc) \
141 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
c79e16ae 142
e8f943c3
HR		 143#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
144
145static bool megasas_intr_enabled(MegasasState *s)
146{
147 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
148 MEGASAS_INTR_DISABLED_MASK) {
149 return true;
150 }
151 return false;
152}
153
154static bool megasas_use_queue64(MegasasState *s)
155{
156 return s->flags & MEGASAS_MASK_USE_QUEUE64;
157}
158
4522b69c
HR		 159static bool megasas_use_msi(MegasasState *s)
160{
161 return s->flags & MEGASAS_MASK_USE_MSI;
162}
163
e8f943c3
HR		 164static bool megasas_use_msix(MegasasState *s)
165{
166 return s->flags & MEGASAS_MASK_USE_MSIX;
167}
168
169static bool megasas_is_jbod(MegasasState *s)
170{
171 return s->flags & MEGASAS_MASK_USE_JBOD;
172}
173
174static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
175{
db3be60d
EI		 176 stb_phys(&address_space_memory,
177 frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 178}
179
180static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
181{
db3be60d
EI		 182 stb_phys(&address_space_memory,
183 frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 184}
185
186/*
187 * Context is considered opaque, but the HBA firmware is running
188 * in little endian mode. So convert it to little endian, too.
189 */
190static uint64_t megasas_frame_get_context(unsigned long frame)
191{
2c17449b
EI		 192 return ldq_le_phys(&address_space_memory,
193 frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 194}
195
196static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
197{
198 return cmd->flags & MFI_FRAME_IEEE_SGL;
199}
200
201static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
202{
203 return cmd->flags & MFI_FRAME_SGL64;
204}
205
206static bool megasas_frame_is_sense64(MegasasCmd *cmd)
207{
208 return cmd->flags & MFI_FRAME_SENSE64;
209}
210
211static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
212 union mfi_sgl *sgl)
213{
214 uint64_t addr;
215
216 if (megasas_frame_is_ieee_sgl(cmd)) {
217 addr = le64_to_cpu(sgl->sg_skinny->addr);
218 } else if (megasas_frame_is_sgl64(cmd)) {
219 addr = le64_to_cpu(sgl->sg64->addr);
220 } else {
221 addr = le32_to_cpu(sgl->sg32->addr);
222 }
223 return addr;
224}
225
226static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
227 union mfi_sgl *sgl)
228{
229 uint32_t len;
230
231 if (megasas_frame_is_ieee_sgl(cmd)) {
232 len = le32_to_cpu(sgl->sg_skinny->len);
233 } else if (megasas_frame_is_sgl64(cmd)) {
234 len = le32_to_cpu(sgl->sg64->len);
235 } else {
236 len = le32_to_cpu(sgl->sg32->len);
237 }
238 return len;
239}
240
241static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
242 union mfi_sgl *sgl)
243{
244 uint8_t *next = (uint8_t *)sgl;
245
246 if (megasas_frame_is_ieee_sgl(cmd)) {
247 next += sizeof(struct mfi_sg_skinny);
248 } else if (megasas_frame_is_sgl64(cmd)) {
249 next += sizeof(struct mfi_sg64);
250 } else {
251 next += sizeof(struct mfi_sg32);
252 }
253
254 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
255 return NULL;
256 }
257 return (union mfi_sgl *)next;
258}
259
260static void megasas_soft_reset(MegasasState *s);
261
262static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
263{
264 int i;
265 int iov_count = 0;
266 size_t iov_size = 0;
267
268 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
269 iov_count = cmd->frame->header.sge_count;
270 if (iov_count > MEGASAS_MAX_SGE) {
271 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
272 MEGASAS_MAX_SGE);
273 return iov_count;
274 }
52190c1e 275 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 276 for (i = 0; i < iov_count; i++) {
277 dma_addr_t iov_pa, iov_size_p;
278
279 if (!sgl) {
280 trace_megasas_iovec_sgl_underflow(cmd->index, i);
281 goto unmap;
282 }
283 iov_pa = megasas_sgl_get_addr(cmd, sgl);
284 iov_size_p = megasas_sgl_get_len(cmd, sgl);
285 if (!iov_pa || !iov_size_p) {
286 trace_megasas_iovec_sgl_invalid(cmd->index, i,
287 iov_pa, iov_size_p);
288 goto unmap;
289 }
290 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
291 sgl = megasas_sgl_next(cmd, sgl);
292 iov_size += (size_t)iov_size_p;
293 }
294 if (cmd->iov_size > iov_size) {
295 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
296 } else if (cmd->iov_size < iov_size) {
297 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
298 }
299 cmd->iov_offset = 0;
300 return 0;
301unmap:
302 qemu_sglist_destroy(&cmd->qsg);
303 return iov_count - i;
304}
305
306static void megasas_unmap_sgl(MegasasCmd *cmd)
307{
308 qemu_sglist_destroy(&cmd->qsg);
309 cmd->iov_offset = 0;
310}
311
312/*
313 * passthrough sense and io sense are at the same offset
314 */
315static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
316 uint8_t sense_len)
317{
1016b239 318 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 319 uint32_t pa_hi = 0, pa_lo;
a8170e5e 320 hwaddr pa;
e8f943c3
HR		 321
322 if (sense_len > cmd->frame->header.sense_len) {
323 sense_len = cmd->frame->header.sense_len;
324 }
325 if (sense_len) {
326 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
327 if (megasas_frame_is_sense64(cmd)) {
328 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
329 }
330 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 331 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 332 cmd->frame->header.sense_len = sense_len;
333 }
334 return sense_len;
335}
336
337static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
338{
339 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
340 uint8_t sense_len = 18;
341
342 memset(sense_buf, 0, sense_len);
343 sense_buf[0] = 0xf0;
344 sense_buf[2] = sense.key;
345 sense_buf[7] = 10;
346 sense_buf[12] = sense.asc;
347 sense_buf[13] = sense.ascq;
348 megasas_build_sense(cmd, sense_buf, sense_len);
349}
350
351static void megasas_copy_sense(MegasasCmd *cmd)
352{
353 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
354 uint8_t sense_len;
355
356 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
357 SCSI_SENSE_BUF_SIZE);
358 megasas_build_sense(cmd, sense_buf, sense_len);
359}
360
361/*
362 * Format an INQUIRY CDB
363 */
364static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
365{
366 memset(cdb, 0, 6);
367 cdb[0] = INQUIRY;
368 if (pg > 0) {
369 cdb[1] = 0x1;
370 cdb[2] = pg;
371 }
372 cdb[3] = (len >> 8) & 0xff;
373 cdb[4] = (len & 0xff);
374 return len;
375}
376
377/*
378 * Encode lba and len into a READ_16/WRITE_16 CDB
379 */
380static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
381 uint32_t len, bool is_write)
382{
383 memset(cdb, 0x0, 16);
384 if (is_write) {
385 cdb[0] = WRITE_16;
386 } else {
387 cdb[0] = READ_16;
388 }
389 cdb[2] = (lba >> 56) & 0xff;
390 cdb[3] = (lba >> 48) & 0xff;
391 cdb[4] = (lba >> 40) & 0xff;
392 cdb[5] = (lba >> 32) & 0xff;
393 cdb[6] = (lba >> 24) & 0xff;
394 cdb[7] = (lba >> 16) & 0xff;
395 cdb[8] = (lba >> 8) & 0xff;
396 cdb[9] = (lba) & 0xff;
397 cdb[10] = (len >> 24) & 0xff;
398 cdb[11] = (len >> 16) & 0xff;
399 cdb[12] = (len >> 8) & 0xff;
400 cdb[13] = (len) & 0xff;
401}
402
403/*
404 * Utility functions
405 */
406static uint64_t megasas_fw_time(void)
407{
408 struct tm curtime;
409 uint64_t bcd_time;
410
411 qemu_get_timedate(&curtime, 0);
412 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
413 ((uint64_t)curtime.tm_min & 0xff) << 40 |
414 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
415 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
416 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
417 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
418
419 return bcd_time;
420}
421
76b523db
HR		 422/*
423 * Default disk sata address
424 * 0x1221 is the magic number as
425 * present in real hardware,
426 * so use it here, too.
427 */
428static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 429{
76b523db
HR		 430 uint64_t addr = (0x1221ULL << 48);
431 return addr & (id << 24);
e8f943c3
HR		 432}
433
434/*
435 * Frame handling
436 */
437static int megasas_next_index(MegasasState *s, int index, int limit)
438{
439 index++;
440 if (index == limit) {
441 index = 0;
442 }
443 return index;
444}
445
446static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 447 hwaddr frame)
e8f943c3
HR		 448{
449 MegasasCmd *cmd = NULL;
450 int num = 0, index;
451
452 index = s->reply_queue_head;
453
454 while (num < s->fw_cmds) {
455 if (s->frames[index].pa && s->frames[index].pa == frame) {
456 cmd = &s->frames[index];
457 break;
458 }
459 index = megasas_next_index(s, index, s->fw_cmds);
460 num++;
461 }
462
463 return cmd;
464}
465
6df5718b 466static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
e8f943c3 467{
6df5718b 468 PCIDevice *p = PCI_DEVICE(s);
e8f943c3 469
6df5718b
HR		 470 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
471 cmd->frame = NULL;
472 cmd->pa = 0;
473 clear_bit(cmd->index, s->frame_map);
e8f943c3
HR		 474}
475
6df5718b
HR		 476/*
477 * This absolutely needs to be locked if
478 * qemu ever goes multithreaded.
479 */
e8f943c3 480static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 481 hwaddr frame, uint64_t context, int count)
e8f943c3 482{
1016b239 483 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 484 MegasasCmd *cmd = NULL;
485 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 486 hwaddr frame_size_p = frame_size;
6df5718b 487 unsigned long index;
e8f943c3 488
6df5718b
HR		 489 index = 0;
490 while (index < s->fw_cmds) {
491 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
492 if (!s->frames[index].pa)
493 break;
494 /* Busy frame found */
495 trace_megasas_qf_mapped(index);
496 }
497 if (index >= s->fw_cmds) {
498 /* All frames busy */
499 trace_megasas_qf_busy(frame);
e8f943c3
HR		 500 return NULL;
501 }
6df5718b
HR		 502 cmd = &s->frames[index];
503 set_bit(index, s->frame_map);
504 trace_megasas_qf_new(index, frame);
505
506 cmd->pa = frame;
507 /* Map all possible frames */
508 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
509 if (frame_size_p != frame_size) {
510 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
511 if (cmd->frame) {
512 megasas_unmap_frame(s, cmd);
e8f943c3 513 }
6df5718b
HR		 514 s->event_count++;
515 return NULL;
516 }
517 cmd->pa_size = frame_size_p;
518 cmd->context = context;
519 if (!megasas_use_queue64(s)) {
520 cmd->context &= (uint64_t)0xFFFFFFFF;
e8f943c3
HR		 521 }
522 cmd->count = count;
523 s->busy++;
524
aaf2a859
HR		 525 if (s->consumer_pa) {
526 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
527 s->consumer_pa);
528 }
e8f943c3 529 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
aaf2a859 530 s->reply_queue_head, s->reply_queue_tail, s->busy);
e8f943c3
HR		 531
532 return cmd;
533}
534
535static void megasas_complete_frame(MegasasState *s, uint64_t context)
536{
52190c1e 537 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 538 int tail, queue_offset;
539
540 /* Decrement busy count */
541 s->busy--;
e8f943c3
HR		 542 if (s->reply_queue_pa) {
543 /*
544 * Put command on the reply queue.
545 * Context is opaque, but emulation is running in
546 * little endian. So convert it.
547 */
548 tail = s->reply_queue_head;
549 if (megasas_use_queue64(s)) {
550 queue_offset = tail * sizeof(uint64_t);
f606604f
EI		 551 stq_le_phys(&address_space_memory,
552 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 553 } else {
554 queue_offset = tail * sizeof(uint32_t);
ab1da857
EI		 555 stl_le_phys(&address_space_memory,
556 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 557 }
558 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
aaf2a859
HR		 559 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
560 s->consumer_pa);
561 trace_megasas_qf_complete(context, s->reply_queue_head,
562 s->reply_queue_tail, s->busy, s->doorbell);
e8f943c3
HR		 563 }
564
565 if (megasas_intr_enabled(s)) {
566 /* Notify HBA */
567 s->doorbell++;
568 if (s->doorbell == 1) {
52190c1e 569 if (msix_enabled(pci_dev)) {
e8f943c3 570 trace_megasas_msix_raise(0);
52190c1e 571 msix_notify(pci_dev, 0);
4522b69c
HR		 572 } else if (msi_enabled(pci_dev)) {
573 trace_megasas_msi_raise(0);
574 msi_notify(pci_dev, 0);
e8f943c3
HR		 575 } else {
576 trace_megasas_irq_raise();
9e64f8a3 577 pci_irq_assert(pci_dev);
e8f943c3
HR		 578 }
579 }
580 } else {
581 trace_megasas_qf_complete_noirq(context);
582 }
583}
584
585static void megasas_reset_frames(MegasasState *s)
586{
587 int i;
588 MegasasCmd *cmd;
589
590 for (i = 0; i < s->fw_cmds; i++) {
591 cmd = &s->frames[i];
592 if (cmd->pa) {
6df5718b 593 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 594 }
595 }
6df5718b 596 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 597}
598
599static void megasas_abort_command(MegasasCmd *cmd)
600{
601 if (cmd->req) {
e2b06058 602 scsi_req_cancel(cmd->req);
e8f943c3
HR		 603 cmd->req = NULL;
604 }
605}
606
607static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
608{
1016b239 609 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 610 uint32_t pa_hi, pa_lo;
96f8f23a
HR		 611 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
612 struct mfi_init_qinfo *initq = NULL;
e8f943c3
HR		 613 uint32_t flags;
614 int ret = MFI_STAT_OK;
615
96f8f23a
HR		 616 if (s->reply_queue_pa) {
617 trace_megasas_initq_mapped(s->reply_queue_pa);
618 goto out;
619 }
e8f943c3
HR		 620 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
621 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
622 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
623 trace_megasas_init_firmware((uint64_t)iq_pa);
1016b239 624 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 625 if (!initq || initq_size != sizeof(*initq)) {
626 trace_megasas_initq_map_failed(cmd->index);
627 s->event_count++;
628 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
629 goto out;
630 }
631 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
632 if (s->reply_queue_len > s->fw_cmds) {
633 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
634 s->event_count++;
635 ret = MFI_STAT_INVALID_PARAMETER;
636 goto out;
637 }
638 pa_lo = le32_to_cpu(initq->rq_addr_lo);
639 pa_hi = le32_to_cpu(initq->rq_addr_hi);
640 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
641 pa_lo = le32_to_cpu(initq->ci_addr_lo);
642 pa_hi = le32_to_cpu(initq->ci_addr_hi);
643 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
644 pa_lo = le32_to_cpu(initq->pi_addr_lo);
645 pa_hi = le32_to_cpu(initq->pi_addr_hi);
646 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
fdfba1a2
EI		 647 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
648 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
e8f943c3
HR		 649 flags = le32_to_cpu(initq->flags);
650 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
651 s->flags |= MEGASAS_MASK_USE_QUEUE64;
652 }
653 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
654 s->reply_queue_len, s->reply_queue_head,
655 s->reply_queue_tail, flags);
656 megasas_reset_frames(s);
657 s->fw_state = MFI_FWSTATE_OPERATIONAL;
658out:
659 if (initq) {
1016b239 660 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 661 }
662 return ret;
663}
664
665static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
666{
667 dma_addr_t iov_pa, iov_size;
668
669 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
670 if (!cmd->frame->header.sge_count) {
671 trace_megasas_dcmd_zero_sge(cmd->index);
672 cmd->iov_size = 0;
673 return 0;
674 } else if (cmd->frame->header.sge_count > 1) {
675 trace_megasas_dcmd_invalid_sge(cmd->index,
676 cmd->frame->header.sge_count);
677 cmd->iov_size = 0;
678 return -1;
679 }
680 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
681 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 682 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 683 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
684 cmd->iov_size = iov_size;
685 return cmd->iov_size;
686}
687
688static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
689{
690 trace_megasas_finish_dcmd(cmd->index, iov_size);
691
692 if (cmd->frame->header.sge_count) {
693 qemu_sglist_destroy(&cmd->qsg);
694 }
695 if (iov_size > cmd->iov_size) {
696 if (megasas_frame_is_ieee_sgl(cmd)) {
697 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
698 } else if (megasas_frame_is_sgl64(cmd)) {
699 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
700 } else {
701 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
702 }
703 }
704 cmd->iov_size = 0;
e8f943c3
HR		 705}
706
707static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
708{
52190c1e 709 PCIDevice *pci_dev = PCI_DEVICE(s);
e23d0498
HR		 710 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
711 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 712 struct mfi_ctrl_info info;
713 size_t dcmd_size = sizeof(info);
714 BusChild *kid;
3f2cd4dd 715 int num_pd_disks = 0;
e8f943c3
HR		 716
717 memset(&info, 0x0, cmd->iov_size);
718 if (cmd->iov_size < dcmd_size) {
719 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
720 dcmd_size);
721 return MFI_STAT_INVALID_PARAMETER;
722 }
723
e23d0498
HR		 724 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
725 info.pci.device = cpu_to_le16(pci_class->device_id);
726 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
727 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
e8f943c3 728
76b523db
HR		 729 /*
730 * For some reason the firmware supports
731 * only up to 8 device ports.
732 * Despite supporting a far larger number
733 * of devices for the physical devices.
734 * So just display the first 8 devices
735 * in the device port list, independent
736 * of how many logical devices are actually
737 * present.
738 */
739 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 740 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 741 info.device.port_count = 8;
742 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
743 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd 744 uint16_t pd_id;
76b523db 745
3f2cd4dd
HR		 746 if (num_pd_disks < 8) {
747 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
748 info.device.port_addr[num_pd_disks] =
749 cpu_to_le64(megasas_get_sata_addr(pd_id));
76b523db 750 }
3f2cd4dd 751 num_pd_disks++;
76b523db 752 }
e8f943c3 753
e23d0498 754 memcpy(info.product_name, base_class->product_name, 24);
fb654157 755 snprintf(info.serial_number, 32, "%s", s->hba_serial);
e8f943c3
HR		 756 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION);
757 memcpy(info.image_component[0].name, "APP", 3);
e23d0498
HR		 758 snprintf(info.image_component[0].version, 10, "%s-QEMU",
759 base_class->product_version);
5a7733b0
OH		 760 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
761 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 762 info.image_component_count = 1;
52190c1e 763 if (pci_dev->has_rom) {
e8f943c3
HR		 764 uint8_t biosver[32];
765 uint8_t *ptr;
766
52190c1e 767 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 768 memcpy(biosver, ptr + 0x41, 31);
e8f943c3
HR		 769 memcpy(info.image_component[1].name, "BIOS", 4);
770 memcpy(info.image_component[1].version, biosver,
771 strlen((const char *)biosver));
772 info.image_component_count++;
773 }
774 info.current_fw_time = cpu_to_le32(megasas_fw_time());
775 info.max_arms = 32;
776 info.max_spans = 8;
777 info.max_arrays = MEGASAS_MAX_ARRAYS;
3f2cd4dd 778 info.max_lds = MFI_MAX_LD;
e8f943c3
HR		 779 info.max_cmds = cpu_to_le16(s->fw_cmds);
780 info.max_sg_elements = cpu_to_le16(s->fw_sge);
781 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
3f2cd4dd
HR		 782 if (!megasas_is_jbod(s))
783 info.lds_present = cpu_to_le16(num_pd_disks);
784 info.pd_present = cpu_to_le16(num_pd_disks);
785 info.pd_disks_present = cpu_to_le16(num_pd_disks);
e8f943c3
HR		 786 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
787 MFI_INFO_HW_MEM |
788 MFI_INFO_HW_FLASH);
789 info.memory_size = cpu_to_le16(512);
790 info.nvram_size = cpu_to_le16(32);
791 info.flash_size = cpu_to_le16(16);
792 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
793 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
794 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
795 MFI_INFO_AOPS_MIXED_ARRAY);
796 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
797 MFI_INFO_LDOPS_ACCESS_POLICY |
798 MFI_INFO_LDOPS_IO_POLICY |
799 MFI_INFO_LDOPS_WRITE_POLICY |
800 MFI_INFO_LDOPS_READ_POLICY);
801 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
802 info.stripe_sz_ops.min = 3;
803 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1;
804 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
805 info.properties.intr_throttle_cnt = cpu_to_le16(16);
806 info.properties.intr_throttle_timeout = cpu_to_le16(50);
807 info.properties.rebuild_rate = 30;
808 info.properties.patrol_read_rate = 30;
809 info.properties.bgi_rate = 30;
810 info.properties.cc_rate = 30;
811 info.properties.recon_rate = 30;
812 info.properties.cache_flush_interval = 4;
813 info.properties.spinup_drv_cnt = 2;
814 info.properties.spinup_delay = 6;
815 info.properties.ecc_bucket_size = 15;
816 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
817 info.properties.expose_encl_devices = 1;
818 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
819 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
820 MFI_INFO_PDOPS_FORCE_OFFLINE);
821 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
822 MFI_INFO_PDMIX_SATA |
823 MFI_INFO_PDMIX_LD);
824
825 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
826 return MFI_STAT_OK;
827}
828
829static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
830{
831 struct mfi_defaults info;
832 size_t dcmd_size = sizeof(struct mfi_defaults);
833
834 memset(&info, 0x0, dcmd_size);
835 if (cmd->iov_size < dcmd_size) {
836 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
837 dcmd_size);
838 return MFI_STAT_INVALID_PARAMETER;
839 }
840
76b523db 841 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 842 info.stripe_size = 3;
843 info.flush_time = 4;
844 info.background_rate = 30;
845 info.allow_mix_in_enclosure = 1;
846 info.allow_mix_in_ld = 1;
847 info.direct_pd_mapping = 1;
848 /* Enable for BIOS support */
849 info.bios_enumerate_lds = 1;
850 info.disable_ctrl_r = 1;
851 info.expose_enclosure_devices = 1;
852 info.disable_preboot_cli = 1;
853 info.cluster_disable = 1;
854
855 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
856 return MFI_STAT_OK;
857}
858
859static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
860{
861 struct mfi_bios_data info;
862 size_t dcmd_size = sizeof(info);
863
864 memset(&info, 0x0, dcmd_size);
865 if (cmd->iov_size < dcmd_size) {
866 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
867 dcmd_size);
868 return MFI_STAT_INVALID_PARAMETER;
869 }
870 info.continue_on_error = 1;
871 info.verbose = 1;
872 if (megasas_is_jbod(s)) {
873 info.expose_all_drives = 1;
874 }
875
876 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
877 return MFI_STAT_OK;
878}
879
880static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
881{
882 uint64_t fw_time;
883 size_t dcmd_size = sizeof(fw_time);
884
885 fw_time = cpu_to_le64(megasas_fw_time());
886
887 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
888 return MFI_STAT_OK;
889}
890
891static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
892{
893 uint64_t fw_time;
894
895 /* This is a dummy; setting of firmware time is not allowed */
896 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
897
898 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
899 fw_time = cpu_to_le64(megasas_fw_time());
900 return MFI_STAT_OK;
901}
902
903static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
904{
905 struct mfi_evt_log_state info;
906 size_t dcmd_size = sizeof(info);
907
908 memset(&info, 0, dcmd_size);
909
910 info.newest_seq_num = cpu_to_le32(s->event_count);
911 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
912 info.boot_seq_num = cpu_to_le32(s->boot_event);
913
914 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
915 return MFI_STAT_OK;
916}
917
918static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
919{
920 union mfi_evt event;
921
922 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
923 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
924 sizeof(struct mfi_evt_detail));
925 return MFI_STAT_INVALID_PARAMETER;
926 }
927 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
928 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
929 s->event_locale = event.members.locale;
930 s->event_class = event.members.class;
931 s->event_cmd = cmd;
932 /* Decrease busy count; event frame doesn't count here */
933 s->busy--;
934 cmd->iov_size = sizeof(struct mfi_evt_detail);
935 return MFI_STAT_INVALID_STATUS;
936}
937
938static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
939{
940 struct mfi_pd_list info;
941 size_t dcmd_size = sizeof(info);
942 BusChild *kid;
943 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
e8f943c3
HR		 944
945 memset(&info, 0, dcmd_size);
946 offset = 8;
947 dcmd_limit = offset + sizeof(struct mfi_pd_address);
948 if (cmd->iov_size < dcmd_limit) {
949 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
950 dcmd_limit);
951 return MFI_STAT_INVALID_PARAMETER;
952 }
953
954 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
3f2cd4dd
HR		 955 if (max_pd_disks > MFI_MAX_SYS_PDS) {
956 max_pd_disks = MFI_MAX_SYS_PDS;
e8f943c3 957 }
e8f943c3
HR		 958 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
959 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd
HR		 960 uint16_t pd_id;
961
962 if (num_pd_disks >= max_pd_disks)
963 break;
e8f943c3 964
3f2cd4dd
HR		 965 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
966 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 967 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
968 info.addr[num_pd_disks].encl_index = 0;
3f2cd4dd 969 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
e8f943c3
HR		 970 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
971 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
972 info.addr[num_pd_disks].sas_addr[0] =
3f2cd4dd 973 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 974 num_pd_disks++;
975 offset += sizeof(struct mfi_pd_address);
976 }
977 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
978 max_pd_disks, offset);
979
980 info.size = cpu_to_le32(offset);
981 info.count = cpu_to_le32(num_pd_disks);
982
983 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
984 return MFI_STAT_OK;
985}
986
987static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
988{
989 uint16_t flags;
990
991 /* mbox0 contains flags */
992 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
993 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
994 if (flags == MR_PD_QUERY_TYPE_ALL ||
995 megasas_is_jbod(s)) {
996 return megasas_dcmd_pd_get_list(s, cmd);
997 }
998
999 return MFI_STAT_OK;
1000}
1001
1002static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1003 MegasasCmd *cmd)
1004{
1005 struct mfi_pd_info *info = cmd->iov_buf;
1006 size_t dcmd_size = sizeof(struct mfi_pd_info);
e8f943c3 1007 uint64_t pd_size;
3f2cd4dd 1008 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1009 uint8_t cmdbuf[6];
1010 SCSIRequest *req;
1011 size_t len, resid;
1012
1013 if (!cmd->iov_buf) {
1014 cmd->iov_buf = g_malloc(dcmd_size);
1015 memset(cmd->iov_buf, 0, dcmd_size);
1016 info = cmd->iov_buf;
1017 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1018 info->vpd_page83[0] = 0x7f;
1019 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1020 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1021 if (!req) {
1022 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1023 "PD get info std inquiry");
1024 g_free(cmd->iov_buf);
1025 cmd->iov_buf = NULL;
1026 return MFI_STAT_FLASH_ALLOC_FAIL;
1027 }
1028 trace_megasas_dcmd_internal_submit(cmd->index,
1029 "PD get info std inquiry", lun);
1030 len = scsi_req_enqueue(req);
1031 if (len > 0) {
1032 cmd->iov_size = len;
1033 scsi_req_continue(req);
1034 }
1035 return MFI_STAT_INVALID_STATUS;
1036 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1037 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1038 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1039 if (!req) {
1040 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1041 "PD get info vpd inquiry");
1042 return MFI_STAT_FLASH_ALLOC_FAIL;
1043 }
1044 trace_megasas_dcmd_internal_submit(cmd->index,
1045 "PD get info vpd inquiry", lun);
1046 len = scsi_req_enqueue(req);
1047 if (len > 0) {
1048 cmd->iov_size = len;
1049 scsi_req_continue(req);
1050 }
1051 return MFI_STAT_INVALID_STATUS;
1052 }
1053 /* Finished, set FW state */
1054 if ((info->inquiry_data[0] >> 5) == 0) {
1055 if (megasas_is_jbod(cmd->state)) {
1056 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1057 } else {
1058 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1059 }
1060 } else {
1061 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1062 }
1063
3f2cd4dd 1064 info->ref.v.device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 1065 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1066 MFI_PD_DDF_TYPE_INTF_SAS);
4be74634 1067 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1068 info->raw_size = cpu_to_le64(pd_size);
1069 info->non_coerced_size = cpu_to_le64(pd_size);
1070 info->coerced_size = cpu_to_le64(pd_size);
1071 info->encl_device_id = 0xFFFF;
1072 info->slot_number = (sdev->id & 0xFF);
1073 info->path_info.count = 1;
1074 info->path_info.sas_addr[0] =
3f2cd4dd 1075 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 1076 info->connected_port_bitmap = 0x1;
1077 info->device_speed = 1;
1078 info->link_speed = 1;
1079 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1080 g_free(cmd->iov_buf);
1081 cmd->iov_size = dcmd_size - resid;
1082 cmd->iov_buf = NULL;
1083 return MFI_STAT_OK;
1084}
1085
1086static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1087{
1088 size_t dcmd_size = sizeof(struct mfi_pd_info);
1089 uint16_t pd_id;
3f2cd4dd 1090 uint8_t target_id, lun_id;
e8f943c3
HR		 1091 SCSIDevice *sdev = NULL;
1092 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1093
1094 if (cmd->iov_size < dcmd_size) {
1095 return MFI_STAT_INVALID_PARAMETER;
1096 }
1097
1098 /* mbox0 has the ID */
1099 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
3f2cd4dd
HR		 1100 target_id = (pd_id >> 8) & 0xFF;
1101 lun_id = pd_id & 0xFF;
1102 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
e8f943c3
HR		 1103 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1104
1105 if (sdev) {
1106 /* Submit inquiry */
1107 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1108 }
1109
1110 return retval;
1111}
1112
1113static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1114{
1115 struct mfi_ld_list info;
1116 size_t dcmd_size = sizeof(info), resid;
3f2cd4dd 1117 uint32_t num_ld_disks = 0, max_ld_disks;
e8f943c3
HR		 1118 uint64_t ld_size;
1119 BusChild *kid;
1120
1121 memset(&info, 0, dcmd_size);
e74a4315 1122 if (cmd->iov_size > dcmd_size) {
e8f943c3
HR		 1123 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1124 dcmd_size);
1125 return MFI_STAT_INVALID_PARAMETER;
1126 }
1127
3f2cd4dd 1128 max_ld_disks = (cmd->iov_size - 8) / 16;
e8f943c3
HR		 1129 if (megasas_is_jbod(s)) {
1130 max_ld_disks = 0;
1131 }
3f2cd4dd
HR		 1132 if (max_ld_disks > MFI_MAX_LD) {
1133 max_ld_disks = MFI_MAX_LD;
1134 }
e8f943c3
HR		 1135 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1136 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
e8f943c3
HR		 1137
1138 if (num_ld_disks >= max_ld_disks) {
1139 break;
1140 }
1141 /* Logical device size is in blocks */
4be74634 1142 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1143 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1144 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1145 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1146 num_ld_disks++;
1147 }
1148 info.ld_count = cpu_to_le32(num_ld_disks);
1149 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1150
1151 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1152 cmd->iov_size = dcmd_size - resid;
1153 return MFI_STAT_OK;
1154}
1155
34bb4d02
HR		 1156static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1157{
1158 uint16_t flags;
d97ae368
HR		 1159 struct mfi_ld_targetid_list info;
1160 size_t dcmd_size = sizeof(info), resid;
1161 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1162 BusChild *kid;
34bb4d02
HR		 1163
1164 /* mbox0 contains flags */
1165 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1166 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
d97ae368
HR		 1167 if (flags != MR_LD_QUERY_TYPE_ALL &&
1168 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1169 max_ld_disks = 0;
1170 }
1171
1172 memset(&info, 0, dcmd_size);
1173 if (cmd->iov_size < 12) {
1174 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1175 dcmd_size);
1176 return MFI_STAT_INVALID_PARAMETER;
1177 }
1178 dcmd_size = sizeof(uint32_t) * 2 + 3;
3f2cd4dd 1179 max_ld_disks = cmd->iov_size - dcmd_size;
d97ae368
HR		 1180 if (megasas_is_jbod(s)) {
1181 max_ld_disks = 0;
34bb4d02 1182 }
3f2cd4dd
HR		 1183 if (max_ld_disks > MFI_MAX_LD) {
1184 max_ld_disks = MFI_MAX_LD;
1185 }
d97ae368
HR		 1186 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1187 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
34bb4d02 1188
d97ae368
HR		 1189 if (num_ld_disks >= max_ld_disks) {
1190 break;
1191 }
1192 info.targetid[num_ld_disks] = sdev->lun;
1193 num_ld_disks++;
1194 dcmd_size++;
1195 }
1196 info.ld_count = cpu_to_le32(num_ld_disks);
1197 info.size = dcmd_size;
1198 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1199
1200 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1201 cmd->iov_size = dcmd_size - resid;
34bb4d02
HR		 1202 return MFI_STAT_OK;
1203}
1204
e8f943c3
HR		 1205static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1206 MegasasCmd *cmd)
1207{
1208 struct mfi_ld_info *info = cmd->iov_buf;
1209 size_t dcmd_size = sizeof(struct mfi_ld_info);
1210 uint8_t cdb[6];
1211 SCSIRequest *req;
1212 ssize_t len, resid;
3f2cd4dd 1213 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1214 uint64_t ld_size;
1215
1216 if (!cmd->iov_buf) {
1217 cmd->iov_buf = g_malloc(dcmd_size);
1218 memset(cmd->iov_buf, 0x0, dcmd_size);
1219 info = cmd->iov_buf;
1220 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1221 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1222 if (!req) {
1223 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1224 "LD get info vpd inquiry");
1225 g_free(cmd->iov_buf);
1226 cmd->iov_buf = NULL;
1227 return MFI_STAT_FLASH_ALLOC_FAIL;
1228 }
1229 trace_megasas_dcmd_internal_submit(cmd->index,
1230 "LD get info vpd inquiry", lun);
1231 len = scsi_req_enqueue(req);
1232 if (len > 0) {
1233 cmd->iov_size = len;
1234 scsi_req_continue(req);
1235 }
1236 return MFI_STAT_INVALID_STATUS;
1237 }
1238
1239 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1240 info->ld_config.properties.ld.v.target_id = lun;
1241 info->ld_config.params.stripe_size = 3;
1242 info->ld_config.params.num_drives = 1;
1243 info->ld_config.params.is_consistent = 1;
1244 /* Logical device size is in blocks */
4be74634 1245 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1246 info->size = cpu_to_le64(ld_size);
1247 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1248 info->ld_config.span[0].start_block = 0;
1249 info->ld_config.span[0].num_blocks = info->size;
1250 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1251
1252 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1253 g_free(cmd->iov_buf);
1254 cmd->iov_size = dcmd_size - resid;
1255 cmd->iov_buf = NULL;
1256 return MFI_STAT_OK;
1257}
1258
1259static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1260{
1261 struct mfi_ld_info info;
1262 size_t dcmd_size = sizeof(info);
1263 uint16_t ld_id;
1264 uint32_t max_ld_disks = s->fw_luns;
1265 SCSIDevice *sdev = NULL;
1266 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1267
1268 if (cmd->iov_size < dcmd_size) {
1269 return MFI_STAT_INVALID_PARAMETER;
1270 }
1271
1272 /* mbox0 has the ID */
1273 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1274 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1275
1276 if (megasas_is_jbod(s)) {
1277 return MFI_STAT_DEVICE_NOT_FOUND;
1278 }
1279
1280 if (ld_id < max_ld_disks) {
1281 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1282 }
1283
1284 if (sdev) {
1285 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1286 }
1287
1288 return retval;
1289}
1290
1291static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1292{
1293 uint8_t data[4096];
1294 struct mfi_config_data *info;
1295 int num_pd_disks = 0, array_offset, ld_offset;
1296 BusChild *kid;
1297
1298 if (cmd->iov_size > 4096) {
1299 return MFI_STAT_INVALID_PARAMETER;
1300 }
1301
1302 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1303 num_pd_disks++;
1304 }
1305 info = (struct mfi_config_data *)&data;
1306 /*
1307 * Array mapping:
1308 * - One array per SCSI device
1309 * - One logical drive per SCSI device
1310 * spanning the entire device
1311 */
1312 info->array_count = num_pd_disks;
1313 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1314 info->log_drv_count = num_pd_disks;
1315 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1316 info->spares_count = 0;
1317 info->spares_size = sizeof(struct mfi_spare);
1318 info->size = sizeof(struct mfi_config_data) + info->array_size +
1319 info->log_drv_size;
1320 if (info->size > 4096) {
1321 return MFI_STAT_INVALID_PARAMETER;
1322 }
1323
1324 array_offset = sizeof(struct mfi_config_data);
1325 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1326
1327 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1328 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
3f2cd4dd 1329 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
e8f943c3
HR		 1330 struct mfi_array *array;
1331 struct mfi_ld_config *ld;
1332 uint64_t pd_size;
1333 int i;
1334
1335 array = (struct mfi_array *)(data + array_offset);
4be74634 1336 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1337 array->size = cpu_to_le64(pd_size);
1338 array->num_drives = 1;
1339 array->array_ref = cpu_to_le16(sdev_id);
1340 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1341 array->pd[0].ref.v.seq_num = 0;
1342 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1343 array->pd[0].encl.pd = 0xFF;
1344 array->pd[0].encl.slot = (sdev->id & 0xFF);
1345 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1346 array->pd[i].ref.v.device_id = 0xFFFF;
1347 array->pd[i].ref.v.seq_num = 0;
1348 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1349 array->pd[i].encl.pd = 0xFF;
1350 array->pd[i].encl.slot = 0xFF;
1351 }
1352 array_offset += sizeof(struct mfi_array);
1353 ld = (struct mfi_ld_config *)(data + ld_offset);
1354 memset(ld, 0, sizeof(struct mfi_ld_config));
3f2cd4dd 1355 ld->properties.ld.v.target_id = sdev->id;
e8f943c3
HR		 1356 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1357 MR_LD_CACHE_READ_ADAPTIVE;
1358 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1359 MR_LD_CACHE_READ_ADAPTIVE;
1360 ld->params.state = MFI_LD_STATE_OPTIMAL;
1361 ld->params.stripe_size = 3;
1362 ld->params.num_drives = 1;
1363 ld->params.span_depth = 1;
1364 ld->params.is_consistent = 1;
1365 ld->span[0].start_block = 0;
1366 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1367 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1368 ld_offset += sizeof(struct mfi_ld_config);
1369 }
1370
1371 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1372 return MFI_STAT_OK;
1373}
1374
1375static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1376{
1377 struct mfi_ctrl_props info;
1378 size_t dcmd_size = sizeof(info);
1379
1380 memset(&info, 0x0, dcmd_size);
1381 if (cmd->iov_size < dcmd_size) {
1382 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1383 dcmd_size);
1384 return MFI_STAT_INVALID_PARAMETER;
1385 }
1386 info.pred_fail_poll_interval = cpu_to_le16(300);
1387 info.intr_throttle_cnt = cpu_to_le16(16);
1388 info.intr_throttle_timeout = cpu_to_le16(50);
1389 info.rebuild_rate = 30;
1390 info.patrol_read_rate = 30;
1391 info.bgi_rate = 30;
1392 info.cc_rate = 30;
1393 info.recon_rate = 30;
1394 info.cache_flush_interval = 4;
1395 info.spinup_drv_cnt = 2;
1396 info.spinup_delay = 6;
1397 info.ecc_bucket_size = 15;
1398 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1399 info.expose_encl_devices = 1;
1400
1401 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1402 return MFI_STAT_OK;
1403}
1404
1405static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1406{
4be74634 1407 blk_drain_all();
e8f943c3
HR		 1408 return MFI_STAT_OK;
1409}
1410
1411static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1412{
1413 s->fw_state = MFI_FWSTATE_READY;
1414 return MFI_STAT_OK;
1415}
1416
200b6966 1417/* Some implementations use CLUSTER RESET LD to simulate a device reset */
e8f943c3
HR		 1418static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1419{
200b6966
HR		 1420 uint16_t target_id;
1421 int i;
1422
1423 /* mbox0 contains the device index */
1424 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1425 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1426 for (i = 0; i < s->fw_cmds; i++) {
1427 MegasasCmd *tmp_cmd = &s->frames[i];
1428 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1429 SCSIDevice *d = tmp_cmd->req->dev;
1430 qdev_reset_all(&d->qdev);
1431 }
1432 }
1433 return MFI_STAT_OK;
e8f943c3
HR		 1434}
1435
1436static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1437{
10d6530c
HR		 1438 struct mfi_ctrl_props info;
1439 size_t dcmd_size = sizeof(info);
1440
1441 if (cmd->iov_size < dcmd_size) {
1442 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1443 dcmd_size);
1444 return MFI_STAT_INVALID_PARAMETER;
1445 }
1446 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg);
1447 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1448 return MFI_STAT_OK;
1449}
1450
1451static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1452{
1453 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1454 return MFI_STAT_OK;
1455}
1456
1457static const struct dcmd_cmd_tbl_t {
1458 int opcode;
1459 const char *desc;
1460 int (*func)(MegasasState *s, MegasasCmd *cmd);
1461} dcmd_cmd_tbl[] = {
1462 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1463 megasas_dcmd_dummy },
1464 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1465 megasas_ctrl_get_info },
1466 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1467 megasas_dcmd_get_properties },
1468 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1469 megasas_dcmd_set_properties },
1470 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1471 megasas_dcmd_dummy },
1472 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1473 megasas_dcmd_dummy },
1474 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1475 megasas_dcmd_dummy },
1476 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1477 megasas_dcmd_dummy },
1478 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1479 megasas_dcmd_dummy },
1480 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1481 megasas_event_info },
1482 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1483 megasas_dcmd_dummy },
1484 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1485 megasas_event_wait },
1486 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1487 megasas_ctrl_shutdown },
1488 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1489 megasas_dcmd_dummy },
1490 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1491 megasas_dcmd_get_fw_time },
1492 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1493 megasas_dcmd_set_fw_time },
1494 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1495 megasas_dcmd_get_bios_info },
1496 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1497 megasas_dcmd_dummy },
1498 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1499 megasas_mfc_get_defaults },
1500 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1501 megasas_dcmd_dummy },
1502 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1503 megasas_cache_flush },
1504 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1505 megasas_dcmd_pd_get_list },
1506 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1507 megasas_dcmd_pd_list_query },
1508 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1509 megasas_dcmd_pd_get_info },
1510 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1511 megasas_dcmd_dummy },
1512 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1513 megasas_dcmd_dummy },
1514 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1515 megasas_dcmd_dummy },
1516 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1517 megasas_dcmd_dummy },
1518 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1519 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1520 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1521 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1522 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1523 megasas_dcmd_ld_get_info },
1524 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1525 megasas_dcmd_dummy },
1526 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1527 megasas_dcmd_dummy },
1528 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1529 megasas_dcmd_dummy },
1530 { MFI_DCMD_CFG_READ, "CFG_READ",
1531 megasas_dcmd_cfg_read },
1532 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1533 megasas_dcmd_dummy },
1534 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1535 megasas_dcmd_dummy },
1536 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1537 megasas_dcmd_dummy },
1538 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1539 megasas_dcmd_dummy },
1540 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1541 megasas_dcmd_dummy },
1542 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1543 megasas_dcmd_dummy },
1544 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1545 megasas_dcmd_dummy },
1546 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1547 megasas_dcmd_dummy },
1548 { MFI_DCMD_CLUSTER, "CLUSTER",
1549 megasas_dcmd_dummy },
1550 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1551 megasas_dcmd_dummy },
1552 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1553 megasas_cluster_reset_ld },
1554 { -1, NULL, NULL }
1555};
1556
1557static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1558{
1559 int opcode, len;
1560 int retval = 0;
1561 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1562
1563 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1564 trace_megasas_handle_dcmd(cmd->index, opcode);
1565 len = megasas_map_dcmd(s, cmd);
1566 if (len < 0) {
1567 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1568 }
1569 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1570 cmdptr++;
1571 }
1572 if (cmdptr->opcode == -1) {
1573 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1574 retval = megasas_dcmd_dummy(s, cmd);
1575 } else {
1576 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1577 retval = cmdptr->func(s, cmd);
1578 }
1579 if (retval != MFI_STAT_INVALID_STATUS) {
1580 megasas_finish_dcmd(cmd, len);
1581 }
1582 return retval;
1583}
1584
1585static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1586 SCSIRequest *req)
1587{
1588 int opcode;
1589 int retval = MFI_STAT_OK;
1590 int lun = req->lun;
1591
1592 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1593 scsi_req_unref(req);
1594 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1595 switch (opcode) {
1596 case MFI_DCMD_PD_GET_INFO:
1597 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1598 break;
1599 case MFI_DCMD_LD_GET_INFO:
1600 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1601 break;
1602 default:
1603 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1604 retval = MFI_STAT_INVALID_DCMD;
1605 break;
1606 }
1607 if (retval != MFI_STAT_INVALID_STATUS) {
1608 megasas_finish_dcmd(cmd, cmd->iov_size);
1609 }
1610 return retval;
1611}
1612
1613static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1614{
1615 int len;
1616
1617 len = scsi_req_enqueue(cmd->req);
1618 if (len < 0) {
1619 len = -len;
1620 }
1621 if (len > 0) {
1622 if (len > cmd->iov_size) {
1623 if (is_write) {
1624 trace_megasas_iov_write_overflow(cmd->index, len,
1625 cmd->iov_size);
1626 } else {
1627 trace_megasas_iov_read_overflow(cmd->index, len,
1628 cmd->iov_size);
1629 }
1630 }
1631 if (len < cmd->iov_size) {
1632 if (is_write) {
1633 trace_megasas_iov_write_underflow(cmd->index, len,
1634 cmd->iov_size);
1635 } else {
1636 trace_megasas_iov_read_underflow(cmd->index, len,
1637 cmd->iov_size);
1638 }
1639 cmd->iov_size = len;
1640 }
1641 scsi_req_continue(cmd->req);
1642 }
1643 return len;
1644}
1645
1646static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1647 bool is_logical)
1648{
1649 uint8_t *cdb;
e8f943c3
HR		 1650 bool is_write;
1651 struct SCSIDevice *sdev = NULL;
1652
1653 cdb = cmd->frame->pass.cdb;
1654
3f2cd4dd
HR		 1655 if (is_logical) {
1656 if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1657 cmd->frame->header.lun_id != 0) {
1658 trace_megasas_scsi_target_not_present(
1659 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1660 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1661 return MFI_STAT_DEVICE_NOT_FOUND;
1662 }
e8f943c3 1663 }
3f2cd4dd
HR		 1664 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1665 cmd->frame->header.lun_id);
1666
e8f943c3
HR		 1667 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1668 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1669 is_logical, cmd->frame->header.target_id,
1670 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1671
1672 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1673 trace_megasas_scsi_target_not_present(
1674 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1675 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1676 return MFI_STAT_DEVICE_NOT_FOUND;
1677 }
1678
1679 if (cmd->frame->header.cdb_len > 16) {
1680 trace_megasas_scsi_invalid_cdb_len(
1681 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1682 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1683 cmd->frame->header.cdb_len);
1684 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1685 cmd->frame->header.scsi_status = CHECK_CONDITION;
1686 s->event_count++;
1687 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1688 }
1689
1690 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1691 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1692 cmd->frame->header.scsi_status = CHECK_CONDITION;
1693 s->event_count++;
1694 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1695 }
1696
1697 cmd->req = scsi_req_new(sdev, cmd->index,
1698 cmd->frame->header.lun_id, cdb, cmd);
1699 if (!cmd->req) {
1700 trace_megasas_scsi_req_alloc_failed(
1701 mfi_frame_desc[cmd->frame->header.frame_cmd],
1702 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1703 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1704 cmd->frame->header.scsi_status = BUSY;
1705 s->event_count++;
1706 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1707 }
1708
1709 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
aaf2a859 1710 if (cmd->iov_size) {
e8f943c3 1711 if (is_write) {
aaf2a859 1712 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
e8f943c3 1713 } else {
aaf2a859 1714 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
e8f943c3
HR		 1715 }
1716 } else {
1717 trace_megasas_scsi_nodata(cmd->index);
1718 }
aaf2a859 1719 megasas_enqueue_req(cmd, is_write);
e8f943c3
HR		 1720 return MFI_STAT_INVALID_STATUS;
1721}
1722
1723static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1724{
1725 uint32_t lba_count, lba_start_hi, lba_start_lo;
1726 uint64_t lba_start;
1727 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1728 uint8_t cdb[16];
1729 int len;
1730 struct SCSIDevice *sdev = NULL;
1731
1732 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1733 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1734 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1735 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1736
3f2cd4dd
HR		 1737 if (cmd->frame->header.target_id < MFI_MAX_LD &&
1738 cmd->frame->header.lun_id == 0) {
e8f943c3
HR		 1739 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1740 cmd->frame->header.lun_id);
1741 }
1742
1743 trace_megasas_handle_io(cmd->index,
1744 mfi_frame_desc[cmd->frame->header.frame_cmd],
1745 cmd->frame->header.target_id,
1746 cmd->frame->header.lun_id,
1747 (unsigned long)lba_start, (unsigned long)lba_count);
1748 if (!sdev) {
1749 trace_megasas_io_target_not_present(cmd->index,
1750 mfi_frame_desc[cmd->frame->header.frame_cmd],
1751 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1752 return MFI_STAT_DEVICE_NOT_FOUND;
1753 }
1754
1755 if (cmd->frame->header.cdb_len > 16) {
1756 trace_megasas_scsi_invalid_cdb_len(
1757 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1758 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1759 cmd->frame->header.cdb_len);
1760 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1761 cmd->frame->header.scsi_status = CHECK_CONDITION;
1762 s->event_count++;
1763 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1764 }
1765
1766 cmd->iov_size = lba_count * sdev->blocksize;
1767 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1768 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1769 cmd->frame->header.scsi_status = CHECK_CONDITION;
1770 s->event_count++;
1771 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1772 }
1773
1774 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1775 cmd->req = scsi_req_new(sdev, cmd->index,
1776 cmd->frame->header.lun_id, cdb, cmd);
1777 if (!cmd->req) {
1778 trace_megasas_scsi_req_alloc_failed(
1779 mfi_frame_desc[cmd->frame->header.frame_cmd],
1780 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1781 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1782 cmd->frame->header.scsi_status = BUSY;
1783 s->event_count++;
1784 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1785 }
1786 len = megasas_enqueue_req(cmd, is_write);
1787 if (len > 0) {
1788 if (is_write) {
1789 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1790 } else {
1791 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1792 }
1793 }
1794 return MFI_STAT_INVALID_STATUS;
1795}
1796
1797static int megasas_finish_internal_command(MegasasCmd *cmd,
1798 SCSIRequest *req, size_t resid)
1799{
1800 int retval = MFI_STAT_INVALID_CMD;
1801
1802 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1803 cmd->iov_size -= resid;
1804 retval = megasas_finish_internal_dcmd(cmd, req);
1805 }
1806 return retval;
1807}
1808
1809static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1810{
1811 MegasasCmd *cmd = req->hba_private;
1812
1813 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1814 return NULL;
1815 } else {
1816 return &cmd->qsg;
1817 }
1818}
1819
1820static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1821{
1822 MegasasCmd *cmd = req->hba_private;
1823 uint8_t *buf;
1824 uint32_t opcode;
1825
1826 trace_megasas_io_complete(cmd->index, len);
1827
1828 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1829 scsi_req_continue(req);
1830 return;
1831 }
1832
1833 buf = scsi_req_get_buf(req);
1834 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1835 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1836 struct mfi_pd_info *info = cmd->iov_buf;
1837
1838 if (info->inquiry_data[0] == 0x7f) {
1839 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1840 memcpy(info->inquiry_data, buf, len);
1841 } else if (info->vpd_page83[0] == 0x7f) {
1842 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1843 memcpy(info->vpd_page83, buf, len);
1844 }
1845 scsi_req_continue(req);
1846 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1847 struct mfi_ld_info *info = cmd->iov_buf;
1848
1849 if (cmd->iov_buf) {
1850 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1851 scsi_req_continue(req);
1852 }
1853 }
1854}
1855
1856static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1857 size_t resid)
1858{
1859 MegasasCmd *cmd = req->hba_private;
1860 uint8_t cmd_status = MFI_STAT_OK;
1861
1862 trace_megasas_command_complete(cmd->index, status, resid);
1863
1864 if (cmd->req != req) {
1865 /*
1866 * Internal command complete
1867 */
1868 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1869 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1870 return;
1871 }
1872 } else {
1873 req->status = status;
1874 trace_megasas_scsi_complete(cmd->index, req->status,
1875 cmd->iov_size, req->cmd.xfer);
1876 if (req->status != GOOD) {
1877 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1878 }
1879 if (req->status == CHECK_CONDITION) {
1880 megasas_copy_sense(cmd);
1881 }
1882
1883 megasas_unmap_sgl(cmd);
1884 cmd->frame->header.scsi_status = req->status;
1885 scsi_req_unref(cmd->req);
1886 cmd->req = NULL;
1887 }
1888 cmd->frame->header.cmd_status = cmd_status;
6df5718b 1889 megasas_unmap_frame(cmd->state, cmd);
e8f943c3
HR		 1890 megasas_complete_frame(cmd->state, cmd->context);
1891}
1892
1893static void megasas_command_cancel(SCSIRequest *req)
1894{
1895 MegasasCmd *cmd = req->hba_private;
1896
1897 if (cmd) {
1898 megasas_abort_command(cmd);
1899 } else {
1900 scsi_req_unref(req);
1901 }
1902}
1903
1904static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1905{
1906 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1907 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1908 MegasasCmd *abort_cmd;
1909
1910 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1911 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1912 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1913
1914 abort_cmd = megasas_lookup_frame(s, abort_addr);
1915 if (!abort_cmd) {
1916 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1917 s->event_count++;
1918 return MFI_STAT_OK;
1919 }
1920 if (!megasas_use_queue64(s)) {
1921 abort_ctx &= (uint64_t)0xFFFFFFFF;
1922 }
1923 if (abort_cmd->context != abort_ctx) {
1924 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1925 abort_cmd->context);
1926 s->event_count++;
1927 return MFI_STAT_ABORT_NOT_POSSIBLE;
1928 }
1929 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1930 megasas_abort_command(abort_cmd);
1931 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1932 s->event_cmd = NULL;
1933 }
1934 s->event_count++;
1935 return MFI_STAT_OK;
1936}
1937
1938static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1939 uint32_t frame_count)
1940{
1941 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1942 uint64_t frame_context;
1943 MegasasCmd *cmd;
1944
1945 /*
1946 * Always read 64bit context, top bits will be
1947 * masked out if required in megasas_enqueue_frame()
1948 */
1949 frame_context = megasas_frame_get_context(frame_addr);
1950
1951 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1952 if (!cmd) {
1953 /* reply queue full */
1954 trace_megasas_frame_busy(frame_addr);
1955 megasas_frame_set_scsi_status(frame_addr, BUSY);
1956 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1957 megasas_complete_frame(s, frame_context);
1958 s->event_count++;
1959 return;
1960 }
1961 switch (cmd->frame->header.frame_cmd) {
1962 case MFI_CMD_INIT:
1963 frame_status = megasas_init_firmware(s, cmd);
1964 break;
1965 case MFI_CMD_DCMD:
1966 frame_status = megasas_handle_dcmd(s, cmd);
1967 break;
1968 case MFI_CMD_ABORT:
1969 frame_status = megasas_handle_abort(s, cmd);
1970 break;
1971 case MFI_CMD_PD_SCSI_IO:
1972 frame_status = megasas_handle_scsi(s, cmd, 0);
1973 break;
1974 case MFI_CMD_LD_SCSI_IO:
1975 frame_status = megasas_handle_scsi(s, cmd, 1);
1976 break;
1977 case MFI_CMD_LD_READ:
1978 case MFI_CMD_LD_WRITE:
1979 frame_status = megasas_handle_io(s, cmd);
1980 break;
1981 default:
1982 trace_megasas_unhandled_frame_cmd(cmd->index,
1983 cmd->frame->header.frame_cmd);
1984 s->event_count++;
1985 break;
1986 }
1987 if (frame_status != MFI_STAT_INVALID_STATUS) {
1988 if (cmd->frame) {
1989 cmd->frame->header.cmd_status = frame_status;
1990 } else {
1991 megasas_frame_set_cmd_status(frame_addr, frame_status);
1992 }
6df5718b 1993 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 1994 megasas_complete_frame(s, cmd->context);
1995 }
1996}
1997
a8170e5e 1998static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1999 unsigned size)
2000{
2001 MegasasState *s = opaque;
e23d0498
HR		 2002 PCIDevice *pci_dev = PCI_DEVICE(s);
2003 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2004 uint32_t retval = 0;
2005
2006 switch (addr) {
2007 case MFI_IDB:
2008 retval = 0;
77bb6b17 2009 trace_megasas_mmio_readl("MFI_IDB", retval);
e8f943c3
HR		 2010 break;
2011 case MFI_OMSG0:
2012 case MFI_OSP0:
e23d0498 2013 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
e8f943c3
HR		 2014 (s->fw_state & MFI_FWSTATE_MASK) |
2015 ((s->fw_sge & 0xff) << 16) |
2016 (s->fw_cmds & 0xFFFF);
77bb6b17
HR		 2017 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2018 retval);
e8f943c3
HR		 2019 break;
2020 case MFI_OSTS:
2021 if (megasas_intr_enabled(s) && s->doorbell) {
e23d0498 2022 retval = base_class->osts;
e8f943c3 2023 }
77bb6b17 2024 trace_megasas_mmio_readl("MFI_OSTS", retval);
e8f943c3
HR		 2025 break;
2026 case MFI_OMSK:
2027 retval = s->intr_mask;
77bb6b17 2028 trace_megasas_mmio_readl("MFI_OMSK", retval);
e8f943c3
HR		 2029 break;
2030 case MFI_ODCR0:
2031 retval = s->doorbell;
77bb6b17 2032 trace_megasas_mmio_readl("MFI_ODCR0", retval);
e8f943c3 2033 break;
e23d0498
HR		 2034 case MFI_DIAG:
2035 retval = s->diag;
77bb6b17 2036 trace_megasas_mmio_readl("MFI_DIAG", retval);
e23d0498
HR		 2037 break;
2038 case MFI_OSP1:
2039 retval = 15;
77bb6b17 2040 trace_megasas_mmio_readl("MFI_OSP1", retval);
e23d0498 2041 break;
e8f943c3
HR		 2042 default:
2043 trace_megasas_mmio_invalid_readl(addr);
2044 break;
2045 }
e8f943c3
HR		 2046 return retval;
2047}
2048
e23d0498
HR		 2049static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2050
a8170e5e 2051static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2052 uint64_t val, unsigned size)
2053{
2054 MegasasState *s = opaque;
52190c1e 2055 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 2056 uint64_t frame_addr;
2057 uint32_t frame_count;
2058 int i;
2059
e8f943c3
HR		 2060 switch (addr) {
2061 case MFI_IDB:
77bb6b17 2062 trace_megasas_mmio_writel("MFI_IDB", val);
e8f943c3
HR		 2063 if (val & MFI_FWINIT_ABORT) {
2064 /* Abort all pending cmds */
2065 for (i = 0; i < s->fw_cmds; i++) {
2066 megasas_abort_command(&s->frames[i]);
2067 }
2068 }
2069 if (val & MFI_FWINIT_READY) {
2070 /* move to FW READY */
2071 megasas_soft_reset(s);
2072 }
2073 if (val & MFI_FWINIT_MFIMODE) {
2074 /* discard MFIs */
2075 }
e23d0498
HR		 2076 if (val & MFI_FWINIT_STOP_ADP) {
2077 /* Terminal error, stop processing */
2078 s->fw_state = MFI_FWSTATE_FAULT;
2079 }
e8f943c3
HR		 2080 break;
2081 case MFI_OMSK:
77bb6b17 2082 trace_megasas_mmio_writel("MFI_OMSK", val);
e8f943c3 2083 s->intr_mask = val;
4522b69c
HR		 2084 if (!megasas_intr_enabled(s) &&
2085 !msi_enabled(pci_dev) &&
2086 !msix_enabled(pci_dev)) {
e8f943c3 2087 trace_megasas_irq_lower();
9e64f8a3 2088 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2089 }
2090 if (megasas_intr_enabled(s)) {
4522b69c
HR		 2091 if (msix_enabled(pci_dev)) {
2092 trace_megasas_msix_enabled(0);
2093 } else if (msi_enabled(pci_dev)) {
2094 trace_megasas_msi_enabled(0);
2095 } else {
2096 trace_megasas_intr_enabled();
2097 }
e8f943c3
HR		 2098 } else {
2099 trace_megasas_intr_disabled();
e23d0498 2100 megasas_soft_reset(s);
e8f943c3
HR		 2101 }
2102 break;
2103 case MFI_ODCR0:
77bb6b17 2104 trace_megasas_mmio_writel("MFI_ODCR0", val);
e8f943c3
HR		 2105 s->doorbell = 0;
2106 if (s->producer_pa && megasas_intr_enabled(s)) {
2107 /* Update reply queue pointer */
aaf2a859
HR		 2108 s->reply_queue_tail = ldl_le_phys(&address_space_memory,
2109 s->consumer_pa);
2110 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
2111 s->busy);
ab1da857
EI		 2112 stl_le_phys(&address_space_memory,
2113 s->producer_pa, s->reply_queue_head);
52190c1e 2114 if (!msix_enabled(pci_dev)) {
e8f943c3 2115 trace_megasas_irq_lower();
9e64f8a3 2116 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2117 }
2118 }
2119 break;
2120 case MFI_IQPH:
77bb6b17 2121 trace_megasas_mmio_writel("MFI_IQPH", val);
e8f943c3
HR		 2122 /* Received high 32 bits of a 64 bit MFI frame address */
2123 s->frame_hi = val;
2124 break;
2125 case MFI_IQPL:
77bb6b17 2126 trace_megasas_mmio_writel("MFI_IQPL", val);
e8f943c3 2127 /* Received low 32 bits of a 64 bit MFI frame address */
e23d0498 2128 /* Fallthrough */
e8f943c3 2129 case MFI_IQP:
77bb6b17
HR		 2130 if (addr == MFI_IQP) {
2131 trace_megasas_mmio_writel("MFI_IQP", val);
2132 /* Received 64 bit MFI frame address */
2133 s->frame_hi = 0;
2134 }
e8f943c3
HR		 2135 frame_addr = (val & ~0x1F);
2136 /* Add possible 64 bit offset */
2137 frame_addr |= ((uint64_t)s->frame_hi << 32);
2138 s->frame_hi = 0;
2139 frame_count = (val >> 1) & 0xF;
2140 megasas_handle_frame(s, frame_addr, frame_count);
2141 break;
e23d0498 2142 case MFI_SEQ:
77bb6b17 2143 trace_megasas_mmio_writel("MFI_SEQ", val);
e23d0498
HR		 2144 /* Magic sequence to start ADP reset */
2145 if (adp_reset_seq[s->adp_reset] == val) {
2146 s->adp_reset++;
2147 } else {
2148 s->adp_reset = 0;
2149 s->diag = 0;
2150 }
2151 if (s->adp_reset == 6) {
2152 s->diag = MFI_DIAG_WRITE_ENABLE;
2153 }
2154 break;
2155 case MFI_DIAG:
77bb6b17 2156 trace_megasas_mmio_writel("MFI_DIAG", val);
e23d0498
HR		 2157 /* ADP reset */
2158 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2159 (val & MFI_DIAG_RESET_ADP)) {
2160 s->diag |= MFI_DIAG_RESET_ADP;
2161 megasas_soft_reset(s);
2162 s->adp_reset = 0;
2163 s->diag = 0;
2164 }
2165 break;
e8f943c3
HR		 2166 default:
2167 trace_megasas_mmio_invalid_writel(addr, val);
2168 break;
2169 }
2170}
2171
2172static const MemoryRegionOps megasas_mmio_ops = {
2173 .read = megasas_mmio_read,
2174 .write = megasas_mmio_write,
2175 .endianness = DEVICE_LITTLE_ENDIAN,
2176 .impl = {
2177 .min_access_size = 8,
2178 .max_access_size = 8,
2179 }
2180};
2181
a8170e5e 2182static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2183 unsigned size)
2184{
2185 return megasas_mmio_read(opaque, addr & 0xff, size);
2186}
2187
a8170e5e 2188static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2189 uint64_t val, unsigned size)
2190{
2191 megasas_mmio_write(opaque, addr & 0xff, val, size);
2192}
2193
2194static const MemoryRegionOps megasas_port_ops = {
2195 .read = megasas_port_read,
2196 .write = megasas_port_write,
2197 .endianness = DEVICE_LITTLE_ENDIAN,
2198 .impl = {
2199 .min_access_size = 4,
2200 .max_access_size = 4,
2201 }
2202};
2203
a8170e5e 2204static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2205 unsigned size)
2206{
2207 return 0;
2208}
2209
2210static const MemoryRegionOps megasas_queue_ops = {
2211 .read = megasas_queue_read,
2212 .endianness = DEVICE_LITTLE_ENDIAN,
2213 .impl = {
2214 .min_access_size = 8,
2215 .max_access_size = 8,
2216 }
2217};
2218
2219static void megasas_soft_reset(MegasasState *s)
2220{
2221 int i;
2222 MegasasCmd *cmd;
2223
8d72db68 2224 trace_megasas_reset(s->fw_state);
e8f943c3
HR		 2225 for (i = 0; i < s->fw_cmds; i++) {
2226 cmd = &s->frames[i];
2227 megasas_abort_command(cmd);
2228 }
8d72db68
HR		 2229 if (s->fw_state == MFI_FWSTATE_READY) {
2230 BusChild *kid;
2231
2232 /*
2233 * The EFI firmware doesn't handle UA,
2234 * so we need to clear the Power On/Reset UA
2235 * after the initial reset.
2236 */
2237 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2238 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
2239
2240 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2241 scsi_device_unit_attention_reported(sdev);
2242 }
2243 }
e8f943c3
HR		 2244 megasas_reset_frames(s);
2245 s->reply_queue_len = s->fw_cmds;
2246 s->reply_queue_pa = 0;
2247 s->consumer_pa = 0;
2248 s->producer_pa = 0;
2249 s->fw_state = MFI_FWSTATE_READY;
2250 s->doorbell = 0;
2251 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2252 s->frame_hi = 0;
2253 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2254 s->event_count++;
2255 s->boot_event = s->event_count;
2256}
2257
2258static void megasas_scsi_reset(DeviceState *dev)
2259{
c79e16ae 2260 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2261
2262 megasas_soft_reset(s);
2263}
2264
e23d0498 2265static const VMStateDescription vmstate_megasas_gen1 = {
e8f943c3
HR		 2266 .name = "megasas",
2267 .version_id = 0,
2268 .minimum_version_id = 0,
d49805ae 2269 .fields = (VMStateField[]) {
52190c1e 2270 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2271 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2272
2273 VMSTATE_INT32(fw_state, MegasasState),
2274 VMSTATE_INT32(intr_mask, MegasasState),
2275 VMSTATE_INT32(doorbell, MegasasState),
2276 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2277 VMSTATE_UINT64(consumer_pa, MegasasState),
2278 VMSTATE_UINT64(producer_pa, MegasasState),
2279 VMSTATE_END_OF_LIST()
2280 }
2281};
2282
e23d0498
HR		 2283static const VMStateDescription vmstate_megasas_gen2 = {
2284 .name = "megasas-gen2",
2285 .version_id = 0,
2286 .minimum_version_id = 0,
2287 .minimum_version_id_old = 0,
2288 .fields = (VMStateField[]) {
2289 VMSTATE_PCIE_DEVICE(parent_obj, MegasasState),
2290 VMSTATE_MSIX(parent_obj, MegasasState),
2291
2292 VMSTATE_INT32(fw_state, MegasasState),
2293 VMSTATE_INT32(intr_mask, MegasasState),
2294 VMSTATE_INT32(doorbell, MegasasState),
2295 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2296 VMSTATE_UINT64(consumer_pa, MegasasState),
2297 VMSTATE_UINT64(producer_pa, MegasasState),
2298 VMSTATE_END_OF_LIST()
2299 }
2300};
2301
18fc611b 2302static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2303{
c79e16ae 2304 MegasasState *s = MEGASAS(d);
e8f943c3 2305
4522b69c
HR		 2306 if (megasas_use_msix(s)) {
2307 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2308 }
2309 if (megasas_use_msi(s)) {
2310 msi_uninit(d);
2311 }
e8f943c3
HR		 2312}
2313
2314static const struct SCSIBusInfo megasas_scsi_info = {
2315 .tcq = true,
2316 .max_target = MFI_MAX_LD,
2317 .max_lun = 255,
2318
2319 .transfer_data = megasas_xfer_complete,
2320 .get_sg_list = megasas_get_sg_list,
2321 .complete = megasas_command_complete,
2322 .cancel = megasas_command_cancel,
2323};
2324
2325static int megasas_scsi_init(PCIDevice *dev)
2326{
22d6aa03 2327 DeviceState *d = DEVICE(dev);
c79e16ae 2328 MegasasState *s = MEGASAS(dev);
e23d0498 2329 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2330 uint8_t *pci_conf;
2331 int i, bar_type;
caad4eb3 2332 Error *err = NULL;
e8f943c3 2333
52190c1e 2334 pci_conf = dev->config;
e8f943c3
HR		 2335
2336 /* PCI latency timer = 0 */
2337 pci_conf[PCI_LATENCY_TIMER] = 0;
2338 /* Interrupt pin 1 */
2339 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2340
29776739 2341 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2342 "megasas-mmio", 0x4000);
29776739 2343 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2344 "megasas-io", 256);
29776739 2345 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2346 "megasas-queue", 0x40000);
2347
4522b69c
HR		 2348 if (megasas_use_msi(s) &&
2349 msi_init(dev, 0x50, 1, true, false)) {
2350 s->flags &= ~MEGASAS_MASK_USE_MSI;
2351 }
e8f943c3 2352 if (megasas_use_msix(s) &&
e23d0498
HR		 2353 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2354 &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) {
e8f943c3
HR		 2355 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2356 }
e23d0498
HR		 2357 if (pci_is_express(dev)) {
2358 pcie_endpoint_cap_init(dev, 0xa0);
2359 }
e8f943c3
HR		 2360
2361 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
e23d0498
HR		 2362 pci_register_bar(dev, b->ioport_bar,
2363 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2364 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
52190c1e 2365 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2366
2367 if (megasas_use_msix(s)) {
52190c1e 2368 msix_vector_use(dev, 0);
e8f943c3
HR		 2369 }
2370
8d72db68 2371 s->fw_state = MFI_FWSTATE_READY;
76b523db
HR		 2372 if (!s->sas_addr) {
2373 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2374 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2375 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2376 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2377 s->sas_addr |= PCI_FUNC(dev->devfn);
2378 }
fb654157 2379 if (!s->hba_serial) {
23335f62 2380 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2381 }
e8f943c3
HR		 2382 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2383 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2384 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2385 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2386 } else {
2387 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2388 }
2389 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2390 s->fw_cmds = MEGASAS_MAX_FRAMES;
2391 }
2392 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3 2393 megasas_is_jbod(s) ? "jbod" : "raid");
3f2cd4dd
HR		 2394
2395 if (megasas_is_jbod(s)) {
2396 s->fw_luns = MFI_MAX_SYS_PDS;
2397 } else {
2398 s->fw_luns = MFI_MAX_LD;
2399 }
e8f943c3
HR		 2400 s->producer_pa = 0;
2401 s->consumer_pa = 0;
2402 for (i = 0; i < s->fw_cmds; i++) {
2403 s->frames[i].index = i;
2404 s->frames[i].context = -1;
2405 s->frames[i].pa = 0;
2406 s->frames[i].state = s;
2407 }
2408
b1187b51
AF		 2409 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2410 &megasas_scsi_info, NULL);
22d6aa03 2411 if (!d->hotplugged) {
caad4eb3
AF		 2412 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2413 if (err != NULL) {
2414 error_free(err);
2415 return -1;
2416 }
22d6aa03 2417 }
e8f943c3
HR		 2418 return 0;
2419}
2420
4522b69c
HR		 2421static void
2422megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
2423{
2424 pci_default_write_config(pci, addr, val, len);
2425 msi_write_config(pci, addr, val, len);
2426}
2427
e23d0498 2428static Property megasas_properties_gen1[] = {
e8f943c3
HR		 2429 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2430 MEGASAS_DEFAULT_SGE),
2431 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2432 MEGASAS_DEFAULT_FRAMES),
fb654157 2433 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2434 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
4522b69c
HR		 2435 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2436 MEGASAS_FLAG_USE_MSI, false),
e8f943c3
HR		 2437 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2438 MEGASAS_FLAG_USE_MSIX, false),
e8f943c3
HR		 2439 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2440 MEGASAS_FLAG_USE_JBOD, false),
2441 DEFINE_PROP_END_OF_LIST(),
2442};
2443
e23d0498
HR		 2444static Property megasas_properties_gen2[] = {
2445 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2446 MEGASAS_DEFAULT_SGE),
2447 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2448 MEGASAS_GEN2_DEFAULT_FRAMES),
2449 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2450 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2451 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2452 MEGASAS_FLAG_USE_MSI, true),
2453 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2454 MEGASAS_FLAG_USE_MSIX, true),
2455 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2456 MEGASAS_FLAG_USE_JBOD, false),
2457 DEFINE_PROP_END_OF_LIST(),
2458};
2459
2460typedef struct MegasasInfo {
2461 const char *name;
2462 const char *desc;
2463 const char *product_name;
2464 const char *product_version;
2465 uint16_t device_id;
2466 uint16_t subsystem_id;
2467 int ioport_bar;
2468 int mmio_bar;
2469 bool is_express;
2470 int osts;
2471 const VMStateDescription *vmsd;
2472 Property *props;
2473} MegasasInfo;
2474
2475static struct MegasasInfo megasas_devices[] = {
2476 {
2477 .name = TYPE_MEGASAS_GEN1,
2478 .desc = "LSI MegaRAID SAS 1078",
2479 .product_name = "LSI MegaRAID SAS 8708EM2",
2480 .product_version = MEGASAS_VERSION_GEN1,
2481 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2482 .subsystem_id = 0x1013,
2483 .ioport_bar = 2,
2484 .mmio_bar = 0,
2485 .osts = MFI_1078_RM | 1,
2486 .is_express = false,
2487 .vmsd = &vmstate_megasas_gen1,
2488 .props = megasas_properties_gen1,
2489 },{
2490 .name = TYPE_MEGASAS_GEN2,
2491 .desc = "LSI MegaRAID SAS 2108",
2492 .product_name = "LSI MegaRAID SAS 9260-8i",
2493 .product_version = MEGASAS_VERSION_GEN2,
2494 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2495 .subsystem_id = 0x9261,
2496 .ioport_bar = 0,
2497 .mmio_bar = 1,
2498 .osts = MFI_GEN2_RM,
2499 .is_express = true,
2500 .vmsd = &vmstate_megasas_gen2,
2501 .props = megasas_properties_gen2,
2502 }
2503};
2504
e8f943c3
HR		 2505static void megasas_class_init(ObjectClass *oc, void *data)
2506{
2507 DeviceClass *dc = DEVICE_CLASS(oc);
2508 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
e23d0498
HR		 2509 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2510 const MegasasInfo *info = data;
e8f943c3
HR		 2511
2512 pc->init = megasas_scsi_init;
2513 pc->exit = megasas_scsi_uninit;
2514 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2515 pc->device_id = info->device_id;
e8f943c3 2516 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2517 pc->subsystem_id = info->subsystem_id;
e8f943c3 2518 pc->class_id = PCI_CLASS_STORAGE_RAID;
e23d0498
HR		 2519 pc->is_express = info->is_express;
2520 e->mmio_bar = info->mmio_bar;
2521 e->ioport_bar = info->ioport_bar;
2522 e->osts = info->osts;
2523 e->product_name = info->product_name;
2524 e->product_version = info->product_version;
2525 dc->props = info->props;
e8f943c3 2526 dc->reset = megasas_scsi_reset;
e23d0498 2527 dc->vmsd = info->vmsd;
125ee0ed 2528 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e23d0498 2529 dc->desc = info->desc;
4522b69c 2530 pc->config_write = megasas_write_config;
e8f943c3
HR		 2531}
2532
2533static const TypeInfo megasas_info = {
e23d0498 2534 .name = TYPE_MEGASAS_BASE,
e8f943c3
HR		 2535 .parent = TYPE_PCI_DEVICE,
2536 .instance_size = sizeof(MegasasState),
e23d0498
HR		 2537 .class_size = sizeof(MegasasBaseClass),
2538 .abstract = true,
e8f943c3
HR		 2539};
2540
2541static void megasas_register_types(void)
2542{
e23d0498
HR		 2543 int i;
2544
e8f943c3 2545 type_register_static(&megasas_info);
e23d0498
HR		 2546 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2547 const MegasasInfo *info = &megasas_devices[i];
2548 TypeInfo type_info = {};
2549
2550 type_info.name = info->name;
2551 type_info.parent = TYPE_MEGASAS_BASE;
2552 type_info.class_data = (void *)info;
2553 type_info.class_init = megasas_class_init;
2554
2555 type_register(&type_info);
2556 }
e8f943c3
HR		 2557}
2558
2559type_init(megasas_register_types)
Empty description
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