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exec: Make lduw_*_phys input an AddressSpace
[qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
9c17d615 23#include "sysemu/dma.h"
83c9f4ca 24#include "hw/pci/msix.h"
1de7afc9 25#include "qemu/iov.h"
0d09e41a
PB		 26#include "hw/scsi/scsi.h"
27#include "block/scsi.h"
e8f943c3
HR		 28#include "trace.h"
29
47b43a1f 30#include "mfi.h"
e8f943c3
HR		 31
32#define MEGASAS_VERSION "1.70"
33#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
34#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
35#define MEGASAS_MAX_SGE 128 /* Firmware limit */
36#define MEGASAS_DEFAULT_SGE 80
37#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
38#define MEGASAS_MAX_ARRAYS 128
39
fb654157 40#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 41#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
42#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
43
e8f943c3
HR		 44#define MEGASAS_FLAG_USE_JBOD 0
45#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
46#define MEGASAS_FLAG_USE_MSIX 1
47#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
48#define MEGASAS_FLAG_USE_QUEUE64 2
49#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
50
a97ad268 51static const char *mfi_frame_desc[] = {
e8f943c3
HR		 52 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
53 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
54
55typedef struct MegasasCmd {
56 uint32_t index;
57 uint16_t flags;
58 uint16_t count;
59 uint64_t context;
60
a8170e5e
AK		 61 hwaddr pa;
62 hwaddr pa_size;
e8f943c3
HR		 63 union mfi_frame *frame;
64 SCSIRequest *req;
65 QEMUSGList qsg;
66 void *iov_buf;
67 size_t iov_size;
68 size_t iov_offset;
69 struct MegasasState *state;
70} MegasasCmd;
71
72typedef struct MegasasState {
52190c1e
AF		 73 /*< private >*/
74 PCIDevice parent_obj;
75 /*< public >*/
76
e8f943c3
HR		 77 MemoryRegion mmio_io;
78 MemoryRegion port_io;
79 MemoryRegion queue_io;
80 uint32_t frame_hi;
81
82 int fw_state;
83 uint32_t fw_sge;
84 uint32_t fw_cmds;
85 uint32_t flags;
86 int fw_luns;
87 int intr_mask;
88 int doorbell;
89 int busy;
90
91 MegasasCmd *event_cmd;
92 int event_locale;
93 int event_class;
94 int event_count;
95 int shutdown_event;
96 int boot_event;
97
76b523db 98 uint64_t sas_addr;
fb654157 99 char *hba_serial;
76b523db 100
e8f943c3
HR		 101 uint64_t reply_queue_pa;
102 void *reply_queue;
103 int reply_queue_len;
104 int reply_queue_head;
105 int reply_queue_tail;
106 uint64_t consumer_pa;
107 uint64_t producer_pa;
108
109 MegasasCmd frames[MEGASAS_MAX_FRAMES];
110
111 SCSIBus bus;
112} MegasasState;
113
c79e16ae
PC		 114#define TYPE_MEGASAS "megasas"
115
116#define MEGASAS(obj) \
117 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS)
118
e8f943c3
HR		 119#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
120
121static bool megasas_intr_enabled(MegasasState *s)
122{
123 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
124 MEGASAS_INTR_DISABLED_MASK) {
125 return true;
126 }
127 return false;
128}
129
130static bool megasas_use_queue64(MegasasState *s)
131{
132 return s->flags & MEGASAS_MASK_USE_QUEUE64;
133}
134
135static bool megasas_use_msix(MegasasState *s)
136{
137 return s->flags & MEGASAS_MASK_USE_MSIX;
138}
139
140static bool megasas_is_jbod(MegasasState *s)
141{
142 return s->flags & MEGASAS_MASK_USE_JBOD;
143}
144
145static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
146{
147 stb_phys(frame + offsetof(struct mfi_frame_header, cmd_status), v);
148}
149
150static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
151{
152 stb_phys(frame + offsetof(struct mfi_frame_header, scsi_status), v);
153}
154
155/*
156 * Context is considered opaque, but the HBA firmware is running
157 * in little endian mode. So convert it to little endian, too.
158 */
159static uint64_t megasas_frame_get_context(unsigned long frame)
160{
2c17449b
EI		 161 return ldq_le_phys(&address_space_memory,
162 frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 163}
164
165static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
166{
167 return cmd->flags & MFI_FRAME_IEEE_SGL;
168}
169
170static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
171{
172 return cmd->flags & MFI_FRAME_SGL64;
173}
174
175static bool megasas_frame_is_sense64(MegasasCmd *cmd)
176{
177 return cmd->flags & MFI_FRAME_SENSE64;
178}
179
180static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
181 union mfi_sgl *sgl)
182{
183 uint64_t addr;
184
185 if (megasas_frame_is_ieee_sgl(cmd)) {
186 addr = le64_to_cpu(sgl->sg_skinny->addr);
187 } else if (megasas_frame_is_sgl64(cmd)) {
188 addr = le64_to_cpu(sgl->sg64->addr);
189 } else {
190 addr = le32_to_cpu(sgl->sg32->addr);
191 }
192 return addr;
193}
194
195static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
196 union mfi_sgl *sgl)
197{
198 uint32_t len;
199
200 if (megasas_frame_is_ieee_sgl(cmd)) {
201 len = le32_to_cpu(sgl->sg_skinny->len);
202 } else if (megasas_frame_is_sgl64(cmd)) {
203 len = le32_to_cpu(sgl->sg64->len);
204 } else {
205 len = le32_to_cpu(sgl->sg32->len);
206 }
207 return len;
208}
209
210static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
211 union mfi_sgl *sgl)
212{
213 uint8_t *next = (uint8_t *)sgl;
214
215 if (megasas_frame_is_ieee_sgl(cmd)) {
216 next += sizeof(struct mfi_sg_skinny);
217 } else if (megasas_frame_is_sgl64(cmd)) {
218 next += sizeof(struct mfi_sg64);
219 } else {
220 next += sizeof(struct mfi_sg32);
221 }
222
223 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
224 return NULL;
225 }
226 return (union mfi_sgl *)next;
227}
228
229static void megasas_soft_reset(MegasasState *s);
230
231static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
232{
233 int i;
234 int iov_count = 0;
235 size_t iov_size = 0;
236
237 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
238 iov_count = cmd->frame->header.sge_count;
239 if (iov_count > MEGASAS_MAX_SGE) {
240 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
241 MEGASAS_MAX_SGE);
242 return iov_count;
243 }
52190c1e 244 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 245 for (i = 0; i < iov_count; i++) {
246 dma_addr_t iov_pa, iov_size_p;
247
248 if (!sgl) {
249 trace_megasas_iovec_sgl_underflow(cmd->index, i);
250 goto unmap;
251 }
252 iov_pa = megasas_sgl_get_addr(cmd, sgl);
253 iov_size_p = megasas_sgl_get_len(cmd, sgl);
254 if (!iov_pa || !iov_size_p) {
255 trace_megasas_iovec_sgl_invalid(cmd->index, i,
256 iov_pa, iov_size_p);
257 goto unmap;
258 }
259 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
260 sgl = megasas_sgl_next(cmd, sgl);
261 iov_size += (size_t)iov_size_p;
262 }
263 if (cmd->iov_size > iov_size) {
264 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
265 } else if (cmd->iov_size < iov_size) {
266 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
267 }
268 cmd->iov_offset = 0;
269 return 0;
270unmap:
271 qemu_sglist_destroy(&cmd->qsg);
272 return iov_count - i;
273}
274
275static void megasas_unmap_sgl(MegasasCmd *cmd)
276{
277 qemu_sglist_destroy(&cmd->qsg);
278 cmd->iov_offset = 0;
279}
280
281/*
282 * passthrough sense and io sense are at the same offset
283 */
284static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
285 uint8_t sense_len)
286{
287 uint32_t pa_hi = 0, pa_lo;
a8170e5e 288 hwaddr pa;
e8f943c3
HR		 289
290 if (sense_len > cmd->frame->header.sense_len) {
291 sense_len = cmd->frame->header.sense_len;
292 }
293 if (sense_len) {
294 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
295 if (megasas_frame_is_sense64(cmd)) {
296 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
297 }
298 pa = ((uint64_t) pa_hi << 32) | pa_lo;
299 cpu_physical_memory_write(pa, sense_ptr, sense_len);
300 cmd->frame->header.sense_len = sense_len;
301 }
302 return sense_len;
303}
304
305static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
306{
307 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
308 uint8_t sense_len = 18;
309
310 memset(sense_buf, 0, sense_len);
311 sense_buf[0] = 0xf0;
312 sense_buf[2] = sense.key;
313 sense_buf[7] = 10;
314 sense_buf[12] = sense.asc;
315 sense_buf[13] = sense.ascq;
316 megasas_build_sense(cmd, sense_buf, sense_len);
317}
318
319static void megasas_copy_sense(MegasasCmd *cmd)
320{
321 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
322 uint8_t sense_len;
323
324 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
325 SCSI_SENSE_BUF_SIZE);
326 megasas_build_sense(cmd, sense_buf, sense_len);
327}
328
329/*
330 * Format an INQUIRY CDB
331 */
332static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
333{
334 memset(cdb, 0, 6);
335 cdb[0] = INQUIRY;
336 if (pg > 0) {
337 cdb[1] = 0x1;
338 cdb[2] = pg;
339 }
340 cdb[3] = (len >> 8) & 0xff;
341 cdb[4] = (len & 0xff);
342 return len;
343}
344
345/*
346 * Encode lba and len into a READ_16/WRITE_16 CDB
347 */
348static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
349 uint32_t len, bool is_write)
350{
351 memset(cdb, 0x0, 16);
352 if (is_write) {
353 cdb[0] = WRITE_16;
354 } else {
355 cdb[0] = READ_16;
356 }
357 cdb[2] = (lba >> 56) & 0xff;
358 cdb[3] = (lba >> 48) & 0xff;
359 cdb[4] = (lba >> 40) & 0xff;
360 cdb[5] = (lba >> 32) & 0xff;
361 cdb[6] = (lba >> 24) & 0xff;
362 cdb[7] = (lba >> 16) & 0xff;
363 cdb[8] = (lba >> 8) & 0xff;
364 cdb[9] = (lba) & 0xff;
365 cdb[10] = (len >> 24) & 0xff;
366 cdb[11] = (len >> 16) & 0xff;
367 cdb[12] = (len >> 8) & 0xff;
368 cdb[13] = (len) & 0xff;
369}
370
371/*
372 * Utility functions
373 */
374static uint64_t megasas_fw_time(void)
375{
376 struct tm curtime;
377 uint64_t bcd_time;
378
379 qemu_get_timedate(&curtime, 0);
380 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
381 ((uint64_t)curtime.tm_min & 0xff) << 40 |
382 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
383 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
384 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
385 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
386
387 return bcd_time;
388}
389
76b523db
HR		 390/*
391 * Default disk sata address
392 * 0x1221 is the magic number as
393 * present in real hardware,
394 * so use it here, too.
395 */
396static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 397{
76b523db
HR		 398 uint64_t addr = (0x1221ULL << 48);
399 return addr & (id << 24);
e8f943c3
HR		 400}
401
402/*
403 * Frame handling
404 */
405static int megasas_next_index(MegasasState *s, int index, int limit)
406{
407 index++;
408 if (index == limit) {
409 index = 0;
410 }
411 return index;
412}
413
414static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 415 hwaddr frame)
e8f943c3
HR		 416{
417 MegasasCmd *cmd = NULL;
418 int num = 0, index;
419
420 index = s->reply_queue_head;
421
422 while (num < s->fw_cmds) {
423 if (s->frames[index].pa && s->frames[index].pa == frame) {
424 cmd = &s->frames[index];
425 break;
426 }
427 index = megasas_next_index(s, index, s->fw_cmds);
428 num++;
429 }
430
431 return cmd;
432}
433
434static MegasasCmd *megasas_next_frame(MegasasState *s,
a8170e5e 435 hwaddr frame)
e8f943c3
HR		 436{
437 MegasasCmd *cmd = NULL;
438 int num = 0, index;
439
440 cmd = megasas_lookup_frame(s, frame);
441 if (cmd) {
442 trace_megasas_qf_found(cmd->index, cmd->pa);
443 return cmd;
444 }
445 index = s->reply_queue_head;
446 num = 0;
447 while (num < s->fw_cmds) {
448 if (!s->frames[index].pa) {
449 cmd = &s->frames[index];
450 break;
451 }
452 index = megasas_next_index(s, index, s->fw_cmds);
453 num++;
454 }
455 if (!cmd) {
456 trace_megasas_qf_failed(frame);
457 }
458 trace_megasas_qf_new(index, cmd);
459 return cmd;
460}
461
462static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 463 hwaddr frame, uint64_t context, int count)
e8f943c3
HR		 464{
465 MegasasCmd *cmd = NULL;
466 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 467 hwaddr frame_size_p = frame_size;
e8f943c3
HR		 468
469 cmd = megasas_next_frame(s, frame);
470 /* All frames busy */
471 if (!cmd) {
472 return NULL;
473 }
474 if (!cmd->pa) {
475 cmd->pa = frame;
476 /* Map all possible frames */
477 cmd->frame = cpu_physical_memory_map(frame, &frame_size_p, 0);
478 if (frame_size_p != frame_size) {
479 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
480 if (cmd->frame) {
481 cpu_physical_memory_unmap(cmd->frame, frame_size_p, 0, 0);
482 cmd->frame = NULL;
483 cmd->pa = 0;
484 }
485 s->event_count++;
486 return NULL;
487 }
488 cmd->pa_size = frame_size_p;
489 cmd->context = context;
490 if (!megasas_use_queue64(s)) {
491 cmd->context &= (uint64_t)0xFFFFFFFF;
492 }
493 }
494 cmd->count = count;
495 s->busy++;
496
497 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
498 s->reply_queue_head, s->busy);
499
500 return cmd;
501}
502
503static void megasas_complete_frame(MegasasState *s, uint64_t context)
504{
52190c1e 505 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 506 int tail, queue_offset;
507
508 /* Decrement busy count */
509 s->busy--;
510
511 if (s->reply_queue_pa) {
512 /*
513 * Put command on the reply queue.
514 * Context is opaque, but emulation is running in
515 * little endian. So convert it.
516 */
517 tail = s->reply_queue_head;
518 if (megasas_use_queue64(s)) {
519 queue_offset = tail * sizeof(uint64_t);
520 stq_le_phys(s->reply_queue_pa + queue_offset, context);
521 } else {
522 queue_offset = tail * sizeof(uint32_t);
523 stl_le_phys(s->reply_queue_pa + queue_offset, context);
524 }
525 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
526 trace_megasas_qf_complete(context, tail, queue_offset,
527 s->busy, s->doorbell);
528 }
529
530 if (megasas_intr_enabled(s)) {
531 /* Notify HBA */
532 s->doorbell++;
533 if (s->doorbell == 1) {
52190c1e 534 if (msix_enabled(pci_dev)) {
e8f943c3 535 trace_megasas_msix_raise(0);
52190c1e 536 msix_notify(pci_dev, 0);
e8f943c3
HR		 537 } else {
538 trace_megasas_irq_raise();
9e64f8a3 539 pci_irq_assert(pci_dev);
e8f943c3
HR		 540 }
541 }
542 } else {
543 trace_megasas_qf_complete_noirq(context);
544 }
545}
546
547static void megasas_reset_frames(MegasasState *s)
548{
549 int i;
550 MegasasCmd *cmd;
551
552 for (i = 0; i < s->fw_cmds; i++) {
553 cmd = &s->frames[i];
554 if (cmd->pa) {
555 cpu_physical_memory_unmap(cmd->frame, cmd->pa_size, 0, 0);
556 cmd->frame = NULL;
557 cmd->pa = 0;
558 }
559 }
560}
561
562static void megasas_abort_command(MegasasCmd *cmd)
563{
564 if (cmd->req) {
e2b06058 565 scsi_req_cancel(cmd->req);
e8f943c3
HR		 566 cmd->req = NULL;
567 }
568}
569
570static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
571{
572 uint32_t pa_hi, pa_lo;
a8170e5e 573 hwaddr iq_pa, initq_size;
e8f943c3
HR		 574 struct mfi_init_qinfo *initq;
575 uint32_t flags;
576 int ret = MFI_STAT_OK;
577
578 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
579 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
580 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
581 trace_megasas_init_firmware((uint64_t)iq_pa);
582 initq_size = sizeof(*initq);
583 initq = cpu_physical_memory_map(iq_pa, &initq_size, 0);
584 if (!initq || initq_size != sizeof(*initq)) {
585 trace_megasas_initq_map_failed(cmd->index);
586 s->event_count++;
587 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
588 goto out;
589 }
590 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
591 if (s->reply_queue_len > s->fw_cmds) {
592 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
593 s->event_count++;
594 ret = MFI_STAT_INVALID_PARAMETER;
595 goto out;
596 }
597 pa_lo = le32_to_cpu(initq->rq_addr_lo);
598 pa_hi = le32_to_cpu(initq->rq_addr_hi);
599 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
600 pa_lo = le32_to_cpu(initq->ci_addr_lo);
601 pa_hi = le32_to_cpu(initq->ci_addr_hi);
602 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
603 pa_lo = le32_to_cpu(initq->pi_addr_lo);
604 pa_hi = le32_to_cpu(initq->pi_addr_hi);
605 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
fdfba1a2
EI		 606 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
607 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
e8f943c3
HR		 608 flags = le32_to_cpu(initq->flags);
609 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
610 s->flags |= MEGASAS_MASK_USE_QUEUE64;
611 }
612 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
613 s->reply_queue_len, s->reply_queue_head,
614 s->reply_queue_tail, flags);
615 megasas_reset_frames(s);
616 s->fw_state = MFI_FWSTATE_OPERATIONAL;
617out:
618 if (initq) {
619 cpu_physical_memory_unmap(initq, initq_size, 0, 0);
620 }
621 return ret;
622}
623
624static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
625{
626 dma_addr_t iov_pa, iov_size;
627
628 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
629 if (!cmd->frame->header.sge_count) {
630 trace_megasas_dcmd_zero_sge(cmd->index);
631 cmd->iov_size = 0;
632 return 0;
633 } else if (cmd->frame->header.sge_count > 1) {
634 trace_megasas_dcmd_invalid_sge(cmd->index,
635 cmd->frame->header.sge_count);
636 cmd->iov_size = 0;
637 return -1;
638 }
639 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
640 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 641 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 642 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
643 cmd->iov_size = iov_size;
644 return cmd->iov_size;
645}
646
647static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
648{
649 trace_megasas_finish_dcmd(cmd->index, iov_size);
650
651 if (cmd->frame->header.sge_count) {
652 qemu_sglist_destroy(&cmd->qsg);
653 }
654 if (iov_size > cmd->iov_size) {
655 if (megasas_frame_is_ieee_sgl(cmd)) {
656 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
657 } else if (megasas_frame_is_sgl64(cmd)) {
658 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
659 } else {
660 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
661 }
662 }
663 cmd->iov_size = 0;
e8f943c3
HR		 664}
665
666static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
667{
52190c1e 668 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 669 struct mfi_ctrl_info info;
670 size_t dcmd_size = sizeof(info);
671 BusChild *kid;
672 int num_ld_disks = 0;
76b523db 673 uint16_t sdev_id;
e8f943c3
HR		 674
675 memset(&info, 0x0, cmd->iov_size);
676 if (cmd->iov_size < dcmd_size) {
677 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
678 dcmd_size);
679 return MFI_STAT_INVALID_PARAMETER;
680 }
681
682 info.pci.vendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
683 info.pci.device = cpu_to_le16(PCI_DEVICE_ID_LSI_SAS1078);
684 info.pci.subvendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
685 info.pci.subdevice = cpu_to_le16(0x1013);
686
76b523db
HR		 687 /*
688 * For some reason the firmware supports
689 * only up to 8 device ports.
690 * Despite supporting a far larger number
691 * of devices for the physical devices.
692 * So just display the first 8 devices
693 * in the device port list, independent
694 * of how many logical devices are actually
695 * present.
696 */
697 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 698 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 699 info.device.port_count = 8;
700 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
701 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
702
703 if (num_ld_disks < 8) {
704 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
705 info.device.port_addr[num_ld_disks] =
706 cpu_to_le64(megasas_get_sata_addr(sdev_id));
707 }
708 num_ld_disks++;
709 }
e8f943c3
HR		 710
711 memcpy(info.product_name, "MegaRAID SAS 8708EM2", 20);
fb654157 712 snprintf(info.serial_number, 32, "%s", s->hba_serial);
e8f943c3
HR		 713 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION);
714 memcpy(info.image_component[0].name, "APP", 3);
715 memcpy(info.image_component[0].version, MEGASAS_VERSION "-QEMU", 9);
716 memcpy(info.image_component[0].build_date, __DATE__, 11);
717 memcpy(info.image_component[0].build_time, __TIME__, 8);
718 info.image_component_count = 1;
52190c1e 719 if (pci_dev->has_rom) {
e8f943c3
HR		 720 uint8_t biosver[32];
721 uint8_t *ptr;
722
52190c1e 723 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 724 memcpy(biosver, ptr + 0x41, 31);
e8f943c3
HR		 725 memcpy(info.image_component[1].name, "BIOS", 4);
726 memcpy(info.image_component[1].version, biosver,
727 strlen((const char *)biosver));
728 info.image_component_count++;
729 }
730 info.current_fw_time = cpu_to_le32(megasas_fw_time());
731 info.max_arms = 32;
732 info.max_spans = 8;
733 info.max_arrays = MEGASAS_MAX_ARRAYS;
734 info.max_lds = s->fw_luns;
735 info.max_cmds = cpu_to_le16(s->fw_cmds);
736 info.max_sg_elements = cpu_to_le16(s->fw_sge);
737 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
738 info.lds_present = cpu_to_le16(num_ld_disks);
739 info.pd_present = cpu_to_le16(num_ld_disks);
740 info.pd_disks_present = cpu_to_le16(num_ld_disks);
741 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
742 MFI_INFO_HW_MEM |
743 MFI_INFO_HW_FLASH);
744 info.memory_size = cpu_to_le16(512);
745 info.nvram_size = cpu_to_le16(32);
746 info.flash_size = cpu_to_le16(16);
747 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
748 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
749 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
750 MFI_INFO_AOPS_MIXED_ARRAY);
751 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
752 MFI_INFO_LDOPS_ACCESS_POLICY |
753 MFI_INFO_LDOPS_IO_POLICY |
754 MFI_INFO_LDOPS_WRITE_POLICY |
755 MFI_INFO_LDOPS_READ_POLICY);
756 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
757 info.stripe_sz_ops.min = 3;
758 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1;
759 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
760 info.properties.intr_throttle_cnt = cpu_to_le16(16);
761 info.properties.intr_throttle_timeout = cpu_to_le16(50);
762 info.properties.rebuild_rate = 30;
763 info.properties.patrol_read_rate = 30;
764 info.properties.bgi_rate = 30;
765 info.properties.cc_rate = 30;
766 info.properties.recon_rate = 30;
767 info.properties.cache_flush_interval = 4;
768 info.properties.spinup_drv_cnt = 2;
769 info.properties.spinup_delay = 6;
770 info.properties.ecc_bucket_size = 15;
771 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
772 info.properties.expose_encl_devices = 1;
773 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
774 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
775 MFI_INFO_PDOPS_FORCE_OFFLINE);
776 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
777 MFI_INFO_PDMIX_SATA |
778 MFI_INFO_PDMIX_LD);
779
780 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
781 return MFI_STAT_OK;
782}
783
784static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
785{
786 struct mfi_defaults info;
787 size_t dcmd_size = sizeof(struct mfi_defaults);
788
789 memset(&info, 0x0, dcmd_size);
790 if (cmd->iov_size < dcmd_size) {
791 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
792 dcmd_size);
793 return MFI_STAT_INVALID_PARAMETER;
794 }
795
76b523db 796 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 797 info.stripe_size = 3;
798 info.flush_time = 4;
799 info.background_rate = 30;
800 info.allow_mix_in_enclosure = 1;
801 info.allow_mix_in_ld = 1;
802 info.direct_pd_mapping = 1;
803 /* Enable for BIOS support */
804 info.bios_enumerate_lds = 1;
805 info.disable_ctrl_r = 1;
806 info.expose_enclosure_devices = 1;
807 info.disable_preboot_cli = 1;
808 info.cluster_disable = 1;
809
810 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
811 return MFI_STAT_OK;
812}
813
814static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
815{
816 struct mfi_bios_data info;
817 size_t dcmd_size = sizeof(info);
818
819 memset(&info, 0x0, dcmd_size);
820 if (cmd->iov_size < dcmd_size) {
821 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
822 dcmd_size);
823 return MFI_STAT_INVALID_PARAMETER;
824 }
825 info.continue_on_error = 1;
826 info.verbose = 1;
827 if (megasas_is_jbod(s)) {
828 info.expose_all_drives = 1;
829 }
830
831 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
832 return MFI_STAT_OK;
833}
834
835static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
836{
837 uint64_t fw_time;
838 size_t dcmd_size = sizeof(fw_time);
839
840 fw_time = cpu_to_le64(megasas_fw_time());
841
842 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
843 return MFI_STAT_OK;
844}
845
846static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
847{
848 uint64_t fw_time;
849
850 /* This is a dummy; setting of firmware time is not allowed */
851 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
852
853 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
854 fw_time = cpu_to_le64(megasas_fw_time());
855 return MFI_STAT_OK;
856}
857
858static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
859{
860 struct mfi_evt_log_state info;
861 size_t dcmd_size = sizeof(info);
862
863 memset(&info, 0, dcmd_size);
864
865 info.newest_seq_num = cpu_to_le32(s->event_count);
866 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
867 info.boot_seq_num = cpu_to_le32(s->boot_event);
868
869 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
870 return MFI_STAT_OK;
871}
872
873static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
874{
875 union mfi_evt event;
876
877 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
878 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
879 sizeof(struct mfi_evt_detail));
880 return MFI_STAT_INVALID_PARAMETER;
881 }
882 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
883 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
884 s->event_locale = event.members.locale;
885 s->event_class = event.members.class;
886 s->event_cmd = cmd;
887 /* Decrease busy count; event frame doesn't count here */
888 s->busy--;
889 cmd->iov_size = sizeof(struct mfi_evt_detail);
890 return MFI_STAT_INVALID_STATUS;
891}
892
893static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
894{
895 struct mfi_pd_list info;
896 size_t dcmd_size = sizeof(info);
897 BusChild *kid;
898 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
899 uint16_t sdev_id;
900
901 memset(&info, 0, dcmd_size);
902 offset = 8;
903 dcmd_limit = offset + sizeof(struct mfi_pd_address);
904 if (cmd->iov_size < dcmd_limit) {
905 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
906 dcmd_limit);
907 return MFI_STAT_INVALID_PARAMETER;
908 }
909
910 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
911 if (max_pd_disks > s->fw_luns) {
912 max_pd_disks = s->fw_luns;
913 }
914
915 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
916 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
917
918 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
919 info.addr[num_pd_disks].device_id = cpu_to_le16(sdev_id);
920 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
921 info.addr[num_pd_disks].encl_index = 0;
922 info.addr[num_pd_disks].slot_number = (sdev->id & 0xFF);
923 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
924 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
925 info.addr[num_pd_disks].sas_addr[0] =
76b523db 926 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 927 num_pd_disks++;
928 offset += sizeof(struct mfi_pd_address);
929 }
930 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
931 max_pd_disks, offset);
932
933 info.size = cpu_to_le32(offset);
934 info.count = cpu_to_le32(num_pd_disks);
935
936 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
937 return MFI_STAT_OK;
938}
939
940static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
941{
942 uint16_t flags;
943
944 /* mbox0 contains flags */
945 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
946 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
947 if (flags == MR_PD_QUERY_TYPE_ALL ||
948 megasas_is_jbod(s)) {
949 return megasas_dcmd_pd_get_list(s, cmd);
950 }
951
952 return MFI_STAT_OK;
953}
954
955static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
956 MegasasCmd *cmd)
957{
958 struct mfi_pd_info *info = cmd->iov_buf;
959 size_t dcmd_size = sizeof(struct mfi_pd_info);
960 BlockConf *conf = &sdev->conf;
961 uint64_t pd_size;
962 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
963 uint8_t cmdbuf[6];
964 SCSIRequest *req;
965 size_t len, resid;
966
967 if (!cmd->iov_buf) {
968 cmd->iov_buf = g_malloc(dcmd_size);
969 memset(cmd->iov_buf, 0, dcmd_size);
970 info = cmd->iov_buf;
971 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
972 info->vpd_page83[0] = 0x7f;
973 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
974 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
975 if (!req) {
976 trace_megasas_dcmd_req_alloc_failed(cmd->index,
977 "PD get info std inquiry");
978 g_free(cmd->iov_buf);
979 cmd->iov_buf = NULL;
980 return MFI_STAT_FLASH_ALLOC_FAIL;
981 }
982 trace_megasas_dcmd_internal_submit(cmd->index,
983 "PD get info std inquiry", lun);
984 len = scsi_req_enqueue(req);
985 if (len > 0) {
986 cmd->iov_size = len;
987 scsi_req_continue(req);
988 }
989 return MFI_STAT_INVALID_STATUS;
990 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
991 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
992 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
993 if (!req) {
994 trace_megasas_dcmd_req_alloc_failed(cmd->index,
995 "PD get info vpd inquiry");
996 return MFI_STAT_FLASH_ALLOC_FAIL;
997 }
998 trace_megasas_dcmd_internal_submit(cmd->index,
999 "PD get info vpd inquiry", lun);
1000 len = scsi_req_enqueue(req);
1001 if (len > 0) {
1002 cmd->iov_size = len;
1003 scsi_req_continue(req);
1004 }
1005 return MFI_STAT_INVALID_STATUS;
1006 }
1007 /* Finished, set FW state */
1008 if ((info->inquiry_data[0] >> 5) == 0) {
1009 if (megasas_is_jbod(cmd->state)) {
1010 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1011 } else {
1012 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1013 }
1014 } else {
1015 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1016 }
1017
1018 info->ref.v.device_id = cpu_to_le16(sdev_id);
1019 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1020 MFI_PD_DDF_TYPE_INTF_SAS);
1021 bdrv_get_geometry(conf->bs, &pd_size);
1022 info->raw_size = cpu_to_le64(pd_size);
1023 info->non_coerced_size = cpu_to_le64(pd_size);
1024 info->coerced_size = cpu_to_le64(pd_size);
1025 info->encl_device_id = 0xFFFF;
1026 info->slot_number = (sdev->id & 0xFF);
1027 info->path_info.count = 1;
1028 info->path_info.sas_addr[0] =
76b523db 1029 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 1030 info->connected_port_bitmap = 0x1;
1031 info->device_speed = 1;
1032 info->link_speed = 1;
1033 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1034 g_free(cmd->iov_buf);
1035 cmd->iov_size = dcmd_size - resid;
1036 cmd->iov_buf = NULL;
1037 return MFI_STAT_OK;
1038}
1039
1040static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1041{
1042 size_t dcmd_size = sizeof(struct mfi_pd_info);
1043 uint16_t pd_id;
1044 SCSIDevice *sdev = NULL;
1045 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1046
1047 if (cmd->iov_size < dcmd_size) {
1048 return MFI_STAT_INVALID_PARAMETER;
1049 }
1050
1051 /* mbox0 has the ID */
1052 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1053 sdev = scsi_device_find(&s->bus, 0, pd_id, 0);
1054 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1055
1056 if (sdev) {
1057 /* Submit inquiry */
1058 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1059 }
1060
1061 return retval;
1062}
1063
1064static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1065{
1066 struct mfi_ld_list info;
1067 size_t dcmd_size = sizeof(info), resid;
1068 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1069 uint64_t ld_size;
1070 BusChild *kid;
1071
1072 memset(&info, 0, dcmd_size);
1073 if (cmd->iov_size < dcmd_size) {
1074 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1075 dcmd_size);
1076 return MFI_STAT_INVALID_PARAMETER;
1077 }
1078
1079 if (megasas_is_jbod(s)) {
1080 max_ld_disks = 0;
1081 }
1082 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1083 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
1084 BlockConf *conf = &sdev->conf;
1085
1086 if (num_ld_disks >= max_ld_disks) {
1087 break;
1088 }
1089 /* Logical device size is in blocks */
1090 bdrv_get_geometry(conf->bs, &ld_size);
1091 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
4003e24f 1092 info.ld_list[num_ld_disks].ld.v.lun_id = sdev->lun;
e8f943c3
HR		 1093 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1094 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1095 num_ld_disks++;
1096 }
1097 info.ld_count = cpu_to_le32(num_ld_disks);
1098 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1099
1100 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1101 cmd->iov_size = dcmd_size - resid;
1102 return MFI_STAT_OK;
1103}
1104
1105static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1106 MegasasCmd *cmd)
1107{
1108 struct mfi_ld_info *info = cmd->iov_buf;
1109 size_t dcmd_size = sizeof(struct mfi_ld_info);
1110 uint8_t cdb[6];
1111 SCSIRequest *req;
1112 ssize_t len, resid;
1113 BlockConf *conf = &sdev->conf;
1114 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
1115 uint64_t ld_size;
1116
1117 if (!cmd->iov_buf) {
1118 cmd->iov_buf = g_malloc(dcmd_size);
1119 memset(cmd->iov_buf, 0x0, dcmd_size);
1120 info = cmd->iov_buf;
1121 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1122 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1123 if (!req) {
1124 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1125 "LD get info vpd inquiry");
1126 g_free(cmd->iov_buf);
1127 cmd->iov_buf = NULL;
1128 return MFI_STAT_FLASH_ALLOC_FAIL;
1129 }
1130 trace_megasas_dcmd_internal_submit(cmd->index,
1131 "LD get info vpd inquiry", lun);
1132 len = scsi_req_enqueue(req);
1133 if (len > 0) {
1134 cmd->iov_size = len;
1135 scsi_req_continue(req);
1136 }
1137 return MFI_STAT_INVALID_STATUS;
1138 }
1139
1140 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1141 info->ld_config.properties.ld.v.target_id = lun;
1142 info->ld_config.params.stripe_size = 3;
1143 info->ld_config.params.num_drives = 1;
1144 info->ld_config.params.is_consistent = 1;
1145 /* Logical device size is in blocks */
1146 bdrv_get_geometry(conf->bs, &ld_size);
1147 info->size = cpu_to_le64(ld_size);
1148 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1149 info->ld_config.span[0].start_block = 0;
1150 info->ld_config.span[0].num_blocks = info->size;
1151 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1152
1153 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1154 g_free(cmd->iov_buf);
1155 cmd->iov_size = dcmd_size - resid;
1156 cmd->iov_buf = NULL;
1157 return MFI_STAT_OK;
1158}
1159
1160static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1161{
1162 struct mfi_ld_info info;
1163 size_t dcmd_size = sizeof(info);
1164 uint16_t ld_id;
1165 uint32_t max_ld_disks = s->fw_luns;
1166 SCSIDevice *sdev = NULL;
1167 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1168
1169 if (cmd->iov_size < dcmd_size) {
1170 return MFI_STAT_INVALID_PARAMETER;
1171 }
1172
1173 /* mbox0 has the ID */
1174 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1175 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1176
1177 if (megasas_is_jbod(s)) {
1178 return MFI_STAT_DEVICE_NOT_FOUND;
1179 }
1180
1181 if (ld_id < max_ld_disks) {
1182 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1183 }
1184
1185 if (sdev) {
1186 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1187 }
1188
1189 return retval;
1190}
1191
1192static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1193{
1194 uint8_t data[4096];
1195 struct mfi_config_data *info;
1196 int num_pd_disks = 0, array_offset, ld_offset;
1197 BusChild *kid;
1198
1199 if (cmd->iov_size > 4096) {
1200 return MFI_STAT_INVALID_PARAMETER;
1201 }
1202
1203 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1204 num_pd_disks++;
1205 }
1206 info = (struct mfi_config_data *)&data;
1207 /*
1208 * Array mapping:
1209 * - One array per SCSI device
1210 * - One logical drive per SCSI device
1211 * spanning the entire device
1212 */
1213 info->array_count = num_pd_disks;
1214 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1215 info->log_drv_count = num_pd_disks;
1216 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1217 info->spares_count = 0;
1218 info->spares_size = sizeof(struct mfi_spare);
1219 info->size = sizeof(struct mfi_config_data) + info->array_size +
1220 info->log_drv_size;
1221 if (info->size > 4096) {
1222 return MFI_STAT_INVALID_PARAMETER;
1223 }
1224
1225 array_offset = sizeof(struct mfi_config_data);
1226 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1227
1228 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1229 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
1230 BlockConf *conf = &sdev->conf;
1231 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
1232 struct mfi_array *array;
1233 struct mfi_ld_config *ld;
1234 uint64_t pd_size;
1235 int i;
1236
1237 array = (struct mfi_array *)(data + array_offset);
1238 bdrv_get_geometry(conf->bs, &pd_size);
1239 array->size = cpu_to_le64(pd_size);
1240 array->num_drives = 1;
1241 array->array_ref = cpu_to_le16(sdev_id);
1242 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1243 array->pd[0].ref.v.seq_num = 0;
1244 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1245 array->pd[0].encl.pd = 0xFF;
1246 array->pd[0].encl.slot = (sdev->id & 0xFF);
1247 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1248 array->pd[i].ref.v.device_id = 0xFFFF;
1249 array->pd[i].ref.v.seq_num = 0;
1250 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1251 array->pd[i].encl.pd = 0xFF;
1252 array->pd[i].encl.slot = 0xFF;
1253 }
1254 array_offset += sizeof(struct mfi_array);
1255 ld = (struct mfi_ld_config *)(data + ld_offset);
1256 memset(ld, 0, sizeof(struct mfi_ld_config));
1257 ld->properties.ld.v.target_id = (sdev->id & 0xFF);
1258 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1259 MR_LD_CACHE_READ_ADAPTIVE;
1260 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1261 MR_LD_CACHE_READ_ADAPTIVE;
1262 ld->params.state = MFI_LD_STATE_OPTIMAL;
1263 ld->params.stripe_size = 3;
1264 ld->params.num_drives = 1;
1265 ld->params.span_depth = 1;
1266 ld->params.is_consistent = 1;
1267 ld->span[0].start_block = 0;
1268 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1269 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1270 ld_offset += sizeof(struct mfi_ld_config);
1271 }
1272
1273 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1274 return MFI_STAT_OK;
1275}
1276
1277static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1278{
1279 struct mfi_ctrl_props info;
1280 size_t dcmd_size = sizeof(info);
1281
1282 memset(&info, 0x0, dcmd_size);
1283 if (cmd->iov_size < dcmd_size) {
1284 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1285 dcmd_size);
1286 return MFI_STAT_INVALID_PARAMETER;
1287 }
1288 info.pred_fail_poll_interval = cpu_to_le16(300);
1289 info.intr_throttle_cnt = cpu_to_le16(16);
1290 info.intr_throttle_timeout = cpu_to_le16(50);
1291 info.rebuild_rate = 30;
1292 info.patrol_read_rate = 30;
1293 info.bgi_rate = 30;
1294 info.cc_rate = 30;
1295 info.recon_rate = 30;
1296 info.cache_flush_interval = 4;
1297 info.spinup_drv_cnt = 2;
1298 info.spinup_delay = 6;
1299 info.ecc_bucket_size = 15;
1300 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1301 info.expose_encl_devices = 1;
1302
1303 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1304 return MFI_STAT_OK;
1305}
1306
1307static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1308{
b618f4a1 1309 bdrv_drain_all();
e8f943c3
HR		 1310 return MFI_STAT_OK;
1311}
1312
1313static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1314{
1315 s->fw_state = MFI_FWSTATE_READY;
1316 return MFI_STAT_OK;
1317}
1318
1319static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1320{
1321 return MFI_STAT_INVALID_DCMD;
1322}
1323
1324static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1325{
10d6530c
HR		 1326 struct mfi_ctrl_props info;
1327 size_t dcmd_size = sizeof(info);
1328
1329 if (cmd->iov_size < dcmd_size) {
1330 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1331 dcmd_size);
1332 return MFI_STAT_INVALID_PARAMETER;
1333 }
1334 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg);
1335 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1336 return MFI_STAT_OK;
1337}
1338
1339static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1340{
1341 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1342 return MFI_STAT_OK;
1343}
1344
1345static const struct dcmd_cmd_tbl_t {
1346 int opcode;
1347 const char *desc;
1348 int (*func)(MegasasState *s, MegasasCmd *cmd);
1349} dcmd_cmd_tbl[] = {
1350 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1351 megasas_dcmd_dummy },
1352 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1353 megasas_ctrl_get_info },
1354 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1355 megasas_dcmd_get_properties },
1356 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1357 megasas_dcmd_set_properties },
1358 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1359 megasas_dcmd_dummy },
1360 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1361 megasas_dcmd_dummy },
1362 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1363 megasas_dcmd_dummy },
1364 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1365 megasas_dcmd_dummy },
1366 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1367 megasas_dcmd_dummy },
1368 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1369 megasas_event_info },
1370 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1371 megasas_dcmd_dummy },
1372 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1373 megasas_event_wait },
1374 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1375 megasas_ctrl_shutdown },
1376 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1377 megasas_dcmd_dummy },
1378 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1379 megasas_dcmd_get_fw_time },
1380 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1381 megasas_dcmd_set_fw_time },
1382 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1383 megasas_dcmd_get_bios_info },
1384 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1385 megasas_dcmd_dummy },
1386 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1387 megasas_mfc_get_defaults },
1388 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1389 megasas_dcmd_dummy },
1390 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1391 megasas_cache_flush },
1392 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1393 megasas_dcmd_pd_get_list },
1394 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1395 megasas_dcmd_pd_list_query },
1396 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1397 megasas_dcmd_pd_get_info },
1398 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1399 megasas_dcmd_dummy },
1400 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1401 megasas_dcmd_dummy },
1402 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1403 megasas_dcmd_dummy },
1404 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1405 megasas_dcmd_dummy },
1406 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1407 megasas_dcmd_ld_get_list},
1408 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1409 megasas_dcmd_ld_get_info },
1410 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1411 megasas_dcmd_dummy },
1412 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1413 megasas_dcmd_dummy },
1414 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1415 megasas_dcmd_dummy },
1416 { MFI_DCMD_CFG_READ, "CFG_READ",
1417 megasas_dcmd_cfg_read },
1418 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1419 megasas_dcmd_dummy },
1420 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1421 megasas_dcmd_dummy },
1422 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1423 megasas_dcmd_dummy },
1424 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1425 megasas_dcmd_dummy },
1426 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1427 megasas_dcmd_dummy },
1428 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1429 megasas_dcmd_dummy },
1430 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1431 megasas_dcmd_dummy },
1432 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1433 megasas_dcmd_dummy },
1434 { MFI_DCMD_CLUSTER, "CLUSTER",
1435 megasas_dcmd_dummy },
1436 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1437 megasas_dcmd_dummy },
1438 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1439 megasas_cluster_reset_ld },
1440 { -1, NULL, NULL }
1441};
1442
1443static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1444{
1445 int opcode, len;
1446 int retval = 0;
1447 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1448
1449 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1450 trace_megasas_handle_dcmd(cmd->index, opcode);
1451 len = megasas_map_dcmd(s, cmd);
1452 if (len < 0) {
1453 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1454 }
1455 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1456 cmdptr++;
1457 }
1458 if (cmdptr->opcode == -1) {
1459 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1460 retval = megasas_dcmd_dummy(s, cmd);
1461 } else {
1462 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1463 retval = cmdptr->func(s, cmd);
1464 }
1465 if (retval != MFI_STAT_INVALID_STATUS) {
1466 megasas_finish_dcmd(cmd, len);
1467 }
1468 return retval;
1469}
1470
1471static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1472 SCSIRequest *req)
1473{
1474 int opcode;
1475 int retval = MFI_STAT_OK;
1476 int lun = req->lun;
1477
1478 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1479 scsi_req_unref(req);
1480 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1481 switch (opcode) {
1482 case MFI_DCMD_PD_GET_INFO:
1483 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1484 break;
1485 case MFI_DCMD_LD_GET_INFO:
1486 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1487 break;
1488 default:
1489 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1490 retval = MFI_STAT_INVALID_DCMD;
1491 break;
1492 }
1493 if (retval != MFI_STAT_INVALID_STATUS) {
1494 megasas_finish_dcmd(cmd, cmd->iov_size);
1495 }
1496 return retval;
1497}
1498
1499static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1500{
1501 int len;
1502
1503 len = scsi_req_enqueue(cmd->req);
1504 if (len < 0) {
1505 len = -len;
1506 }
1507 if (len > 0) {
1508 if (len > cmd->iov_size) {
1509 if (is_write) {
1510 trace_megasas_iov_write_overflow(cmd->index, len,
1511 cmd->iov_size);
1512 } else {
1513 trace_megasas_iov_read_overflow(cmd->index, len,
1514 cmd->iov_size);
1515 }
1516 }
1517 if (len < cmd->iov_size) {
1518 if (is_write) {
1519 trace_megasas_iov_write_underflow(cmd->index, len,
1520 cmd->iov_size);
1521 } else {
1522 trace_megasas_iov_read_underflow(cmd->index, len,
1523 cmd->iov_size);
1524 }
1525 cmd->iov_size = len;
1526 }
1527 scsi_req_continue(cmd->req);
1528 }
1529 return len;
1530}
1531
1532static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1533 bool is_logical)
1534{
1535 uint8_t *cdb;
1536 int len;
1537 bool is_write;
1538 struct SCSIDevice *sdev = NULL;
1539
1540 cdb = cmd->frame->pass.cdb;
1541
1542 if (cmd->frame->header.target_id < s->fw_luns) {
1543 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1544 cmd->frame->header.lun_id);
1545 }
1546 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1547 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1548 is_logical, cmd->frame->header.target_id,
1549 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1550
1551 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1552 trace_megasas_scsi_target_not_present(
1553 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1554 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1555 return MFI_STAT_DEVICE_NOT_FOUND;
1556 }
1557
1558 if (cmd->frame->header.cdb_len > 16) {
1559 trace_megasas_scsi_invalid_cdb_len(
1560 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1561 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1562 cmd->frame->header.cdb_len);
1563 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1564 cmd->frame->header.scsi_status = CHECK_CONDITION;
1565 s->event_count++;
1566 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1567 }
1568
1569 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1570 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1571 cmd->frame->header.scsi_status = CHECK_CONDITION;
1572 s->event_count++;
1573 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1574 }
1575
1576 cmd->req = scsi_req_new(sdev, cmd->index,
1577 cmd->frame->header.lun_id, cdb, cmd);
1578 if (!cmd->req) {
1579 trace_megasas_scsi_req_alloc_failed(
1580 mfi_frame_desc[cmd->frame->header.frame_cmd],
1581 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1582 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1583 cmd->frame->header.scsi_status = BUSY;
1584 s->event_count++;
1585 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1586 }
1587
1588 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1589 len = megasas_enqueue_req(cmd, is_write);
1590 if (len > 0) {
1591 if (is_write) {
1592 trace_megasas_scsi_write_start(cmd->index, len);
1593 } else {
1594 trace_megasas_scsi_read_start(cmd->index, len);
1595 }
1596 } else {
1597 trace_megasas_scsi_nodata(cmd->index);
1598 }
1599 return MFI_STAT_INVALID_STATUS;
1600}
1601
1602static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1603{
1604 uint32_t lba_count, lba_start_hi, lba_start_lo;
1605 uint64_t lba_start;
1606 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1607 uint8_t cdb[16];
1608 int len;
1609 struct SCSIDevice *sdev = NULL;
1610
1611 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1612 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1613 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1614 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1615
1616 if (cmd->frame->header.target_id < s->fw_luns) {
1617 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1618 cmd->frame->header.lun_id);
1619 }
1620
1621 trace_megasas_handle_io(cmd->index,
1622 mfi_frame_desc[cmd->frame->header.frame_cmd],
1623 cmd->frame->header.target_id,
1624 cmd->frame->header.lun_id,
1625 (unsigned long)lba_start, (unsigned long)lba_count);
1626 if (!sdev) {
1627 trace_megasas_io_target_not_present(cmd->index,
1628 mfi_frame_desc[cmd->frame->header.frame_cmd],
1629 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1630 return MFI_STAT_DEVICE_NOT_FOUND;
1631 }
1632
1633 if (cmd->frame->header.cdb_len > 16) {
1634 trace_megasas_scsi_invalid_cdb_len(
1635 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1636 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1637 cmd->frame->header.cdb_len);
1638 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1639 cmd->frame->header.scsi_status = CHECK_CONDITION;
1640 s->event_count++;
1641 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1642 }
1643
1644 cmd->iov_size = lba_count * sdev->blocksize;
1645 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1646 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1647 cmd->frame->header.scsi_status = CHECK_CONDITION;
1648 s->event_count++;
1649 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1650 }
1651
1652 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1653 cmd->req = scsi_req_new(sdev, cmd->index,
1654 cmd->frame->header.lun_id, cdb, cmd);
1655 if (!cmd->req) {
1656 trace_megasas_scsi_req_alloc_failed(
1657 mfi_frame_desc[cmd->frame->header.frame_cmd],
1658 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1659 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1660 cmd->frame->header.scsi_status = BUSY;
1661 s->event_count++;
1662 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1663 }
1664 len = megasas_enqueue_req(cmd, is_write);
1665 if (len > 0) {
1666 if (is_write) {
1667 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1668 } else {
1669 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1670 }
1671 }
1672 return MFI_STAT_INVALID_STATUS;
1673}
1674
1675static int megasas_finish_internal_command(MegasasCmd *cmd,
1676 SCSIRequest *req, size_t resid)
1677{
1678 int retval = MFI_STAT_INVALID_CMD;
1679
1680 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1681 cmd->iov_size -= resid;
1682 retval = megasas_finish_internal_dcmd(cmd, req);
1683 }
1684 return retval;
1685}
1686
1687static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1688{
1689 MegasasCmd *cmd = req->hba_private;
1690
1691 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1692 return NULL;
1693 } else {
1694 return &cmd->qsg;
1695 }
1696}
1697
1698static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1699{
1700 MegasasCmd *cmd = req->hba_private;
1701 uint8_t *buf;
1702 uint32_t opcode;
1703
1704 trace_megasas_io_complete(cmd->index, len);
1705
1706 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1707 scsi_req_continue(req);
1708 return;
1709 }
1710
1711 buf = scsi_req_get_buf(req);
1712 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1713 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1714 struct mfi_pd_info *info = cmd->iov_buf;
1715
1716 if (info->inquiry_data[0] == 0x7f) {
1717 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1718 memcpy(info->inquiry_data, buf, len);
1719 } else if (info->vpd_page83[0] == 0x7f) {
1720 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1721 memcpy(info->vpd_page83, buf, len);
1722 }
1723 scsi_req_continue(req);
1724 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1725 struct mfi_ld_info *info = cmd->iov_buf;
1726
1727 if (cmd->iov_buf) {
1728 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1729 scsi_req_continue(req);
1730 }
1731 }
1732}
1733
1734static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1735 size_t resid)
1736{
1737 MegasasCmd *cmd = req->hba_private;
1738 uint8_t cmd_status = MFI_STAT_OK;
1739
1740 trace_megasas_command_complete(cmd->index, status, resid);
1741
1742 if (cmd->req != req) {
1743 /*
1744 * Internal command complete
1745 */
1746 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1747 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1748 return;
1749 }
1750 } else {
1751 req->status = status;
1752 trace_megasas_scsi_complete(cmd->index, req->status,
1753 cmd->iov_size, req->cmd.xfer);
1754 if (req->status != GOOD) {
1755 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1756 }
1757 if (req->status == CHECK_CONDITION) {
1758 megasas_copy_sense(cmd);
1759 }
1760
1761 megasas_unmap_sgl(cmd);
1762 cmd->frame->header.scsi_status = req->status;
1763 scsi_req_unref(cmd->req);
1764 cmd->req = NULL;
1765 }
1766 cmd->frame->header.cmd_status = cmd_status;
1767 megasas_complete_frame(cmd->state, cmd->context);
1768}
1769
1770static void megasas_command_cancel(SCSIRequest *req)
1771{
1772 MegasasCmd *cmd = req->hba_private;
1773
1774 if (cmd) {
1775 megasas_abort_command(cmd);
1776 } else {
1777 scsi_req_unref(req);
1778 }
1779}
1780
1781static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1782{
1783 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1784 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1785 MegasasCmd *abort_cmd;
1786
1787 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1788 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1789 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1790
1791 abort_cmd = megasas_lookup_frame(s, abort_addr);
1792 if (!abort_cmd) {
1793 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1794 s->event_count++;
1795 return MFI_STAT_OK;
1796 }
1797 if (!megasas_use_queue64(s)) {
1798 abort_ctx &= (uint64_t)0xFFFFFFFF;
1799 }
1800 if (abort_cmd->context != abort_ctx) {
1801 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1802 abort_cmd->context);
1803 s->event_count++;
1804 return MFI_STAT_ABORT_NOT_POSSIBLE;
1805 }
1806 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1807 megasas_abort_command(abort_cmd);
1808 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1809 s->event_cmd = NULL;
1810 }
1811 s->event_count++;
1812 return MFI_STAT_OK;
1813}
1814
1815static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1816 uint32_t frame_count)
1817{
1818 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1819 uint64_t frame_context;
1820 MegasasCmd *cmd;
1821
1822 /*
1823 * Always read 64bit context, top bits will be
1824 * masked out if required in megasas_enqueue_frame()
1825 */
1826 frame_context = megasas_frame_get_context(frame_addr);
1827
1828 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1829 if (!cmd) {
1830 /* reply queue full */
1831 trace_megasas_frame_busy(frame_addr);
1832 megasas_frame_set_scsi_status(frame_addr, BUSY);
1833 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1834 megasas_complete_frame(s, frame_context);
1835 s->event_count++;
1836 return;
1837 }
1838 switch (cmd->frame->header.frame_cmd) {
1839 case MFI_CMD_INIT:
1840 frame_status = megasas_init_firmware(s, cmd);
1841 break;
1842 case MFI_CMD_DCMD:
1843 frame_status = megasas_handle_dcmd(s, cmd);
1844 break;
1845 case MFI_CMD_ABORT:
1846 frame_status = megasas_handle_abort(s, cmd);
1847 break;
1848 case MFI_CMD_PD_SCSI_IO:
1849 frame_status = megasas_handle_scsi(s, cmd, 0);
1850 break;
1851 case MFI_CMD_LD_SCSI_IO:
1852 frame_status = megasas_handle_scsi(s, cmd, 1);
1853 break;
1854 case MFI_CMD_LD_READ:
1855 case MFI_CMD_LD_WRITE:
1856 frame_status = megasas_handle_io(s, cmd);
1857 break;
1858 default:
1859 trace_megasas_unhandled_frame_cmd(cmd->index,
1860 cmd->frame->header.frame_cmd);
1861 s->event_count++;
1862 break;
1863 }
1864 if (frame_status != MFI_STAT_INVALID_STATUS) {
1865 if (cmd->frame) {
1866 cmd->frame->header.cmd_status = frame_status;
1867 } else {
1868 megasas_frame_set_cmd_status(frame_addr, frame_status);
1869 }
1870 megasas_complete_frame(s, cmd->context);
1871 }
1872}
1873
a8170e5e 1874static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1875 unsigned size)
1876{
1877 MegasasState *s = opaque;
1878 uint32_t retval = 0;
1879
1880 switch (addr) {
1881 case MFI_IDB:
1882 retval = 0;
1883 break;
1884 case MFI_OMSG0:
1885 case MFI_OSP0:
1886 retval = (megasas_use_msix(s) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
1887 (s->fw_state & MFI_FWSTATE_MASK) |
1888 ((s->fw_sge & 0xff) << 16) |
1889 (s->fw_cmds & 0xFFFF);
1890 break;
1891 case MFI_OSTS:
1892 if (megasas_intr_enabled(s) && s->doorbell) {
1893 retval = MFI_1078_RM | 1;
1894 }
1895 break;
1896 case MFI_OMSK:
1897 retval = s->intr_mask;
1898 break;
1899 case MFI_ODCR0:
1900 retval = s->doorbell;
1901 break;
1902 default:
1903 trace_megasas_mmio_invalid_readl(addr);
1904 break;
1905 }
1906 trace_megasas_mmio_readl(addr, retval);
1907 return retval;
1908}
1909
a8170e5e 1910static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 1911 uint64_t val, unsigned size)
1912{
1913 MegasasState *s = opaque;
52190c1e 1914 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 1915 uint64_t frame_addr;
1916 uint32_t frame_count;
1917 int i;
1918
1919 trace_megasas_mmio_writel(addr, val);
1920 switch (addr) {
1921 case MFI_IDB:
1922 if (val & MFI_FWINIT_ABORT) {
1923 /* Abort all pending cmds */
1924 for (i = 0; i < s->fw_cmds; i++) {
1925 megasas_abort_command(&s->frames[i]);
1926 }
1927 }
1928 if (val & MFI_FWINIT_READY) {
1929 /* move to FW READY */
1930 megasas_soft_reset(s);
1931 }
1932 if (val & MFI_FWINIT_MFIMODE) {
1933 /* discard MFIs */
1934 }
1935 break;
1936 case MFI_OMSK:
1937 s->intr_mask = val;
52190c1e 1938 if (!megasas_intr_enabled(s) && !msix_enabled(pci_dev)) {
e8f943c3 1939 trace_megasas_irq_lower();
9e64f8a3 1940 pci_irq_deassert(pci_dev);
e8f943c3
HR		 1941 }
1942 if (megasas_intr_enabled(s)) {
1943 trace_megasas_intr_enabled();
1944 } else {
1945 trace_megasas_intr_disabled();
1946 }
1947 break;
1948 case MFI_ODCR0:
1949 s->doorbell = 0;
1950 if (s->producer_pa && megasas_intr_enabled(s)) {
1951 /* Update reply queue pointer */
1952 trace_megasas_qf_update(s->reply_queue_head, s->busy);
1953 stl_le_phys(s->producer_pa, s->reply_queue_head);
52190c1e 1954 if (!msix_enabled(pci_dev)) {
e8f943c3 1955 trace_megasas_irq_lower();
9e64f8a3 1956 pci_irq_deassert(pci_dev);
e8f943c3
HR		 1957 }
1958 }
1959 break;
1960 case MFI_IQPH:
1961 /* Received high 32 bits of a 64 bit MFI frame address */
1962 s->frame_hi = val;
1963 break;
1964 case MFI_IQPL:
1965 /* Received low 32 bits of a 64 bit MFI frame address */
1966 case MFI_IQP:
1967 /* Received 32 bit MFI frame address */
1968 frame_addr = (val & ~0x1F);
1969 /* Add possible 64 bit offset */
1970 frame_addr |= ((uint64_t)s->frame_hi << 32);
1971 s->frame_hi = 0;
1972 frame_count = (val >> 1) & 0xF;
1973 megasas_handle_frame(s, frame_addr, frame_count);
1974 break;
1975 default:
1976 trace_megasas_mmio_invalid_writel(addr, val);
1977 break;
1978 }
1979}
1980
1981static const MemoryRegionOps megasas_mmio_ops = {
1982 .read = megasas_mmio_read,
1983 .write = megasas_mmio_write,
1984 .endianness = DEVICE_LITTLE_ENDIAN,
1985 .impl = {
1986 .min_access_size = 8,
1987 .max_access_size = 8,
1988 }
1989};
1990
a8170e5e 1991static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1992 unsigned size)
1993{
1994 return megasas_mmio_read(opaque, addr & 0xff, size);
1995}
1996
a8170e5e 1997static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 1998 uint64_t val, unsigned size)
1999{
2000 megasas_mmio_write(opaque, addr & 0xff, val, size);
2001}
2002
2003static const MemoryRegionOps megasas_port_ops = {
2004 .read = megasas_port_read,
2005 .write = megasas_port_write,
2006 .endianness = DEVICE_LITTLE_ENDIAN,
2007 .impl = {
2008 .min_access_size = 4,
2009 .max_access_size = 4,
2010 }
2011};
2012
a8170e5e 2013static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2014 unsigned size)
2015{
2016 return 0;
2017}
2018
2019static const MemoryRegionOps megasas_queue_ops = {
2020 .read = megasas_queue_read,
2021 .endianness = DEVICE_LITTLE_ENDIAN,
2022 .impl = {
2023 .min_access_size = 8,
2024 .max_access_size = 8,
2025 }
2026};
2027
2028static void megasas_soft_reset(MegasasState *s)
2029{
2030 int i;
2031 MegasasCmd *cmd;
2032
2033 trace_megasas_reset();
2034 for (i = 0; i < s->fw_cmds; i++) {
2035 cmd = &s->frames[i];
2036 megasas_abort_command(cmd);
2037 }
2038 megasas_reset_frames(s);
2039 s->reply_queue_len = s->fw_cmds;
2040 s->reply_queue_pa = 0;
2041 s->consumer_pa = 0;
2042 s->producer_pa = 0;
2043 s->fw_state = MFI_FWSTATE_READY;
2044 s->doorbell = 0;
2045 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2046 s->frame_hi = 0;
2047 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2048 s->event_count++;
2049 s->boot_event = s->event_count;
2050}
2051
2052static void megasas_scsi_reset(DeviceState *dev)
2053{
c79e16ae 2054 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2055
2056 megasas_soft_reset(s);
2057}
2058
2059static const VMStateDescription vmstate_megasas = {
2060 .name = "megasas",
2061 .version_id = 0,
2062 .minimum_version_id = 0,
2063 .minimum_version_id_old = 0,
2064 .fields = (VMStateField[]) {
52190c1e 2065 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
e8f943c3
HR		 2066
2067 VMSTATE_INT32(fw_state, MegasasState),
2068 VMSTATE_INT32(intr_mask, MegasasState),
2069 VMSTATE_INT32(doorbell, MegasasState),
2070 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2071 VMSTATE_UINT64(consumer_pa, MegasasState),
2072 VMSTATE_UINT64(producer_pa, MegasasState),
2073 VMSTATE_END_OF_LIST()
2074 }
2075};
2076
18fc611b 2077static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2078{
c79e16ae 2079 MegasasState *s = MEGASAS(d);
e8f943c3
HR		 2080
2081#ifdef USE_MSIX
52190c1e 2082 msix_uninit(d, &s->mmio_io);
e8f943c3
HR		 2083#endif
2084 memory_region_destroy(&s->mmio_io);
2085 memory_region_destroy(&s->port_io);
2086 memory_region_destroy(&s->queue_io);
e8f943c3
HR		 2087}
2088
2089static const struct SCSIBusInfo megasas_scsi_info = {
2090 .tcq = true,
2091 .max_target = MFI_MAX_LD,
2092 .max_lun = 255,
2093
2094 .transfer_data = megasas_xfer_complete,
2095 .get_sg_list = megasas_get_sg_list,
2096 .complete = megasas_command_complete,
2097 .cancel = megasas_command_cancel,
2098};
2099
2100static int megasas_scsi_init(PCIDevice *dev)
2101{
22d6aa03 2102 DeviceState *d = DEVICE(dev);
c79e16ae 2103 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2104 uint8_t *pci_conf;
2105 int i, bar_type;
caad4eb3 2106 Error *err = NULL;
e8f943c3 2107
52190c1e 2108 pci_conf = dev->config;
e8f943c3
HR		 2109
2110 /* PCI latency timer = 0 */
2111 pci_conf[PCI_LATENCY_TIMER] = 0;
2112 /* Interrupt pin 1 */
2113 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2114
29776739 2115 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2116 "megasas-mmio", 0x4000);
29776739 2117 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2118 "megasas-io", 256);
29776739 2119 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2120 "megasas-queue", 0x40000);
2121
2122#ifdef USE_MSIX
2123 /* MSI-X support is currently broken */
2124 if (megasas_use_msix(s) &&
52190c1e 2125 msix_init(dev, 15, &s->mmio_io, 0, 0x2000)) {
e8f943c3
HR		 2126 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2127 }
2128#else
2129 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2130#endif
2131
2132 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
52190c1e
AF		 2133 pci_register_bar(dev, 0, bar_type, &s->mmio_io);
2134 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2135 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2136
2137 if (megasas_use_msix(s)) {
52190c1e 2138 msix_vector_use(dev, 0);
e8f943c3
HR		 2139 }
2140
76b523db
HR		 2141 if (!s->sas_addr) {
2142 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2143 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2144 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2145 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2146 s->sas_addr |= PCI_FUNC(dev->devfn);
2147 }
fb654157
HR		 2148 if (!s->hba_serial) {
2149 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2150 }
e8f943c3
HR		 2151 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2152 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2153 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2154 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2155 } else {
2156 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2157 }
2158 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2159 s->fw_cmds = MEGASAS_MAX_FRAMES;
2160 }
2161 trace_megasas_init(s->fw_sge, s->fw_cmds,
2162 megasas_use_msix(s) ? "MSI-X" : "INTx",
2163 megasas_is_jbod(s) ? "jbod" : "raid");
2164 s->fw_luns = (MFI_MAX_LD > MAX_SCSI_DEVS) ?
2165 MAX_SCSI_DEVS : MFI_MAX_LD;
2166 s->producer_pa = 0;
2167 s->consumer_pa = 0;
2168 for (i = 0; i < s->fw_cmds; i++) {
2169 s->frames[i].index = i;
2170 s->frames[i].context = -1;
2171 s->frames[i].pa = 0;
2172 s->frames[i].state = s;
2173 }
2174
b1187b51
AF		 2175 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2176 &megasas_scsi_info, NULL);
22d6aa03 2177 if (!d->hotplugged) {
caad4eb3
AF		 2178 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2179 if (err != NULL) {
2180 error_free(err);
2181 return -1;
2182 }
22d6aa03 2183 }
e8f943c3
HR		 2184 return 0;
2185}
2186
2187static Property megasas_properties[] = {
2188 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2189 MEGASAS_DEFAULT_SGE),
2190 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2191 MEGASAS_DEFAULT_FRAMES),
fb654157 2192 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
76b523db 2193 DEFINE_PROP_HEX64("sas_address", MegasasState, sas_addr, 0),
e8f943c3
HR		 2194#ifdef USE_MSIX
2195 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2196 MEGASAS_FLAG_USE_MSIX, false),
2197#endif
2198 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2199 MEGASAS_FLAG_USE_JBOD, false),
2200 DEFINE_PROP_END_OF_LIST(),
2201};
2202
2203static void megasas_class_init(ObjectClass *oc, void *data)
2204{
2205 DeviceClass *dc = DEVICE_CLASS(oc);
2206 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2207
2208 pc->init = megasas_scsi_init;
2209 pc->exit = megasas_scsi_uninit;
2210 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2211 pc->device_id = PCI_DEVICE_ID_LSI_SAS1078;
2212 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2213 pc->subsystem_id = 0x1013;
2214 pc->class_id = PCI_CLASS_STORAGE_RAID;
2215 dc->props = megasas_properties;
2216 dc->reset = megasas_scsi_reset;
2217 dc->vmsd = &vmstate_megasas;
125ee0ed 2218 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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HR		 2219 dc->desc = "LSI MegaRAID SAS 1078";
2220}
2221
2222static const TypeInfo megasas_info = {
c79e16ae 2223 .name = TYPE_MEGASAS,
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HR		 2224 .parent = TYPE_PCI_DEVICE,
2225 .instance_size = sizeof(MegasasState),
2226 .class_init = megasas_class_init,
2227};
2228
2229static void megasas_register_types(void)
2230{
2231 type_register_static(&megasas_info);
2232}
2233
2234type_init(megasas_register_types)
Empty description
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