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tcg: Return bool success from tcg_out_mov
[qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
a7ce790a
PM		 25#ifndef TCG_TCG_OP_H
26#define TCG_TCG_OP_H
27
c896fe29 28#include "tcg.h"
944eea96 29#include "exec/helper-proto.h"
c017230d
RH		 30#include "exec/helper-gen.h"
31
951c6300 32/* Basic output routines. Not for general consumption. */
c896fe29 33
b7e8b17a
RH		 34void tcg_gen_op1(TCGOpcode, TCGArg);
35void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
36void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
37void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
38void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
39void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
951c6300 40
d2fd745f
RH		 41void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
42void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
43void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
44
951c6300 45static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 46{
ae8b75dc 47 tcg_gen_op1(opc, tcgv_i32_arg(a1));
a7812ae4
PB		 48}
49
951c6300 50static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 51{
ae8b75dc 52 tcg_gen_op1(opc, tcgv_i64_arg(a1));
c896fe29
FB		 53}
54
951c6300 55static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 56{
b7e8b17a 57 tcg_gen_op1(opc, a1);
c896fe29
FB		 58}
59
951c6300 60static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 61{
ae8b75dc 62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
a7812ae4
PB		 63}
64
951c6300 65static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 66{
ae8b75dc 67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
a7812ae4
PB		 68}
69
951c6300 70static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 71{
ae8b75dc 72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
c896fe29
FB		 73}
74
951c6300 75static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 76{
ae8b75dc 77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
ac56dd48
PB		 78}
79
951c6300 80static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 81{
b7e8b17a 82 tcg_gen_op2(opc, a1, a2);
bcb0126f
PB		 83}
84
951c6300
RH		 85static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
86 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 87{
ae8b75dc 88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
a7812ae4
PB		 89}
90
951c6300
RH		 91static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
92 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 93{
ae8b75dc 94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
a7812ae4
PB		 95}
96
951c6300
RH		 97static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
98 TCGv_i32 a2, TCGArg a3)
ac56dd48 99{
ae8b75dc 100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
ac56dd48
PB		 101}
102
951c6300
RH		 103static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
104 TCGv_i64 a2, TCGArg a3)
ac56dd48 105{
ae8b75dc 106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
ac56dd48
PB		 107}
108
a9751609
RH		 109static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
110 TCGv_ptr base, TCGArg offset)
a7812ae4 111{
ae8b75dc 112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 113}
114
a9751609
RH		 115static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
116 TCGv_ptr base, TCGArg offset)
a7812ae4 117{
ae8b75dc 118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 119}
120
951c6300
RH		 121static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
122 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 123{
ae8b75dc
RH		 124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
125 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
a7812ae4
PB		 126}
127
951c6300
RH		 128static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
129 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 130{
ae8b75dc
RH		 131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
132 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
a7812ae4
PB		 133}
134
951c6300
RH		 135static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
136 TCGv_i32 a3, TCGArg a4)
a7812ae4 137{
ae8b75dc
RH		 138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
139 tcgv_i32_arg(a3), a4);
a7812ae4
PB		 140}
141
951c6300
RH		 142static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
143 TCGv_i64 a3, TCGArg a4)
ac56dd48 144{
ae8b75dc
RH		 145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
146 tcgv_i64_arg(a3), a4);
ac56dd48
PB		 147}
148
951c6300
RH		 149static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
150 TCGArg a3, TCGArg a4)
ac56dd48 151{
ae8b75dc 152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
c896fe29
FB		 153}
154
951c6300
RH		 155static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
156 TCGArg a3, TCGArg a4)
c896fe29 157{
ae8b75dc 158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
ac56dd48
PB		 159}
160
951c6300
RH		 161static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 163{
ae8b75dc
RH		 164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
a7812ae4
PB		 166}
167
951c6300
RH		 168static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 170{
ae8b75dc
RH		 171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
a7812ae4
PB		 173}
174
951c6300
RH		 175static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 177{
ae8b75dc
RH		 178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
ac56dd48
PB		 180}
181
951c6300
RH		 182static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 184{
ae8b75dc
RH		 185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
c896fe29
FB		 187}
188
951c6300
RH		 189static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
190 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 191{
ae8b75dc
RH		 192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
193 tcgv_i32_arg(a3), a4, a5);
b7767f0f
RH		 194}
195
951c6300
RH		 196static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
197 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 198{
ae8b75dc
RH		 199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
200 tcgv_i64_arg(a3), a4, a5);
b7767f0f
RH		 201}
202
951c6300
RH		 203static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
204 TCGv_i32 a3, TCGv_i32 a4,
205 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 206{
ae8b75dc
RH		 207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
209 tcgv_i32_arg(a6));
a7812ae4
PB		 210}
211
951c6300
RH		 212static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
213 TCGv_i64 a3, TCGv_i64 a4,
214 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 215{
ae8b75dc
RH		 216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
218 tcgv_i64_arg(a6));
ac56dd48
PB		 219}
220
951c6300
RH		 221static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
222 TCGv_i32 a3, TCGv_i32 a4,
223 TCGv_i32 a5, TCGArg a6)
be210acb 224{
ae8b75dc
RH		 225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
be210acb
RH		 227}
228
951c6300
RH		 229static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
230 TCGv_i64 a3, TCGv_i64 a4,
231 TCGv_i64 a5, TCGArg a6)
be210acb 232{
ae8b75dc
RH		 233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
be210acb
RH		 235}
236
951c6300
RH		 237static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
238 TCGv_i32 a3, TCGv_i32 a4,
239 TCGArg a5, TCGArg a6)
ac56dd48 240{
ae8b75dc
RH		 241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
a7812ae4
PB		 243}
244
951c6300
RH		 245static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
246 TCGv_i64 a3, TCGv_i64 a4,
247 TCGArg a5, TCGArg a6)
a7812ae4 248{
ae8b75dc
RH		 249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
c896fe29
FB		 251}
252
f713d6ad 253
951c6300
RH		 254/* Generic ops. */
255
42a268c2 256static inline void gen_set_label(TCGLabel *l)
c896fe29 257{
bef16ab4 258 l->present = 1;
b7e8b17a 259 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
c896fe29
FB		 260}
261
42a268c2 262static inline void tcg_gen_br(TCGLabel *l)
fb50d413 263{
d88a117e 264 l->refs++;
b7e8b17a 265 tcg_gen_op1(INDEX_op_br, label_arg(l));
951c6300
RH		 266}
267
f65e19bc
PK		 268void tcg_gen_mb(TCGBar);
269
951c6300
RH		 270/* Helper calls. */
271
272/* 32 bit ops */
273
274void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
275void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
276void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f 277void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 278void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
279void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f
RH		 280void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
281void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
282void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 283void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
284void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
291void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
292void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
0e28d006
RH		 293void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
294void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
295void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
296void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
086920c2 297void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
a768e4e9 298void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
951c6300
RH		 299void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
300void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
301void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
302void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
303void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
304 unsigned int ofs, unsigned int len);
07cc68d5
RH		 305void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
306 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 307void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
308 unsigned int ofs, unsigned int len);
309void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
310 unsigned int ofs, unsigned int len);
2089fcc9
DH		 311void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
312 unsigned int ofs);
42a268c2
RH		 313void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
314void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 315void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
316 TCGv_i32 arg1, TCGv_i32 arg2);
317void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
318 TCGv_i32 arg1, int32_t arg2);
319void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
320 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
321void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
322 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
323void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
324 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
325void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
326void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 327void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 328void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
329void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
330void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
331void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
332void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
333void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
b87fb8cd
RH		 334void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
335void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
336void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
337void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 338
339static inline void tcg_gen_discard_i32(TCGv_i32 arg)
340{
341 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 342}
343
a7812ae4 344static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 345{
11f4e8f8 346 if (ret != arg) {
a7812ae4 347 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 348 }
c896fe29
FB		 349}
350
a7812ae4 351static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 352{
a7812ae4 353 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 354}
355
951c6300
RH		 356static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
357 tcg_target_long offset)
c896fe29 358{
a7812ae4 359 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 360}
361
951c6300
RH		 362static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
363 tcg_target_long offset)
c896fe29 364{
a7812ae4 365 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 366}
367
951c6300
RH		 368static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
369 tcg_target_long offset)
c896fe29 370{
a7812ae4 371 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 372}
373
951c6300
RH		 374static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
375 tcg_target_long offset)
c896fe29 376{
a7812ae4 377 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 378}
379
951c6300
RH		 380static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
381 tcg_target_long offset)
c896fe29 382{
a7812ae4 383 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 384}
385
951c6300
RH		 386static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
387 tcg_target_long offset)
c896fe29 388{
a7812ae4 389 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 390}
391
951c6300
RH		 392static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
393 tcg_target_long offset)
c896fe29 394{
a7812ae4 395 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 396}
397
951c6300
RH		 398static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
399 tcg_target_long offset)
c896fe29 400{
a7812ae4 401 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 402}
403
a7812ae4 404static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 405{
a7812ae4 406 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 407}
408
a7812ae4 409static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 410{
a7812ae4 411 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 412}
413
a7812ae4 414static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 415{
951c6300 416 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 417}
418
a7812ae4 419static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 420{
951c6300 421 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 422}
423
a7812ae4 424static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 425{
951c6300 426 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 427}
428
a7812ae4 429static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 430{
a7812ae4 431 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 432}
433
a7812ae4 434static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 435{
a7812ae4 436 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 437}
438
a7812ae4 439static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 440{
a7812ae4 441 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 442}
443
a7812ae4 444static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 445{
a7812ae4 446 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 447}
448
951c6300 449static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 450{
951c6300
RH		 451 if (TCG_TARGET_HAS_neg_i32) {
452 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 453 } else {
951c6300 454 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 455 }
31d66551
AJ		 456}
457
951c6300 458static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 459{
951c6300
RH		 460 if (TCG_TARGET_HAS_not_i32) {
461 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 462 } else {
951c6300 463 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 464 }
31d66551
AJ		 465}
466
951c6300
RH		 467/* 64 bit ops */
468
469void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
470void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
471void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f 472void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 473void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f
RH		 475void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
476void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
477void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 478void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
479void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
481void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
482void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
483void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
484void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
485void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
486void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
487void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
0e28d006
RH		 488void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
489void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
490void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
491void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
086920c2 492void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
a768e4e9 493void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
951c6300
RH		 494void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
495void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
496void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
497void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
498void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
499 unsigned int ofs, unsigned int len);
07cc68d5
RH		 500void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
501 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 502void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
503 unsigned int ofs, unsigned int len);
504void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
505 unsigned int ofs, unsigned int len);
2089fcc9
DH		 506void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
507 unsigned int ofs);
42a268c2
RH		 508void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
509void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 510void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
511 TCGv_i64 arg1, TCGv_i64 arg2);
512void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
513 TCGv_i64 arg1, int64_t arg2);
514void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
515 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
516void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
517 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
518void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
519 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
520void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
521void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 522void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 523void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
524void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
525void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
526void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
527void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
528void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
529void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
530void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
531void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
532void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
b87fb8cd
RH		 533void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
534void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
535void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
536void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
c896fe29 537
951c6300
RH		 538#if TCG_TARGET_REG_BITS == 64
539static inline void tcg_gen_discard_i64(TCGv_i64 arg)
540{
541 tcg_gen_op1_i64(INDEX_op_discard, arg);
542}
c896fe29 543
a7812ae4 544static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 545{
11f4e8f8 546 if (ret != arg) {
951c6300 547 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 548 }
c896fe29
FB		 549}
550
a7812ae4 551static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 552{
951c6300 553 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 554}
555
a7812ae4
PB		 556static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
557 tcg_target_long offset)
c896fe29 558{
951c6300 559 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 560}
561
a7812ae4
PB		 562static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
563 tcg_target_long offset)
c896fe29 564{
951c6300 565 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 566}
567
a7812ae4
PB		 568static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
569 tcg_target_long offset)
c896fe29 570{
951c6300 571 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 572}
573
a7812ae4
PB		 574static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
575 tcg_target_long offset)
c896fe29 576{
951c6300 577 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 578}
579
a7812ae4
PB		 580static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
581 tcg_target_long offset)
c896fe29 582{
951c6300 583 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 584}
585
a7812ae4
PB		 586static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
587 tcg_target_long offset)
c896fe29 588{
951c6300 589 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 590}
591
a7812ae4
PB		 592static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
593 tcg_target_long offset)
c896fe29 594{
951c6300 595 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 596}
597
a7812ae4
PB		 598static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
599 tcg_target_long offset)
c896fe29 600{
951c6300 601 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 602}
603
a7812ae4
PB		 604static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
605 tcg_target_long offset)
c896fe29 606{
951c6300 607 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 608}
609
a7812ae4
PB		 610static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
611 tcg_target_long offset)
c896fe29 612{
951c6300 613 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 614}
615
a7812ae4
PB		 616static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
617 tcg_target_long offset)
c896fe29 618{
951c6300 619 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 620}
621
a7812ae4 622static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 623{
951c6300 624 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 625}
626
a7812ae4 627static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 628{
951c6300 629 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 630}
631
a7812ae4 632static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 633{
951c6300 634 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 635}
636
a7812ae4 637static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 638{
951c6300 639 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 640}
641
a7812ae4 642static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 643{
951c6300 644 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 645}
646
a7812ae4 647static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 648{
951c6300 649 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 650}
651
a7812ae4 652static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 653{
951c6300 654 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 655}
656
a7812ae4 657static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 658{
951c6300 659 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 660}
661
a7812ae4 662static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 663{
951c6300 664 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 665}
951c6300
RH		 666#else /* TCG_TARGET_REG_BITS == 32 */
667static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
668 tcg_target_long offset)
c896fe29 669{
951c6300 670 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 671}
672
951c6300
RH		 673static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
674 tcg_target_long offset)
c896fe29 675{
951c6300 676 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 677}
678
951c6300
RH		 679static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
680 tcg_target_long offset)
c896fe29 681{
951c6300 682 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 683}
684
951c6300 685static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 686{
951c6300
RH		 687 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
688 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
c896fe29
FB		 689}
690
951c6300 691static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 692{
951c6300
RH		 693 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
694 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
695}
696
697void tcg_gen_discard_i64(TCGv_i64 arg);
698void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
699void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
700void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
701void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
702void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
703void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
704void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
705void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
706void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
707void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
708void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
709void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
710void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
711void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
712void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
713void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
714void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
715#endif /* TCG_TARGET_REG_BITS */
c896fe29 716
951c6300 717static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 718{
951c6300
RH		 719 if (TCG_TARGET_HAS_neg_i64) {
720 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
721 } else {
722 tcg_gen_subfi_i64(ret, 0, arg);
723 }
c896fe29
FB		 724}
725
951c6300 726/* Size changing operations. */
c896fe29 727
951c6300
RH		 728void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
729void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
730void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 731void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
732void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 733void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
734void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 735
951c6300 736static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 737{
951c6300 738 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 739}
740
951c6300 741/* QEMU specific operations. */
c896fe29 742
951c6300
RH		 743#ifndef TARGET_LONG_BITS
744#error must include QEMU headers
745#endif
c896fe29 746
9aef40ed
RH		 747#if TARGET_INSN_START_WORDS == 1
748# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
749static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 750{
b7e8b17a 751 tcg_gen_op1(INDEX_op_insn_start, pc);
9aef40ed
RH		 752}
753# else
754static inline void tcg_gen_insn_start(target_ulong pc)
755{
b7e8b17a 756 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
9aef40ed
RH		 757}
758# endif
759#elif TARGET_INSN_START_WORDS == 2
760# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
761static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
762{
b7e8b17a 763 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
9aef40ed
RH		 764}
765# else
766static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
767{
b7e8b17a 768 tcg_gen_op4(INDEX_op_insn_start,
9aef40ed
RH		 769 (uint32_t)pc, (uint32_t)(pc >> 32),
770 (uint32_t)a1, (uint32_t)(a1 >> 32));
771}
772# endif
773#elif TARGET_INSN_START_WORDS == 3
774# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
775static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
776 target_ulong a2)
777{
b7e8b17a 778 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
9aef40ed
RH		 779}
780# else
781static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
782 target_ulong a2)
783{
b7e8b17a 784 tcg_gen_op6(INDEX_op_insn_start,
9aef40ed
RH		 785 (uint32_t)pc, (uint32_t)(pc >> 32),
786 (uint32_t)a1, (uint32_t)(a1 >> 32),
787 (uint32_t)a2, (uint32_t)(a2 >> 32));
788}
789# endif
951c6300 790#else
9aef40ed 791# error "Unhandled number of operands to insn_start"
951c6300 792#endif
c896fe29 793
07ea28b4
RH		 794/**
795 * tcg_gen_exit_tb() - output exit_tb TCG operation
796 * @tb: The TranslationBlock from which we are exiting
797 * @idx: Direct jump slot index, or exit request
798 *
799 * See tcg/README for more info about this TCG operation.
800 * See also tcg.h and the block comment above TB_EXIT_MASK.
801 *
802 * For a normal exit from the TB, back to the main loop, @tb should
803 * be NULL and @idx should be 0. Otherwise, @tb should be valid and
804 * @idx should be one of the TB_EXIT_ values.
805 */
806void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx);
c896fe29 807
5b053a4a
SF		 808/**
809 * tcg_gen_goto_tb() - output goto_tb TCG operation
810 * @idx: Direct jump slot index (0 or 1)
811 *
812 * See tcg/README for more info about this TCG operation.
813 *
90aa39a1
SF		 814 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
815 * the pages this TB resides in because we don't take care of direct jumps when
816 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
817 * static address translation, so the destination address is always valid, TBs
818 * are always invalidated properly, and direct jumps are reset when mapping
819 * changes.
5b053a4a 820 */
951c6300 821void tcg_gen_goto_tb(unsigned idx);
c896fe29 822
cedbcb01 823/**
7f11636d 824 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
cedbcb01
EC		 825 * @addr: Guest address of the target TB
826 *
827 * If the TB is not valid, jump to the epilogue.
828 *
829 * This operation is optional. If the TCG backend does not implement goto_ptr,
830 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
831 */
7f11636d 832void tcg_gen_lookup_and_goto_ptr(void);
cedbcb01 833
a7812ae4 834#if TARGET_LONG_BITS == 32
a7812ae4
PB		 835#define tcg_temp_new() tcg_temp_new_i32()
836#define tcg_global_reg_new tcg_global_reg_new_i32
837#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 838#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 839#define tcg_temp_free tcg_temp_free_i32
f713d6ad
RH		 840#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
841#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 842#else
a7812ae4
PB		 843#define tcg_temp_new() tcg_temp_new_i64()
844#define tcg_global_reg_new tcg_global_reg_new_i64
845#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 846#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 847#define tcg_temp_free tcg_temp_free_i64
f713d6ad
RH		 848#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
849#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 850#endif
851
f713d6ad
RH		 852void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
853void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
854void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
855void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 856
ac56dd48 857static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 858{
f713d6ad 859 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 860}
861
ac56dd48 862static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 863{
f713d6ad 864 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 865}
866
ac56dd48 867static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 868{
f713d6ad 869 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 870}
871
ac56dd48 872static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 873{
f713d6ad 874 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 875}
876
ac56dd48 877static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 878{
f713d6ad 879 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 880}
881
ac56dd48 882static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 883{
f713d6ad 884 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 885}
886
a7812ae4 887static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 888{
f713d6ad 889 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 890}
891
ac56dd48 892static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 893{
f713d6ad 894 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 895}
896
ac56dd48 897static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 898{
f713d6ad 899 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 900}
901
ac56dd48 902static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 903{
f713d6ad 904 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 905}
906
a7812ae4 907static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 908{
f713d6ad 909 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 910}
911
c482cb11
RH		 912void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
913 TCGArg, TCGMemOp);
914void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
915 TCGArg, TCGMemOp);
916
917void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
918void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf 919
c482cb11
RH		 920void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
921void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
922void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
923void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
924void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
925void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
926void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
927void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 928void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
929void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
930void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
931void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
932void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
933void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
934void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
935void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
936
c482cb11
RH		 937void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
938void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
939void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
940void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
941void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
942void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
943void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
944void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 945void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
946void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
947void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
948void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
949void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
950void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
951void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
952void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
c482cb11 953
d2fd745f
RH		 954void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
955void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
956void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
957void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
958void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
959void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
960void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
db432672 961void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
d2fd745f
RH		 962void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
963void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
3774030a 964void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 965void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
966void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
967void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
968void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
969void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
f550805d
RH		 970void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
971void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
972void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 973void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
974void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
8afaf050
RH		 975void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
976void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
977void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
978void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
dd0a0fcd
RH		 979void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
980void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
981void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
982void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f 983
d0ec9796
RH		 984void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
985void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
986void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
987
212be173
RH		 988void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
989 TCGv_vec a, TCGv_vec b);
990
d2fd745f
RH		 991void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
992void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
993void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
994
f8422f52 995#if TARGET_LONG_BITS == 64
f8422f52
BS		 996#define tcg_gen_movi_tl tcg_gen_movi_i64
997#define tcg_gen_mov_tl tcg_gen_mov_i64
998#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
999#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1000#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1001#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1002#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1003#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1004#define tcg_gen_ld_tl tcg_gen_ld_i64
1005#define tcg_gen_st8_tl tcg_gen_st8_i64
1006#define tcg_gen_st16_tl tcg_gen_st16_i64
1007#define tcg_gen_st32_tl tcg_gen_st32_i64
1008#define tcg_gen_st_tl tcg_gen_st_i64
1009#define tcg_gen_add_tl tcg_gen_add_i64
1010#define tcg_gen_addi_tl tcg_gen_addi_i64
1011#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 1012#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 1013#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 1014#define tcg_gen_subi_tl tcg_gen_subi_i64
1015#define tcg_gen_and_tl tcg_gen_and_i64
1016#define tcg_gen_andi_tl tcg_gen_andi_i64
1017#define tcg_gen_or_tl tcg_gen_or_i64
1018#define tcg_gen_ori_tl tcg_gen_ori_i64
1019#define tcg_gen_xor_tl tcg_gen_xor_i64
1020#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 1021#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 1022#define tcg_gen_shl_tl tcg_gen_shl_i64
1023#define tcg_gen_shli_tl tcg_gen_shli_i64
1024#define tcg_gen_shr_tl tcg_gen_shr_i64
1025#define tcg_gen_shri_tl tcg_gen_shri_i64
1026#define tcg_gen_sar_tl tcg_gen_sar_i64
1027#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 1028#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 1029#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 1030#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 1031#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 1032#define tcg_gen_mul_tl tcg_gen_mul_i64
1033#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 1034#define tcg_gen_div_tl tcg_gen_div_i64
1035#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 1036#define tcg_gen_divu_tl tcg_gen_divu_i64
1037#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 1038#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 1039#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 1040#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1041#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1042#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1043#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1044#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 1045#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1046#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1047#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1048#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1049#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1050#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 1051#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
1052#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
1053#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 1054#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 1055#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 1056#define tcg_gen_andc_tl tcg_gen_andc_i64
1057#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1058#define tcg_gen_nand_tl tcg_gen_nand_i64
1059#define tcg_gen_nor_tl tcg_gen_nor_i64
1060#define tcg_gen_orc_tl tcg_gen_orc_i64
0e28d006
RH		 1061#define tcg_gen_clz_tl tcg_gen_clz_i64
1062#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1063#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1064#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
086920c2 1065#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
a768e4e9 1066#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
15824571
AJ		 1067#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1068#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1069#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1070#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 1071#define tcg_gen_deposit_tl tcg_gen_deposit_i64
07cc68d5 1072#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
7ec8bab3
RH		 1073#define tcg_gen_extract_tl tcg_gen_extract_i64
1074#define tcg_gen_sextract_tl tcg_gen_sextract_i64
2089fcc9 1075#define tcg_gen_extract2_tl tcg_gen_extract2_i64
a98824ac 1076#define tcg_const_tl tcg_const_i64
bdffd4a9 1077#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 1078#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 1079#define tcg_gen_add2_tl tcg_gen_add2_i64
1080#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 1081#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1082#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 1083#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
b87fb8cd
RH		 1084#define tcg_gen_smin_tl tcg_gen_smin_i64
1085#define tcg_gen_umin_tl tcg_gen_umin_i64
1086#define tcg_gen_smax_tl tcg_gen_smax_i64
1087#define tcg_gen_umax_tl tcg_gen_umax_i64
c482cb11
RH		 1088#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1089#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1090#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1091#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1092#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1093#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
5507c2bf
RH		 1094#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
1095#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
1096#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
1097#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
c482cb11
RH		 1098#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1099#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1100#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1101#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
5507c2bf
RH		 1102#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
1103#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
1104#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
1105#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
d2fd745f 1106#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
f8422f52 1107#else
f8422f52
BS		 1108#define tcg_gen_movi_tl tcg_gen_movi_i32
1109#define tcg_gen_mov_tl tcg_gen_mov_i32
1110#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1111#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1112#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1113#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1114#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1115#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1116#define tcg_gen_ld_tl tcg_gen_ld_i32
1117#define tcg_gen_st8_tl tcg_gen_st8_i32
1118#define tcg_gen_st16_tl tcg_gen_st16_i32
1119#define tcg_gen_st32_tl tcg_gen_st_i32
1120#define tcg_gen_st_tl tcg_gen_st_i32
1121#define tcg_gen_add_tl tcg_gen_add_i32
1122#define tcg_gen_addi_tl tcg_gen_addi_i32
1123#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 1124#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 1125#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 1126#define tcg_gen_subi_tl tcg_gen_subi_i32
1127#define tcg_gen_and_tl tcg_gen_and_i32
1128#define tcg_gen_andi_tl tcg_gen_andi_i32
1129#define tcg_gen_or_tl tcg_gen_or_i32
1130#define tcg_gen_ori_tl tcg_gen_ori_i32
1131#define tcg_gen_xor_tl tcg_gen_xor_i32
1132#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 1133#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 1134#define tcg_gen_shl_tl tcg_gen_shl_i32
1135#define tcg_gen_shli_tl tcg_gen_shli_i32
1136#define tcg_gen_shr_tl tcg_gen_shr_i32
1137#define tcg_gen_shri_tl tcg_gen_shri_i32
1138#define tcg_gen_sar_tl tcg_gen_sar_i32
1139#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1140#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1141#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1142#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1143#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1144#define tcg_gen_mul_tl tcg_gen_mul_i32
1145#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1146#define tcg_gen_div_tl tcg_gen_div_i32
1147#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1148#define tcg_gen_divu_tl tcg_gen_divu_i32
1149#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1150#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1151#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1152#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1153#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1154#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1155#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1156#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1157#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1158#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1159#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1160#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1161#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1162#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 1163#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1164#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 1165#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1166#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1167#define tcg_gen_andc_tl tcg_gen_andc_i32
1168#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1169#define tcg_gen_nand_tl tcg_gen_nand_i32
1170#define tcg_gen_nor_tl tcg_gen_nor_i32
1171#define tcg_gen_orc_tl tcg_gen_orc_i32
0e28d006
RH		 1172#define tcg_gen_clz_tl tcg_gen_clz_i32
1173#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1174#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1175#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
086920c2 1176#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
a768e4e9 1177#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
15824571
AJ		 1178#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1179#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1180#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1181#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1182#define tcg_gen_deposit_tl tcg_gen_deposit_i32
07cc68d5 1183#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
7ec8bab3
RH		 1184#define tcg_gen_extract_tl tcg_gen_extract_i32
1185#define tcg_gen_sextract_tl tcg_gen_sextract_i32
2089fcc9 1186#define tcg_gen_extract2_tl tcg_gen_extract2_i32
a98824ac 1187#define tcg_const_tl tcg_const_i32
bdffd4a9 1188#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 1189#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1190#define tcg_gen_add2_tl tcg_gen_add2_i32
1191#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1192#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1193#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1194#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
b87fb8cd
RH		 1195#define tcg_gen_smin_tl tcg_gen_smin_i32
1196#define tcg_gen_umin_tl tcg_gen_umin_i32
1197#define tcg_gen_smax_tl tcg_gen_smax_i32
1198#define tcg_gen_umax_tl tcg_gen_umax_i32
c482cb11
RH		 1199#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1200#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1201#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1202#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1203#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1204#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
5507c2bf
RH		 1205#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
1206#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
1207#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
1208#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
c482cb11
RH		 1209#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1210#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1211#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1212#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
5507c2bf
RH		 1213#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
1214#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
1215#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
1216#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
d2fd745f 1217#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
f8422f52 1218#endif
6ddbc6e4 1219
71b92699 1220#if UINTPTR_MAX == UINT32_MAX
5bfa8034
RH		 1221# define PTR i32
1222# define NAT TCGv_i32
f713d6ad 1223#else
5bfa8034
RH		 1224# define PTR i64
1225# define NAT TCGv_i64
1226#endif
1227
1228static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1229{
1230 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1231}
1232
1233static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1234{
1235 glue(tcg_gen_discard_,PTR)((NAT)a);
1236}
1237
1238static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1239{
1240 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1241}
1242
1243static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1244{
1245 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1246}
1247
1248static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1249 intptr_t b, TCGLabel *label)
1250{
1251 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1252}
1253
1254static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1255{
1256#if UINTPTR_MAX == UINT32_MAX
1257 tcg_gen_mov_i32((NAT)r, a);
1258#else
1259 tcg_gen_ext_i32_i64((NAT)r, a);
1260#endif
1261}
1262
1263static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1264{
1265#if UINTPTR_MAX == UINT32_MAX
1266 tcg_gen_extrl_i64_i32((NAT)r, a);
1267#else
1268 tcg_gen_mov_i64((NAT)r, a);
1269#endif
1270}
1271
1272static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1273{
1274#if UINTPTR_MAX == UINT32_MAX
1275 tcg_gen_extu_i32_i64(r, (NAT)a);
1276#else
1277 tcg_gen_mov_i64(r, (NAT)a);
1278#endif
1279}
1280
1281static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1282{
1283#if UINTPTR_MAX == UINT32_MAX
1284 tcg_gen_mov_i32(r, (NAT)a);
1285#else
1286 tcg_gen_extrl_i64_i32(r, (NAT)a);
1287#endif
1288}
1289
1290#undef PTR
1291#undef NAT
a7ce790a
PM		 1292
1293#endif /* TCG_TCG_OP_H */
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