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tcg: Add write_aofs to GVecGen4
[qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
a7ce790a
PM		 25#ifndef TCG_TCG_OP_H
26#define TCG_TCG_OP_H
27
c896fe29 28#include "tcg.h"
944eea96 29#include "exec/helper-proto.h"
c017230d
RH		 30#include "exec/helper-gen.h"
31
951c6300 32/* Basic output routines. Not for general consumption. */
c896fe29 33
b7e8b17a
RH		 34void tcg_gen_op1(TCGOpcode, TCGArg);
35void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
36void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
37void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
38void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
39void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
951c6300 40
d2fd745f
RH		 41void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
42void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
43void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
44
951c6300 45static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 46{
ae8b75dc 47 tcg_gen_op1(opc, tcgv_i32_arg(a1));
a7812ae4
PB		 48}
49
951c6300 50static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 51{
ae8b75dc 52 tcg_gen_op1(opc, tcgv_i64_arg(a1));
c896fe29
FB		 53}
54
951c6300 55static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 56{
b7e8b17a 57 tcg_gen_op1(opc, a1);
c896fe29
FB		 58}
59
951c6300 60static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 61{
ae8b75dc 62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
a7812ae4
PB		 63}
64
951c6300 65static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 66{
ae8b75dc 67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
a7812ae4
PB		 68}
69
951c6300 70static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 71{
ae8b75dc 72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
c896fe29
FB		 73}
74
951c6300 75static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 76{
ae8b75dc 77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
ac56dd48
PB		 78}
79
951c6300 80static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 81{
b7e8b17a 82 tcg_gen_op2(opc, a1, a2);
bcb0126f
PB		 83}
84
951c6300
RH		 85static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
86 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 87{
ae8b75dc 88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
a7812ae4
PB		 89}
90
951c6300
RH		 91static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
92 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 93{
ae8b75dc 94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
a7812ae4
PB		 95}
96
951c6300
RH		 97static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
98 TCGv_i32 a2, TCGArg a3)
ac56dd48 99{
ae8b75dc 100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
ac56dd48
PB		 101}
102
951c6300
RH		 103static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
104 TCGv_i64 a2, TCGArg a3)
ac56dd48 105{
ae8b75dc 106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
ac56dd48
PB		 107}
108
a9751609
RH		 109static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
110 TCGv_ptr base, TCGArg offset)
a7812ae4 111{
ae8b75dc 112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 113}
114
a9751609
RH		 115static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
116 TCGv_ptr base, TCGArg offset)
a7812ae4 117{
ae8b75dc 118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 119}
120
951c6300
RH		 121static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
122 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 123{
ae8b75dc
RH		 124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
125 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
a7812ae4
PB		 126}
127
951c6300
RH		 128static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
129 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 130{
ae8b75dc
RH		 131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
132 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
a7812ae4
PB		 133}
134
951c6300
RH		 135static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
136 TCGv_i32 a3, TCGArg a4)
a7812ae4 137{
ae8b75dc
RH		 138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
139 tcgv_i32_arg(a3), a4);
a7812ae4
PB		 140}
141
951c6300
RH		 142static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
143 TCGv_i64 a3, TCGArg a4)
ac56dd48 144{
ae8b75dc
RH		 145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
146 tcgv_i64_arg(a3), a4);
ac56dd48
PB		 147}
148
951c6300
RH		 149static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
150 TCGArg a3, TCGArg a4)
ac56dd48 151{
ae8b75dc 152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
c896fe29
FB		 153}
154
951c6300
RH		 155static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
156 TCGArg a3, TCGArg a4)
c896fe29 157{
ae8b75dc 158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
ac56dd48
PB		 159}
160
951c6300
RH		 161static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 163{
ae8b75dc
RH		 164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
a7812ae4
PB		 166}
167
951c6300
RH		 168static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 170{
ae8b75dc
RH		 171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
a7812ae4
PB		 173}
174
951c6300
RH		 175static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 177{
ae8b75dc
RH		 178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
ac56dd48
PB		 180}
181
951c6300
RH		 182static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 184{
ae8b75dc
RH		 185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
c896fe29
FB		 187}
188
951c6300
RH		 189static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
190 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 191{
ae8b75dc
RH		 192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
193 tcgv_i32_arg(a3), a4, a5);
b7767f0f
RH		 194}
195
951c6300
RH		 196static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
197 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 198{
ae8b75dc
RH		 199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
200 tcgv_i64_arg(a3), a4, a5);
b7767f0f
RH		 201}
202
951c6300
RH		 203static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
204 TCGv_i32 a3, TCGv_i32 a4,
205 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 206{
ae8b75dc
RH		 207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
209 tcgv_i32_arg(a6));
a7812ae4
PB		 210}
211
951c6300
RH		 212static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
213 TCGv_i64 a3, TCGv_i64 a4,
214 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 215{
ae8b75dc
RH		 216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
218 tcgv_i64_arg(a6));
ac56dd48
PB		 219}
220
951c6300
RH		 221static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
222 TCGv_i32 a3, TCGv_i32 a4,
223 TCGv_i32 a5, TCGArg a6)
be210acb 224{
ae8b75dc
RH		 225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
be210acb
RH		 227}
228
951c6300
RH		 229static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
230 TCGv_i64 a3, TCGv_i64 a4,
231 TCGv_i64 a5, TCGArg a6)
be210acb 232{
ae8b75dc
RH		 233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
be210acb
RH		 235}
236
951c6300
RH		 237static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
238 TCGv_i32 a3, TCGv_i32 a4,
239 TCGArg a5, TCGArg a6)
ac56dd48 240{
ae8b75dc
RH		 241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
a7812ae4
PB		 243}
244
951c6300
RH		 245static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
246 TCGv_i64 a3, TCGv_i64 a4,
247 TCGArg a5, TCGArg a6)
a7812ae4 248{
ae8b75dc
RH		 249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
c896fe29
FB		 251}
252
f713d6ad 253
951c6300
RH		 254/* Generic ops. */
255
42a268c2 256static inline void gen_set_label(TCGLabel *l)
c896fe29 257{
b7e8b17a 258 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
c896fe29
FB		 259}
260
42a268c2 261static inline void tcg_gen_br(TCGLabel *l)
fb50d413 262{
d88a117e 263 l->refs++;
b7e8b17a 264 tcg_gen_op1(INDEX_op_br, label_arg(l));
951c6300
RH		 265}
266
f65e19bc
PK		 267void tcg_gen_mb(TCGBar);
268
951c6300
RH		 269/* Helper calls. */
270
271/* 32 bit ops */
272
273void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
274void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
275void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f 276void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 277void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
278void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f
RH		 279void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
280void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
281void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 282void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
283void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
291void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
0e28d006
RH		 292void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
293void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
294void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
295void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
086920c2 296void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
a768e4e9 297void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
951c6300
RH		 298void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
299void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
300void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
301void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
302void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
303 unsigned int ofs, unsigned int len);
07cc68d5
RH		 304void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
305 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 306void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
307 unsigned int ofs, unsigned int len);
308void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
309 unsigned int ofs, unsigned int len);
42a268c2
RH		 310void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
311void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 312void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
313 TCGv_i32 arg1, TCGv_i32 arg2);
314void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
315 TCGv_i32 arg1, int32_t arg2);
316void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
317 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
318void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
319 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
320void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
321 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
322void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
323void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 324void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 325void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
326void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
327void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
328void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
329void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
330void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
b87fb8cd
RH		 331void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
332void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
333void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
334void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 335
336static inline void tcg_gen_discard_i32(TCGv_i32 arg)
337{
338 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 339}
340
a7812ae4 341static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 342{
11f4e8f8 343 if (ret != arg) {
a7812ae4 344 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 345 }
c896fe29
FB		 346}
347
a7812ae4 348static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 349{
a7812ae4 350 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 351}
352
951c6300
RH		 353static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
354 tcg_target_long offset)
c896fe29 355{
a7812ae4 356 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 357}
358
951c6300
RH		 359static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
360 tcg_target_long offset)
c896fe29 361{
a7812ae4 362 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 363}
364
951c6300
RH		 365static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
366 tcg_target_long offset)
c896fe29 367{
a7812ae4 368 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 369}
370
951c6300
RH		 371static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
372 tcg_target_long offset)
c896fe29 373{
a7812ae4 374 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 375}
376
951c6300
RH		 377static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
378 tcg_target_long offset)
c896fe29 379{
a7812ae4 380 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 381}
382
951c6300
RH		 383static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
384 tcg_target_long offset)
c896fe29 385{
a7812ae4 386 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 387}
388
951c6300
RH		 389static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
390 tcg_target_long offset)
c896fe29 391{
a7812ae4 392 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 393}
394
951c6300
RH		 395static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
396 tcg_target_long offset)
c896fe29 397{
a7812ae4 398 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 399}
400
a7812ae4 401static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 402{
a7812ae4 403 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 404}
405
a7812ae4 406static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 407{
a7812ae4 408 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 409}
410
a7812ae4 411static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 412{
951c6300 413 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 414}
415
a7812ae4 416static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 417{
951c6300 418 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 419}
420
a7812ae4 421static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 422{
951c6300 423 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 424}
425
a7812ae4 426static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 427{
a7812ae4 428 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 429}
430
a7812ae4 431static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 432{
a7812ae4 433 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 434}
435
a7812ae4 436static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 437{
a7812ae4 438 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 439}
440
a7812ae4 441static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 442{
a7812ae4 443 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 444}
445
951c6300 446static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 447{
951c6300
RH		 448 if (TCG_TARGET_HAS_neg_i32) {
449 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 450 } else {
951c6300 451 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 452 }
31d66551
AJ		 453}
454
951c6300 455static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 456{
951c6300
RH		 457 if (TCG_TARGET_HAS_not_i32) {
458 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 459 } else {
951c6300 460 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 461 }
31d66551
AJ		 462}
463
951c6300
RH		 464/* 64 bit ops */
465
466void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
467void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
468void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f 469void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 470void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
471void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f
RH		 472void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
473void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 475void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
476void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
477void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
481void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
482void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
483void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
484void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
0e28d006
RH		 485void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
486void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
487void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
488void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
086920c2 489void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
a768e4e9 490void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
951c6300
RH		 491void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
492void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
493void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
494void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
495void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
496 unsigned int ofs, unsigned int len);
07cc68d5
RH		 497void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
498 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 499void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
500 unsigned int ofs, unsigned int len);
501void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
502 unsigned int ofs, unsigned int len);
42a268c2
RH		 503void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
504void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 505void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
506 TCGv_i64 arg1, TCGv_i64 arg2);
507void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
508 TCGv_i64 arg1, int64_t arg2);
509void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
510 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
511void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
512 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
513void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
514 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
515void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
516void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 517void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 518void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
519void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
520void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
521void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
522void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
523void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
524void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
525void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
526void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
527void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
b87fb8cd
RH		 528void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
529void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
530void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
531void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
c896fe29 532
951c6300
RH		 533#if TCG_TARGET_REG_BITS == 64
534static inline void tcg_gen_discard_i64(TCGv_i64 arg)
535{
536 tcg_gen_op1_i64(INDEX_op_discard, arg);
537}
c896fe29 538
a7812ae4 539static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 540{
11f4e8f8 541 if (ret != arg) {
951c6300 542 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 543 }
c896fe29
FB		 544}
545
a7812ae4 546static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 547{
951c6300 548 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 549}
550
a7812ae4
PB		 551static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
552 tcg_target_long offset)
c896fe29 553{
951c6300 554 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 555}
556
a7812ae4
PB		 557static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
558 tcg_target_long offset)
c896fe29 559{
951c6300 560 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 561}
562
a7812ae4
PB		 563static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
564 tcg_target_long offset)
c896fe29 565{
951c6300 566 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 567}
568
a7812ae4
PB		 569static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
570 tcg_target_long offset)
c896fe29 571{
951c6300 572 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 573}
574
a7812ae4
PB		 575static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
576 tcg_target_long offset)
c896fe29 577{
951c6300 578 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 579}
580
a7812ae4
PB		 581static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
582 tcg_target_long offset)
c896fe29 583{
951c6300 584 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 585}
586
a7812ae4
PB		 587static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
588 tcg_target_long offset)
c896fe29 589{
951c6300 590 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 591}
592
a7812ae4
PB		 593static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
594 tcg_target_long offset)
c896fe29 595{
951c6300 596 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 597}
598
a7812ae4
PB		 599static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
600 tcg_target_long offset)
c896fe29 601{
951c6300 602 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 603}
604
a7812ae4
PB		 605static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
606 tcg_target_long offset)
c896fe29 607{
951c6300 608 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 609}
610
a7812ae4
PB		 611static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
612 tcg_target_long offset)
c896fe29 613{
951c6300 614 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 615}
616
a7812ae4 617static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 618{
951c6300 619 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 620}
621
a7812ae4 622static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 623{
951c6300 624 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 625}
626
a7812ae4 627static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 628{
951c6300 629 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 630}
631
a7812ae4 632static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 633{
951c6300 634 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 635}
636
a7812ae4 637static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 638{
951c6300 639 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 640}
641
a7812ae4 642static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 643{
951c6300 644 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 645}
646
a7812ae4 647static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 648{
951c6300 649 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 650}
651
a7812ae4 652static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 653{
951c6300 654 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 655}
656
a7812ae4 657static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 658{
951c6300 659 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 660}
951c6300
RH		 661#else /* TCG_TARGET_REG_BITS == 32 */
662static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
663 tcg_target_long offset)
c896fe29 664{
951c6300 665 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 666}
667
951c6300
RH		 668static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
669 tcg_target_long offset)
c896fe29 670{
951c6300 671 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 672}
673
951c6300
RH		 674static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
675 tcg_target_long offset)
c896fe29 676{
951c6300 677 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 678}
679
951c6300 680static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 681{
951c6300
RH		 682 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
683 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
c896fe29
FB		 684}
685
951c6300 686static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 687{
951c6300
RH		 688 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
689 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
690}
691
692void tcg_gen_discard_i64(TCGv_i64 arg);
693void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
694void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
695void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
696void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
697void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
698void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
699void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
700void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
701void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
702void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
703void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
704void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
705void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
706void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
707void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
708void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
709void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
710#endif /* TCG_TARGET_REG_BITS */
c896fe29 711
951c6300 712static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 713{
951c6300
RH		 714 if (TCG_TARGET_HAS_neg_i64) {
715 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
716 } else {
717 tcg_gen_subfi_i64(ret, 0, arg);
718 }
c896fe29
FB		 719}
720
951c6300 721/* Size changing operations. */
c896fe29 722
951c6300
RH		 723void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
724void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
725void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 726void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
727void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 728void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
729void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 730
951c6300 731static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 732{
951c6300 733 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 734}
735
951c6300 736/* QEMU specific operations. */
c896fe29 737
951c6300
RH		 738#ifndef TARGET_LONG_BITS
739#error must include QEMU headers
740#endif
c896fe29 741
9aef40ed
RH		 742#if TARGET_INSN_START_WORDS == 1
743# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
744static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 745{
b7e8b17a 746 tcg_gen_op1(INDEX_op_insn_start, pc);
9aef40ed
RH		 747}
748# else
749static inline void tcg_gen_insn_start(target_ulong pc)
750{
b7e8b17a 751 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
9aef40ed
RH		 752}
753# endif
754#elif TARGET_INSN_START_WORDS == 2
755# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
756static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
757{
b7e8b17a 758 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
9aef40ed
RH		 759}
760# else
761static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
762{
b7e8b17a 763 tcg_gen_op4(INDEX_op_insn_start,
9aef40ed
RH		 764 (uint32_t)pc, (uint32_t)(pc >> 32),
765 (uint32_t)a1, (uint32_t)(a1 >> 32));
766}
767# endif
768#elif TARGET_INSN_START_WORDS == 3
769# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
770static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
771 target_ulong a2)
772{
b7e8b17a 773 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
9aef40ed
RH		 774}
775# else
776static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
777 target_ulong a2)
778{
b7e8b17a 779 tcg_gen_op6(INDEX_op_insn_start,
9aef40ed
RH		 780 (uint32_t)pc, (uint32_t)(pc >> 32),
781 (uint32_t)a1, (uint32_t)(a1 >> 32),
782 (uint32_t)a2, (uint32_t)(a2 >> 32));
783}
784# endif
951c6300 785#else
9aef40ed 786# error "Unhandled number of operands to insn_start"
951c6300 787#endif
c896fe29 788
07ea28b4
RH		 789/**
790 * tcg_gen_exit_tb() - output exit_tb TCG operation
791 * @tb: The TranslationBlock from which we are exiting
792 * @idx: Direct jump slot index, or exit request
793 *
794 * See tcg/README for more info about this TCG operation.
795 * See also tcg.h and the block comment above TB_EXIT_MASK.
796 *
797 * For a normal exit from the TB, back to the main loop, @tb should
798 * be NULL and @idx should be 0. Otherwise, @tb should be valid and
799 * @idx should be one of the TB_EXIT_ values.
800 */
801void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx);
c896fe29 802
5b053a4a
SF		 803/**
804 * tcg_gen_goto_tb() - output goto_tb TCG operation
805 * @idx: Direct jump slot index (0 or 1)
806 *
807 * See tcg/README for more info about this TCG operation.
808 *
90aa39a1
SF		 809 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
810 * the pages this TB resides in because we don't take care of direct jumps when
811 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
812 * static address translation, so the destination address is always valid, TBs
813 * are always invalidated properly, and direct jumps are reset when mapping
814 * changes.
5b053a4a 815 */
951c6300 816void tcg_gen_goto_tb(unsigned idx);
c896fe29 817
cedbcb01 818/**
7f11636d 819 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
cedbcb01
EC		 820 * @addr: Guest address of the target TB
821 *
822 * If the TB is not valid, jump to the epilogue.
823 *
824 * This operation is optional. If the TCG backend does not implement goto_ptr,
825 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
826 */
7f11636d 827void tcg_gen_lookup_and_goto_ptr(void);
cedbcb01 828
a7812ae4 829#if TARGET_LONG_BITS == 32
a7812ae4
PB		 830#define tcg_temp_new() tcg_temp_new_i32()
831#define tcg_global_reg_new tcg_global_reg_new_i32
832#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 833#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 834#define tcg_temp_free tcg_temp_free_i32
f713d6ad
RH		 835#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
836#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 837#else
a7812ae4
PB		 838#define tcg_temp_new() tcg_temp_new_i64()
839#define tcg_global_reg_new tcg_global_reg_new_i64
840#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 841#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 842#define tcg_temp_free tcg_temp_free_i64
f713d6ad
RH		 843#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
844#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 845#endif
846
f713d6ad
RH		 847void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
848void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
849void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
850void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 851
ac56dd48 852static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 853{
f713d6ad 854 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 855}
856
ac56dd48 857static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 858{
f713d6ad 859 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 860}
861
ac56dd48 862static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 863{
f713d6ad 864 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 865}
866
ac56dd48 867static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 868{
f713d6ad 869 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 870}
871
ac56dd48 872static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 873{
f713d6ad 874 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 875}
876
ac56dd48 877static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 878{
f713d6ad 879 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 880}
881
a7812ae4 882static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 883{
f713d6ad 884 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 885}
886
ac56dd48 887static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 888{
f713d6ad 889 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 890}
891
ac56dd48 892static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 893{
f713d6ad 894 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 895}
896
ac56dd48 897static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 898{
f713d6ad 899 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 900}
901
a7812ae4 902static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 903{
f713d6ad 904 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 905}
906
c482cb11
RH		 907void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
908 TCGArg, TCGMemOp);
909void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
910 TCGArg, TCGMemOp);
911
912void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
913void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf 914
c482cb11
RH		 915void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
916void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
917void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
918void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
919void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
920void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
921void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
922void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 923void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
924void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
925void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
926void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
927void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
928void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
929void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
930void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
931
c482cb11
RH		 932void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
933void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
934void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
935void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
936void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
937void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
938void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
939void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
5507c2bf
RH		 940void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
941void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
942void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
943void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
944void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
945void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
946void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
947void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
c482cb11 948
d2fd745f
RH		 949void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
950void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
951void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
952void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
953void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
954void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
955void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
db432672 956void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
d2fd745f
RH		 957void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
958void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
3774030a 959void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 960void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
961void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
962void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
963void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
964void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
f550805d
RH		 965void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
966void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
967void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 968void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
969void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
970
d0ec9796
RH		 971void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
972void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
973void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
974
212be173
RH		 975void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
976 TCGv_vec a, TCGv_vec b);
977
d2fd745f
RH		 978void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
979void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
980void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
981
f8422f52 982#if TARGET_LONG_BITS == 64
f8422f52
BS		 983#define tcg_gen_movi_tl tcg_gen_movi_i64
984#define tcg_gen_mov_tl tcg_gen_mov_i64
985#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
986#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
987#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
988#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
989#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
990#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
991#define tcg_gen_ld_tl tcg_gen_ld_i64
992#define tcg_gen_st8_tl tcg_gen_st8_i64
993#define tcg_gen_st16_tl tcg_gen_st16_i64
994#define tcg_gen_st32_tl tcg_gen_st32_i64
995#define tcg_gen_st_tl tcg_gen_st_i64
996#define tcg_gen_add_tl tcg_gen_add_i64
997#define tcg_gen_addi_tl tcg_gen_addi_i64
998#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 999#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 1000#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 1001#define tcg_gen_subi_tl tcg_gen_subi_i64
1002#define tcg_gen_and_tl tcg_gen_and_i64
1003#define tcg_gen_andi_tl tcg_gen_andi_i64
1004#define tcg_gen_or_tl tcg_gen_or_i64
1005#define tcg_gen_ori_tl tcg_gen_ori_i64
1006#define tcg_gen_xor_tl tcg_gen_xor_i64
1007#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 1008#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 1009#define tcg_gen_shl_tl tcg_gen_shl_i64
1010#define tcg_gen_shli_tl tcg_gen_shli_i64
1011#define tcg_gen_shr_tl tcg_gen_shr_i64
1012#define tcg_gen_shri_tl tcg_gen_shri_i64
1013#define tcg_gen_sar_tl tcg_gen_sar_i64
1014#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 1015#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 1016#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 1017#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 1018#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 1019#define tcg_gen_mul_tl tcg_gen_mul_i64
1020#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 1021#define tcg_gen_div_tl tcg_gen_div_i64
1022#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 1023#define tcg_gen_divu_tl tcg_gen_divu_i64
1024#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 1025#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 1026#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 1027#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1028#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1029#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1030#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1031#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 1032#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1033#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1034#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1035#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1036#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1037#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 1038#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
1039#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
1040#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 1041#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 1042#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 1043#define tcg_gen_andc_tl tcg_gen_andc_i64
1044#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1045#define tcg_gen_nand_tl tcg_gen_nand_i64
1046#define tcg_gen_nor_tl tcg_gen_nor_i64
1047#define tcg_gen_orc_tl tcg_gen_orc_i64
0e28d006
RH		 1048#define tcg_gen_clz_tl tcg_gen_clz_i64
1049#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1050#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1051#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
086920c2 1052#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
a768e4e9 1053#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
15824571
AJ		 1054#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1055#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1056#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1057#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 1058#define tcg_gen_deposit_tl tcg_gen_deposit_i64
07cc68d5 1059#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
7ec8bab3
RH		 1060#define tcg_gen_extract_tl tcg_gen_extract_i64
1061#define tcg_gen_sextract_tl tcg_gen_sextract_i64
a98824ac 1062#define tcg_const_tl tcg_const_i64
bdffd4a9 1063#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 1064#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 1065#define tcg_gen_add2_tl tcg_gen_add2_i64
1066#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 1067#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1068#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 1069#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
b87fb8cd
RH		 1070#define tcg_gen_smin_tl tcg_gen_smin_i64
1071#define tcg_gen_umin_tl tcg_gen_umin_i64
1072#define tcg_gen_smax_tl tcg_gen_smax_i64
1073#define tcg_gen_umax_tl tcg_gen_umax_i64
c482cb11
RH		 1074#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1075#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1076#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1077#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1078#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1079#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
5507c2bf
RH		 1080#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
1081#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
1082#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
1083#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
c482cb11
RH		 1084#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1085#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1086#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1087#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
5507c2bf
RH		 1088#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
1089#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
1090#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
1091#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
d2fd745f 1092#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
f8422f52 1093#else
f8422f52
BS		 1094#define tcg_gen_movi_tl tcg_gen_movi_i32
1095#define tcg_gen_mov_tl tcg_gen_mov_i32
1096#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1097#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1098#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1099#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1100#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1101#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1102#define tcg_gen_ld_tl tcg_gen_ld_i32
1103#define tcg_gen_st8_tl tcg_gen_st8_i32
1104#define tcg_gen_st16_tl tcg_gen_st16_i32
1105#define tcg_gen_st32_tl tcg_gen_st_i32
1106#define tcg_gen_st_tl tcg_gen_st_i32
1107#define tcg_gen_add_tl tcg_gen_add_i32
1108#define tcg_gen_addi_tl tcg_gen_addi_i32
1109#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 1110#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 1111#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 1112#define tcg_gen_subi_tl tcg_gen_subi_i32
1113#define tcg_gen_and_tl tcg_gen_and_i32
1114#define tcg_gen_andi_tl tcg_gen_andi_i32
1115#define tcg_gen_or_tl tcg_gen_or_i32
1116#define tcg_gen_ori_tl tcg_gen_ori_i32
1117#define tcg_gen_xor_tl tcg_gen_xor_i32
1118#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 1119#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 1120#define tcg_gen_shl_tl tcg_gen_shl_i32
1121#define tcg_gen_shli_tl tcg_gen_shli_i32
1122#define tcg_gen_shr_tl tcg_gen_shr_i32
1123#define tcg_gen_shri_tl tcg_gen_shri_i32
1124#define tcg_gen_sar_tl tcg_gen_sar_i32
1125#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1126#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1127#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1128#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1129#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1130#define tcg_gen_mul_tl tcg_gen_mul_i32
1131#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1132#define tcg_gen_div_tl tcg_gen_div_i32
1133#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1134#define tcg_gen_divu_tl tcg_gen_divu_i32
1135#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1136#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1137#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1138#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1139#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1140#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1141#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1142#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1143#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1144#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1145#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1146#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1147#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1148#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 1149#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1150#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 1151#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1152#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1153#define tcg_gen_andc_tl tcg_gen_andc_i32
1154#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1155#define tcg_gen_nand_tl tcg_gen_nand_i32
1156#define tcg_gen_nor_tl tcg_gen_nor_i32
1157#define tcg_gen_orc_tl tcg_gen_orc_i32
0e28d006
RH		 1158#define tcg_gen_clz_tl tcg_gen_clz_i32
1159#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1160#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1161#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
086920c2 1162#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
a768e4e9 1163#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
15824571
AJ		 1164#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1165#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1166#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1167#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1168#define tcg_gen_deposit_tl tcg_gen_deposit_i32
07cc68d5 1169#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
7ec8bab3
RH		 1170#define tcg_gen_extract_tl tcg_gen_extract_i32
1171#define tcg_gen_sextract_tl tcg_gen_sextract_i32
a98824ac 1172#define tcg_const_tl tcg_const_i32
bdffd4a9 1173#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 1174#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1175#define tcg_gen_add2_tl tcg_gen_add2_i32
1176#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1177#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1178#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1179#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
b87fb8cd
RH		 1180#define tcg_gen_smin_tl tcg_gen_smin_i32
1181#define tcg_gen_umin_tl tcg_gen_umin_i32
1182#define tcg_gen_smax_tl tcg_gen_smax_i32
1183#define tcg_gen_umax_tl tcg_gen_umax_i32
c482cb11
RH		 1184#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1185#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1186#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1187#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1188#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1189#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
5507c2bf
RH		 1190#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
1191#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
1192#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
1193#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
c482cb11
RH		 1194#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1195#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1196#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1197#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
5507c2bf
RH		 1198#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
1199#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
1200#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
1201#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
d2fd745f 1202#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
f8422f52 1203#endif
6ddbc6e4 1204
71b92699 1205#if UINTPTR_MAX == UINT32_MAX
5bfa8034
RH		 1206# define PTR i32
1207# define NAT TCGv_i32
f713d6ad 1208#else
5bfa8034
RH		 1209# define PTR i64
1210# define NAT TCGv_i64
1211#endif
1212
1213static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1214{
1215 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1216}
1217
1218static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1219{
1220 glue(tcg_gen_discard_,PTR)((NAT)a);
1221}
1222
1223static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1224{
1225 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1226}
1227
1228static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1229{
1230 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1231}
1232
1233static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1234 intptr_t b, TCGLabel *label)
1235{
1236 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1237}
1238
1239static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1240{
1241#if UINTPTR_MAX == UINT32_MAX
1242 tcg_gen_mov_i32((NAT)r, a);
1243#else
1244 tcg_gen_ext_i32_i64((NAT)r, a);
1245#endif
1246}
1247
1248static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1249{
1250#if UINTPTR_MAX == UINT32_MAX
1251 tcg_gen_extrl_i64_i32((NAT)r, a);
1252#else
1253 tcg_gen_mov_i64((NAT)r, a);
1254#endif
1255}
1256
1257static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1258{
1259#if UINTPTR_MAX == UINT32_MAX
1260 tcg_gen_extu_i32_i64(r, (NAT)a);
1261#else
1262 tcg_gen_mov_i64(r, (NAT)a);
1263#endif
1264}
1265
1266static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1267{
1268#if UINTPTR_MAX == UINT32_MAX
1269 tcg_gen_mov_i32(r, (NAT)a);
1270#else
1271 tcg_gen_extrl_i64_i32(r, (NAT)a);
1272#endif
1273}
1274
1275#undef PTR
1276#undef NAT
a7ce790a
PM		 1277
1278#endif /* TCG_TCG_OP_H */
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