[qemu.git] / target / openrisc / sys_helper.c

/*
 * OpenRISC system instructions helper routines
 *
 * Copyright (c) 2011-2012 Jia Liu <[email protected]>
 *                         Zhizhou Zhang <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"

#define TO_SPR(group, number) (((group) << 11) + (number))

void HELPER(mtspr)(CPUOpenRISCState *env,
                   target_ulong ra, target_ulong rb, target_ulong offset)
{
#ifndef CONFIG_USER_ONLY
    int spr = (ra | offset);
    int idx;

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
    CPUState *cs = CPU(cpu);

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        env->vr = rb;
        break;

    case TO_SPR(0, 16): /* NPC */
        env->npc = rb;
        break;

    case TO_SPR(0, 17): /* SR */
        if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
            (rb & (SR_IME | SR_DME | SR_SM))) {
            tlb_flush(cs);
        }
        cpu_set_sr(env, rb);
        if (env->sr & SR_DME) {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_data;
        } else {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_nommu;
        }

        if (env->sr & SR_IME) {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_code;
        } else {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_nommu;
        }
        break;

    case TO_SPR(0, 18): /* PPC */
        env->ppc = rb;
        break;

    case TO_SPR(0, 32): /* EPCR */
        env->epcr = rb;
        break;

    case TO_SPR(0, 48): /* EEAR */
        env->eear = rb;
        break;

    case TO_SPR(0, 64): /* ESR */
        env->esr = rb;
        break;
    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        if (!(rb & 1)) {
            tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->dtlb[0][idx].mr = rb;
        break;

    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        env->tlb->dtlb[0][idx].tr = rb;
        break;
    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;
    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        if (!(rb & 1)) {
            tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->itlb[0][idx].mr = rb;
        break;

    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        env->tlb->itlb[0][idx].tr = rb;
        break;
    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;
    case TO_SPR(5, 1):  /* MACLO */
        env->mac = deposit64(env->mac, 0, 32, rb);
        break;
    case TO_SPR(5, 2):  /* MACHI */
        env->mac = deposit64(env->mac, 32, 32, rb);
        break;
    case TO_SPR(9, 0):  /* PICMR */
        env->picmr |= rb;
        break;
    case TO_SPR(9, 2):  /* PICSR */
        env->picsr &= ~rb;
        break;
    case TO_SPR(10, 0): /* TTMR */
        {
            if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
                switch (rb & TTMR_M) {
                case TIMER_NONE:
                    cpu_openrisc_count_stop(cpu);
                    break;
                case TIMER_INTR:
                case TIMER_SHOT:
                case TIMER_CONT:
                    cpu_openrisc_count_start(cpu);
                    break;
                default:
                    break;
                }
            }

            int ip = env->ttmr & TTMR_IP;

            if (rb & TTMR_IP) {    /* Keep IP bit.  */
                env->ttmr = (rb & ~TTMR_IP) | ip;
            } else {    /* Clear IP bit.  */
                env->ttmr = rb & ~TTMR_IP;
                cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
            }

            cpu_openrisc_timer_update(cpu);
        }
        break;

    case TO_SPR(10, 1): /* TTCR */
        env->ttcr = rb;
        if (env->ttmr & TIMER_NONE) {
            return;
        }
        cpu_openrisc_timer_update(cpu);
        break;
    default:

        break;
    }
#endif
}

target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
                           target_ulong rd, target_ulong ra, uint32_t offset)
{
#ifndef CONFIG_USER_ONLY
    int spr = (ra | offset);
    int idx;

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        return env->vr & SPR_VR;

    case TO_SPR(0, 1): /* UPR */
        return env->upr;    /* TT, DM, IM, UP present */

    case TO_SPR(0, 2): /* CPUCFGR */
        return env->cpucfgr;

    case TO_SPR(0, 3): /* DMMUCFGR */
        return env->dmmucfgr;    /* 1Way, 64 entries */

    case TO_SPR(0, 4): /* IMMUCFGR */
        return env->immucfgr;

    case TO_SPR(0, 16): /* NPC */
        return env->npc;

    case TO_SPR(0, 17): /* SR */
        return cpu_get_sr(env);

    case TO_SPR(0, 18): /* PPC */
        return env->ppc;

    case TO_SPR(0, 32): /* EPCR */
        return env->epcr;

    case TO_SPR(0, 48): /* EEAR */
        return env->eear;

    case TO_SPR(0, 64): /* ESR */
        return env->esr;

    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        return env->tlb->dtlb[0][idx].mr;

    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        return env->tlb->dtlb[0][idx].tr;

    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;

    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        return env->tlb->itlb[0][idx].mr;

    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        return env->tlb->itlb[0][idx].tr;

    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;

    case TO_SPR(5, 1):  /* MACLO */
        return (uint32_t)env->mac;
        break;
    case TO_SPR(5, 2):  /* MACHI */
        return env->mac >> 32;
        break;

    case TO_SPR(9, 0):  /* PICMR */
        return env->picmr;

    case TO_SPR(9, 2):  /* PICSR */
        return env->picsr;

    case TO_SPR(10, 0): /* TTMR */
        return env->ttmr;

    case TO_SPR(10, 1): /* TTCR */
        cpu_openrisc_count_update(cpu);
        return env->ttcr;

    default:
        break;
    }
#endif

/*If we later need to add tracepoints (or debug printfs) for the return
value, it may be useful to structure the code like this:

target_ulong ret = 0;

switch() {
case x:
 ret = y;
 break;
case z:
 ret = 42;
 break;
...
}

later something like trace_spr_read(ret);

return ret;*/

    /* for rd is passed in, if rd unchanged, just keep it back.  */
    return rd;
}
Commit	Line	Data
4dd044c6 JL	1	/*
	2	* OpenRISC system instructions helper routines
	3	*
	4	* Copyright (c) 2011-2012 Jia Liu <[email protected]>
	5	* Zhizhou Zhang <[email protected]>
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
ed2decc6	21	#include "qemu/osdep.h"
4dd044c6	22	#include "cpu.h"
63c91552	23	#include "exec/exec-all.h"
2ef6175a	24	#include "exec/helper-proto.h"
4dd044c6 JL	25
	26	#define TO_SPR(group, number) (((group) << 11) + (number))
	27
	28	void HELPER(mtspr)(CPUOpenRISCState *env,
	29	target_ulong ra, target_ulong rb, target_ulong offset)
	30	{
	31	#ifndef CONFIG_USER_ONLY
	32	int spr = (ra \| offset);
	33	int idx;
	34
dd51dc52	35	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
259186a7	36	CPUState *cs = CPU(cpu);
4dd044c6 JL	37
	38	switch (spr) {
	39	case TO_SPR(0, 0): /* VR */
	40	env->vr = rb;
	41	break;
	42
	43	case TO_SPR(0, 16): /* NPC */
	44	env->npc = rb;
	45	break;
	46
	47	case TO_SPR(0, 17): /* SR */
	48	if ((env->sr & (SR_IME \| SR_DME \| SR_SM)) ^
	49	(rb & (SR_IME \| SR_DME \| SR_SM))) {
d10eb08f	50	tlb_flush(cs);
4dd044c6	51	}
84775c43	52	cpu_set_sr(env, rb);
4dd044c6 JL	53	if (env->sr & SR_DME) {
	54	env->tlb->cpu_openrisc_map_address_data =
	55	&cpu_openrisc_get_phys_data;
	56	} else {
	57	env->tlb->cpu_openrisc_map_address_data =
	58	&cpu_openrisc_get_phys_nommu;
	59	}
	60
	61	if (env->sr & SR_IME) {
	62	env->tlb->cpu_openrisc_map_address_code =
	63	&cpu_openrisc_get_phys_code;
	64	} else {
	65	env->tlb->cpu_openrisc_map_address_code =
	66	&cpu_openrisc_get_phys_nommu;
	67	}
	68	break;
	69
	70	case TO_SPR(0, 18): /* PPC */
	71	env->ppc = rb;
	72	break;
	73
	74	case TO_SPR(0, 32): /* EPCR */
	75	env->epcr = rb;
	76	break;
	77
	78	case TO_SPR(0, 48): /* EEAR */
	79	env->eear = rb;
	80	break;
	81
	82	case TO_SPR(0, 64): /* ESR */
	83	env->esr = rb;
	84	break;
93147a18	85	case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
4dd044c6 JL	86	idx = spr - TO_SPR(1, 512);
4dd044c6 JL	87	if (!(rb & 1)) {
31b030d4	88	tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
4dd044c6 JL	89	}
	90	env->tlb->dtlb[0][idx].mr = rb;
	91	break;
	92
93147a18	93	case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
4dd044c6 JL	94	idx = spr - TO_SPR(1, 640);
	95	env->tlb->dtlb[0][idx].tr = rb;
	96	break;
	97	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	98	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	99	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	100	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	101	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	102	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	103	break;
93147a18	104	case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
4dd044c6 JL	105	idx = spr - TO_SPR(2, 512);
4dd044c6 JL	106	if (!(rb & 1)) {
31b030d4	107	tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
4dd044c6 JL	108	}
	109	env->tlb->itlb[0][idx].mr = rb;
	110	break;
	111
93147a18	112	case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
4dd044c6 JL	113	idx = spr - TO_SPR(2, 640);
	114	env->tlb->itlb[0][idx].tr = rb;
	115	break;
	116	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	117	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	118	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	119	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	120	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	121	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	122	break;
6f7332ba RH	123	case TO_SPR(5, 1): /* MACLO */
	124	env->mac = deposit64(env->mac, 0, 32, rb);
	125	break;
	126	case TO_SPR(5, 2): /* MACHI */
	127	env->mac = deposit64(env->mac, 32, 32, rb);
	128	break;
4dd044c6 JL	129	case TO_SPR(9, 0): /* PICMR */
	130	env->picmr \|= rb;
	131	break;
	132	case TO_SPR(9, 2): /* PICSR */
	133	env->picsr &= ~rb;
	134	break;
	135	case TO_SPR(10, 0): /* TTMR */
	136	{
d5155217 SM	137	if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
	138	switch (rb & TTMR_M) {
	139	case TIMER_NONE:
	140	cpu_openrisc_count_stop(cpu);
	141	break;
	142	case TIMER_INTR:
	143	case TIMER_SHOT:
	144	case TIMER_CONT:
	145	cpu_openrisc_count_start(cpu);
	146	break;
	147	default:
	148	break;
	149	}
	150	}
	151
4dd044c6 JL	152	int ip = env->ttmr & TTMR_IP;
	153
	154	if (rb & TTMR_IP) { /* Keep IP bit. */
d5155217	155	env->ttmr = (rb & ~TTMR_IP) \| ip;
4dd044c6 JL	156	} else { /* Clear IP bit. */
4dd044c6 JL	157	env->ttmr = rb & ~TTMR_IP;
259186a7	158	cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
4dd044c6 JL	159	}
4dd044c6 JL	160
d5155217	161	cpu_openrisc_timer_update(cpu);
4dd044c6 JL	162	}
	163	break;
	164
	165	case TO_SPR(10, 1): /* TTCR */
	166	env->ttcr = rb;
	167	if (env->ttmr & TIMER_NONE) {
	168	return;
	169	}
d5155217	170	cpu_openrisc_timer_update(cpu);
4dd044c6 JL	171	break;
	172	default:
	173
	174	break;
	175	}
	176	#endif
	177	}
	178
	179	target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
	180	target_ulong rd, target_ulong ra, uint32_t offset)
	181	{
	182	#ifndef CONFIG_USER_ONLY
	183	int spr = (ra \| offset);
	184	int idx;
	185
dd51dc52	186	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
4dd044c6 JL	187
	188	switch (spr) {
	189	case TO_SPR(0, 0): /* VR */
	190	return env->vr & SPR_VR;
	191
	192	case TO_SPR(0, 1): /* UPR */
	193	return env->upr; /* TT, DM, IM, UP present */
	194
	195	case TO_SPR(0, 2): /* CPUCFGR */
	196	return env->cpucfgr;
	197
	198	case TO_SPR(0, 3): /* DMMUCFGR */
	199	return env->dmmucfgr; /* 1Way, 64 entries */
	200
	201	case TO_SPR(0, 4): /* IMMUCFGR */
	202	return env->immucfgr;
	203
	204	case TO_SPR(0, 16): /* NPC */
	205	return env->npc;
	206
	207	case TO_SPR(0, 17): /* SR */
84775c43	208	return cpu_get_sr(env);
4dd044c6 JL	209
	210	case TO_SPR(0, 18): /* PPC */
	211	return env->ppc;
	212
	213	case TO_SPR(0, 32): /* EPCR */
	214	return env->epcr;
	215
	216	case TO_SPR(0, 48): /* EEAR */
	217	return env->eear;
	218
	219	case TO_SPR(0, 64): /* ESR */
	220	return env->esr;
	221
93147a18	222	case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
4dd044c6 JL	223	idx = spr - TO_SPR(1, 512);
	224	return env->tlb->dtlb[0][idx].mr;
	225
93147a18	226	case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
4dd044c6 JL	227	idx = spr - TO_SPR(1, 640);
	228	return env->tlb->dtlb[0][idx].tr;
	229
	230	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	231	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	232	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	233	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	234	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	235	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	236	break;
	237
93147a18	238	case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
4dd044c6 JL	239	idx = spr - TO_SPR(2, 512);
	240	return env->tlb->itlb[0][idx].mr;
	241
93147a18	242	case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
4dd044c6 JL	243	idx = spr - TO_SPR(2, 640);
	244	return env->tlb->itlb[0][idx].tr;
	245
	246	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	247	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	248	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	249	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	250	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	251	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	252	break;
	253
6f7332ba RH	254	case TO_SPR(5, 1): /* MACLO */
	255	return (uint32_t)env->mac;
	256	break;
	257	case TO_SPR(5, 2): /* MACHI */
	258	return env->mac >> 32;
	259	break;
	260
4dd044c6 JL	261	case TO_SPR(9, 0): /* PICMR */
	262	return env->picmr;
	263
	264	case TO_SPR(9, 2): /* PICSR */
	265	return env->picsr;
	266
	267	case TO_SPR(10, 0): /* TTMR */
	268	return env->ttmr;
	269
	270	case TO_SPR(10, 1): /* TTCR */
	271	cpu_openrisc_count_update(cpu);
	272	return env->ttcr;
	273
	274	default:
	275	break;
	276	}
	277	#endif
	278
	279	/*If we later need to add tracepoints (or debug printfs) for the return
	280	value, it may be useful to structure the code like this:
	281
	282	target_ulong ret = 0;
	283
	284	switch() {
	285	case x:
	286	ret = y;
	287	break;
	288	case z:
	289	ret = 42;
	290	break;
	291	...
	292	}
	293
	294	later something like trace_spr_read(ret);
	295
	296	return ret;*/
	297
	298	/* for rd is passed in, if rd unchanged, just keep it back. */
	299	return rd;
	300	}