[qemu.git] / target / openrisc / sys_helper.c

/*
 * OpenRISC system instructions helper routines
 *
 * Copyright (c) 2011-2012 Jia Liu <[email protected]>
 *                         Zhizhou Zhang <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"

#define TO_SPR(group, number) (((group) << 11) + (number))

void HELPER(mtspr)(CPUOpenRISCState *env,
                   target_ulong ra, target_ulong rb, target_ulong offset)
{
#ifndef CONFIG_USER_ONLY
    int spr = (ra | offset);
    int idx;

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
    CPUState *cs = CPU(cpu);

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        env->vr = rb;
        break;

    case TO_SPR(0, 16): /* NPC */
        env->npc = rb;
        break;

    case TO_SPR(0, 17): /* SR */
        if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
            (rb & (SR_IME | SR_DME | SR_SM))) {
            tlb_flush(cs);
        }
        env->sr = rb;
        env->sr |= SR_FO;      /* FO is const equal to 1 */
        if (env->sr & SR_DME) {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_data;
        } else {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_nommu;
        }

        if (env->sr & SR_IME) {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_code;
        } else {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_nommu;
        }
        break;

    case TO_SPR(0, 18): /* PPC */
        env->ppc = rb;
        break;

    case TO_SPR(0, 32): /* EPCR */
        env->epcr = rb;
        break;

    case TO_SPR(0, 48): /* EEAR */
        env->eear = rb;
        break;

    case TO_SPR(0, 64): /* ESR */
        env->esr = rb;
        break;
    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        if (!(rb & 1)) {
            tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->dtlb[0][idx].mr = rb;
        break;

    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        env->tlb->dtlb[0][idx].tr = rb;
        break;
    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;
    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        if (!(rb & 1)) {
            tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->itlb[0][idx].mr = rb;
        break;

    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        env->tlb->itlb[0][idx].tr = rb;
        break;
    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;
    case TO_SPR(9, 0):  /* PICMR */
        env->picmr |= rb;
        break;
    case TO_SPR(9, 2):  /* PICSR */
        env->picsr &= ~rb;
        break;
    case TO_SPR(10, 0): /* TTMR */
        {
            if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
                switch (rb & TTMR_M) {
                case TIMER_NONE:
                    cpu_openrisc_count_stop(cpu);
                    break;
                case TIMER_INTR:
                case TIMER_SHOT:
                case TIMER_CONT:
                    cpu_openrisc_count_start(cpu);
                    break;
                default:
                    break;
                }
            }

            int ip = env->ttmr & TTMR_IP;

            if (rb & TTMR_IP) {    /* Keep IP bit.  */
                env->ttmr = (rb & ~TTMR_IP) | ip;
            } else {    /* Clear IP bit.  */
                env->ttmr = rb & ~TTMR_IP;
                cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
            }

            cpu_openrisc_timer_update(cpu);
        }
        break;

    case TO_SPR(10, 1): /* TTCR */
        env->ttcr = rb;
        if (env->ttmr & TIMER_NONE) {
            return;
        }
        cpu_openrisc_timer_update(cpu);
        break;
    default:

        break;
    }
#endif
}

target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
                           target_ulong rd, target_ulong ra, uint32_t offset)
{
#ifndef CONFIG_USER_ONLY
    int spr = (ra | offset);
    int idx;

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        return env->vr & SPR_VR;

    case TO_SPR(0, 1): /* UPR */
        return env->upr;    /* TT, DM, IM, UP present */

    case TO_SPR(0, 2): /* CPUCFGR */
        return env->cpucfgr;

    case TO_SPR(0, 3): /* DMMUCFGR */
        return env->dmmucfgr;    /* 1Way, 64 entries */

    case TO_SPR(0, 4): /* IMMUCFGR */
        return env->immucfgr;

    case TO_SPR(0, 16): /* NPC */
        return env->npc;

    case TO_SPR(0, 17): /* SR */
        return env->sr;

    case TO_SPR(0, 18): /* PPC */
        return env->ppc;

    case TO_SPR(0, 32): /* EPCR */
        return env->epcr;

    case TO_SPR(0, 48): /* EEAR */
        return env->eear;

    case TO_SPR(0, 64): /* ESR */
        return env->esr;

    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        return env->tlb->dtlb[0][idx].mr;

    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        return env->tlb->dtlb[0][idx].tr;

    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;

    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        return env->tlb->itlb[0][idx].mr;

    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        return env->tlb->itlb[0][idx].tr;

    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;

    case TO_SPR(9, 0):  /* PICMR */
        return env->picmr;

    case TO_SPR(9, 2):  /* PICSR */
        return env->picsr;

    case TO_SPR(10, 0): /* TTMR */
        return env->ttmr;

    case TO_SPR(10, 1): /* TTCR */
        cpu_openrisc_count_update(cpu);
        return env->ttcr;

    default:
        break;
    }
#endif

/*If we later need to add tracepoints (or debug printfs) for the return
value, it may be useful to structure the code like this:

target_ulong ret = 0;

switch() {
case x:
 ret = y;
 break;
case z:
 ret = 42;
 break;
...
}

later something like trace_spr_read(ret);

return ret;*/

    /* for rd is passed in, if rd unchanged, just keep it back.  */
    return rd;
}
Commit	Line	Data
4dd044c6 JL	1	/*
	2	* OpenRISC system instructions helper routines
	3	*
	4	* Copyright (c) 2011-2012 Jia Liu <[email protected]>
	5	* Zhizhou Zhang <[email protected]>
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
ed2decc6	21	#include "qemu/osdep.h"
4dd044c6	22	#include "cpu.h"
63c91552	23	#include "exec/exec-all.h"
2ef6175a	24	#include "exec/helper-proto.h"
4dd044c6 JL	25
	26	#define TO_SPR(group, number) (((group) << 11) + (number))
	27
	28	void HELPER(mtspr)(CPUOpenRISCState *env,
	29	target_ulong ra, target_ulong rb, target_ulong offset)
	30	{
	31	#ifndef CONFIG_USER_ONLY
	32	int spr = (ra \| offset);
	33	int idx;
	34
dd51dc52	35	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
259186a7	36	CPUState *cs = CPU(cpu);
4dd044c6 JL	37
	38	switch (spr) {
	39	case TO_SPR(0, 0): /* VR */
	40	env->vr = rb;
	41	break;
	42
	43	case TO_SPR(0, 16): /* NPC */
	44	env->npc = rb;
	45	break;
	46
	47	case TO_SPR(0, 17): /* SR */
	48	if ((env->sr & (SR_IME \| SR_DME \| SR_SM)) ^
	49	(rb & (SR_IME \| SR_DME \| SR_SM))) {
d10eb08f	50	tlb_flush(cs);
4dd044c6 JL	51	}
	52	env->sr = rb;
	53	env->sr \|= SR_FO; /* FO is const equal to 1 */
	54	if (env->sr & SR_DME) {
	55	env->tlb->cpu_openrisc_map_address_data =
	56	&cpu_openrisc_get_phys_data;
	57	} else {
	58	env->tlb->cpu_openrisc_map_address_data =
	59	&cpu_openrisc_get_phys_nommu;
	60	}
	61
	62	if (env->sr & SR_IME) {
	63	env->tlb->cpu_openrisc_map_address_code =
	64	&cpu_openrisc_get_phys_code;
	65	} else {
	66	env->tlb->cpu_openrisc_map_address_code =
	67	&cpu_openrisc_get_phys_nommu;
	68	}
	69	break;
	70
	71	case TO_SPR(0, 18): /* PPC */
	72	env->ppc = rb;
	73	break;
	74
	75	case TO_SPR(0, 32): /* EPCR */
	76	env->epcr = rb;
	77	break;
	78
	79	case TO_SPR(0, 48): /* EEAR */
	80	env->eear = rb;
	81	break;
	82
	83	case TO_SPR(0, 64): /* ESR */
	84	env->esr = rb;
	85	break;
93147a18	86	case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
4dd044c6 JL	87	idx = spr - TO_SPR(1, 512);
4dd044c6 JL	88	if (!(rb & 1)) {
31b030d4	89	tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
4dd044c6 JL	90	}
	91	env->tlb->dtlb[0][idx].mr = rb;
	92	break;
	93
93147a18	94	case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
4dd044c6 JL	95	idx = spr - TO_SPR(1, 640);
	96	env->tlb->dtlb[0][idx].tr = rb;
	97	break;
	98	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	99	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	100	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	101	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	102	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	103	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	104	break;
93147a18	105	case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
4dd044c6 JL	106	idx = spr - TO_SPR(2, 512);
4dd044c6 JL	107	if (!(rb & 1)) {
31b030d4	108	tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
4dd044c6 JL	109	}
	110	env->tlb->itlb[0][idx].mr = rb;
	111	break;
	112
93147a18	113	case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
4dd044c6 JL	114	idx = spr - TO_SPR(2, 640);
	115	env->tlb->itlb[0][idx].tr = rb;
	116	break;
	117	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	118	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	119	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	120	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	121	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	122	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	123	break;
	124	case TO_SPR(9, 0): /* PICMR */
	125	env->picmr \|= rb;
	126	break;
	127	case TO_SPR(9, 2): /* PICSR */
	128	env->picsr &= ~rb;
	129	break;
	130	case TO_SPR(10, 0): /* TTMR */
	131	{
d5155217 SM	132	if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
	133	switch (rb & TTMR_M) {
	134	case TIMER_NONE:
	135	cpu_openrisc_count_stop(cpu);
	136	break;
	137	case TIMER_INTR:
	138	case TIMER_SHOT:
	139	case TIMER_CONT:
	140	cpu_openrisc_count_start(cpu);
	141	break;
	142	default:
	143	break;
	144	}
	145	}
	146
4dd044c6 JL	147	int ip = env->ttmr & TTMR_IP;
	148
	149	if (rb & TTMR_IP) { /* Keep IP bit. */
d5155217	150	env->ttmr = (rb & ~TTMR_IP) \| ip;
4dd044c6 JL	151	} else { /* Clear IP bit. */
4dd044c6 JL	152	env->ttmr = rb & ~TTMR_IP;
259186a7	153	cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
4dd044c6 JL	154	}
4dd044c6 JL	155
d5155217	156	cpu_openrisc_timer_update(cpu);
4dd044c6 JL	157	}
	158	break;
	159
	160	case TO_SPR(10, 1): /* TTCR */
	161	env->ttcr = rb;
	162	if (env->ttmr & TIMER_NONE) {
	163	return;
	164	}
d5155217	165	cpu_openrisc_timer_update(cpu);
4dd044c6 JL	166	break;
	167	default:
	168
	169	break;
	170	}
	171	#endif
	172	}
	173
	174	target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
	175	target_ulong rd, target_ulong ra, uint32_t offset)
	176	{
	177	#ifndef CONFIG_USER_ONLY
	178	int spr = (ra \| offset);
	179	int idx;
	180
dd51dc52	181	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
4dd044c6 JL	182
	183	switch (spr) {
	184	case TO_SPR(0, 0): /* VR */
	185	return env->vr & SPR_VR;
	186
	187	case TO_SPR(0, 1): /* UPR */
	188	return env->upr; /* TT, DM, IM, UP present */
	189
	190	case TO_SPR(0, 2): /* CPUCFGR */
	191	return env->cpucfgr;
	192
	193	case TO_SPR(0, 3): /* DMMUCFGR */
	194	return env->dmmucfgr; /* 1Way, 64 entries */
	195
	196	case TO_SPR(0, 4): /* IMMUCFGR */
	197	return env->immucfgr;
	198
	199	case TO_SPR(0, 16): /* NPC */
	200	return env->npc;
	201
	202	case TO_SPR(0, 17): /* SR */
	203	return env->sr;
	204
	205	case TO_SPR(0, 18): /* PPC */
	206	return env->ppc;
	207
	208	case TO_SPR(0, 32): /* EPCR */
	209	return env->epcr;
	210
	211	case TO_SPR(0, 48): /* EEAR */
	212	return env->eear;
	213
	214	case TO_SPR(0, 64): /* ESR */
	215	return env->esr;
	216
93147a18	217	case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
4dd044c6 JL	218	idx = spr - TO_SPR(1, 512);
	219	return env->tlb->dtlb[0][idx].mr;
	220
93147a18	221	case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
4dd044c6 JL	222	idx = spr - TO_SPR(1, 640);
	223	return env->tlb->dtlb[0][idx].tr;
	224
	225	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	226	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	227	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	228	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	229	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	230	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	231	break;
	232
93147a18	233	case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
4dd044c6 JL	234	idx = spr - TO_SPR(2, 512);
	235	return env->tlb->itlb[0][idx].mr;
	236
93147a18	237	case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
4dd044c6 JL	238	idx = spr - TO_SPR(2, 640);
	239	return env->tlb->itlb[0][idx].tr;
	240
	241	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	242	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	243	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	244	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	245	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	246	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	247	break;
	248
	249	case TO_SPR(9, 0): /* PICMR */
	250	return env->picmr;
	251
	252	case TO_SPR(9, 2): /* PICSR */
	253	return env->picsr;
	254
	255	case TO_SPR(10, 0): /* TTMR */
	256	return env->ttmr;
	257
	258	case TO_SPR(10, 1): /* TTCR */
	259	cpu_openrisc_count_update(cpu);
	260	return env->ttcr;
	261
	262	default:
	263	break;
	264	}
	265	#endif
	266
	267	/*If we later need to add tracepoints (or debug printfs) for the return
	268	value, it may be useful to structure the code like this:
	269
	270	target_ulong ret = 0;
	271
	272	switch() {
	273	case x:
	274	ret = y;
	275	break;
	276	case z:
	277	ret = 42;
	278	break;
	279	...
	280	}
	281
	282	later something like trace_spr_read(ret);
	283
	284	return ret;*/
	285
	286	/* for rd is passed in, if rd unchanged, just keep it back. */
	287	return rd;
	288	}