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target/openrisc: Represent MACHI:MACLO as a single unit
[qemu.git] / target / openrisc / sys_helper.c
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1/*
2 * OpenRISC system instructions helper routines
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Zhizhou Zhang <etouzh@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "exec/exec-all.h"
24#include "exec/helper-proto.h"
25
26#define TO_SPR(group, number) (((group) << 11) + (number))
27
28void HELPER(mtspr)(CPUOpenRISCState *env,
29 target_ulong ra, target_ulong rb, target_ulong offset)
30{
31#ifndef CONFIG_USER_ONLY
32 int spr = (ra | offset);
33 int idx;
34
35 OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
36 CPUState *cs = CPU(cpu);
37
38 switch (spr) {
39 case TO_SPR(0, 0): /* VR */
40 env->vr = rb;
41 break;
42
43 case TO_SPR(0, 16): /* NPC */
44 env->npc = rb;
45 break;
46
47 case TO_SPR(0, 17): /* SR */
48 if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
49 (rb & (SR_IME | SR_DME | SR_SM))) {
50 tlb_flush(cs);
51 }
52 cpu_set_sr(env, rb);
53 if (env->sr & SR_DME) {
54 env->tlb->cpu_openrisc_map_address_data =
55 &cpu_openrisc_get_phys_data;
56 } else {
57 env->tlb->cpu_openrisc_map_address_data =
58 &cpu_openrisc_get_phys_nommu;
59 }
60
61 if (env->sr & SR_IME) {
62 env->tlb->cpu_openrisc_map_address_code =
63 &cpu_openrisc_get_phys_code;
64 } else {
65 env->tlb->cpu_openrisc_map_address_code =
66 &cpu_openrisc_get_phys_nommu;
67 }
68 break;
69
70 case TO_SPR(0, 18): /* PPC */
71 env->ppc = rb;
72 break;
73
74 case TO_SPR(0, 32): /* EPCR */
75 env->epcr = rb;
76 break;
77
78 case TO_SPR(0, 48): /* EEAR */
79 env->eear = rb;
80 break;
81
82 case TO_SPR(0, 64): /* ESR */
83 env->esr = rb;
84 break;
85 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
86 idx = spr - TO_SPR(1, 512);
87 if (!(rb & 1)) {
88 tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
89 }
90 env->tlb->dtlb[0][idx].mr = rb;
91 break;
92
93 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
94 idx = spr - TO_SPR(1, 640);
95 env->tlb->dtlb[0][idx].tr = rb;
96 break;
97 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
98 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
99 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
100 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
101 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
102 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
103 break;
104 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
105 idx = spr - TO_SPR(2, 512);
106 if (!(rb & 1)) {
107 tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
108 }
109 env->tlb->itlb[0][idx].mr = rb;
110 break;
111
112 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
113 idx = spr - TO_SPR(2, 640);
114 env->tlb->itlb[0][idx].tr = rb;
115 break;
116 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
117 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
118 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
119 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
120 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
121 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
122 break;
123 case TO_SPR(5, 1): /* MACLO */
124 env->mac = deposit64(env->mac, 0, 32, rb);
125 break;
126 case TO_SPR(5, 2): /* MACHI */
127 env->mac = deposit64(env->mac, 32, 32, rb);
128 break;
129 case TO_SPR(9, 0): /* PICMR */
130 env->picmr |= rb;
131 break;
132 case TO_SPR(9, 2): /* PICSR */
133 env->picsr &= ~rb;
134 break;
135 case TO_SPR(10, 0): /* TTMR */
136 {
137 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
138 switch (rb & TTMR_M) {
139 case TIMER_NONE:
140 cpu_openrisc_count_stop(cpu);
141 break;
142 case TIMER_INTR:
143 case TIMER_SHOT:
144 case TIMER_CONT:
145 cpu_openrisc_count_start(cpu);
146 break;
147 default:
148 break;
149 }
150 }
151
152 int ip = env->ttmr & TTMR_IP;
153
154 if (rb & TTMR_IP) { /* Keep IP bit. */
155 env->ttmr = (rb & ~TTMR_IP) | ip;
156 } else { /* Clear IP bit. */
157 env->ttmr = rb & ~TTMR_IP;
158 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
159 }
160
161 cpu_openrisc_timer_update(cpu);
162 }
163 break;
164
165 case TO_SPR(10, 1): /* TTCR */
166 env->ttcr = rb;
167 if (env->ttmr & TIMER_NONE) {
168 return;
169 }
170 cpu_openrisc_timer_update(cpu);
171 break;
172 default:
173
174 break;
175 }
176#endif
177}
178
179target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
180 target_ulong rd, target_ulong ra, uint32_t offset)
181{
182#ifndef CONFIG_USER_ONLY
183 int spr = (ra | offset);
184 int idx;
185
186 OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
187
188 switch (spr) {
189 case TO_SPR(0, 0): /* VR */
190 return env->vr & SPR_VR;
191
192 case TO_SPR(0, 1): /* UPR */
193 return env->upr; /* TT, DM, IM, UP present */
194
195 case TO_SPR(0, 2): /* CPUCFGR */
196 return env->cpucfgr;
197
198 case TO_SPR(0, 3): /* DMMUCFGR */
199 return env->dmmucfgr; /* 1Way, 64 entries */
200
201 case TO_SPR(0, 4): /* IMMUCFGR */
202 return env->immucfgr;
203
204 case TO_SPR(0, 16): /* NPC */
205 return env->npc;
206
207 case TO_SPR(0, 17): /* SR */
208 return cpu_get_sr(env);
209
210 case TO_SPR(0, 18): /* PPC */
211 return env->ppc;
212
213 case TO_SPR(0, 32): /* EPCR */
214 return env->epcr;
215
216 case TO_SPR(0, 48): /* EEAR */
217 return env->eear;
218
219 case TO_SPR(0, 64): /* ESR */
220 return env->esr;
221
222 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
223 idx = spr - TO_SPR(1, 512);
224 return env->tlb->dtlb[0][idx].mr;
225
226 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
227 idx = spr - TO_SPR(1, 640);
228 return env->tlb->dtlb[0][idx].tr;
229
230 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
231 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
232 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
233 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
234 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
235 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
236 break;
237
238 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
239 idx = spr - TO_SPR(2, 512);
240 return env->tlb->itlb[0][idx].mr;
241
242 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
243 idx = spr - TO_SPR(2, 640);
244 return env->tlb->itlb[0][idx].tr;
245
246 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
247 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
248 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
249 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
250 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
251 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
252 break;
253
254 case TO_SPR(5, 1): /* MACLO */
255 return (uint32_t)env->mac;
256 break;
257 case TO_SPR(5, 2): /* MACHI */
258 return env->mac >> 32;
259 break;
260
261 case TO_SPR(9, 0): /* PICMR */
262 return env->picmr;
263
264 case TO_SPR(9, 2): /* PICSR */
265 return env->picsr;
266
267 case TO_SPR(10, 0): /* TTMR */
268 return env->ttmr;
269
270 case TO_SPR(10, 1): /* TTCR */
271 cpu_openrisc_count_update(cpu);
272 return env->ttcr;
273
274 default:
275 break;
276 }
277#endif
278
279/*If we later need to add tracepoints (or debug printfs) for the return
280value, it may be useful to structure the code like this:
281
282target_ulong ret = 0;
283
284switch() {
285case x:
286 ret = y;
287 break;
288case z:
289 ret = 42;
290 break;
291...
292}
293
294later something like trace_spr_read(ret);
295
296return ret;*/
297
298 /* for rd is passed in, if rd unchanged, just keep it back. */
299 return rd;
300}
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