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xen/pt: Use xen_host_pci_get_[byte|word] instead of dev.config
[qemu.git] / hw / xen / xen_pt_config_init.c
CommitLineData
93d7ae8e
AK		 1/*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <[email protected]>
9 * Allen Kay <[email protected]>
10 * Guy Zana <[email protected]>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
1de7afc9 15#include "qemu/timer.h"
0d09e41a 16#include "hw/xen/xen_backend.h"
47b43a1f 17#include "xen_pt.h"
eaab4d60 18
93d7ae8e
AK		 19#define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
21
22#define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
23
24/* prototype */
25
26static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
27 uint32_t real_offset, uint32_t *data);
28
29
30/* helper */
31
32/* A return value of 1 means the capability should NOT be exposed to guest. */
33static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id)
34{
35 switch (grp_id) {
36 case PCI_CAP_ID_EXP:
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
40 *
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
43 *
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
49 */
50 if (d->vendor_id == PCI_VENDOR_ID_INTEL &&
51 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) {
52 return 1;
53 }
54 break;
55 }
56 return 0;
57}
58
59/* find emulate register group entry */
eaab4d60
AK		 60XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address)
61{
93d7ae8e
AK		 62 XenPTRegGroup *entry = NULL;
63
64 /* find register group entry */
65 QLIST_FOREACH(entry, &s->reg_grps, entries) {
66 /* check address */
67 if ((entry->base_offset <= address)
68 && ((entry->base_offset + entry->size) > address)) {
69 return entry;
70 }
71 }
72
73 /* group entry not found */
eaab4d60
AK		 74 return NULL;
75}
76
93d7ae8e 77/* find emulate register entry */
eaab4d60
AK		 78XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address)
79{
93d7ae8e
AK		 80 XenPTReg *reg_entry = NULL;
81 XenPTRegInfo *reg = NULL;
82 uint32_t real_offset = 0;
83
84 /* find register entry */
85 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) {
86 reg = reg_entry->reg;
87 real_offset = reg_grp->base_offset + reg->offset;
88 /* check address */
89 if ((real_offset <= address)
90 && ((real_offset + reg->size) > address)) {
91 return reg_entry;
92 }
93 }
94
eaab4d60
AK		 95 return NULL;
96}
93d7ae8e 97
0e7ef221 98static uint32_t get_throughable_mask(const XenPCIPassthroughState *s,
74526eb0 99 XenPTRegInfo *reg, uint32_t valid_mask)
0e7ef221
JB		 100{
101 uint32_t throughable_mask = ~(reg->emu_mask | reg->ro_mask);
102
c25bbf15
JB		 103 if (!s->permissive) {
104 throughable_mask &= ~reg->res_mask;
105 }
106
0e7ef221
JB		 107 return throughable_mask & valid_mask;
108}
93d7ae8e
AK		 109
110/****************
111 * general register functions
112 */
113
114/* register initialization function */
115
116static int xen_pt_common_reg_init(XenPCIPassthroughState *s,
117 XenPTRegInfo *reg, uint32_t real_offset,
118 uint32_t *data)
119{
120 *data = reg->init_val;
121 return 0;
122}
123
124/* Read register functions */
125
126static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
127 uint8_t *value, uint8_t valid_mask)
128{
129 XenPTRegInfo *reg = cfg_entry->reg;
130 uint8_t valid_emu_mask = 0;
131
132 /* emulate byte register */
133 valid_emu_mask = reg->emu_mask & valid_mask;
134 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
135
136 return 0;
137}
138static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
139 uint16_t *value, uint16_t valid_mask)
140{
141 XenPTRegInfo *reg = cfg_entry->reg;
142 uint16_t valid_emu_mask = 0;
143
144 /* emulate word register */
145 valid_emu_mask = reg->emu_mask & valid_mask;
146 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
147
148 return 0;
149}
150static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
151 uint32_t *value, uint32_t valid_mask)
152{
153 XenPTRegInfo *reg = cfg_entry->reg;
154 uint32_t valid_emu_mask = 0;
155
156 /* emulate long register */
157 valid_emu_mask = reg->emu_mask & valid_mask;
158 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
159
160 return 0;
161}
162
163/* Write register functions */
164
165static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
166 uint8_t *val, uint8_t dev_value,
167 uint8_t valid_mask)
168{
169 XenPTRegInfo *reg = cfg_entry->reg;
170 uint8_t writable_mask = 0;
0e7ef221 171 uint8_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 172
173 /* modify emulate register */
174 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
175 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
176
177 /* create value for writing to I/O device register */
93d7ae8e
AK		 178 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
179
180 return 0;
181}
182static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
183 uint16_t *val, uint16_t dev_value,
184 uint16_t valid_mask)
185{
186 XenPTRegInfo *reg = cfg_entry->reg;
187 uint16_t writable_mask = 0;
0e7ef221 188 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 189
190 /* modify emulate register */
191 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
192 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
193
194 /* create value for writing to I/O device register */
93d7ae8e
AK		 195 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
196
197 return 0;
198}
199static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
200 uint32_t *val, uint32_t dev_value,
201 uint32_t valid_mask)
202{
203 XenPTRegInfo *reg = cfg_entry->reg;
204 uint32_t writable_mask = 0;
0e7ef221 205 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 206
207 /* modify emulate register */
208 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
209 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
210
211 /* create value for writing to I/O device register */
93d7ae8e
AK		 212 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
213
214 return 0;
215}
216
217
218/* XenPTRegInfo declaration
219 * - only for emulated register (either a part or whole bit).
220 * - for passthrough register that need special behavior (like interacting with
221 * other component), set emu_mask to all 0 and specify r/w func properly.
222 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
223 */
224
225/********************
226 * Header Type0
227 */
228
229static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s,
230 XenPTRegInfo *reg, uint32_t real_offset,
231 uint32_t *data)
232{
233 *data = s->real_device.vendor_id;
234 return 0;
235}
236static int xen_pt_device_reg_init(XenPCIPassthroughState *s,
237 XenPTRegInfo *reg, uint32_t real_offset,
238 uint32_t *data)
239{
240 *data = s->real_device.device_id;
241 return 0;
242}
243static int xen_pt_status_reg_init(XenPCIPassthroughState *s,
244 XenPTRegInfo *reg, uint32_t real_offset,
245 uint32_t *data)
246{
247 XenPTRegGroup *reg_grp_entry = NULL;
248 XenPTReg *reg_entry = NULL;
249 uint32_t reg_field = 0;
250
251 /* find Header register group */
252 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST);
253 if (reg_grp_entry) {
254 /* find Capabilities Pointer register */
255 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
256 if (reg_entry) {
257 /* check Capabilities Pointer register */
258 if (reg_entry->data) {
259 reg_field |= PCI_STATUS_CAP_LIST;
260 } else {
261 reg_field &= ~PCI_STATUS_CAP_LIST;
262 }
263 } else {
264 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
265 " for Capabilities Pointer register."
266 " (%s)\n", __func__);
267 return -1;
268 }
269 } else {
270 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
271 " for Header. (%s)\n", __func__);
272 return -1;
273 }
274
275 *data = reg_field;
276 return 0;
277}
278static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s,
279 XenPTRegInfo *reg, uint32_t real_offset,
280 uint32_t *data)
281{
282 /* read PCI_HEADER_TYPE */
283 *data = reg->init_val | 0x80;
284 return 0;
285}
286
287/* initialize Interrupt Pin register */
288static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s,
289 XenPTRegInfo *reg, uint32_t real_offset,
290 uint32_t *data)
291{
292 *data = xen_pt_pci_read_intx(s);
293 return 0;
294}
295
296/* Command register */
93d7ae8e
AK		 297static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
298 uint16_t *val, uint16_t dev_value,
299 uint16_t valid_mask)
300{
301 XenPTRegInfo *reg = cfg_entry->reg;
302 uint16_t writable_mask = 0;
0e7ef221 303 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 304
305 /* modify emulate register */
306 writable_mask = ~reg->ro_mask & valid_mask;
307 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
308
309 /* create value for writing to I/O device register */
93d7ae8e
AK		 310 if (*val & PCI_COMMAND_INTX_DISABLE) {
311 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
312 } else {
313 if (s->machine_irq) {
314 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
315 }
316 }
317
318 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
319
320 return 0;
321}
322
323/* BAR */
324#define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
325#define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
326#define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
327#define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
328
aabc8530
XH		 329static bool is_64bit_bar(PCIIORegion *r)
330{
331 return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
332}
333
334static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
335{
336 if (is_64bit_bar(r)) {
337 uint64_t size64;
338 size64 = (r + 1)->size;
339 size64 <<= 32;
340 size64 += r->size;
341 return size64;
342 }
343 return r->size;
344}
345
93d7ae8e 346static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
d4cd4502 347 int index)
93d7ae8e
AK		 348{
349 PCIDevice *d = &s->dev;
350 XenPTRegion *region = NULL;
351 PCIIORegion *r;
93d7ae8e
AK		 352
353 /* check 64bit BAR */
93d7ae8e
AK		 354 if ((0 < index) && (index < PCI_ROM_SLOT)) {
355 int type = s->real_device.io_regions[index - 1].type;
356
357 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM)
358 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) {
359 region = &s->bases[index - 1];
360 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) {
361 return XEN_PT_BAR_FLAG_UPPER;
362 }
363 }
364 }
365
366 /* check unused BAR */
367 r = &d->io_regions[index];
aabc8530 368 if (!xen_pt_get_bar_size(r)) {
93d7ae8e
AK		 369 return XEN_PT_BAR_FLAG_UNUSED;
370 }
371
372 /* for ExpROM BAR */
373 if (index == PCI_ROM_SLOT) {
374 return XEN_PT_BAR_FLAG_MEM;
375 }
376
377 /* check BAR I/O indicator */
378 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) {
379 return XEN_PT_BAR_FLAG_IO;
380 } else {
381 return XEN_PT_BAR_FLAG_MEM;
382 }
383}
384
385static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr)
386{
387 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) {
388 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK);
389 } else {
390 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK);
391 }
392}
393
394static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
395 uint32_t real_offset, uint32_t *data)
396{
397 uint32_t reg_field = 0;
398 int index;
399
400 index = xen_pt_bar_offset_to_index(reg->offset);
401 if (index < 0 || index >= PCI_NUM_REGIONS) {
402 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
403 return -1;
404 }
405
406 /* set BAR flag */
d4cd4502 407 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, index);
93d7ae8e
AK		 408 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) {
409 reg_field = XEN_PT_INVALID_REG;
410 }
411
412 *data = reg_field;
413 return 0;
414}
415static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
416 uint32_t *value, uint32_t valid_mask)
417{
418 XenPTRegInfo *reg = cfg_entry->reg;
419 uint32_t valid_emu_mask = 0;
420 uint32_t bar_emu_mask = 0;
421 int index;
422
423 /* get BAR index */
424 index = xen_pt_bar_offset_to_index(reg->offset);
14cec170 425 if (index < 0 || index >= PCI_NUM_REGIONS - 1) {
93d7ae8e
AK		 426 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
427 return -1;
428 }
429
430 /* use fixed-up value from kernel sysfs */
431 *value = base_address_with_flags(&s->real_device.io_regions[index]);
432
433 /* set emulate mask depend on BAR flag */
434 switch (s->bases[index].bar_flag) {
435 case XEN_PT_BAR_FLAG_MEM:
436 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
437 break;
438 case XEN_PT_BAR_FLAG_IO:
439 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
440 break;
441 case XEN_PT_BAR_FLAG_UPPER:
442 bar_emu_mask = XEN_PT_BAR_ALLF;
443 break;
444 default:
445 break;
446 }
447
448 /* emulate BAR */
449 valid_emu_mask = bar_emu_mask & valid_mask;
450 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
451
452 return 0;
453}
454static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
455 uint32_t *val, uint32_t dev_value,
456 uint32_t valid_mask)
457{
458 XenPTRegInfo *reg = cfg_entry->reg;
459 XenPTRegion *base = NULL;
460 PCIDevice *d = &s->dev;
461 const PCIIORegion *r;
462 uint32_t writable_mask = 0;
93d7ae8e
AK		 463 uint32_t bar_emu_mask = 0;
464 uint32_t bar_ro_mask = 0;
465 uint32_t r_size = 0;
466 int index = 0;
467
468 index = xen_pt_bar_offset_to_index(reg->offset);
469 if (index < 0 || index >= PCI_NUM_REGIONS) {
470 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index);
471 return -1;
472 }
473
474 r = &d->io_regions[index];
475 base = &s->bases[index];
476 r_size = xen_pt_get_emul_size(base->bar_flag, r->size);
477
478 /* set emulate mask and read-only mask values depend on the BAR flag */
479 switch (s->bases[index].bar_flag) {
480 case XEN_PT_BAR_FLAG_MEM:
481 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
aabc8530
XH		 482 if (!r_size) {
483 /* low 32 bits mask for 64 bit bars */
484 bar_ro_mask = XEN_PT_BAR_ALLF;
485 } else {
486 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
487 }
93d7ae8e
AK		 488 break;
489 case XEN_PT_BAR_FLAG_IO:
490 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
491 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1);
492 break;
493 case XEN_PT_BAR_FLAG_UPPER:
494 bar_emu_mask = XEN_PT_BAR_ALLF;
aabc8530 495 bar_ro_mask = r_size ? r_size - 1 : 0;
93d7ae8e
AK		 496 break;
497 default:
498 break;
499 }
500
501 /* modify emulate register */
502 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
503 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
504
505 /* check whether we need to update the virtual region address or not */
506 switch (s->bases[index].bar_flag) {
aabc8530 507 case XEN_PT_BAR_FLAG_UPPER:
93d7ae8e
AK		 508 case XEN_PT_BAR_FLAG_MEM:
509 /* nothing to do */
510 break;
511 case XEN_PT_BAR_FLAG_IO:
512 /* nothing to do */
513 break;
93d7ae8e
AK		 514 default:
515 break;
516 }
517
518 /* create value for writing to I/O device register */
0e7ef221 519 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
93d7ae8e
AK		 520
521 return 0;
522}
523
524/* write Exp ROM BAR */
525static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
526 XenPTReg *cfg_entry, uint32_t *val,
527 uint32_t dev_value, uint32_t valid_mask)
528{
529 XenPTRegInfo *reg = cfg_entry->reg;
530 XenPTRegion *base = NULL;
531 PCIDevice *d = (PCIDevice *)&s->dev;
532 uint32_t writable_mask = 0;
0e7ef221 533 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e 534 pcibus_t r_size = 0;
93d7ae8e
AK		 535 uint32_t bar_ro_mask = 0;
536
537 r_size = d->io_regions[PCI_ROM_SLOT].size;
538 base = &s->bases[PCI_ROM_SLOT];
539 /* align memory type resource size */
540 r_size = xen_pt_get_emul_size(base->bar_flag, r_size);
541
542 /* set emulate mask and read-only mask */
93d7ae8e
AK		 543 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;
544
545 /* modify emulate register */
546 writable_mask = ~bar_ro_mask & valid_mask;
547 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
548
549 /* create value for writing to I/O device register */
93d7ae8e
AK		 550 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
551
552 return 0;
553}
554
5cec8aa3
TC		 555static int xen_pt_intel_opregion_read(XenPCIPassthroughState *s,
556 XenPTReg *cfg_entry,
557 uint32_t *value, uint32_t valid_mask)
558{
559 *value = igd_read_opregion(s);
560 return 0;
561}
562
563static int xen_pt_intel_opregion_write(XenPCIPassthroughState *s,
564 XenPTReg *cfg_entry, uint32_t *value,
565 uint32_t dev_value, uint32_t valid_mask)
566{
567 igd_write_opregion(s, *value);
568 return 0;
569}
570
0546b8c2 571/* Header Type0 reg static information table */
93d7ae8e
AK		 572static XenPTRegInfo xen_pt_emu_reg_header0[] = {
573 /* Vendor ID reg */
574 {
575 .offset = PCI_VENDOR_ID,
576 .size = 2,
577 .init_val = 0x0000,
578 .ro_mask = 0xFFFF,
579 .emu_mask = 0xFFFF,
580 .init = xen_pt_vendor_reg_init,
581 .u.w.read = xen_pt_word_reg_read,
582 .u.w.write = xen_pt_word_reg_write,
583 },
584 /* Device ID reg */
585 {
586 .offset = PCI_DEVICE_ID,
587 .size = 2,
588 .init_val = 0x0000,
589 .ro_mask = 0xFFFF,
590 .emu_mask = 0xFFFF,
591 .init = xen_pt_device_reg_init,
592 .u.w.read = xen_pt_word_reg_read,
593 .u.w.write = xen_pt_word_reg_write,
594 },
595 /* Command reg */
596 {
597 .offset = PCI_COMMAND,
598 .size = 2,
599 .init_val = 0x0000,
0ad3393a 600 .res_mask = 0xF880,
81b23ef8 601 .emu_mask = 0x0743,
93d7ae8e 602 .init = xen_pt_common_reg_init,
81b23ef8 603 .u.w.read = xen_pt_word_reg_read,
93d7ae8e
AK		 604 .u.w.write = xen_pt_cmd_reg_write,
605 },
606 /* Capabilities Pointer reg */
607 {
608 .offset = PCI_CAPABILITY_LIST,
609 .size = 1,
610 .init_val = 0x00,
611 .ro_mask = 0xFF,
612 .emu_mask = 0xFF,
613 .init = xen_pt_ptr_reg_init,
614 .u.b.read = xen_pt_byte_reg_read,
615 .u.b.write = xen_pt_byte_reg_write,
616 },
617 /* Status reg */
618 /* use emulated Cap Ptr value to initialize,
619 * so need to be declared after Cap Ptr reg
620 */
621 {
622 .offset = PCI_STATUS,
623 .size = 2,
624 .init_val = 0x0000,
0ad3393a
JB		 625 .res_mask = 0x0007,
626 .ro_mask = 0x06F8,
93d7ae8e
AK		 627 .emu_mask = 0x0010,
628 .init = xen_pt_status_reg_init,
629 .u.w.read = xen_pt_word_reg_read,
630 .u.w.write = xen_pt_word_reg_write,
631 },
632 /* Cache Line Size reg */
633 {
634 .offset = PCI_CACHE_LINE_SIZE,
635 .size = 1,
636 .init_val = 0x00,
637 .ro_mask = 0x00,
638 .emu_mask = 0xFF,
639 .init = xen_pt_common_reg_init,
640 .u.b.read = xen_pt_byte_reg_read,
641 .u.b.write = xen_pt_byte_reg_write,
642 },
643 /* Latency Timer reg */
644 {
645 .offset = PCI_LATENCY_TIMER,
646 .size = 1,
647 .init_val = 0x00,
648 .ro_mask = 0x00,
649 .emu_mask = 0xFF,
650 .init = xen_pt_common_reg_init,
651 .u.b.read = xen_pt_byte_reg_read,
652 .u.b.write = xen_pt_byte_reg_write,
653 },
654 /* Header Type reg */
655 {
656 .offset = PCI_HEADER_TYPE,
657 .size = 1,
658 .init_val = 0x00,
659 .ro_mask = 0xFF,
660 .emu_mask = 0x00,
661 .init = xen_pt_header_type_reg_init,
662 .u.b.read = xen_pt_byte_reg_read,
663 .u.b.write = xen_pt_byte_reg_write,
664 },
665 /* Interrupt Line reg */
666 {
667 .offset = PCI_INTERRUPT_LINE,
668 .size = 1,
669 .init_val = 0x00,
670 .ro_mask = 0x00,
671 .emu_mask = 0xFF,
672 .init = xen_pt_common_reg_init,
673 .u.b.read = xen_pt_byte_reg_read,
674 .u.b.write = xen_pt_byte_reg_write,
675 },
676 /* Interrupt Pin reg */
677 {
678 .offset = PCI_INTERRUPT_PIN,
679 .size = 1,
680 .init_val = 0x00,
681 .ro_mask = 0xFF,
682 .emu_mask = 0xFF,
683 .init = xen_pt_irqpin_reg_init,
684 .u.b.read = xen_pt_byte_reg_read,
685 .u.b.write = xen_pt_byte_reg_write,
686 },
687 /* BAR 0 reg */
688 /* mask of BAR need to be decided later, depends on IO/MEM type */
689 {
690 .offset = PCI_BASE_ADDRESS_0,
691 .size = 4,
692 .init_val = 0x00000000,
693 .init = xen_pt_bar_reg_init,
694 .u.dw.read = xen_pt_bar_reg_read,
695 .u.dw.write = xen_pt_bar_reg_write,
696 },
697 /* BAR 1 reg */
698 {
699 .offset = PCI_BASE_ADDRESS_1,
700 .size = 4,
701 .init_val = 0x00000000,
702 .init = xen_pt_bar_reg_init,
703 .u.dw.read = xen_pt_bar_reg_read,
704 .u.dw.write = xen_pt_bar_reg_write,
705 },
706 /* BAR 2 reg */
707 {
708 .offset = PCI_BASE_ADDRESS_2,
709 .size = 4,
710 .init_val = 0x00000000,
711 .init = xen_pt_bar_reg_init,
712 .u.dw.read = xen_pt_bar_reg_read,
713 .u.dw.write = xen_pt_bar_reg_write,
714 },
715 /* BAR 3 reg */
716 {
717 .offset = PCI_BASE_ADDRESS_3,
718 .size = 4,
719 .init_val = 0x00000000,
720 .init = xen_pt_bar_reg_init,
721 .u.dw.read = xen_pt_bar_reg_read,
722 .u.dw.write = xen_pt_bar_reg_write,
723 },
724 /* BAR 4 reg */
725 {
726 .offset = PCI_BASE_ADDRESS_4,
727 .size = 4,
728 .init_val = 0x00000000,
729 .init = xen_pt_bar_reg_init,
730 .u.dw.read = xen_pt_bar_reg_read,
731 .u.dw.write = xen_pt_bar_reg_write,
732 },
733 /* BAR 5 reg */
734 {
735 .offset = PCI_BASE_ADDRESS_5,
736 .size = 4,
737 .init_val = 0x00000000,
738 .init = xen_pt_bar_reg_init,
739 .u.dw.read = xen_pt_bar_reg_read,
740 .u.dw.write = xen_pt_bar_reg_write,
741 },
742 /* Expansion ROM BAR reg */
743 {
744 .offset = PCI_ROM_ADDRESS,
745 .size = 4,
746 .init_val = 0x00000000,
69976894
JB		 747 .ro_mask = ~PCI_ROM_ADDRESS_MASK & ~PCI_ROM_ADDRESS_ENABLE,
748 .emu_mask = (uint32_t)PCI_ROM_ADDRESS_MASK,
93d7ae8e
AK		 749 .init = xen_pt_bar_reg_init,
750 .u.dw.read = xen_pt_long_reg_read,
751 .u.dw.write = xen_pt_exp_rom_bar_reg_write,
752 },
753 {
754 .size = 0,
755 },
756};
757
758
759/*********************************
760 * Vital Product Data Capability
761 */
762
0546b8c2 763/* Vital Product Data Capability Structure reg static information table */
93d7ae8e
AK		 764static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
765 {
766 .offset = PCI_CAP_LIST_NEXT,
767 .size = 1,
768 .init_val = 0x00,
769 .ro_mask = 0xFF,
770 .emu_mask = 0xFF,
771 .init = xen_pt_ptr_reg_init,
772 .u.b.read = xen_pt_byte_reg_read,
773 .u.b.write = xen_pt_byte_reg_write,
774 },
a88a3f88
JB		 775 {
776 .offset = PCI_VPD_ADDR,
777 .size = 2,
778 .ro_mask = 0x0003,
779 .emu_mask = 0x0003,
780 .init = xen_pt_common_reg_init,
781 .u.w.read = xen_pt_word_reg_read,
782 .u.w.write = xen_pt_word_reg_write,
783 },
93d7ae8e
AK		 784 {
785 .size = 0,
786 },
787};
788
789
790/**************************************
791 * Vendor Specific Capability
792 */
793
0546b8c2 794/* Vendor Specific Capability Structure reg static information table */
93d7ae8e
AK		 795static XenPTRegInfo xen_pt_emu_reg_vendor[] = {
796 {
797 .offset = PCI_CAP_LIST_NEXT,
798 .size = 1,
799 .init_val = 0x00,
800 .ro_mask = 0xFF,
801 .emu_mask = 0xFF,
802 .init = xen_pt_ptr_reg_init,
803 .u.b.read = xen_pt_byte_reg_read,
804 .u.b.write = xen_pt_byte_reg_write,
805 },
806 {
807 .size = 0,
808 },
809};
810
811
812/*****************************
813 * PCI Express Capability
814 */
815
816static inline uint8_t get_capability_version(XenPCIPassthroughState *s,
817 uint32_t offset)
818{
6aa07b14
KRW		 819 uint8_t flag;
820 if (xen_host_pci_get_byte(&s->real_device, offset + PCI_EXP_FLAGS, &flag)) {
821 return 0;
822 }
823 return flag & PCI_EXP_FLAGS_VERS;
93d7ae8e
AK		 824}
825
826static inline uint8_t get_device_type(XenPCIPassthroughState *s,
827 uint32_t offset)
828{
6aa07b14
KRW		 829 uint8_t flag;
830 if (xen_host_pci_get_byte(&s->real_device, offset + PCI_EXP_FLAGS, &flag)) {
831 return 0;
832 }
833 return (flag & PCI_EXP_FLAGS_TYPE) >> 4;
93d7ae8e
AK		 834}
835
836/* initialize Link Control register */
837static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s,
838 XenPTRegInfo *reg, uint32_t real_offset,
839 uint32_t *data)
840{
841 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
842 uint8_t dev_type = get_device_type(s, real_offset - reg->offset);
843
844 /* no need to initialize in case of Root Complex Integrated Endpoint
845 * with cap_ver 1.x
846 */
847 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) {
848 *data = XEN_PT_INVALID_REG;
849 }
850
851 *data = reg->init_val;
852 return 0;
853}
854/* initialize Device Control 2 register */
855static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s,
856 XenPTRegInfo *reg, uint32_t real_offset,
857 uint32_t *data)
858{
859 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
860
861 /* no need to initialize in case of cap_ver 1.x */
862 if (cap_ver == 1) {
863 *data = XEN_PT_INVALID_REG;
864 }
865
866 *data = reg->init_val;
867 return 0;
868}
869/* initialize Link Control 2 register */
870static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s,
871 XenPTRegInfo *reg, uint32_t real_offset,
872 uint32_t *data)
873{
874 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
875 uint32_t reg_field = 0;
876
877 /* no need to initialize in case of cap_ver 1.x */
878 if (cap_ver == 1) {
879 reg_field = XEN_PT_INVALID_REG;
880 } else {
881 /* set Supported Link Speed */
6aa07b14
KRW		 882 uint8_t lnkcap;
883 int rc;
884 rc = xen_host_pci_get_byte(&s->real_device,
885 real_offset - reg->offset + PCI_EXP_LNKCAP,
886 &lnkcap);
887 if (rc) {
888 return rc;
889 }
93d7ae8e
AK		 890 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap;
891 }
892
893 *data = reg_field;
894 return 0;
895}
896
0546b8c2 897/* PCI Express Capability Structure reg static information table */
93d7ae8e
AK		 898static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
899 /* Next Pointer reg */
900 {
901 .offset = PCI_CAP_LIST_NEXT,
902 .size = 1,
903 .init_val = 0x00,
904 .ro_mask = 0xFF,
905 .emu_mask = 0xFF,
906 .init = xen_pt_ptr_reg_init,
907 .u.b.read = xen_pt_byte_reg_read,
908 .u.b.write = xen_pt_byte_reg_write,
909 },
910 /* Device Capabilities reg */
911 {
912 .offset = PCI_EXP_DEVCAP,
913 .size = 4,
914 .init_val = 0x00000000,
45ebe391 915 .ro_mask = 0xFFFFFFFF,
93d7ae8e
AK		 916 .emu_mask = 0x10000000,
917 .init = xen_pt_common_reg_init,
918 .u.dw.read = xen_pt_long_reg_read,
919 .u.dw.write = xen_pt_long_reg_write,
920 },
921 /* Device Control reg */
922 {
923 .offset = PCI_EXP_DEVCTL,
924 .size = 2,
925 .init_val = 0x2810,
926 .ro_mask = 0x8400,
927 .emu_mask = 0xFFFF,
928 .init = xen_pt_common_reg_init,
929 .u.w.read = xen_pt_word_reg_read,
930 .u.w.write = xen_pt_word_reg_write,
931 },
a88a3f88
JB		 932 /* Device Status reg */
933 {
934 .offset = PCI_EXP_DEVSTA,
935 .size = 2,
936 .res_mask = 0xFFC0,
937 .ro_mask = 0x0030,
938 .init = xen_pt_common_reg_init,
939 .u.w.read = xen_pt_word_reg_read,
940 .u.w.write = xen_pt_word_reg_write,
941 },
93d7ae8e
AK		 942 /* Link Control reg */
943 {
944 .offset = PCI_EXP_LNKCTL,
945 .size = 2,
946 .init_val = 0x0000,
947 .ro_mask = 0xFC34,
948 .emu_mask = 0xFFFF,
949 .init = xen_pt_linkctrl_reg_init,
950 .u.w.read = xen_pt_word_reg_read,
a88a3f88
JB		 951 .u.w.write = xen_pt_word_reg_write,
952 },
953 /* Link Status reg */
954 {
955 .offset = PCI_EXP_LNKSTA,
956 .size = 2,
957 .ro_mask = 0x3FFF,
958 .init = xen_pt_common_reg_init,
959 .u.w.read = xen_pt_word_reg_read,
93d7ae8e
AK		 960 .u.w.write = xen_pt_word_reg_write,
961 },
962 /* Device Control 2 reg */
963 {
964 .offset = 0x28,
965 .size = 2,
966 .init_val = 0x0000,
967 .ro_mask = 0xFFE0,
968 .emu_mask = 0xFFFF,
969 .init = xen_pt_devctrl2_reg_init,
970 .u.w.read = xen_pt_word_reg_read,
971 .u.w.write = xen_pt_word_reg_write,
972 },
973 /* Link Control 2 reg */
974 {
975 .offset = 0x30,
976 .size = 2,
977 .init_val = 0x0000,
978 .ro_mask = 0xE040,
979 .emu_mask = 0xFFFF,
980 .init = xen_pt_linkctrl2_reg_init,
981 .u.w.read = xen_pt_word_reg_read,
982 .u.w.write = xen_pt_word_reg_write,
983 },
984 {
985 .size = 0,
986 },
987};
988
989
990/*********************************
991 * Power Management Capability
992 */
993
93d7ae8e
AK		 994/* write Power Management Control/Status register */
995static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
996 XenPTReg *cfg_entry, uint16_t *val,
997 uint16_t dev_value, uint16_t valid_mask)
998{
999 XenPTRegInfo *reg = cfg_entry->reg;
93d7ae8e 1000 uint16_t writable_mask = 0;
0e7ef221 1001 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e 1002
93d7ae8e 1003 /* modify emulate register */
d61bb248 1004 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
93d7ae8e
AK		 1005 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1006
1007 /* create value for writing to I/O device register */
c4ff1e68
JB		 1008 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS,
1009 throughable_mask);
93d7ae8e
AK		 1010
1011 return 0;
1012}
1013
0546b8c2 1014/* Power Management Capability reg static information table */
93d7ae8e
AK		 1015static XenPTRegInfo xen_pt_emu_reg_pm[] = {
1016 /* Next Pointer reg */
1017 {
1018 .offset = PCI_CAP_LIST_NEXT,
1019 .size = 1,
1020 .init_val = 0x00,
1021 .ro_mask = 0xFF,
1022 .emu_mask = 0xFF,
1023 .init = xen_pt_ptr_reg_init,
1024 .u.b.read = xen_pt_byte_reg_read,
1025 .u.b.write = xen_pt_byte_reg_write,
1026 },
1027 /* Power Management Capabilities reg */
1028 {
1029 .offset = PCI_CAP_FLAGS,
1030 .size = 2,
1031 .init_val = 0x0000,
1032 .ro_mask = 0xFFFF,
1033 .emu_mask = 0xF9C8,
1034 .init = xen_pt_common_reg_init,
1035 .u.w.read = xen_pt_word_reg_read,
1036 .u.w.write = xen_pt_word_reg_write,
1037 },
1038 /* PCI Power Management Control/Status reg */
1039 {
1040 .offset = PCI_PM_CTRL,
1041 .size = 2,
1042 .init_val = 0x0008,
0ad3393a
JB		 1043 .res_mask = 0x00F0,
1044 .ro_mask = 0xE10C,
d61bb248 1045 .emu_mask = 0x810B,
93d7ae8e 1046 .init = xen_pt_common_reg_init,
d61bb248 1047 .u.w.read = xen_pt_word_reg_read,
93d7ae8e
AK		 1048 .u.w.write = xen_pt_pmcsr_reg_write,
1049 },
1050 {
1051 .size = 0,
1052 },
1053};
1054
1055
3854ca57
JY		 1056/********************************
1057 * MSI Capability
1058 */
1059
1060/* Helper */
7611dae8
JB		 1061#define xen_pt_msi_check_type(offset, flags, what) \
1062 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1063 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
3854ca57
JY		 1064
1065/* Message Control register */
1066static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
1067 XenPTRegInfo *reg, uint32_t real_offset,
1068 uint32_t *data)
1069{
3854ca57 1070 XenPTMSI *msi = s->msi;
6aa07b14
KRW		 1071 uint16_t reg_field;
1072 int rc;
3854ca57
JY		 1073
1074 /* use I/O device register's value as initial value */
6aa07b14
KRW		 1075 rc = xen_host_pci_get_word(&s->real_device, real_offset, &reg_field);
1076 if (rc) {
1077 return rc;
1078 }
3854ca57
JY		 1079 if (reg_field & PCI_MSI_FLAGS_ENABLE) {
1080 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n");
1081 xen_host_pci_set_word(&s->real_device, real_offset,
1082 reg_field & ~PCI_MSI_FLAGS_ENABLE);
1083 }
1084 msi->flags |= reg_field;
1085 msi->ctrl_offset = real_offset;
1086 msi->initialized = false;
1087 msi->mapped = false;
1088
1089 *data = reg->init_val;
1090 return 0;
1091}
1092static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
1093 XenPTReg *cfg_entry, uint16_t *val,
1094 uint16_t dev_value, uint16_t valid_mask)
1095{
1096 XenPTRegInfo *reg = cfg_entry->reg;
1097 XenPTMSI *msi = s->msi;
1098 uint16_t writable_mask = 0;
0e7ef221 1099 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
3854ca57
JY		 1100
1101 /* Currently no support for multi-vector */
1102 if (*val & PCI_MSI_FLAGS_QSIZE) {
1103 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val);
1104 }
1105
1106 /* modify emulate register */
1107 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1108 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1109 msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE;
1110
1111 /* create value for writing to I/O device register */
3854ca57
JY		 1112 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1113
1114 /* update MSI */
d1d35cf4 1115 if (*val & PCI_MSI_FLAGS_ENABLE) {
3854ca57
JY		 1116 /* setup MSI pirq for the first time */
1117 if (!msi->initialized) {
1118 /* Init physical one */
faf5f56b 1119 XEN_PT_LOG(&s->dev, "setup MSI (register: %x).\n", *val);
3854ca57
JY		 1120 if (xen_pt_msi_setup(s)) {
1121 /* We do not broadcast the error to the framework code, so
1122 * that MSI errors are contained in MSI emulation code and
1123 * QEMU can go on running.
1124 * Guest MSI would be actually not working.
1125 */
1126 *val &= ~PCI_MSI_FLAGS_ENABLE;
faf5f56b 1127 XEN_PT_WARN(&s->dev, "Can not map MSI (register: %x)!\n", *val);
3854ca57
JY		 1128 return 0;
1129 }
1130 if (xen_pt_msi_update(s)) {
1131 *val &= ~PCI_MSI_FLAGS_ENABLE;
faf5f56b 1132 XEN_PT_WARN(&s->dev, "Can not bind MSI (register: %x)!\n", *val);
3854ca57
JY		 1133 return 0;
1134 }
1135 msi->initialized = true;
1136 msi->mapped = true;
1137 }
1138 msi->flags |= PCI_MSI_FLAGS_ENABLE;
c976437c
ZD		 1139 } else if (msi->mapped) {
1140 xen_pt_msi_disable(s);
3854ca57
JY		 1141 }
1142
3854ca57
JY		 1143 return 0;
1144}
1145
1146/* initialize Message Upper Address register */
1147static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s,
1148 XenPTRegInfo *reg, uint32_t real_offset,
1149 uint32_t *data)
1150{
1151 /* no need to initialize in case of 32 bit type */
1152 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1153 *data = XEN_PT_INVALID_REG;
1154 } else {
1155 *data = reg->init_val;
1156 }
1157
1158 return 0;
1159}
1160/* this function will be called twice (for 32 bit and 64 bit type) */
1161/* initialize Message Data register */
1162static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
1163 XenPTRegInfo *reg, uint32_t real_offset,
1164 uint32_t *data)
1165{
1166 uint32_t flags = s->msi->flags;
1167 uint32_t offset = reg->offset;
1168
1169 /* check the offset whether matches the type or not */
7611dae8
JB		 1170 if (xen_pt_msi_check_type(offset, flags, DATA)) {
1171 *data = reg->init_val;
1172 } else {
1173 *data = XEN_PT_INVALID_REG;
1174 }
1175 return 0;
1176}
1177
1178/* this function will be called twice (for 32 bit and 64 bit type) */
1179/* initialize Mask register */
1180static int xen_pt_mask_reg_init(XenPCIPassthroughState *s,
1181 XenPTRegInfo *reg, uint32_t real_offset,
1182 uint32_t *data)
1183{
1184 uint32_t flags = s->msi->flags;
1185
1186 /* check the offset whether matches the type or not */
1187 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1188 *data = XEN_PT_INVALID_REG;
1189 } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) {
1190 *data = reg->init_val;
1191 } else {
1192 *data = XEN_PT_INVALID_REG;
1193 }
1194 return 0;
1195}
1196
1197/* this function will be called twice (for 32 bit and 64 bit type) */
1198/* initialize Pending register */
1199static int xen_pt_pending_reg_init(XenPCIPassthroughState *s,
1200 XenPTRegInfo *reg, uint32_t real_offset,
1201 uint32_t *data)
1202{
1203 uint32_t flags = s->msi->flags;
1204
1205 /* check the offset whether matches the type or not */
1206 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1207 *data = XEN_PT_INVALID_REG;
1208 } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) {
3854ca57
JY		 1209 *data = reg->init_val;
1210 } else {
1211 *data = XEN_PT_INVALID_REG;
1212 }
1213 return 0;
1214}
1215
1216/* write Message Address register */
1217static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s,
1218 XenPTReg *cfg_entry, uint32_t *val,
1219 uint32_t dev_value, uint32_t valid_mask)
1220{
1221 XenPTRegInfo *reg = cfg_entry->reg;
1222 uint32_t writable_mask = 0;
3854ca57
JY		 1223 uint32_t old_addr = cfg_entry->data;
1224
1225 /* modify emulate register */
1226 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1227 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1228 s->msi->addr_lo = cfg_entry->data;
1229
1230 /* create value for writing to I/O device register */
0e7ef221 1231 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
3854ca57
JY		 1232
1233 /* update MSI */
1234 if (cfg_entry->data != old_addr) {
1235 if (s->msi->mapped) {
1236 xen_pt_msi_update(s);
1237 }
1238 }
1239
1240 return 0;
1241}
1242/* write Message Upper Address register */
1243static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s,
1244 XenPTReg *cfg_entry, uint32_t *val,
1245 uint32_t dev_value, uint32_t valid_mask)
1246{
1247 XenPTRegInfo *reg = cfg_entry->reg;
1248 uint32_t writable_mask = 0;
3854ca57
JY		 1249 uint32_t old_addr = cfg_entry->data;
1250
1251 /* check whether the type is 64 bit or not */
1252 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1253 XEN_PT_ERR(&s->dev,
1254 "Can't write to the upper address without 64 bit support\n");
1255 return -1;
1256 }
1257
1258 /* modify emulate register */
1259 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1260 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1261 /* update the msi_info too */
1262 s->msi->addr_hi = cfg_entry->data;
1263
1264 /* create value for writing to I/O device register */
0e7ef221 1265 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
3854ca57
JY		 1266
1267 /* update MSI */
1268 if (cfg_entry->data != old_addr) {
1269 if (s->msi->mapped) {
1270 xen_pt_msi_update(s);
1271 }
1272 }
1273
1274 return 0;
1275}
1276
1277
1278/* this function will be called twice (for 32 bit and 64 bit type) */
1279/* write Message Data register */
1280static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
1281 XenPTReg *cfg_entry, uint16_t *val,
1282 uint16_t dev_value, uint16_t valid_mask)
1283{
1284 XenPTRegInfo *reg = cfg_entry->reg;
1285 XenPTMSI *msi = s->msi;
1286 uint16_t writable_mask = 0;
3854ca57
JY		 1287 uint16_t old_data = cfg_entry->data;
1288 uint32_t offset = reg->offset;
1289
1290 /* check the offset whether matches the type or not */
7611dae8 1291 if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) {
3854ca57
JY		 1292 /* exit I/O emulator */
1293 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
1294 return -1;
1295 }
1296
1297 /* modify emulate register */
1298 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1299 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1300 /* update the msi_info too */
1301 msi->data = cfg_entry->data;
1302
1303 /* create value for writing to I/O device register */
0e7ef221 1304 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
3854ca57
JY		 1305
1306 /* update MSI */
1307 if (cfg_entry->data != old_data) {
1308 if (msi->mapped) {
1309 xen_pt_msi_update(s);
1310 }
1311 }
1312
1313 return 0;
1314}
1315
0546b8c2 1316/* MSI Capability Structure reg static information table */
3854ca57
JY		 1317static XenPTRegInfo xen_pt_emu_reg_msi[] = {
1318 /* Next Pointer reg */
1319 {
1320 .offset = PCI_CAP_LIST_NEXT,
1321 .size = 1,
1322 .init_val = 0x00,
1323 .ro_mask = 0xFF,
1324 .emu_mask = 0xFF,
1325 .init = xen_pt_ptr_reg_init,
1326 .u.b.read = xen_pt_byte_reg_read,
1327 .u.b.write = xen_pt_byte_reg_write,
1328 },
1329 /* Message Control reg */
1330 {
1331 .offset = PCI_MSI_FLAGS,
1332 .size = 2,
1333 .init_val = 0x0000,
0ad3393a
JB		 1334 .res_mask = 0xFE00,
1335 .ro_mask = 0x018E,
d1d35cf4 1336 .emu_mask = 0x017E,
3854ca57
JY		 1337 .init = xen_pt_msgctrl_reg_init,
1338 .u.w.read = xen_pt_word_reg_read,
1339 .u.w.write = xen_pt_msgctrl_reg_write,
1340 },
1341 /* Message Address reg */
1342 {
1343 .offset = PCI_MSI_ADDRESS_LO,
1344 .size = 4,
1345 .init_val = 0x00000000,
1346 .ro_mask = 0x00000003,
1347 .emu_mask = 0xFFFFFFFF,
3854ca57
JY		 1348 .init = xen_pt_common_reg_init,
1349 .u.dw.read = xen_pt_long_reg_read,
1350 .u.dw.write = xen_pt_msgaddr32_reg_write,
1351 },
1352 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1353 {
1354 .offset = PCI_MSI_ADDRESS_HI,
1355 .size = 4,
1356 .init_val = 0x00000000,
1357 .ro_mask = 0x00000000,
1358 .emu_mask = 0xFFFFFFFF,
3854ca57
JY		 1359 .init = xen_pt_msgaddr64_reg_init,
1360 .u.dw.read = xen_pt_long_reg_read,
1361 .u.dw.write = xen_pt_msgaddr64_reg_write,
1362 },
1363 /* Message Data reg (16 bits of data for 32-bit devices) */
1364 {
1365 .offset = PCI_MSI_DATA_32,
1366 .size = 2,
1367 .init_val = 0x0000,
1368 .ro_mask = 0x0000,
1369 .emu_mask = 0xFFFF,
3854ca57
JY		 1370 .init = xen_pt_msgdata_reg_init,
1371 .u.w.read = xen_pt_word_reg_read,
1372 .u.w.write = xen_pt_msgdata_reg_write,
1373 },
1374 /* Message Data reg (16 bits of data for 64-bit devices) */
1375 {
1376 .offset = PCI_MSI_DATA_64,
1377 .size = 2,
1378 .init_val = 0x0000,
1379 .ro_mask = 0x0000,
1380 .emu_mask = 0xFFFF,
3854ca57
JY		 1381 .init = xen_pt_msgdata_reg_init,
1382 .u.w.read = xen_pt_word_reg_read,
1383 .u.w.write = xen_pt_msgdata_reg_write,
1384 },
7611dae8
JB		 1385 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1386 {
1387 .offset = PCI_MSI_MASK_32,
1388 .size = 4,
1389 .init_val = 0x00000000,
1390 .ro_mask = 0xFFFFFFFF,
1391 .emu_mask = 0xFFFFFFFF,
1392 .init = xen_pt_mask_reg_init,
1393 .u.dw.read = xen_pt_long_reg_read,
1394 .u.dw.write = xen_pt_long_reg_write,
1395 },
1396 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1397 {
1398 .offset = PCI_MSI_MASK_64,
1399 .size = 4,
1400 .init_val = 0x00000000,
1401 .ro_mask = 0xFFFFFFFF,
1402 .emu_mask = 0xFFFFFFFF,
1403 .init = xen_pt_mask_reg_init,
1404 .u.dw.read = xen_pt_long_reg_read,
1405 .u.dw.write = xen_pt_long_reg_write,
1406 },
1407 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1408 {
1409 .offset = PCI_MSI_MASK_32 + 4,
1410 .size = 4,
1411 .init_val = 0x00000000,
1412 .ro_mask = 0xFFFFFFFF,
1413 .emu_mask = 0x00000000,
1414 .init = xen_pt_pending_reg_init,
1415 .u.dw.read = xen_pt_long_reg_read,
1416 .u.dw.write = xen_pt_long_reg_write,
1417 },
1418 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1419 {
1420 .offset = PCI_MSI_MASK_64 + 4,
1421 .size = 4,
1422 .init_val = 0x00000000,
1423 .ro_mask = 0xFFFFFFFF,
1424 .emu_mask = 0x00000000,
1425 .init = xen_pt_pending_reg_init,
1426 .u.dw.read = xen_pt_long_reg_read,
1427 .u.dw.write = xen_pt_long_reg_write,
1428 },
3854ca57
JY		 1429 {
1430 .size = 0,
1431 },
1432};
1433
1434
1435/**************************************
1436 * MSI-X Capability
1437 */
1438
1439/* Message Control register for MSI-X */
1440static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
1441 XenPTRegInfo *reg, uint32_t real_offset,
1442 uint32_t *data)
1443{
6aa07b14
KRW		 1444 uint16_t reg_field;
1445 int rc;
3854ca57
JY		 1446
1447 /* use I/O device register's value as initial value */
6aa07b14
KRW		 1448 rc = xen_host_pci_get_word(&s->real_device, real_offset, &reg_field);
1449 if (rc) {
1450 return rc;
1451 }
3854ca57 1452 if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
54fd0813 1453 XEN_PT_LOG(&s->dev, "MSIX already enabled, disabling it first\n");
3854ca57
JY		 1454 xen_host_pci_set_word(&s->real_device, real_offset,
1455 reg_field & ~PCI_MSIX_FLAGS_ENABLE);
1456 }
1457
1458 s->msix->ctrl_offset = real_offset;
1459
1460 *data = reg->init_val;
1461 return 0;
1462}
1463static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
1464 XenPTReg *cfg_entry, uint16_t *val,
1465 uint16_t dev_value, uint16_t valid_mask)
1466{
1467 XenPTRegInfo *reg = cfg_entry->reg;
1468 uint16_t writable_mask = 0;
0e7ef221 1469 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
3854ca57
JY		 1470 int debug_msix_enabled_old;
1471
1472 /* modify emulate register */
1473 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1474 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1475
1476 /* create value for writing to I/O device register */
3854ca57
JY		 1477 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1478
1479 /* update MSI-X */
1480 if ((*val & PCI_MSIX_FLAGS_ENABLE)
1481 && !(*val & PCI_MSIX_FLAGS_MASKALL)) {
1482 xen_pt_msix_update(s);
c976437c
ZD		 1483 } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {
1484 xen_pt_msix_disable(s);
3854ca57
JY		 1485 }
1486
1487 debug_msix_enabled_old = s->msix->enabled;
1488 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
1489 if (s->msix->enabled != debug_msix_enabled_old) {
1490 XEN_PT_LOG(&s->dev, "%s MSI-X\n",
1491 s->msix->enabled ? "enable" : "disable");
1492 }
1493
1494 return 0;
1495}
1496
0546b8c2 1497/* MSI-X Capability Structure reg static information table */
3854ca57
JY		 1498static XenPTRegInfo xen_pt_emu_reg_msix[] = {
1499 /* Next Pointer reg */
1500 {
1501 .offset = PCI_CAP_LIST_NEXT,
1502 .size = 1,
1503 .init_val = 0x00,
1504 .ro_mask = 0xFF,
1505 .emu_mask = 0xFF,
1506 .init = xen_pt_ptr_reg_init,
1507 .u.b.read = xen_pt_byte_reg_read,
1508 .u.b.write = xen_pt_byte_reg_write,
1509 },
1510 /* Message Control reg */
1511 {
1512 .offset = PCI_MSI_FLAGS,
1513 .size = 2,
1514 .init_val = 0x0000,
0ad3393a
JB		 1515 .res_mask = 0x3800,
1516 .ro_mask = 0x07FF,
3854ca57
JY		 1517 .emu_mask = 0x0000,
1518 .init = xen_pt_msixctrl_reg_init,
1519 .u.w.read = xen_pt_word_reg_read,
1520 .u.w.write = xen_pt_msixctrl_reg_write,
1521 },
1522 {
1523 .size = 0,
1524 },
1525};
1526
5cec8aa3
TC		 1527static XenPTRegInfo xen_pt_emu_reg_igd_opregion[] = {
1528 /* Intel IGFX OpRegion reg */
1529 {
1530 .offset = 0x0,
1531 .size = 4,
1532 .init_val = 0,
1533 .u.dw.read = xen_pt_intel_opregion_read,
1534 .u.dw.write = xen_pt_intel_opregion_write,
1535 },
1536 {
1537 .size = 0,
1538 },
1539};
3854ca57 1540
93d7ae8e
AK		 1541/****************************
1542 * Capabilities
1543 */
1544
1545/* capability structure register group size functions */
1546
1547static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s,
1548 const XenPTRegGroupInfo *grp_reg,
1549 uint32_t base_offset, uint8_t *size)
1550{
1551 *size = grp_reg->grp_size;
1552 return 0;
1553}
1554/* get Vendor Specific Capability Structure register group size */
1555static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
1556 const XenPTRegGroupInfo *grp_reg,
1557 uint32_t base_offset, uint8_t *size)
1558{
6aa07b14 1559 return xen_host_pci_get_byte(&s->real_device, base_offset + 0x02, size);
93d7ae8e
AK		 1560}
1561/* get PCI Express Capability Structure register group size */
1562static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
1563 const XenPTRegGroupInfo *grp_reg,
1564 uint32_t base_offset, uint8_t *size)
1565{
1566 PCIDevice *d = &s->dev;
1567 uint8_t version = get_capability_version(s, base_offset);
1568 uint8_t type = get_device_type(s, base_offset);
1569 uint8_t pcie_size = 0;
1570
1571
1572 /* calculate size depend on capability version and device/port type */
1573 /* in case of PCI Express Base Specification Rev 1.x */
1574 if (version == 1) {
1575 /* The PCI Express Capabilities, Device Capabilities, and Device
1576 * Status/Control registers are required for all PCI Express devices.
1577 * The Link Capabilities and Link Status/Control are required for all
1578 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1579 * are not required to implement registers other than those listed
1580 * above and terminate the capability structure.
1581 */
1582 switch (type) {
1583 case PCI_EXP_TYPE_ENDPOINT:
1584 case PCI_EXP_TYPE_LEG_END:
1585 pcie_size = 0x14;
1586 break;
1587 case PCI_EXP_TYPE_RC_END:
1588 /* has no link */
1589 pcie_size = 0x0C;
1590 break;
1591 /* only EndPoint passthrough is supported */
1592 case PCI_EXP_TYPE_ROOT_PORT:
1593 case PCI_EXP_TYPE_UPSTREAM:
1594 case PCI_EXP_TYPE_DOWNSTREAM:
1595 case PCI_EXP_TYPE_PCI_BRIDGE:
1596 case PCI_EXP_TYPE_PCIE_BRIDGE:
1597 case PCI_EXP_TYPE_RC_EC:
1598 default:
1599 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1600 return -1;
1601 }
1602 }
1603 /* in case of PCI Express Base Specification Rev 2.0 */
1604 else if (version == 2) {
1605 switch (type) {
1606 case PCI_EXP_TYPE_ENDPOINT:
1607 case PCI_EXP_TYPE_LEG_END:
1608 case PCI_EXP_TYPE_RC_END:
1609 /* For Functions that do not implement the registers,
1610 * these spaces must be hardwired to 0b.
1611 */
1612 pcie_size = 0x3C;
1613 break;
1614 /* only EndPoint passthrough is supported */
1615 case PCI_EXP_TYPE_ROOT_PORT:
1616 case PCI_EXP_TYPE_UPSTREAM:
1617 case PCI_EXP_TYPE_DOWNSTREAM:
1618 case PCI_EXP_TYPE_PCI_BRIDGE:
1619 case PCI_EXP_TYPE_PCIE_BRIDGE:
1620 case PCI_EXP_TYPE_RC_EC:
1621 default:
1622 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1623 return -1;
1624 }
1625 } else {
1626 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version);
1627 return -1;
1628 }
1629
1630 *size = pcie_size;
1631 return 0;
1632}
3854ca57
JY		 1633/* get MSI Capability Structure register group size */
1634static int xen_pt_msi_size_init(XenPCIPassthroughState *s,
1635 const XenPTRegGroupInfo *grp_reg,
1636 uint32_t base_offset, uint8_t *size)
1637{
3854ca57
JY		 1638 uint16_t msg_ctrl = 0;
1639 uint8_t msi_size = 0xa;
6aa07b14 1640 int rc;
3854ca57 1641
6aa07b14
KRW		 1642 rc = xen_host_pci_get_word(&s->real_device, base_offset + PCI_MSI_FLAGS,
1643 &msg_ctrl);
1644 if (rc) {
1645 return rc;
1646 }
3854ca57
JY		 1647 /* check if 64-bit address is capable of per-vector masking */
1648 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) {
1649 msi_size += 4;
1650 }
1651 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) {
1652 msi_size += 10;
1653 }
1654
1655 s->msi = g_new0(XenPTMSI, 1);
1656 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
1657
1658 *size = msi_size;
1659 return 0;
1660}
1661/* get MSI-X Capability Structure register group size */
1662static int xen_pt_msix_size_init(XenPCIPassthroughState *s,
1663 const XenPTRegGroupInfo *grp_reg,
1664 uint32_t base_offset, uint8_t *size)
1665{
1666 int rc = 0;
1667
1668 rc = xen_pt_msix_init(s, base_offset);
1669
1670 if (rc < 0) {
1671 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n");
1672 return rc;
1673 }
1674
1675 *size = grp_reg->grp_size;
1676 return 0;
1677}
1678
93d7ae8e
AK		 1679
1680static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
1681 /* Header Type0 reg group */
1682 {
1683 .grp_id = 0xFF,
1684 .grp_type = XEN_PT_GRP_TYPE_EMU,
1685 .grp_size = 0x40,
1686 .size_init = xen_pt_reg_grp_size_init,
1687 .emu_regs = xen_pt_emu_reg_header0,
1688 },
1689 /* PCI PowerManagement Capability reg group */
1690 {
1691 .grp_id = PCI_CAP_ID_PM,
1692 .grp_type = XEN_PT_GRP_TYPE_EMU,
1693 .grp_size = PCI_PM_SIZEOF,
1694 .size_init = xen_pt_reg_grp_size_init,
1695 .emu_regs = xen_pt_emu_reg_pm,
1696 },
1697 /* AGP Capability Structure reg group */
1698 {
1699 .grp_id = PCI_CAP_ID_AGP,
1700 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1701 .grp_size = 0x30,
1702 .size_init = xen_pt_reg_grp_size_init,
1703 },
1704 /* Vital Product Data Capability Structure reg group */
1705 {
1706 .grp_id = PCI_CAP_ID_VPD,
1707 .grp_type = XEN_PT_GRP_TYPE_EMU,
1708 .grp_size = 0x08,
1709 .size_init = xen_pt_reg_grp_size_init,
1710 .emu_regs = xen_pt_emu_reg_vpd,
1711 },
1712 /* Slot Identification reg group */
1713 {
1714 .grp_id = PCI_CAP_ID_SLOTID,
1715 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1716 .grp_size = 0x04,
1717 .size_init = xen_pt_reg_grp_size_init,
1718 },
3854ca57
JY		 1719 /* MSI Capability Structure reg group */
1720 {
1721 .grp_id = PCI_CAP_ID_MSI,
1722 .grp_type = XEN_PT_GRP_TYPE_EMU,
1723 .grp_size = 0xFF,
1724 .size_init = xen_pt_msi_size_init,
1725 .emu_regs = xen_pt_emu_reg_msi,
1726 },
93d7ae8e
AK		 1727 /* PCI-X Capabilities List Item reg group */
1728 {
1729 .grp_id = PCI_CAP_ID_PCIX,
1730 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1731 .grp_size = 0x18,
1732 .size_init = xen_pt_reg_grp_size_init,
1733 },
1734 /* Vendor Specific Capability Structure reg group */
1735 {
1736 .grp_id = PCI_CAP_ID_VNDR,
1737 .grp_type = XEN_PT_GRP_TYPE_EMU,
1738 .grp_size = 0xFF,
1739 .size_init = xen_pt_vendor_size_init,
1740 .emu_regs = xen_pt_emu_reg_vendor,
1741 },
1742 /* SHPC Capability List Item reg group */
1743 {
1744 .grp_id = PCI_CAP_ID_SHPC,
1745 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1746 .grp_size = 0x08,
1747 .size_init = xen_pt_reg_grp_size_init,
1748 },
1749 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1750 {
1751 .grp_id = PCI_CAP_ID_SSVID,
1752 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1753 .grp_size = 0x08,
1754 .size_init = xen_pt_reg_grp_size_init,
1755 },
1756 /* AGP 8x Capability Structure reg group */
1757 {
1758 .grp_id = PCI_CAP_ID_AGP3,
1759 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1760 .grp_size = 0x30,
1761 .size_init = xen_pt_reg_grp_size_init,
1762 },
1763 /* PCI Express Capability Structure reg group */
1764 {
1765 .grp_id = PCI_CAP_ID_EXP,
1766 .grp_type = XEN_PT_GRP_TYPE_EMU,
1767 .grp_size = 0xFF,
1768 .size_init = xen_pt_pcie_size_init,
1769 .emu_regs = xen_pt_emu_reg_pcie,
1770 },
3854ca57
JY		 1771 /* MSI-X Capability Structure reg group */
1772 {
1773 .grp_id = PCI_CAP_ID_MSIX,
1774 .grp_type = XEN_PT_GRP_TYPE_EMU,
1775 .grp_size = 0x0C,
1776 .size_init = xen_pt_msix_size_init,
1777 .emu_regs = xen_pt_emu_reg_msix,
1778 },
5cec8aa3
TC		 1779 /* Intel IGD Opregion group */
1780 {
1781 .grp_id = XEN_PCI_INTEL_OPREGION,
1782 .grp_type = XEN_PT_GRP_TYPE_EMU,
1783 .grp_size = 0x4,
1784 .size_init = xen_pt_reg_grp_size_init,
1785 .emu_regs = xen_pt_emu_reg_igd_opregion,
1786 },
93d7ae8e
AK		 1787 {
1788 .grp_size = 0,
1789 },
1790};
1791
1792/* initialize Capabilities Pointer or Next Pointer register */
1793static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s,
1794 XenPTRegInfo *reg, uint32_t real_offset,
1795 uint32_t *data)
1796{
6aa07b14
KRW		 1797 int i, rc;
1798 uint8_t reg_field;
93d7ae8e
AK		 1799 uint8_t cap_id = 0;
1800
6aa07b14
KRW		 1801 rc = xen_host_pci_get_byte(&s->real_device, real_offset, &reg_field);
1802 if (rc) {
1803 return rc;
1804 }
93d7ae8e
AK		 1805 /* find capability offset */
1806 while (reg_field) {
1807 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1808 if (xen_pt_hide_dev_cap(&s->real_device,
1809 xen_pt_emu_reg_grps[i].grp_id)) {
1810 continue;
1811 }
1812
6aa07b14
KRW		 1813 rc = xen_host_pci_get_byte(&s->real_device,
1814 reg_field + PCI_CAP_LIST_ID, &cap_id);
1815 if (rc) {
1816 return rc;
1817 }
93d7ae8e
AK		 1818 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) {
1819 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1820 goto out;
1821 }
1822 /* ignore the 0 hardwired capability, find next one */
1823 break;
1824 }
1825 }
1826
1827 /* next capability */
6aa07b14
KRW		 1828 rc = xen_host_pci_get_byte(&s->real_device,
1829 reg_field + PCI_CAP_LIST_NEXT, &reg_field);
1830 if (rc) {
1831 return rc;
1832 }
93d7ae8e
AK		 1833 }
1834
1835out:
1836 *data = reg_field;
1837 return 0;
1838}
1839
1840
1841/*************
1842 * Main
1843 */
1844
1845static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap)
1846{
1847 uint8_t id;
5cec8aa3 1848 unsigned max_cap = XEN_PCI_CAP_MAX;
93d7ae8e
AK		 1849 uint8_t pos = PCI_CAPABILITY_LIST;
1850 uint8_t status = 0;
1851
1852 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) {
1853 return 0;
1854 }
1855 if ((status & PCI_STATUS_CAP_LIST) == 0) {
1856 return 0;
1857 }
1858
1859 while (max_cap--) {
1860 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) {
1861 break;
1862 }
1863 if (pos < PCI_CONFIG_HEADER_SIZE) {
1864 break;
1865 }
1866
1867 pos &= ~3;
1868 if (xen_host_pci_get_byte(&s->real_device,
1869 pos + PCI_CAP_LIST_ID, &id)) {
1870 break;
1871 }
1872
1873 if (id == 0xff) {
1874 break;
1875 }
1876 if (id == cap) {
1877 return pos;
1878 }
1879
1880 pos += PCI_CAP_LIST_NEXT;
1881 }
1882 return 0;
1883}
1884
1885static int xen_pt_config_reg_init(XenPCIPassthroughState *s,
1886 XenPTRegGroup *reg_grp, XenPTRegInfo *reg)
1887{
1888 XenPTReg *reg_entry;
1889 uint32_t data = 0;
1890 int rc = 0;
1891
1892 reg_entry = g_new0(XenPTReg, 1);
1893 reg_entry->reg = reg;
1894
1895 if (reg->init) {
1896 /* initialize emulate register */
1897 rc = reg->init(s, reg_entry->reg,
1898 reg_grp->base_offset + reg->offset, &data);
1899 if (rc < 0) {
c5633d99 1900 g_free(reg_entry);
93d7ae8e
AK		 1901 return rc;
1902 }
1903 if (data == XEN_PT_INVALID_REG) {
1904 /* free unused BAR register entry */
c5633d99 1905 g_free(reg_entry);
93d7ae8e
AK		 1906 return 0;
1907 }
1908 /* set register value */
1909 reg_entry->data = data;
1910 }
1911 /* list add register entry */
1912 QLIST_INSERT_HEAD(&reg_grp->reg_tbl_list, reg_entry, entries);
1913
1914 return 0;
1915}
1916
1917int xen_pt_config_init(XenPCIPassthroughState *s)
1918{
1919 int i, rc;
1920
1921 QLIST_INIT(&s->reg_grps);
1922
1923 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1924 uint32_t reg_grp_offset = 0;
1925 XenPTRegGroup *reg_grp_entry = NULL;
1926
5cec8aa3
TC		 1927 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF
1928 && xen_pt_emu_reg_grps[i].grp_id != XEN_PCI_INTEL_OPREGION) {
93d7ae8e
AK		 1929 if (xen_pt_hide_dev_cap(&s->real_device,
1930 xen_pt_emu_reg_grps[i].grp_id)) {
1931 continue;
1932 }
1933
1934 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id);
1935
1936 if (!reg_grp_offset) {
1937 continue;
1938 }
1939 }
1940
5cec8aa3
TC		 1941 /*
1942 * By default we will trap up to 0x40 in the cfg space.
1943 * If an intel device is pass through we need to trap 0xfc,
1944 * therefore the size should be 0xff.
1945 */
1946 if (xen_pt_emu_reg_grps[i].grp_id == XEN_PCI_INTEL_OPREGION) {
1947 reg_grp_offset = XEN_PCI_INTEL_OPREGION;
1948 }
1949
93d7ae8e
AK		 1950 reg_grp_entry = g_new0(XenPTRegGroup, 1);
1951 QLIST_INIT(&reg_grp_entry->reg_tbl_list);
1952 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
1953
1954 reg_grp_entry->base_offset = reg_grp_offset;
1955 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i;
1956 if (xen_pt_emu_reg_grps[i].size_init) {
1957 /* get register group size */
1958 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp,
1959 reg_grp_offset,
1960 &reg_grp_entry->size);
1961 if (rc < 0) {
1962 xen_pt_config_delete(s);
1963 return rc;
1964 }
1965 }
1966
1967 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1968 if (xen_pt_emu_reg_grps[i].emu_regs) {
1969 int j = 0;
1970 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs;
1971 /* initialize capability register */
1972 for (j = 0; regs->size != 0; j++, regs++) {
1973 /* initialize capability register */
1974 rc = xen_pt_config_reg_init(s, reg_grp_entry, regs);
1975 if (rc < 0) {
1976 xen_pt_config_delete(s);
1977 return rc;
1978 }
1979 }
1980 }
1981 }
1982 }
1983
1984 return 0;
1985}
1986
1987/* delete all emulate register */
1988void xen_pt_config_delete(XenPCIPassthroughState *s)
1989{
1990 struct XenPTRegGroup *reg_group, *next_grp;
1991 struct XenPTReg *reg, *next_reg;
1992
3854ca57
JY		 1993 /* free MSI/MSI-X info table */
1994 if (s->msix) {
1995 xen_pt_msix_delete(s);
1996 }
1997 if (s->msi) {
1998 g_free(s->msi);
1999 }
2000
93d7ae8e
AK		 2001 /* free all register group entry */
2002 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) {
2003 /* free all register entry */
2004 QLIST_FOREACH_SAFE(reg, &reg_group->reg_tbl_list, entries, next_reg) {
2005 QLIST_REMOVE(reg, entries);
2006 g_free(reg);
2007 }
2008
2009 QLIST_REMOVE(reg_group, entries);
2010 g_free(reg_group);
2011 }
2012}
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