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xen/MSI: don't open-code pass-through of enable bit modifications
[qemu.git] / hw / xen / xen_pt_config_init.c
CommitLineData
93d7ae8e
AK		 1/*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <[email protected]>
9 * Allen Kay <[email protected]>
10 * Guy Zana <[email protected]>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
1de7afc9 15#include "qemu/timer.h"
0d09e41a 16#include "hw/xen/xen_backend.h"
47b43a1f 17#include "xen_pt.h"
eaab4d60 18
93d7ae8e
AK		 19#define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
21
22#define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
23
24/* prototype */
25
26static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
27 uint32_t real_offset, uint32_t *data);
28
29
30/* helper */
31
32/* A return value of 1 means the capability should NOT be exposed to guest. */
33static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id)
34{
35 switch (grp_id) {
36 case PCI_CAP_ID_EXP:
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
40 *
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
43 *
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
49 */
50 if (d->vendor_id == PCI_VENDOR_ID_INTEL &&
51 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) {
52 return 1;
53 }
54 break;
55 }
56 return 0;
57}
58
59/* find emulate register group entry */
eaab4d60
AK		 60XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address)
61{
93d7ae8e
AK		 62 XenPTRegGroup *entry = NULL;
63
64 /* find register group entry */
65 QLIST_FOREACH(entry, &s->reg_grps, entries) {
66 /* check address */
67 if ((entry->base_offset <= address)
68 && ((entry->base_offset + entry->size) > address)) {
69 return entry;
70 }
71 }
72
73 /* group entry not found */
eaab4d60
AK		 74 return NULL;
75}
76
93d7ae8e 77/* find emulate register entry */
eaab4d60
AK		 78XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address)
79{
93d7ae8e
AK		 80 XenPTReg *reg_entry = NULL;
81 XenPTRegInfo *reg = NULL;
82 uint32_t real_offset = 0;
83
84 /* find register entry */
85 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) {
86 reg = reg_entry->reg;
87 real_offset = reg_grp->base_offset + reg->offset;
88 /* check address */
89 if ((real_offset <= address)
90 && ((real_offset + reg->size) > address)) {
91 return reg_entry;
92 }
93 }
94
eaab4d60
AK		 95 return NULL;
96}
93d7ae8e
AK		 97
98
99/****************
100 * general register functions
101 */
102
103/* register initialization function */
104
105static int xen_pt_common_reg_init(XenPCIPassthroughState *s,
106 XenPTRegInfo *reg, uint32_t real_offset,
107 uint32_t *data)
108{
109 *data = reg->init_val;
110 return 0;
111}
112
113/* Read register functions */
114
115static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
116 uint8_t *value, uint8_t valid_mask)
117{
118 XenPTRegInfo *reg = cfg_entry->reg;
119 uint8_t valid_emu_mask = 0;
120
121 /* emulate byte register */
122 valid_emu_mask = reg->emu_mask & valid_mask;
123 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
124
125 return 0;
126}
127static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
128 uint16_t *value, uint16_t valid_mask)
129{
130 XenPTRegInfo *reg = cfg_entry->reg;
131 uint16_t valid_emu_mask = 0;
132
133 /* emulate word register */
134 valid_emu_mask = reg->emu_mask & valid_mask;
135 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
136
137 return 0;
138}
139static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
140 uint32_t *value, uint32_t valid_mask)
141{
142 XenPTRegInfo *reg = cfg_entry->reg;
143 uint32_t valid_emu_mask = 0;
144
145 /* emulate long register */
146 valid_emu_mask = reg->emu_mask & valid_mask;
147 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
148
149 return 0;
150}
151
152/* Write register functions */
153
154static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
155 uint8_t *val, uint8_t dev_value,
156 uint8_t valid_mask)
157{
158 XenPTRegInfo *reg = cfg_entry->reg;
159 uint8_t writable_mask = 0;
160 uint8_t throughable_mask = 0;
161
162 /* modify emulate register */
163 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
164 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
165
166 /* create value for writing to I/O device register */
167 throughable_mask = ~reg->emu_mask & valid_mask;
168 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
169
170 return 0;
171}
172static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
173 uint16_t *val, uint16_t dev_value,
174 uint16_t valid_mask)
175{
176 XenPTRegInfo *reg = cfg_entry->reg;
177 uint16_t writable_mask = 0;
178 uint16_t throughable_mask = 0;
179
180 /* modify emulate register */
181 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
182 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
183
184 /* create value for writing to I/O device register */
185 throughable_mask = ~reg->emu_mask & valid_mask;
186 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
187
188 return 0;
189}
190static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
191 uint32_t *val, uint32_t dev_value,
192 uint32_t valid_mask)
193{
194 XenPTRegInfo *reg = cfg_entry->reg;
195 uint32_t writable_mask = 0;
196 uint32_t throughable_mask = 0;
197
198 /* modify emulate register */
199 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
200 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
201
202 /* create value for writing to I/O device register */
203 throughable_mask = ~reg->emu_mask & valid_mask;
204 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
205
206 return 0;
207}
208
209
210/* XenPTRegInfo declaration
211 * - only for emulated register (either a part or whole bit).
212 * - for passthrough register that need special behavior (like interacting with
213 * other component), set emu_mask to all 0 and specify r/w func properly.
214 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
215 */
216
217/********************
218 * Header Type0
219 */
220
221static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s,
222 XenPTRegInfo *reg, uint32_t real_offset,
223 uint32_t *data)
224{
225 *data = s->real_device.vendor_id;
226 return 0;
227}
228static int xen_pt_device_reg_init(XenPCIPassthroughState *s,
229 XenPTRegInfo *reg, uint32_t real_offset,
230 uint32_t *data)
231{
232 *data = s->real_device.device_id;
233 return 0;
234}
235static int xen_pt_status_reg_init(XenPCIPassthroughState *s,
236 XenPTRegInfo *reg, uint32_t real_offset,
237 uint32_t *data)
238{
239 XenPTRegGroup *reg_grp_entry = NULL;
240 XenPTReg *reg_entry = NULL;
241 uint32_t reg_field = 0;
242
243 /* find Header register group */
244 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST);
245 if (reg_grp_entry) {
246 /* find Capabilities Pointer register */
247 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
248 if (reg_entry) {
249 /* check Capabilities Pointer register */
250 if (reg_entry->data) {
251 reg_field |= PCI_STATUS_CAP_LIST;
252 } else {
253 reg_field &= ~PCI_STATUS_CAP_LIST;
254 }
255 } else {
256 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
257 " for Capabilities Pointer register."
258 " (%s)\n", __func__);
259 return -1;
260 }
261 } else {
262 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
263 " for Header. (%s)\n", __func__);
264 return -1;
265 }
266
267 *data = reg_field;
268 return 0;
269}
270static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s,
271 XenPTRegInfo *reg, uint32_t real_offset,
272 uint32_t *data)
273{
274 /* read PCI_HEADER_TYPE */
275 *data = reg->init_val | 0x80;
276 return 0;
277}
278
279/* initialize Interrupt Pin register */
280static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s,
281 XenPTRegInfo *reg, uint32_t real_offset,
282 uint32_t *data)
283{
284 *data = xen_pt_pci_read_intx(s);
285 return 0;
286}
287
288/* Command register */
93d7ae8e
AK		 289static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
290 uint16_t *val, uint16_t dev_value,
291 uint16_t valid_mask)
292{
293 XenPTRegInfo *reg = cfg_entry->reg;
294 uint16_t writable_mask = 0;
295 uint16_t throughable_mask = 0;
93d7ae8e
AK		 296
297 /* modify emulate register */
298 writable_mask = ~reg->ro_mask & valid_mask;
299 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
300
301 /* create value for writing to I/O device register */
81b23ef8 302 throughable_mask = ~reg->emu_mask & valid_mask;
93d7ae8e
AK		 303
304 if (*val & PCI_COMMAND_INTX_DISABLE) {
305 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
306 } else {
307 if (s->machine_irq) {
308 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
309 }
310 }
311
312 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
313
314 return 0;
315}
316
317/* BAR */
318#define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
319#define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
320#define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
321#define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
322
aabc8530
XH		 323static bool is_64bit_bar(PCIIORegion *r)
324{
325 return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
326}
327
328static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
329{
330 if (is_64bit_bar(r)) {
331 uint64_t size64;
332 size64 = (r + 1)->size;
333 size64 <<= 32;
334 size64 += r->size;
335 return size64;
336 }
337 return r->size;
338}
339
93d7ae8e 340static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
d4cd4502 341 int index)
93d7ae8e
AK		 342{
343 PCIDevice *d = &s->dev;
344 XenPTRegion *region = NULL;
345 PCIIORegion *r;
93d7ae8e
AK		 346
347 /* check 64bit BAR */
93d7ae8e
AK		 348 if ((0 < index) && (index < PCI_ROM_SLOT)) {
349 int type = s->real_device.io_regions[index - 1].type;
350
351 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM)
352 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) {
353 region = &s->bases[index - 1];
354 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) {
355 return XEN_PT_BAR_FLAG_UPPER;
356 }
357 }
358 }
359
360 /* check unused BAR */
361 r = &d->io_regions[index];
aabc8530 362 if (!xen_pt_get_bar_size(r)) {
93d7ae8e
AK		 363 return XEN_PT_BAR_FLAG_UNUSED;
364 }
365
366 /* for ExpROM BAR */
367 if (index == PCI_ROM_SLOT) {
368 return XEN_PT_BAR_FLAG_MEM;
369 }
370
371 /* check BAR I/O indicator */
372 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) {
373 return XEN_PT_BAR_FLAG_IO;
374 } else {
375 return XEN_PT_BAR_FLAG_MEM;
376 }
377}
378
379static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr)
380{
381 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) {
382 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK);
383 } else {
384 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK);
385 }
386}
387
388static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
389 uint32_t real_offset, uint32_t *data)
390{
391 uint32_t reg_field = 0;
392 int index;
393
394 index = xen_pt_bar_offset_to_index(reg->offset);
395 if (index < 0 || index >= PCI_NUM_REGIONS) {
396 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
397 return -1;
398 }
399
400 /* set BAR flag */
d4cd4502 401 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, index);
93d7ae8e
AK		 402 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) {
403 reg_field = XEN_PT_INVALID_REG;
404 }
405
406 *data = reg_field;
407 return 0;
408}
409static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
410 uint32_t *value, uint32_t valid_mask)
411{
412 XenPTRegInfo *reg = cfg_entry->reg;
413 uint32_t valid_emu_mask = 0;
414 uint32_t bar_emu_mask = 0;
415 int index;
416
417 /* get BAR index */
418 index = xen_pt_bar_offset_to_index(reg->offset);
14cec170 419 if (index < 0 || index >= PCI_NUM_REGIONS - 1) {
93d7ae8e
AK		 420 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
421 return -1;
422 }
423
424 /* use fixed-up value from kernel sysfs */
425 *value = base_address_with_flags(&s->real_device.io_regions[index]);
426
427 /* set emulate mask depend on BAR flag */
428 switch (s->bases[index].bar_flag) {
429 case XEN_PT_BAR_FLAG_MEM:
430 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
431 break;
432 case XEN_PT_BAR_FLAG_IO:
433 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
434 break;
435 case XEN_PT_BAR_FLAG_UPPER:
436 bar_emu_mask = XEN_PT_BAR_ALLF;
437 break;
438 default:
439 break;
440 }
441
442 /* emulate BAR */
443 valid_emu_mask = bar_emu_mask & valid_mask;
444 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
445
446 return 0;
447}
448static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
449 uint32_t *val, uint32_t dev_value,
450 uint32_t valid_mask)
451{
452 XenPTRegInfo *reg = cfg_entry->reg;
453 XenPTRegion *base = NULL;
454 PCIDevice *d = &s->dev;
455 const PCIIORegion *r;
456 uint32_t writable_mask = 0;
457 uint32_t throughable_mask = 0;
458 uint32_t bar_emu_mask = 0;
459 uint32_t bar_ro_mask = 0;
460 uint32_t r_size = 0;
461 int index = 0;
462
463 index = xen_pt_bar_offset_to_index(reg->offset);
464 if (index < 0 || index >= PCI_NUM_REGIONS) {
465 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index);
466 return -1;
467 }
468
469 r = &d->io_regions[index];
470 base = &s->bases[index];
471 r_size = xen_pt_get_emul_size(base->bar_flag, r->size);
472
473 /* set emulate mask and read-only mask values depend on the BAR flag */
474 switch (s->bases[index].bar_flag) {
475 case XEN_PT_BAR_FLAG_MEM:
476 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
aabc8530
XH		 477 if (!r_size) {
478 /* low 32 bits mask for 64 bit bars */
479 bar_ro_mask = XEN_PT_BAR_ALLF;
480 } else {
481 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
482 }
93d7ae8e
AK		 483 break;
484 case XEN_PT_BAR_FLAG_IO:
485 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
486 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1);
487 break;
488 case XEN_PT_BAR_FLAG_UPPER:
489 bar_emu_mask = XEN_PT_BAR_ALLF;
aabc8530 490 bar_ro_mask = r_size ? r_size - 1 : 0;
93d7ae8e
AK		 491 break;
492 default:
493 break;
494 }
495
496 /* modify emulate register */
497 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
498 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
499
500 /* check whether we need to update the virtual region address or not */
501 switch (s->bases[index].bar_flag) {
aabc8530 502 case XEN_PT_BAR_FLAG_UPPER:
93d7ae8e
AK		 503 case XEN_PT_BAR_FLAG_MEM:
504 /* nothing to do */
505 break;
506 case XEN_PT_BAR_FLAG_IO:
507 /* nothing to do */
508 break;
93d7ae8e
AK		 509 default:
510 break;
511 }
512
513 /* create value for writing to I/O device register */
514 throughable_mask = ~bar_emu_mask & valid_mask;
515 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
516
517 return 0;
518}
519
520/* write Exp ROM BAR */
521static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
522 XenPTReg *cfg_entry, uint32_t *val,
523 uint32_t dev_value, uint32_t valid_mask)
524{
525 XenPTRegInfo *reg = cfg_entry->reg;
526 XenPTRegion *base = NULL;
527 PCIDevice *d = (PCIDevice *)&s->dev;
528 uint32_t writable_mask = 0;
529 uint32_t throughable_mask = 0;
530 pcibus_t r_size = 0;
531 uint32_t bar_emu_mask = 0;
532 uint32_t bar_ro_mask = 0;
533
534 r_size = d->io_regions[PCI_ROM_SLOT].size;
535 base = &s->bases[PCI_ROM_SLOT];
536 /* align memory type resource size */
537 r_size = xen_pt_get_emul_size(base->bar_flag, r_size);
538
539 /* set emulate mask and read-only mask */
540 bar_emu_mask = reg->emu_mask;
541 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;
542
543 /* modify emulate register */
544 writable_mask = ~bar_ro_mask & valid_mask;
545 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
546
547 /* create value for writing to I/O device register */
548 throughable_mask = ~bar_emu_mask & valid_mask;
549 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
550
551 return 0;
552}
553
0546b8c2 554/* Header Type0 reg static information table */
93d7ae8e
AK		 555static XenPTRegInfo xen_pt_emu_reg_header0[] = {
556 /* Vendor ID reg */
557 {
558 .offset = PCI_VENDOR_ID,
559 .size = 2,
560 .init_val = 0x0000,
561 .ro_mask = 0xFFFF,
562 .emu_mask = 0xFFFF,
563 .init = xen_pt_vendor_reg_init,
564 .u.w.read = xen_pt_word_reg_read,
565 .u.w.write = xen_pt_word_reg_write,
566 },
567 /* Device ID reg */
568 {
569 .offset = PCI_DEVICE_ID,
570 .size = 2,
571 .init_val = 0x0000,
572 .ro_mask = 0xFFFF,
573 .emu_mask = 0xFFFF,
574 .init = xen_pt_device_reg_init,
575 .u.w.read = xen_pt_word_reg_read,
576 .u.w.write = xen_pt_word_reg_write,
577 },
578 /* Command reg */
579 {
580 .offset = PCI_COMMAND,
581 .size = 2,
582 .init_val = 0x0000,
583 .ro_mask = 0xF880,
81b23ef8 584 .emu_mask = 0x0743,
93d7ae8e 585 .init = xen_pt_common_reg_init,
81b23ef8 586 .u.w.read = xen_pt_word_reg_read,
93d7ae8e
AK		 587 .u.w.write = xen_pt_cmd_reg_write,
588 },
589 /* Capabilities Pointer reg */
590 {
591 .offset = PCI_CAPABILITY_LIST,
592 .size = 1,
593 .init_val = 0x00,
594 .ro_mask = 0xFF,
595 .emu_mask = 0xFF,
596 .init = xen_pt_ptr_reg_init,
597 .u.b.read = xen_pt_byte_reg_read,
598 .u.b.write = xen_pt_byte_reg_write,
599 },
600 /* Status reg */
601 /* use emulated Cap Ptr value to initialize,
602 * so need to be declared after Cap Ptr reg
603 */
604 {
605 .offset = PCI_STATUS,
606 .size = 2,
607 .init_val = 0x0000,
608 .ro_mask = 0x06FF,
609 .emu_mask = 0x0010,
610 .init = xen_pt_status_reg_init,
611 .u.w.read = xen_pt_word_reg_read,
612 .u.w.write = xen_pt_word_reg_write,
613 },
614 /* Cache Line Size reg */
615 {
616 .offset = PCI_CACHE_LINE_SIZE,
617 .size = 1,
618 .init_val = 0x00,
619 .ro_mask = 0x00,
620 .emu_mask = 0xFF,
621 .init = xen_pt_common_reg_init,
622 .u.b.read = xen_pt_byte_reg_read,
623 .u.b.write = xen_pt_byte_reg_write,
624 },
625 /* Latency Timer reg */
626 {
627 .offset = PCI_LATENCY_TIMER,
628 .size = 1,
629 .init_val = 0x00,
630 .ro_mask = 0x00,
631 .emu_mask = 0xFF,
632 .init = xen_pt_common_reg_init,
633 .u.b.read = xen_pt_byte_reg_read,
634 .u.b.write = xen_pt_byte_reg_write,
635 },
636 /* Header Type reg */
637 {
638 .offset = PCI_HEADER_TYPE,
639 .size = 1,
640 .init_val = 0x00,
641 .ro_mask = 0xFF,
642 .emu_mask = 0x00,
643 .init = xen_pt_header_type_reg_init,
644 .u.b.read = xen_pt_byte_reg_read,
645 .u.b.write = xen_pt_byte_reg_write,
646 },
647 /* Interrupt Line reg */
648 {
649 .offset = PCI_INTERRUPT_LINE,
650 .size = 1,
651 .init_val = 0x00,
652 .ro_mask = 0x00,
653 .emu_mask = 0xFF,
654 .init = xen_pt_common_reg_init,
655 .u.b.read = xen_pt_byte_reg_read,
656 .u.b.write = xen_pt_byte_reg_write,
657 },
658 /* Interrupt Pin reg */
659 {
660 .offset = PCI_INTERRUPT_PIN,
661 .size = 1,
662 .init_val = 0x00,
663 .ro_mask = 0xFF,
664 .emu_mask = 0xFF,
665 .init = xen_pt_irqpin_reg_init,
666 .u.b.read = xen_pt_byte_reg_read,
667 .u.b.write = xen_pt_byte_reg_write,
668 },
669 /* BAR 0 reg */
670 /* mask of BAR need to be decided later, depends on IO/MEM type */
671 {
672 .offset = PCI_BASE_ADDRESS_0,
673 .size = 4,
674 .init_val = 0x00000000,
675 .init = xen_pt_bar_reg_init,
676 .u.dw.read = xen_pt_bar_reg_read,
677 .u.dw.write = xen_pt_bar_reg_write,
678 },
679 /* BAR 1 reg */
680 {
681 .offset = PCI_BASE_ADDRESS_1,
682 .size = 4,
683 .init_val = 0x00000000,
684 .init = xen_pt_bar_reg_init,
685 .u.dw.read = xen_pt_bar_reg_read,
686 .u.dw.write = xen_pt_bar_reg_write,
687 },
688 /* BAR 2 reg */
689 {
690 .offset = PCI_BASE_ADDRESS_2,
691 .size = 4,
692 .init_val = 0x00000000,
693 .init = xen_pt_bar_reg_init,
694 .u.dw.read = xen_pt_bar_reg_read,
695 .u.dw.write = xen_pt_bar_reg_write,
696 },
697 /* BAR 3 reg */
698 {
699 .offset = PCI_BASE_ADDRESS_3,
700 .size = 4,
701 .init_val = 0x00000000,
702 .init = xen_pt_bar_reg_init,
703 .u.dw.read = xen_pt_bar_reg_read,
704 .u.dw.write = xen_pt_bar_reg_write,
705 },
706 /* BAR 4 reg */
707 {
708 .offset = PCI_BASE_ADDRESS_4,
709 .size = 4,
710 .init_val = 0x00000000,
711 .init = xen_pt_bar_reg_init,
712 .u.dw.read = xen_pt_bar_reg_read,
713 .u.dw.write = xen_pt_bar_reg_write,
714 },
715 /* BAR 5 reg */
716 {
717 .offset = PCI_BASE_ADDRESS_5,
718 .size = 4,
719 .init_val = 0x00000000,
720 .init = xen_pt_bar_reg_init,
721 .u.dw.read = xen_pt_bar_reg_read,
722 .u.dw.write = xen_pt_bar_reg_write,
723 },
724 /* Expansion ROM BAR reg */
725 {
726 .offset = PCI_ROM_ADDRESS,
727 .size = 4,
728 .init_val = 0x00000000,
729 .ro_mask = 0x000007FE,
730 .emu_mask = 0xFFFFF800,
731 .init = xen_pt_bar_reg_init,
732 .u.dw.read = xen_pt_long_reg_read,
733 .u.dw.write = xen_pt_exp_rom_bar_reg_write,
734 },
735 {
736 .size = 0,
737 },
738};
739
740
741/*********************************
742 * Vital Product Data Capability
743 */
744
0546b8c2 745/* Vital Product Data Capability Structure reg static information table */
93d7ae8e
AK		 746static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
747 {
748 .offset = PCI_CAP_LIST_NEXT,
749 .size = 1,
750 .init_val = 0x00,
751 .ro_mask = 0xFF,
752 .emu_mask = 0xFF,
753 .init = xen_pt_ptr_reg_init,
754 .u.b.read = xen_pt_byte_reg_read,
755 .u.b.write = xen_pt_byte_reg_write,
756 },
757 {
758 .size = 0,
759 },
760};
761
762
763/**************************************
764 * Vendor Specific Capability
765 */
766
0546b8c2 767/* Vendor Specific Capability Structure reg static information table */
93d7ae8e
AK		 768static XenPTRegInfo xen_pt_emu_reg_vendor[] = {
769 {
770 .offset = PCI_CAP_LIST_NEXT,
771 .size = 1,
772 .init_val = 0x00,
773 .ro_mask = 0xFF,
774 .emu_mask = 0xFF,
775 .init = xen_pt_ptr_reg_init,
776 .u.b.read = xen_pt_byte_reg_read,
777 .u.b.write = xen_pt_byte_reg_write,
778 },
779 {
780 .size = 0,
781 },
782};
783
784
785/*****************************
786 * PCI Express Capability
787 */
788
789static inline uint8_t get_capability_version(XenPCIPassthroughState *s,
790 uint32_t offset)
791{
792 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
793 return flags & PCI_EXP_FLAGS_VERS;
794}
795
796static inline uint8_t get_device_type(XenPCIPassthroughState *s,
797 uint32_t offset)
798{
799 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
800 return (flags & PCI_EXP_FLAGS_TYPE) >> 4;
801}
802
803/* initialize Link Control register */
804static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s,
805 XenPTRegInfo *reg, uint32_t real_offset,
806 uint32_t *data)
807{
808 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
809 uint8_t dev_type = get_device_type(s, real_offset - reg->offset);
810
811 /* no need to initialize in case of Root Complex Integrated Endpoint
812 * with cap_ver 1.x
813 */
814 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) {
815 *data = XEN_PT_INVALID_REG;
816 }
817
818 *data = reg->init_val;
819 return 0;
820}
821/* initialize Device Control 2 register */
822static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s,
823 XenPTRegInfo *reg, uint32_t real_offset,
824 uint32_t *data)
825{
826 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
827
828 /* no need to initialize in case of cap_ver 1.x */
829 if (cap_ver == 1) {
830 *data = XEN_PT_INVALID_REG;
831 }
832
833 *data = reg->init_val;
834 return 0;
835}
836/* initialize Link Control 2 register */
837static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s,
838 XenPTRegInfo *reg, uint32_t real_offset,
839 uint32_t *data)
840{
841 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
842 uint32_t reg_field = 0;
843
844 /* no need to initialize in case of cap_ver 1.x */
845 if (cap_ver == 1) {
846 reg_field = XEN_PT_INVALID_REG;
847 } else {
848 /* set Supported Link Speed */
849 uint8_t lnkcap = pci_get_byte(s->dev.config + real_offset - reg->offset
850 + PCI_EXP_LNKCAP);
851 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap;
852 }
853
854 *data = reg_field;
855 return 0;
856}
857
0546b8c2 858/* PCI Express Capability Structure reg static information table */
93d7ae8e
AK		 859static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
860 /* Next Pointer reg */
861 {
862 .offset = PCI_CAP_LIST_NEXT,
863 .size = 1,
864 .init_val = 0x00,
865 .ro_mask = 0xFF,
866 .emu_mask = 0xFF,
867 .init = xen_pt_ptr_reg_init,
868 .u.b.read = xen_pt_byte_reg_read,
869 .u.b.write = xen_pt_byte_reg_write,
870 },
871 /* Device Capabilities reg */
872 {
873 .offset = PCI_EXP_DEVCAP,
874 .size = 4,
875 .init_val = 0x00000000,
876 .ro_mask = 0x1FFCFFFF,
877 .emu_mask = 0x10000000,
878 .init = xen_pt_common_reg_init,
879 .u.dw.read = xen_pt_long_reg_read,
880 .u.dw.write = xen_pt_long_reg_write,
881 },
882 /* Device Control reg */
883 {
884 .offset = PCI_EXP_DEVCTL,
885 .size = 2,
886 .init_val = 0x2810,
887 .ro_mask = 0x8400,
888 .emu_mask = 0xFFFF,
889 .init = xen_pt_common_reg_init,
890 .u.w.read = xen_pt_word_reg_read,
891 .u.w.write = xen_pt_word_reg_write,
892 },
893 /* Link Control reg */
894 {
895 .offset = PCI_EXP_LNKCTL,
896 .size = 2,
897 .init_val = 0x0000,
898 .ro_mask = 0xFC34,
899 .emu_mask = 0xFFFF,
900 .init = xen_pt_linkctrl_reg_init,
901 .u.w.read = xen_pt_word_reg_read,
902 .u.w.write = xen_pt_word_reg_write,
903 },
904 /* Device Control 2 reg */
905 {
906 .offset = 0x28,
907 .size = 2,
908 .init_val = 0x0000,
909 .ro_mask = 0xFFE0,
910 .emu_mask = 0xFFFF,
911 .init = xen_pt_devctrl2_reg_init,
912 .u.w.read = xen_pt_word_reg_read,
913 .u.w.write = xen_pt_word_reg_write,
914 },
915 /* Link Control 2 reg */
916 {
917 .offset = 0x30,
918 .size = 2,
919 .init_val = 0x0000,
920 .ro_mask = 0xE040,
921 .emu_mask = 0xFFFF,
922 .init = xen_pt_linkctrl2_reg_init,
923 .u.w.read = xen_pt_word_reg_read,
924 .u.w.write = xen_pt_word_reg_write,
925 },
926 {
927 .size = 0,
928 },
929};
930
931
932/*********************************
933 * Power Management Capability
934 */
935
936/* read Power Management Control/Status register */
937static int xen_pt_pmcsr_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
938 uint16_t *value, uint16_t valid_mask)
939{
940 XenPTRegInfo *reg = cfg_entry->reg;
941 uint16_t valid_emu_mask = reg->emu_mask;
942
943 valid_emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
944
945 valid_emu_mask = valid_emu_mask & valid_mask;
946 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
947
948 return 0;
949}
950/* write Power Management Control/Status register */
951static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
952 XenPTReg *cfg_entry, uint16_t *val,
953 uint16_t dev_value, uint16_t valid_mask)
954{
955 XenPTRegInfo *reg = cfg_entry->reg;
956 uint16_t emu_mask = reg->emu_mask;
957 uint16_t writable_mask = 0;
958 uint16_t throughable_mask = 0;
959
960 emu_mask |= PCI_PM_CTRL_STATE_MASK | PCI_PM_CTRL_NO_SOFT_RESET;
961
962 /* modify emulate register */
963 writable_mask = emu_mask & ~reg->ro_mask & valid_mask;
964 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
965
966 /* create value for writing to I/O device register */
967 throughable_mask = ~emu_mask & valid_mask;
968 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
969
970 return 0;
971}
972
0546b8c2 973/* Power Management Capability reg static information table */
93d7ae8e
AK		 974static XenPTRegInfo xen_pt_emu_reg_pm[] = {
975 /* Next Pointer reg */
976 {
977 .offset = PCI_CAP_LIST_NEXT,
978 .size = 1,
979 .init_val = 0x00,
980 .ro_mask = 0xFF,
981 .emu_mask = 0xFF,
982 .init = xen_pt_ptr_reg_init,
983 .u.b.read = xen_pt_byte_reg_read,
984 .u.b.write = xen_pt_byte_reg_write,
985 },
986 /* Power Management Capabilities reg */
987 {
988 .offset = PCI_CAP_FLAGS,
989 .size = 2,
990 .init_val = 0x0000,
991 .ro_mask = 0xFFFF,
992 .emu_mask = 0xF9C8,
993 .init = xen_pt_common_reg_init,
994 .u.w.read = xen_pt_word_reg_read,
995 .u.w.write = xen_pt_word_reg_write,
996 },
997 /* PCI Power Management Control/Status reg */
998 {
999 .offset = PCI_PM_CTRL,
1000 .size = 2,
1001 .init_val = 0x0008,
1002 .ro_mask = 0xE1FC,
1003 .emu_mask = 0x8100,
1004 .init = xen_pt_common_reg_init,
1005 .u.w.read = xen_pt_pmcsr_reg_read,
1006 .u.w.write = xen_pt_pmcsr_reg_write,
1007 },
1008 {
1009 .size = 0,
1010 },
1011};
1012
1013
3854ca57
JY		 1014/********************************
1015 * MSI Capability
1016 */
1017
1018/* Helper */
7611dae8
JB		 1019#define xen_pt_msi_check_type(offset, flags, what) \
1020 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1021 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
3854ca57
JY		 1022
1023/* Message Control register */
1024static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
1025 XenPTRegInfo *reg, uint32_t real_offset,
1026 uint32_t *data)
1027{
1028 PCIDevice *d = &s->dev;
1029 XenPTMSI *msi = s->msi;
1030 uint16_t reg_field = 0;
1031
1032 /* use I/O device register's value as initial value */
1033 reg_field = pci_get_word(d->config + real_offset);
1034
1035 if (reg_field & PCI_MSI_FLAGS_ENABLE) {
1036 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n");
1037 xen_host_pci_set_word(&s->real_device, real_offset,
1038 reg_field & ~PCI_MSI_FLAGS_ENABLE);
1039 }
1040 msi->flags |= reg_field;
1041 msi->ctrl_offset = real_offset;
1042 msi->initialized = false;
1043 msi->mapped = false;
1044
1045 *data = reg->init_val;
1046 return 0;
1047}
1048static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
1049 XenPTReg *cfg_entry, uint16_t *val,
1050 uint16_t dev_value, uint16_t valid_mask)
1051{
1052 XenPTRegInfo *reg = cfg_entry->reg;
1053 XenPTMSI *msi = s->msi;
1054 uint16_t writable_mask = 0;
1055 uint16_t throughable_mask = 0;
3854ca57
JY		 1056
1057 /* Currently no support for multi-vector */
1058 if (*val & PCI_MSI_FLAGS_QSIZE) {
1059 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val);
1060 }
1061
1062 /* modify emulate register */
1063 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1064 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1065 msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE;
1066
1067 /* create value for writing to I/O device register */
3854ca57
JY		 1068 throughable_mask = ~reg->emu_mask & valid_mask;
1069 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1070
1071 /* update MSI */
d1d35cf4 1072 if (*val & PCI_MSI_FLAGS_ENABLE) {
3854ca57
JY		 1073 /* setup MSI pirq for the first time */
1074 if (!msi->initialized) {
1075 /* Init physical one */
1076 XEN_PT_LOG(&s->dev, "setup MSI\n");
1077 if (xen_pt_msi_setup(s)) {
1078 /* We do not broadcast the error to the framework code, so
1079 * that MSI errors are contained in MSI emulation code and
1080 * QEMU can go on running.
1081 * Guest MSI would be actually not working.
1082 */
1083 *val &= ~PCI_MSI_FLAGS_ENABLE;
1084 XEN_PT_WARN(&s->dev, "Can not map MSI.\n");
1085 return 0;
1086 }
1087 if (xen_pt_msi_update(s)) {
1088 *val &= ~PCI_MSI_FLAGS_ENABLE;
1089 XEN_PT_WARN(&s->dev, "Can not bind MSI\n");
1090 return 0;
1091 }
1092 msi->initialized = true;
1093 msi->mapped = true;
1094 }
1095 msi->flags |= PCI_MSI_FLAGS_ENABLE;
c976437c
ZD		 1096 } else if (msi->mapped) {
1097 xen_pt_msi_disable(s);
3854ca57
JY		 1098 }
1099
3854ca57
JY		 1100 return 0;
1101}
1102
1103/* initialize Message Upper Address register */
1104static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s,
1105 XenPTRegInfo *reg, uint32_t real_offset,
1106 uint32_t *data)
1107{
1108 /* no need to initialize in case of 32 bit type */
1109 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1110 *data = XEN_PT_INVALID_REG;
1111 } else {
1112 *data = reg->init_val;
1113 }
1114
1115 return 0;
1116}
1117/* this function will be called twice (for 32 bit and 64 bit type) */
1118/* initialize Message Data register */
1119static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
1120 XenPTRegInfo *reg, uint32_t real_offset,
1121 uint32_t *data)
1122{
1123 uint32_t flags = s->msi->flags;
1124 uint32_t offset = reg->offset;
1125
1126 /* check the offset whether matches the type or not */
7611dae8
JB		 1127 if (xen_pt_msi_check_type(offset, flags, DATA)) {
1128 *data = reg->init_val;
1129 } else {
1130 *data = XEN_PT_INVALID_REG;
1131 }
1132 return 0;
1133}
1134
1135/* this function will be called twice (for 32 bit and 64 bit type) */
1136/* initialize Mask register */
1137static int xen_pt_mask_reg_init(XenPCIPassthroughState *s,
1138 XenPTRegInfo *reg, uint32_t real_offset,
1139 uint32_t *data)
1140{
1141 uint32_t flags = s->msi->flags;
1142
1143 /* check the offset whether matches the type or not */
1144 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1145 *data = XEN_PT_INVALID_REG;
1146 } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) {
1147 *data = reg->init_val;
1148 } else {
1149 *data = XEN_PT_INVALID_REG;
1150 }
1151 return 0;
1152}
1153
1154/* this function will be called twice (for 32 bit and 64 bit type) */
1155/* initialize Pending register */
1156static int xen_pt_pending_reg_init(XenPCIPassthroughState *s,
1157 XenPTRegInfo *reg, uint32_t real_offset,
1158 uint32_t *data)
1159{
1160 uint32_t flags = s->msi->flags;
1161
1162 /* check the offset whether matches the type or not */
1163 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1164 *data = XEN_PT_INVALID_REG;
1165 } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) {
3854ca57
JY		 1166 *data = reg->init_val;
1167 } else {
1168 *data = XEN_PT_INVALID_REG;
1169 }
1170 return 0;
1171}
1172
1173/* write Message Address register */
1174static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s,
1175 XenPTReg *cfg_entry, uint32_t *val,
1176 uint32_t dev_value, uint32_t valid_mask)
1177{
1178 XenPTRegInfo *reg = cfg_entry->reg;
1179 uint32_t writable_mask = 0;
1180 uint32_t throughable_mask = 0;
1181 uint32_t old_addr = cfg_entry->data;
1182
1183 /* modify emulate register */
1184 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1185 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1186 s->msi->addr_lo = cfg_entry->data;
1187
1188 /* create value for writing to I/O device register */
1189 throughable_mask = ~reg->emu_mask & valid_mask;
1190 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1191
1192 /* update MSI */
1193 if (cfg_entry->data != old_addr) {
1194 if (s->msi->mapped) {
1195 xen_pt_msi_update(s);
1196 }
1197 }
1198
1199 return 0;
1200}
1201/* write Message Upper Address register */
1202static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s,
1203 XenPTReg *cfg_entry, uint32_t *val,
1204 uint32_t dev_value, uint32_t valid_mask)
1205{
1206 XenPTRegInfo *reg = cfg_entry->reg;
1207 uint32_t writable_mask = 0;
1208 uint32_t throughable_mask = 0;
1209 uint32_t old_addr = cfg_entry->data;
1210
1211 /* check whether the type is 64 bit or not */
1212 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1213 XEN_PT_ERR(&s->dev,
1214 "Can't write to the upper address without 64 bit support\n");
1215 return -1;
1216 }
1217
1218 /* modify emulate register */
1219 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1220 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1221 /* update the msi_info too */
1222 s->msi->addr_hi = cfg_entry->data;
1223
1224 /* create value for writing to I/O device register */
1225 throughable_mask = ~reg->emu_mask & valid_mask;
1226 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1227
1228 /* update MSI */
1229 if (cfg_entry->data != old_addr) {
1230 if (s->msi->mapped) {
1231 xen_pt_msi_update(s);
1232 }
1233 }
1234
1235 return 0;
1236}
1237
1238
1239/* this function will be called twice (for 32 bit and 64 bit type) */
1240/* write Message Data register */
1241static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
1242 XenPTReg *cfg_entry, uint16_t *val,
1243 uint16_t dev_value, uint16_t valid_mask)
1244{
1245 XenPTRegInfo *reg = cfg_entry->reg;
1246 XenPTMSI *msi = s->msi;
1247 uint16_t writable_mask = 0;
1248 uint16_t throughable_mask = 0;
1249 uint16_t old_data = cfg_entry->data;
1250 uint32_t offset = reg->offset;
1251
1252 /* check the offset whether matches the type or not */
7611dae8 1253 if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) {
3854ca57
JY		 1254 /* exit I/O emulator */
1255 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
1256 return -1;
1257 }
1258
1259 /* modify emulate register */
1260 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1261 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1262 /* update the msi_info too */
1263 msi->data = cfg_entry->data;
1264
1265 /* create value for writing to I/O device register */
1266 throughable_mask = ~reg->emu_mask & valid_mask;
1267 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1268
1269 /* update MSI */
1270 if (cfg_entry->data != old_data) {
1271 if (msi->mapped) {
1272 xen_pt_msi_update(s);
1273 }
1274 }
1275
1276 return 0;
1277}
1278
0546b8c2 1279/* MSI Capability Structure reg static information table */
3854ca57
JY		 1280static XenPTRegInfo xen_pt_emu_reg_msi[] = {
1281 /* Next Pointer reg */
1282 {
1283 .offset = PCI_CAP_LIST_NEXT,
1284 .size = 1,
1285 .init_val = 0x00,
1286 .ro_mask = 0xFF,
1287 .emu_mask = 0xFF,
1288 .init = xen_pt_ptr_reg_init,
1289 .u.b.read = xen_pt_byte_reg_read,
1290 .u.b.write = xen_pt_byte_reg_write,
1291 },
1292 /* Message Control reg */
1293 {
1294 .offset = PCI_MSI_FLAGS,
1295 .size = 2,
1296 .init_val = 0x0000,
1297 .ro_mask = 0xFF8E,
d1d35cf4 1298 .emu_mask = 0x017E,
3854ca57
JY		 1299 .init = xen_pt_msgctrl_reg_init,
1300 .u.w.read = xen_pt_word_reg_read,
1301 .u.w.write = xen_pt_msgctrl_reg_write,
1302 },
1303 /* Message Address reg */
1304 {
1305 .offset = PCI_MSI_ADDRESS_LO,
1306 .size = 4,
1307 .init_val = 0x00000000,
1308 .ro_mask = 0x00000003,
1309 .emu_mask = 0xFFFFFFFF,
3854ca57
JY		 1310 .init = xen_pt_common_reg_init,
1311 .u.dw.read = xen_pt_long_reg_read,
1312 .u.dw.write = xen_pt_msgaddr32_reg_write,
1313 },
1314 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1315 {
1316 .offset = PCI_MSI_ADDRESS_HI,
1317 .size = 4,
1318 .init_val = 0x00000000,
1319 .ro_mask = 0x00000000,
1320 .emu_mask = 0xFFFFFFFF,
3854ca57
JY		 1321 .init = xen_pt_msgaddr64_reg_init,
1322 .u.dw.read = xen_pt_long_reg_read,
1323 .u.dw.write = xen_pt_msgaddr64_reg_write,
1324 },
1325 /* Message Data reg (16 bits of data for 32-bit devices) */
1326 {
1327 .offset = PCI_MSI_DATA_32,
1328 .size = 2,
1329 .init_val = 0x0000,
1330 .ro_mask = 0x0000,
1331 .emu_mask = 0xFFFF,
3854ca57
JY		 1332 .init = xen_pt_msgdata_reg_init,
1333 .u.w.read = xen_pt_word_reg_read,
1334 .u.w.write = xen_pt_msgdata_reg_write,
1335 },
1336 /* Message Data reg (16 bits of data for 64-bit devices) */
1337 {
1338 .offset = PCI_MSI_DATA_64,
1339 .size = 2,
1340 .init_val = 0x0000,
1341 .ro_mask = 0x0000,
1342 .emu_mask = 0xFFFF,
3854ca57
JY		 1343 .init = xen_pt_msgdata_reg_init,
1344 .u.w.read = xen_pt_word_reg_read,
1345 .u.w.write = xen_pt_msgdata_reg_write,
1346 },
7611dae8
JB		 1347 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1348 {
1349 .offset = PCI_MSI_MASK_32,
1350 .size = 4,
1351 .init_val = 0x00000000,
1352 .ro_mask = 0xFFFFFFFF,
1353 .emu_mask = 0xFFFFFFFF,
1354 .init = xen_pt_mask_reg_init,
1355 .u.dw.read = xen_pt_long_reg_read,
1356 .u.dw.write = xen_pt_long_reg_write,
1357 },
1358 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1359 {
1360 .offset = PCI_MSI_MASK_64,
1361 .size = 4,
1362 .init_val = 0x00000000,
1363 .ro_mask = 0xFFFFFFFF,
1364 .emu_mask = 0xFFFFFFFF,
1365 .init = xen_pt_mask_reg_init,
1366 .u.dw.read = xen_pt_long_reg_read,
1367 .u.dw.write = xen_pt_long_reg_write,
1368 },
1369 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1370 {
1371 .offset = PCI_MSI_MASK_32 + 4,
1372 .size = 4,
1373 .init_val = 0x00000000,
1374 .ro_mask = 0xFFFFFFFF,
1375 .emu_mask = 0x00000000,
1376 .init = xen_pt_pending_reg_init,
1377 .u.dw.read = xen_pt_long_reg_read,
1378 .u.dw.write = xen_pt_long_reg_write,
1379 },
1380 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1381 {
1382 .offset = PCI_MSI_MASK_64 + 4,
1383 .size = 4,
1384 .init_val = 0x00000000,
1385 .ro_mask = 0xFFFFFFFF,
1386 .emu_mask = 0x00000000,
1387 .init = xen_pt_pending_reg_init,
1388 .u.dw.read = xen_pt_long_reg_read,
1389 .u.dw.write = xen_pt_long_reg_write,
1390 },
3854ca57
JY		 1391 {
1392 .size = 0,
1393 },
1394};
1395
1396
1397/**************************************
1398 * MSI-X Capability
1399 */
1400
1401/* Message Control register for MSI-X */
1402static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
1403 XenPTRegInfo *reg, uint32_t real_offset,
1404 uint32_t *data)
1405{
1406 PCIDevice *d = &s->dev;
1407 uint16_t reg_field = 0;
1408
1409 /* use I/O device register's value as initial value */
1410 reg_field = pci_get_word(d->config + real_offset);
1411
1412 if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
1413 XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
1414 xen_host_pci_set_word(&s->real_device, real_offset,
1415 reg_field & ~PCI_MSIX_FLAGS_ENABLE);
1416 }
1417
1418 s->msix->ctrl_offset = real_offset;
1419
1420 *data = reg->init_val;
1421 return 0;
1422}
1423static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
1424 XenPTReg *cfg_entry, uint16_t *val,
1425 uint16_t dev_value, uint16_t valid_mask)
1426{
1427 XenPTRegInfo *reg = cfg_entry->reg;
1428 uint16_t writable_mask = 0;
1429 uint16_t throughable_mask = 0;
1430 int debug_msix_enabled_old;
1431
1432 /* modify emulate register */
1433 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1434 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1435
1436 /* create value for writing to I/O device register */
1437 throughable_mask = ~reg->emu_mask & valid_mask;
1438 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1439
1440 /* update MSI-X */
1441 if ((*val & PCI_MSIX_FLAGS_ENABLE)
1442 && !(*val & PCI_MSIX_FLAGS_MASKALL)) {
1443 xen_pt_msix_update(s);
c976437c
ZD		 1444 } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {
1445 xen_pt_msix_disable(s);
3854ca57
JY		 1446 }
1447
1448 debug_msix_enabled_old = s->msix->enabled;
1449 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
1450 if (s->msix->enabled != debug_msix_enabled_old) {
1451 XEN_PT_LOG(&s->dev, "%s MSI-X\n",
1452 s->msix->enabled ? "enable" : "disable");
1453 }
1454
1455 return 0;
1456}
1457
0546b8c2 1458/* MSI-X Capability Structure reg static information table */
3854ca57
JY		 1459static XenPTRegInfo xen_pt_emu_reg_msix[] = {
1460 /* Next Pointer reg */
1461 {
1462 .offset = PCI_CAP_LIST_NEXT,
1463 .size = 1,
1464 .init_val = 0x00,
1465 .ro_mask = 0xFF,
1466 .emu_mask = 0xFF,
1467 .init = xen_pt_ptr_reg_init,
1468 .u.b.read = xen_pt_byte_reg_read,
1469 .u.b.write = xen_pt_byte_reg_write,
1470 },
1471 /* Message Control reg */
1472 {
1473 .offset = PCI_MSI_FLAGS,
1474 .size = 2,
1475 .init_val = 0x0000,
1476 .ro_mask = 0x3FFF,
1477 .emu_mask = 0x0000,
1478 .init = xen_pt_msixctrl_reg_init,
1479 .u.w.read = xen_pt_word_reg_read,
1480 .u.w.write = xen_pt_msixctrl_reg_write,
1481 },
1482 {
1483 .size = 0,
1484 },
1485};
1486
1487
93d7ae8e
AK		 1488/****************************
1489 * Capabilities
1490 */
1491
1492/* capability structure register group size functions */
1493
1494static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s,
1495 const XenPTRegGroupInfo *grp_reg,
1496 uint32_t base_offset, uint8_t *size)
1497{
1498 *size = grp_reg->grp_size;
1499 return 0;
1500}
1501/* get Vendor Specific Capability Structure register group size */
1502static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
1503 const XenPTRegGroupInfo *grp_reg,
1504 uint32_t base_offset, uint8_t *size)
1505{
1506 *size = pci_get_byte(s->dev.config + base_offset + 0x02);
1507 return 0;
1508}
1509/* get PCI Express Capability Structure register group size */
1510static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
1511 const XenPTRegGroupInfo *grp_reg,
1512 uint32_t base_offset, uint8_t *size)
1513{
1514 PCIDevice *d = &s->dev;
1515 uint8_t version = get_capability_version(s, base_offset);
1516 uint8_t type = get_device_type(s, base_offset);
1517 uint8_t pcie_size = 0;
1518
1519
1520 /* calculate size depend on capability version and device/port type */
1521 /* in case of PCI Express Base Specification Rev 1.x */
1522 if (version == 1) {
1523 /* The PCI Express Capabilities, Device Capabilities, and Device
1524 * Status/Control registers are required for all PCI Express devices.
1525 * The Link Capabilities and Link Status/Control are required for all
1526 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1527 * are not required to implement registers other than those listed
1528 * above and terminate the capability structure.
1529 */
1530 switch (type) {
1531 case PCI_EXP_TYPE_ENDPOINT:
1532 case PCI_EXP_TYPE_LEG_END:
1533 pcie_size = 0x14;
1534 break;
1535 case PCI_EXP_TYPE_RC_END:
1536 /* has no link */
1537 pcie_size = 0x0C;
1538 break;
1539 /* only EndPoint passthrough is supported */
1540 case PCI_EXP_TYPE_ROOT_PORT:
1541 case PCI_EXP_TYPE_UPSTREAM:
1542 case PCI_EXP_TYPE_DOWNSTREAM:
1543 case PCI_EXP_TYPE_PCI_BRIDGE:
1544 case PCI_EXP_TYPE_PCIE_BRIDGE:
1545 case PCI_EXP_TYPE_RC_EC:
1546 default:
1547 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1548 return -1;
1549 }
1550 }
1551 /* in case of PCI Express Base Specification Rev 2.0 */
1552 else if (version == 2) {
1553 switch (type) {
1554 case PCI_EXP_TYPE_ENDPOINT:
1555 case PCI_EXP_TYPE_LEG_END:
1556 case PCI_EXP_TYPE_RC_END:
1557 /* For Functions that do not implement the registers,
1558 * these spaces must be hardwired to 0b.
1559 */
1560 pcie_size = 0x3C;
1561 break;
1562 /* only EndPoint passthrough is supported */
1563 case PCI_EXP_TYPE_ROOT_PORT:
1564 case PCI_EXP_TYPE_UPSTREAM:
1565 case PCI_EXP_TYPE_DOWNSTREAM:
1566 case PCI_EXP_TYPE_PCI_BRIDGE:
1567 case PCI_EXP_TYPE_PCIE_BRIDGE:
1568 case PCI_EXP_TYPE_RC_EC:
1569 default:
1570 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1571 return -1;
1572 }
1573 } else {
1574 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version);
1575 return -1;
1576 }
1577
1578 *size = pcie_size;
1579 return 0;
1580}
3854ca57
JY		 1581/* get MSI Capability Structure register group size */
1582static int xen_pt_msi_size_init(XenPCIPassthroughState *s,
1583 const XenPTRegGroupInfo *grp_reg,
1584 uint32_t base_offset, uint8_t *size)
1585{
1586 PCIDevice *d = &s->dev;
1587 uint16_t msg_ctrl = 0;
1588 uint8_t msi_size = 0xa;
1589
1590 msg_ctrl = pci_get_word(d->config + (base_offset + PCI_MSI_FLAGS));
1591
1592 /* check if 64-bit address is capable of per-vector masking */
1593 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) {
1594 msi_size += 4;
1595 }
1596 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) {
1597 msi_size += 10;
1598 }
1599
1600 s->msi = g_new0(XenPTMSI, 1);
1601 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
1602
1603 *size = msi_size;
1604 return 0;
1605}
1606/* get MSI-X Capability Structure register group size */
1607static int xen_pt_msix_size_init(XenPCIPassthroughState *s,
1608 const XenPTRegGroupInfo *grp_reg,
1609 uint32_t base_offset, uint8_t *size)
1610{
1611 int rc = 0;
1612
1613 rc = xen_pt_msix_init(s, base_offset);
1614
1615 if (rc < 0) {
1616 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n");
1617 return rc;
1618 }
1619
1620 *size = grp_reg->grp_size;
1621 return 0;
1622}
1623
93d7ae8e
AK		 1624
1625static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
1626 /* Header Type0 reg group */
1627 {
1628 .grp_id = 0xFF,
1629 .grp_type = XEN_PT_GRP_TYPE_EMU,
1630 .grp_size = 0x40,
1631 .size_init = xen_pt_reg_grp_size_init,
1632 .emu_regs = xen_pt_emu_reg_header0,
1633 },
1634 /* PCI PowerManagement Capability reg group */
1635 {
1636 .grp_id = PCI_CAP_ID_PM,
1637 .grp_type = XEN_PT_GRP_TYPE_EMU,
1638 .grp_size = PCI_PM_SIZEOF,
1639 .size_init = xen_pt_reg_grp_size_init,
1640 .emu_regs = xen_pt_emu_reg_pm,
1641 },
1642 /* AGP Capability Structure reg group */
1643 {
1644 .grp_id = PCI_CAP_ID_AGP,
1645 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1646 .grp_size = 0x30,
1647 .size_init = xen_pt_reg_grp_size_init,
1648 },
1649 /* Vital Product Data Capability Structure reg group */
1650 {
1651 .grp_id = PCI_CAP_ID_VPD,
1652 .grp_type = XEN_PT_GRP_TYPE_EMU,
1653 .grp_size = 0x08,
1654 .size_init = xen_pt_reg_grp_size_init,
1655 .emu_regs = xen_pt_emu_reg_vpd,
1656 },
1657 /* Slot Identification reg group */
1658 {
1659 .grp_id = PCI_CAP_ID_SLOTID,
1660 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1661 .grp_size = 0x04,
1662 .size_init = xen_pt_reg_grp_size_init,
1663 },
3854ca57
JY		 1664 /* MSI Capability Structure reg group */
1665 {
1666 .grp_id = PCI_CAP_ID_MSI,
1667 .grp_type = XEN_PT_GRP_TYPE_EMU,
1668 .grp_size = 0xFF,
1669 .size_init = xen_pt_msi_size_init,
1670 .emu_regs = xen_pt_emu_reg_msi,
1671 },
93d7ae8e
AK		 1672 /* PCI-X Capabilities List Item reg group */
1673 {
1674 .grp_id = PCI_CAP_ID_PCIX,
1675 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1676 .grp_size = 0x18,
1677 .size_init = xen_pt_reg_grp_size_init,
1678 },
1679 /* Vendor Specific Capability Structure reg group */
1680 {
1681 .grp_id = PCI_CAP_ID_VNDR,
1682 .grp_type = XEN_PT_GRP_TYPE_EMU,
1683 .grp_size = 0xFF,
1684 .size_init = xen_pt_vendor_size_init,
1685 .emu_regs = xen_pt_emu_reg_vendor,
1686 },
1687 /* SHPC Capability List Item reg group */
1688 {
1689 .grp_id = PCI_CAP_ID_SHPC,
1690 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1691 .grp_size = 0x08,
1692 .size_init = xen_pt_reg_grp_size_init,
1693 },
1694 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1695 {
1696 .grp_id = PCI_CAP_ID_SSVID,
1697 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1698 .grp_size = 0x08,
1699 .size_init = xen_pt_reg_grp_size_init,
1700 },
1701 /* AGP 8x Capability Structure reg group */
1702 {
1703 .grp_id = PCI_CAP_ID_AGP3,
1704 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1705 .grp_size = 0x30,
1706 .size_init = xen_pt_reg_grp_size_init,
1707 },
1708 /* PCI Express Capability Structure reg group */
1709 {
1710 .grp_id = PCI_CAP_ID_EXP,
1711 .grp_type = XEN_PT_GRP_TYPE_EMU,
1712 .grp_size = 0xFF,
1713 .size_init = xen_pt_pcie_size_init,
1714 .emu_regs = xen_pt_emu_reg_pcie,
1715 },
3854ca57
JY		 1716 /* MSI-X Capability Structure reg group */
1717 {
1718 .grp_id = PCI_CAP_ID_MSIX,
1719 .grp_type = XEN_PT_GRP_TYPE_EMU,
1720 .grp_size = 0x0C,
1721 .size_init = xen_pt_msix_size_init,
1722 .emu_regs = xen_pt_emu_reg_msix,
1723 },
93d7ae8e
AK		 1724 {
1725 .grp_size = 0,
1726 },
1727};
1728
1729/* initialize Capabilities Pointer or Next Pointer register */
1730static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s,
1731 XenPTRegInfo *reg, uint32_t real_offset,
1732 uint32_t *data)
1733{
1734 int i;
1735 uint8_t *config = s->dev.config;
1736 uint32_t reg_field = pci_get_byte(config + real_offset);
1737 uint8_t cap_id = 0;
1738
1739 /* find capability offset */
1740 while (reg_field) {
1741 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1742 if (xen_pt_hide_dev_cap(&s->real_device,
1743 xen_pt_emu_reg_grps[i].grp_id)) {
1744 continue;
1745 }
1746
1747 cap_id = pci_get_byte(config + reg_field + PCI_CAP_LIST_ID);
1748 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) {
1749 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1750 goto out;
1751 }
1752 /* ignore the 0 hardwired capability, find next one */
1753 break;
1754 }
1755 }
1756
1757 /* next capability */
1758 reg_field = pci_get_byte(config + reg_field + PCI_CAP_LIST_NEXT);
1759 }
1760
1761out:
1762 *data = reg_field;
1763 return 0;
1764}
1765
1766
1767/*************
1768 * Main
1769 */
1770
1771static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap)
1772{
1773 uint8_t id;
1774 unsigned max_cap = PCI_CAP_MAX;
1775 uint8_t pos = PCI_CAPABILITY_LIST;
1776 uint8_t status = 0;
1777
1778 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) {
1779 return 0;
1780 }
1781 if ((status & PCI_STATUS_CAP_LIST) == 0) {
1782 return 0;
1783 }
1784
1785 while (max_cap--) {
1786 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) {
1787 break;
1788 }
1789 if (pos < PCI_CONFIG_HEADER_SIZE) {
1790 break;
1791 }
1792
1793 pos &= ~3;
1794 if (xen_host_pci_get_byte(&s->real_device,
1795 pos + PCI_CAP_LIST_ID, &id)) {
1796 break;
1797 }
1798
1799 if (id == 0xff) {
1800 break;
1801 }
1802 if (id == cap) {
1803 return pos;
1804 }
1805
1806 pos += PCI_CAP_LIST_NEXT;
1807 }
1808 return 0;
1809}
1810
1811static int xen_pt_config_reg_init(XenPCIPassthroughState *s,
1812 XenPTRegGroup *reg_grp, XenPTRegInfo *reg)
1813{
1814 XenPTReg *reg_entry;
1815 uint32_t data = 0;
1816 int rc = 0;
1817
1818 reg_entry = g_new0(XenPTReg, 1);
1819 reg_entry->reg = reg;
1820
1821 if (reg->init) {
1822 /* initialize emulate register */
1823 rc = reg->init(s, reg_entry->reg,
1824 reg_grp->base_offset + reg->offset, &data);
1825 if (rc < 0) {
c5633d99 1826 g_free(reg_entry);
93d7ae8e
AK		 1827 return rc;
1828 }
1829 if (data == XEN_PT_INVALID_REG) {
1830 /* free unused BAR register entry */
c5633d99 1831 g_free(reg_entry);
93d7ae8e
AK		 1832 return 0;
1833 }
1834 /* set register value */
1835 reg_entry->data = data;
1836 }
1837 /* list add register entry */
1838 QLIST_INSERT_HEAD(&reg_grp->reg_tbl_list, reg_entry, entries);
1839
1840 return 0;
1841}
1842
1843int xen_pt_config_init(XenPCIPassthroughState *s)
1844{
1845 int i, rc;
1846
1847 QLIST_INIT(&s->reg_grps);
1848
1849 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1850 uint32_t reg_grp_offset = 0;
1851 XenPTRegGroup *reg_grp_entry = NULL;
1852
1853 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF) {
1854 if (xen_pt_hide_dev_cap(&s->real_device,
1855 xen_pt_emu_reg_grps[i].grp_id)) {
1856 continue;
1857 }
1858
1859 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id);
1860
1861 if (!reg_grp_offset) {
1862 continue;
1863 }
1864 }
1865
1866 reg_grp_entry = g_new0(XenPTRegGroup, 1);
1867 QLIST_INIT(&reg_grp_entry->reg_tbl_list);
1868 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
1869
1870 reg_grp_entry->base_offset = reg_grp_offset;
1871 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i;
1872 if (xen_pt_emu_reg_grps[i].size_init) {
1873 /* get register group size */
1874 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp,
1875 reg_grp_offset,
1876 &reg_grp_entry->size);
1877 if (rc < 0) {
1878 xen_pt_config_delete(s);
1879 return rc;
1880 }
1881 }
1882
1883 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1884 if (xen_pt_emu_reg_grps[i].emu_regs) {
1885 int j = 0;
1886 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs;
1887 /* initialize capability register */
1888 for (j = 0; regs->size != 0; j++, regs++) {
1889 /* initialize capability register */
1890 rc = xen_pt_config_reg_init(s, reg_grp_entry, regs);
1891 if (rc < 0) {
1892 xen_pt_config_delete(s);
1893 return rc;
1894 }
1895 }
1896 }
1897 }
1898 }
1899
1900 return 0;
1901}
1902
1903/* delete all emulate register */
1904void xen_pt_config_delete(XenPCIPassthroughState *s)
1905{
1906 struct XenPTRegGroup *reg_group, *next_grp;
1907 struct XenPTReg *reg, *next_reg;
1908
3854ca57
JY		 1909 /* free MSI/MSI-X info table */
1910 if (s->msix) {
1911 xen_pt_msix_delete(s);
1912 }
1913 if (s->msi) {
1914 g_free(s->msi);
1915 }
1916
93d7ae8e
AK		 1917 /* free all register group entry */
1918 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) {
1919 /* free all register entry */
1920 QLIST_FOREACH_SAFE(reg, &reg_group->reg_tbl_list, entries, next_reg) {
1921 QLIST_REMOVE(reg, entries);
1922 g_free(reg);
1923 }
1924
1925 QLIST_REMOVE(reg_group, entries);
1926 g_free(reg_group);
1927 }
1928}
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