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xen/pt: mark all PCIe capability bits read-only
[qemu.git] / hw / xen / xen_pt_config_init.c
CommitLineData
93d7ae8e
AK		 1/*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <[email protected]>
9 * Allen Kay <[email protected]>
10 * Guy Zana <[email protected]>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
1de7afc9 15#include "qemu/timer.h"
0d09e41a 16#include "hw/xen/xen_backend.h"
47b43a1f 17#include "xen_pt.h"
eaab4d60 18
93d7ae8e
AK		 19#define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
21
22#define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
23
24/* prototype */
25
26static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
27 uint32_t real_offset, uint32_t *data);
28
29
30/* helper */
31
32/* A return value of 1 means the capability should NOT be exposed to guest. */
33static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id)
34{
35 switch (grp_id) {
36 case PCI_CAP_ID_EXP:
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
40 *
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
43 *
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
49 */
50 if (d->vendor_id == PCI_VENDOR_ID_INTEL &&
51 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) {
52 return 1;
53 }
54 break;
55 }
56 return 0;
57}
58
59/* find emulate register group entry */
eaab4d60
AK		 60XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address)
61{
93d7ae8e
AK		 62 XenPTRegGroup *entry = NULL;
63
64 /* find register group entry */
65 QLIST_FOREACH(entry, &s->reg_grps, entries) {
66 /* check address */
67 if ((entry->base_offset <= address)
68 && ((entry->base_offset + entry->size) > address)) {
69 return entry;
70 }
71 }
72
73 /* group entry not found */
eaab4d60
AK		 74 return NULL;
75}
76
93d7ae8e 77/* find emulate register entry */
eaab4d60
AK		 78XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address)
79{
93d7ae8e
AK		 80 XenPTReg *reg_entry = NULL;
81 XenPTRegInfo *reg = NULL;
82 uint32_t real_offset = 0;
83
84 /* find register entry */
85 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) {
86 reg = reg_entry->reg;
87 real_offset = reg_grp->base_offset + reg->offset;
88 /* check address */
89 if ((real_offset <= address)
90 && ((real_offset + reg->size) > address)) {
91 return reg_entry;
92 }
93 }
94
eaab4d60
AK		 95 return NULL;
96}
93d7ae8e 97
0e7ef221
JB		 98static uint32_t get_throughable_mask(const XenPCIPassthroughState *s,
99 const XenPTRegInfo *reg,
100 uint32_t valid_mask)
101{
102 uint32_t throughable_mask = ~(reg->emu_mask | reg->ro_mask);
103
104 return throughable_mask & valid_mask;
105}
93d7ae8e
AK		 106
107/****************
108 * general register functions
109 */
110
111/* register initialization function */
112
113static int xen_pt_common_reg_init(XenPCIPassthroughState *s,
114 XenPTRegInfo *reg, uint32_t real_offset,
115 uint32_t *data)
116{
117 *data = reg->init_val;
118 return 0;
119}
120
121/* Read register functions */
122
123static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
124 uint8_t *value, uint8_t valid_mask)
125{
126 XenPTRegInfo *reg = cfg_entry->reg;
127 uint8_t valid_emu_mask = 0;
128
129 /* emulate byte register */
130 valid_emu_mask = reg->emu_mask & valid_mask;
131 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
132
133 return 0;
134}
135static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
136 uint16_t *value, uint16_t valid_mask)
137{
138 XenPTRegInfo *reg = cfg_entry->reg;
139 uint16_t valid_emu_mask = 0;
140
141 /* emulate word register */
142 valid_emu_mask = reg->emu_mask & valid_mask;
143 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
144
145 return 0;
146}
147static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
148 uint32_t *value, uint32_t valid_mask)
149{
150 XenPTRegInfo *reg = cfg_entry->reg;
151 uint32_t valid_emu_mask = 0;
152
153 /* emulate long register */
154 valid_emu_mask = reg->emu_mask & valid_mask;
155 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
156
157 return 0;
158}
159
160/* Write register functions */
161
162static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
163 uint8_t *val, uint8_t dev_value,
164 uint8_t valid_mask)
165{
166 XenPTRegInfo *reg = cfg_entry->reg;
167 uint8_t writable_mask = 0;
0e7ef221 168 uint8_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 169
170 /* modify emulate register */
171 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
172 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
173
174 /* create value for writing to I/O device register */
93d7ae8e
AK		 175 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
176
177 return 0;
178}
179static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
180 uint16_t *val, uint16_t dev_value,
181 uint16_t valid_mask)
182{
183 XenPTRegInfo *reg = cfg_entry->reg;
184 uint16_t writable_mask = 0;
0e7ef221 185 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 186
187 /* modify emulate register */
188 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
189 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
190
191 /* create value for writing to I/O device register */
93d7ae8e
AK		 192 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
193
194 return 0;
195}
196static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
197 uint32_t *val, uint32_t dev_value,
198 uint32_t valid_mask)
199{
200 XenPTRegInfo *reg = cfg_entry->reg;
201 uint32_t writable_mask = 0;
0e7ef221 202 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 203
204 /* modify emulate register */
205 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
206 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
207
208 /* create value for writing to I/O device register */
93d7ae8e
AK		 209 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
210
211 return 0;
212}
213
214
215/* XenPTRegInfo declaration
216 * - only for emulated register (either a part or whole bit).
217 * - for passthrough register that need special behavior (like interacting with
218 * other component), set emu_mask to all 0 and specify r/w func properly.
219 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
220 */
221
222/********************
223 * Header Type0
224 */
225
226static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s,
227 XenPTRegInfo *reg, uint32_t real_offset,
228 uint32_t *data)
229{
230 *data = s->real_device.vendor_id;
231 return 0;
232}
233static int xen_pt_device_reg_init(XenPCIPassthroughState *s,
234 XenPTRegInfo *reg, uint32_t real_offset,
235 uint32_t *data)
236{
237 *data = s->real_device.device_id;
238 return 0;
239}
240static int xen_pt_status_reg_init(XenPCIPassthroughState *s,
241 XenPTRegInfo *reg, uint32_t real_offset,
242 uint32_t *data)
243{
244 XenPTRegGroup *reg_grp_entry = NULL;
245 XenPTReg *reg_entry = NULL;
246 uint32_t reg_field = 0;
247
248 /* find Header register group */
249 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST);
250 if (reg_grp_entry) {
251 /* find Capabilities Pointer register */
252 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
253 if (reg_entry) {
254 /* check Capabilities Pointer register */
255 if (reg_entry->data) {
256 reg_field |= PCI_STATUS_CAP_LIST;
257 } else {
258 reg_field &= ~PCI_STATUS_CAP_LIST;
259 }
260 } else {
261 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
262 " for Capabilities Pointer register."
263 " (%s)\n", __func__);
264 return -1;
265 }
266 } else {
267 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
268 " for Header. (%s)\n", __func__);
269 return -1;
270 }
271
272 *data = reg_field;
273 return 0;
274}
275static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s,
276 XenPTRegInfo *reg, uint32_t real_offset,
277 uint32_t *data)
278{
279 /* read PCI_HEADER_TYPE */
280 *data = reg->init_val | 0x80;
281 return 0;
282}
283
284/* initialize Interrupt Pin register */
285static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s,
286 XenPTRegInfo *reg, uint32_t real_offset,
287 uint32_t *data)
288{
289 *data = xen_pt_pci_read_intx(s);
290 return 0;
291}
292
293/* Command register */
93d7ae8e
AK		 294static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
295 uint16_t *val, uint16_t dev_value,
296 uint16_t valid_mask)
297{
298 XenPTRegInfo *reg = cfg_entry->reg;
299 uint16_t writable_mask = 0;
0e7ef221 300 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e
AK		 301
302 /* modify emulate register */
303 writable_mask = ~reg->ro_mask & valid_mask;
304 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
305
306 /* create value for writing to I/O device register */
93d7ae8e
AK		 307 if (*val & PCI_COMMAND_INTX_DISABLE) {
308 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
309 } else {
310 if (s->machine_irq) {
311 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
312 }
313 }
314
315 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
316
317 return 0;
318}
319
320/* BAR */
321#define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
322#define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
323#define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
324#define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
325
aabc8530
XH		 326static bool is_64bit_bar(PCIIORegion *r)
327{
328 return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
329}
330
331static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
332{
333 if (is_64bit_bar(r)) {
334 uint64_t size64;
335 size64 = (r + 1)->size;
336 size64 <<= 32;
337 size64 += r->size;
338 return size64;
339 }
340 return r->size;
341}
342
93d7ae8e 343static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
d4cd4502 344 int index)
93d7ae8e
AK		 345{
346 PCIDevice *d = &s->dev;
347 XenPTRegion *region = NULL;
348 PCIIORegion *r;
93d7ae8e
AK		 349
350 /* check 64bit BAR */
93d7ae8e
AK		 351 if ((0 < index) && (index < PCI_ROM_SLOT)) {
352 int type = s->real_device.io_regions[index - 1].type;
353
354 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM)
355 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) {
356 region = &s->bases[index - 1];
357 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) {
358 return XEN_PT_BAR_FLAG_UPPER;
359 }
360 }
361 }
362
363 /* check unused BAR */
364 r = &d->io_regions[index];
aabc8530 365 if (!xen_pt_get_bar_size(r)) {
93d7ae8e
AK		 366 return XEN_PT_BAR_FLAG_UNUSED;
367 }
368
369 /* for ExpROM BAR */
370 if (index == PCI_ROM_SLOT) {
371 return XEN_PT_BAR_FLAG_MEM;
372 }
373
374 /* check BAR I/O indicator */
375 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) {
376 return XEN_PT_BAR_FLAG_IO;
377 } else {
378 return XEN_PT_BAR_FLAG_MEM;
379 }
380}
381
382static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr)
383{
384 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) {
385 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK);
386 } else {
387 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK);
388 }
389}
390
391static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
392 uint32_t real_offset, uint32_t *data)
393{
394 uint32_t reg_field = 0;
395 int index;
396
397 index = xen_pt_bar_offset_to_index(reg->offset);
398 if (index < 0 || index >= PCI_NUM_REGIONS) {
399 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
400 return -1;
401 }
402
403 /* set BAR flag */
d4cd4502 404 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, index);
93d7ae8e
AK		 405 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) {
406 reg_field = XEN_PT_INVALID_REG;
407 }
408
409 *data = reg_field;
410 return 0;
411}
412static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
413 uint32_t *value, uint32_t valid_mask)
414{
415 XenPTRegInfo *reg = cfg_entry->reg;
416 uint32_t valid_emu_mask = 0;
417 uint32_t bar_emu_mask = 0;
418 int index;
419
420 /* get BAR index */
421 index = xen_pt_bar_offset_to_index(reg->offset);
14cec170 422 if (index < 0 || index >= PCI_NUM_REGIONS - 1) {
93d7ae8e
AK		 423 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
424 return -1;
425 }
426
427 /* use fixed-up value from kernel sysfs */
428 *value = base_address_with_flags(&s->real_device.io_regions[index]);
429
430 /* set emulate mask depend on BAR flag */
431 switch (s->bases[index].bar_flag) {
432 case XEN_PT_BAR_FLAG_MEM:
433 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
434 break;
435 case XEN_PT_BAR_FLAG_IO:
436 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
437 break;
438 case XEN_PT_BAR_FLAG_UPPER:
439 bar_emu_mask = XEN_PT_BAR_ALLF;
440 break;
441 default:
442 break;
443 }
444
445 /* emulate BAR */
446 valid_emu_mask = bar_emu_mask & valid_mask;
447 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
448
449 return 0;
450}
451static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
452 uint32_t *val, uint32_t dev_value,
453 uint32_t valid_mask)
454{
455 XenPTRegInfo *reg = cfg_entry->reg;
456 XenPTRegion *base = NULL;
457 PCIDevice *d = &s->dev;
458 const PCIIORegion *r;
459 uint32_t writable_mask = 0;
93d7ae8e
AK		 460 uint32_t bar_emu_mask = 0;
461 uint32_t bar_ro_mask = 0;
462 uint32_t r_size = 0;
463 int index = 0;
464
465 index = xen_pt_bar_offset_to_index(reg->offset);
466 if (index < 0 || index >= PCI_NUM_REGIONS) {
467 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index);
468 return -1;
469 }
470
471 r = &d->io_regions[index];
472 base = &s->bases[index];
473 r_size = xen_pt_get_emul_size(base->bar_flag, r->size);
474
475 /* set emulate mask and read-only mask values depend on the BAR flag */
476 switch (s->bases[index].bar_flag) {
477 case XEN_PT_BAR_FLAG_MEM:
478 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
aabc8530
XH		 479 if (!r_size) {
480 /* low 32 bits mask for 64 bit bars */
481 bar_ro_mask = XEN_PT_BAR_ALLF;
482 } else {
483 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
484 }
93d7ae8e
AK		 485 break;
486 case XEN_PT_BAR_FLAG_IO:
487 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
488 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1);
489 break;
490 case XEN_PT_BAR_FLAG_UPPER:
491 bar_emu_mask = XEN_PT_BAR_ALLF;
aabc8530 492 bar_ro_mask = r_size ? r_size - 1 : 0;
93d7ae8e
AK		 493 break;
494 default:
495 break;
496 }
497
498 /* modify emulate register */
499 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
500 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
501
502 /* check whether we need to update the virtual region address or not */
503 switch (s->bases[index].bar_flag) {
aabc8530 504 case XEN_PT_BAR_FLAG_UPPER:
93d7ae8e
AK		 505 case XEN_PT_BAR_FLAG_MEM:
506 /* nothing to do */
507 break;
508 case XEN_PT_BAR_FLAG_IO:
509 /* nothing to do */
510 break;
93d7ae8e
AK		 511 default:
512 break;
513 }
514
515 /* create value for writing to I/O device register */
0e7ef221 516 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
93d7ae8e
AK		 517
518 return 0;
519}
520
521/* write Exp ROM BAR */
522static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
523 XenPTReg *cfg_entry, uint32_t *val,
524 uint32_t dev_value, uint32_t valid_mask)
525{
526 XenPTRegInfo *reg = cfg_entry->reg;
527 XenPTRegion *base = NULL;
528 PCIDevice *d = (PCIDevice *)&s->dev;
529 uint32_t writable_mask = 0;
0e7ef221 530 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e 531 pcibus_t r_size = 0;
93d7ae8e
AK		 532 uint32_t bar_ro_mask = 0;
533
534 r_size = d->io_regions[PCI_ROM_SLOT].size;
535 base = &s->bases[PCI_ROM_SLOT];
536 /* align memory type resource size */
537 r_size = xen_pt_get_emul_size(base->bar_flag, r_size);
538
539 /* set emulate mask and read-only mask */
93d7ae8e
AK		 540 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;
541
542 /* modify emulate register */
543 writable_mask = ~bar_ro_mask & valid_mask;
544 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
545
546 /* create value for writing to I/O device register */
93d7ae8e
AK		 547 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
548
549 return 0;
550}
551
0546b8c2 552/* Header Type0 reg static information table */
93d7ae8e
AK		 553static XenPTRegInfo xen_pt_emu_reg_header0[] = {
554 /* Vendor ID reg */
555 {
556 .offset = PCI_VENDOR_ID,
557 .size = 2,
558 .init_val = 0x0000,
559 .ro_mask = 0xFFFF,
560 .emu_mask = 0xFFFF,
561 .init = xen_pt_vendor_reg_init,
562 .u.w.read = xen_pt_word_reg_read,
563 .u.w.write = xen_pt_word_reg_write,
564 },
565 /* Device ID reg */
566 {
567 .offset = PCI_DEVICE_ID,
568 .size = 2,
569 .init_val = 0x0000,
570 .ro_mask = 0xFFFF,
571 .emu_mask = 0xFFFF,
572 .init = xen_pt_device_reg_init,
573 .u.w.read = xen_pt_word_reg_read,
574 .u.w.write = xen_pt_word_reg_write,
575 },
576 /* Command reg */
577 {
578 .offset = PCI_COMMAND,
579 .size = 2,
580 .init_val = 0x0000,
581 .ro_mask = 0xF880,
81b23ef8 582 .emu_mask = 0x0743,
93d7ae8e 583 .init = xen_pt_common_reg_init,
81b23ef8 584 .u.w.read = xen_pt_word_reg_read,
93d7ae8e
AK		 585 .u.w.write = xen_pt_cmd_reg_write,
586 },
587 /* Capabilities Pointer reg */
588 {
589 .offset = PCI_CAPABILITY_LIST,
590 .size = 1,
591 .init_val = 0x00,
592 .ro_mask = 0xFF,
593 .emu_mask = 0xFF,
594 .init = xen_pt_ptr_reg_init,
595 .u.b.read = xen_pt_byte_reg_read,
596 .u.b.write = xen_pt_byte_reg_write,
597 },
598 /* Status reg */
599 /* use emulated Cap Ptr value to initialize,
600 * so need to be declared after Cap Ptr reg
601 */
602 {
603 .offset = PCI_STATUS,
604 .size = 2,
605 .init_val = 0x0000,
606 .ro_mask = 0x06FF,
607 .emu_mask = 0x0010,
608 .init = xen_pt_status_reg_init,
609 .u.w.read = xen_pt_word_reg_read,
610 .u.w.write = xen_pt_word_reg_write,
611 },
612 /* Cache Line Size reg */
613 {
614 .offset = PCI_CACHE_LINE_SIZE,
615 .size = 1,
616 .init_val = 0x00,
617 .ro_mask = 0x00,
618 .emu_mask = 0xFF,
619 .init = xen_pt_common_reg_init,
620 .u.b.read = xen_pt_byte_reg_read,
621 .u.b.write = xen_pt_byte_reg_write,
622 },
623 /* Latency Timer reg */
624 {
625 .offset = PCI_LATENCY_TIMER,
626 .size = 1,
627 .init_val = 0x00,
628 .ro_mask = 0x00,
629 .emu_mask = 0xFF,
630 .init = xen_pt_common_reg_init,
631 .u.b.read = xen_pt_byte_reg_read,
632 .u.b.write = xen_pt_byte_reg_write,
633 },
634 /* Header Type reg */
635 {
636 .offset = PCI_HEADER_TYPE,
637 .size = 1,
638 .init_val = 0x00,
639 .ro_mask = 0xFF,
640 .emu_mask = 0x00,
641 .init = xen_pt_header_type_reg_init,
642 .u.b.read = xen_pt_byte_reg_read,
643 .u.b.write = xen_pt_byte_reg_write,
644 },
645 /* Interrupt Line reg */
646 {
647 .offset = PCI_INTERRUPT_LINE,
648 .size = 1,
649 .init_val = 0x00,
650 .ro_mask = 0x00,
651 .emu_mask = 0xFF,
652 .init = xen_pt_common_reg_init,
653 .u.b.read = xen_pt_byte_reg_read,
654 .u.b.write = xen_pt_byte_reg_write,
655 },
656 /* Interrupt Pin reg */
657 {
658 .offset = PCI_INTERRUPT_PIN,
659 .size = 1,
660 .init_val = 0x00,
661 .ro_mask = 0xFF,
662 .emu_mask = 0xFF,
663 .init = xen_pt_irqpin_reg_init,
664 .u.b.read = xen_pt_byte_reg_read,
665 .u.b.write = xen_pt_byte_reg_write,
666 },
667 /* BAR 0 reg */
668 /* mask of BAR need to be decided later, depends on IO/MEM type */
669 {
670 .offset = PCI_BASE_ADDRESS_0,
671 .size = 4,
672 .init_val = 0x00000000,
673 .init = xen_pt_bar_reg_init,
674 .u.dw.read = xen_pt_bar_reg_read,
675 .u.dw.write = xen_pt_bar_reg_write,
676 },
677 /* BAR 1 reg */
678 {
679 .offset = PCI_BASE_ADDRESS_1,
680 .size = 4,
681 .init_val = 0x00000000,
682 .init = xen_pt_bar_reg_init,
683 .u.dw.read = xen_pt_bar_reg_read,
684 .u.dw.write = xen_pt_bar_reg_write,
685 },
686 /* BAR 2 reg */
687 {
688 .offset = PCI_BASE_ADDRESS_2,
689 .size = 4,
690 .init_val = 0x00000000,
691 .init = xen_pt_bar_reg_init,
692 .u.dw.read = xen_pt_bar_reg_read,
693 .u.dw.write = xen_pt_bar_reg_write,
694 },
695 /* BAR 3 reg */
696 {
697 .offset = PCI_BASE_ADDRESS_3,
698 .size = 4,
699 .init_val = 0x00000000,
700 .init = xen_pt_bar_reg_init,
701 .u.dw.read = xen_pt_bar_reg_read,
702 .u.dw.write = xen_pt_bar_reg_write,
703 },
704 /* BAR 4 reg */
705 {
706 .offset = PCI_BASE_ADDRESS_4,
707 .size = 4,
708 .init_val = 0x00000000,
709 .init = xen_pt_bar_reg_init,
710 .u.dw.read = xen_pt_bar_reg_read,
711 .u.dw.write = xen_pt_bar_reg_write,
712 },
713 /* BAR 5 reg */
714 {
715 .offset = PCI_BASE_ADDRESS_5,
716 .size = 4,
717 .init_val = 0x00000000,
718 .init = xen_pt_bar_reg_init,
719 .u.dw.read = xen_pt_bar_reg_read,
720 .u.dw.write = xen_pt_bar_reg_write,
721 },
722 /* Expansion ROM BAR reg */
723 {
724 .offset = PCI_ROM_ADDRESS,
725 .size = 4,
726 .init_val = 0x00000000,
727 .ro_mask = 0x000007FE,
728 .emu_mask = 0xFFFFF800,
729 .init = xen_pt_bar_reg_init,
730 .u.dw.read = xen_pt_long_reg_read,
731 .u.dw.write = xen_pt_exp_rom_bar_reg_write,
732 },
733 {
734 .size = 0,
735 },
736};
737
738
739/*********************************
740 * Vital Product Data Capability
741 */
742
0546b8c2 743/* Vital Product Data Capability Structure reg static information table */
93d7ae8e
AK		 744static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
745 {
746 .offset = PCI_CAP_LIST_NEXT,
747 .size = 1,
748 .init_val = 0x00,
749 .ro_mask = 0xFF,
750 .emu_mask = 0xFF,
751 .init = xen_pt_ptr_reg_init,
752 .u.b.read = xen_pt_byte_reg_read,
753 .u.b.write = xen_pt_byte_reg_write,
754 },
755 {
756 .size = 0,
757 },
758};
759
760
761/**************************************
762 * Vendor Specific Capability
763 */
764
0546b8c2 765/* Vendor Specific Capability Structure reg static information table */
93d7ae8e
AK		 766static XenPTRegInfo xen_pt_emu_reg_vendor[] = {
767 {
768 .offset = PCI_CAP_LIST_NEXT,
769 .size = 1,
770 .init_val = 0x00,
771 .ro_mask = 0xFF,
772 .emu_mask = 0xFF,
773 .init = xen_pt_ptr_reg_init,
774 .u.b.read = xen_pt_byte_reg_read,
775 .u.b.write = xen_pt_byte_reg_write,
776 },
777 {
778 .size = 0,
779 },
780};
781
782
783/*****************************
784 * PCI Express Capability
785 */
786
787static inline uint8_t get_capability_version(XenPCIPassthroughState *s,
788 uint32_t offset)
789{
790 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
791 return flags & PCI_EXP_FLAGS_VERS;
792}
793
794static inline uint8_t get_device_type(XenPCIPassthroughState *s,
795 uint32_t offset)
796{
797 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
798 return (flags & PCI_EXP_FLAGS_TYPE) >> 4;
799}
800
801/* initialize Link Control register */
802static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s,
803 XenPTRegInfo *reg, uint32_t real_offset,
804 uint32_t *data)
805{
806 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
807 uint8_t dev_type = get_device_type(s, real_offset - reg->offset);
808
809 /* no need to initialize in case of Root Complex Integrated Endpoint
810 * with cap_ver 1.x
811 */
812 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) {
813 *data = XEN_PT_INVALID_REG;
814 }
815
816 *data = reg->init_val;
817 return 0;
818}
819/* initialize Device Control 2 register */
820static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s,
821 XenPTRegInfo *reg, uint32_t real_offset,
822 uint32_t *data)
823{
824 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
825
826 /* no need to initialize in case of cap_ver 1.x */
827 if (cap_ver == 1) {
828 *data = XEN_PT_INVALID_REG;
829 }
830
831 *data = reg->init_val;
832 return 0;
833}
834/* initialize Link Control 2 register */
835static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s,
836 XenPTRegInfo *reg, uint32_t real_offset,
837 uint32_t *data)
838{
839 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
840 uint32_t reg_field = 0;
841
842 /* no need to initialize in case of cap_ver 1.x */
843 if (cap_ver == 1) {
844 reg_field = XEN_PT_INVALID_REG;
845 } else {
846 /* set Supported Link Speed */
847 uint8_t lnkcap = pci_get_byte(s->dev.config + real_offset - reg->offset
848 + PCI_EXP_LNKCAP);
849 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap;
850 }
851
852 *data = reg_field;
853 return 0;
854}
855
0546b8c2 856/* PCI Express Capability Structure reg static information table */
93d7ae8e
AK		 857static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
858 /* Next Pointer reg */
859 {
860 .offset = PCI_CAP_LIST_NEXT,
861 .size = 1,
862 .init_val = 0x00,
863 .ro_mask = 0xFF,
864 .emu_mask = 0xFF,
865 .init = xen_pt_ptr_reg_init,
866 .u.b.read = xen_pt_byte_reg_read,
867 .u.b.write = xen_pt_byte_reg_write,
868 },
869 /* Device Capabilities reg */
870 {
871 .offset = PCI_EXP_DEVCAP,
872 .size = 4,
873 .init_val = 0x00000000,
45ebe391 874 .ro_mask = 0xFFFFFFFF,
93d7ae8e
AK		 875 .emu_mask = 0x10000000,
876 .init = xen_pt_common_reg_init,
877 .u.dw.read = xen_pt_long_reg_read,
878 .u.dw.write = xen_pt_long_reg_write,
879 },
880 /* Device Control reg */
881 {
882 .offset = PCI_EXP_DEVCTL,
883 .size = 2,
884 .init_val = 0x2810,
885 .ro_mask = 0x8400,
886 .emu_mask = 0xFFFF,
887 .init = xen_pt_common_reg_init,
888 .u.w.read = xen_pt_word_reg_read,
889 .u.w.write = xen_pt_word_reg_write,
890 },
891 /* Link Control reg */
892 {
893 .offset = PCI_EXP_LNKCTL,
894 .size = 2,
895 .init_val = 0x0000,
896 .ro_mask = 0xFC34,
897 .emu_mask = 0xFFFF,
898 .init = xen_pt_linkctrl_reg_init,
899 .u.w.read = xen_pt_word_reg_read,
900 .u.w.write = xen_pt_word_reg_write,
901 },
902 /* Device Control 2 reg */
903 {
904 .offset = 0x28,
905 .size = 2,
906 .init_val = 0x0000,
907 .ro_mask = 0xFFE0,
908 .emu_mask = 0xFFFF,
909 .init = xen_pt_devctrl2_reg_init,
910 .u.w.read = xen_pt_word_reg_read,
911 .u.w.write = xen_pt_word_reg_write,
912 },
913 /* Link Control 2 reg */
914 {
915 .offset = 0x30,
916 .size = 2,
917 .init_val = 0x0000,
918 .ro_mask = 0xE040,
919 .emu_mask = 0xFFFF,
920 .init = xen_pt_linkctrl2_reg_init,
921 .u.w.read = xen_pt_word_reg_read,
922 .u.w.write = xen_pt_word_reg_write,
923 },
924 {
925 .size = 0,
926 },
927};
928
929
930/*********************************
931 * Power Management Capability
932 */
933
93d7ae8e
AK		 934/* write Power Management Control/Status register */
935static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
936 XenPTReg *cfg_entry, uint16_t *val,
937 uint16_t dev_value, uint16_t valid_mask)
938{
939 XenPTRegInfo *reg = cfg_entry->reg;
93d7ae8e 940 uint16_t writable_mask = 0;
0e7ef221 941 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
93d7ae8e 942
93d7ae8e 943 /* modify emulate register */
d61bb248 944 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
93d7ae8e
AK		 945 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
946
947 /* create value for writing to I/O device register */
c4ff1e68
JB		 948 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS,
949 throughable_mask);
93d7ae8e
AK		 950
951 return 0;
952}
953
0546b8c2 954/* Power Management Capability reg static information table */
93d7ae8e
AK		 955static XenPTRegInfo xen_pt_emu_reg_pm[] = {
956 /* Next Pointer reg */
957 {
958 .offset = PCI_CAP_LIST_NEXT,
959 .size = 1,
960 .init_val = 0x00,
961 .ro_mask = 0xFF,
962 .emu_mask = 0xFF,
963 .init = xen_pt_ptr_reg_init,
964 .u.b.read = xen_pt_byte_reg_read,
965 .u.b.write = xen_pt_byte_reg_write,
966 },
967 /* Power Management Capabilities reg */
968 {
969 .offset = PCI_CAP_FLAGS,
970 .size = 2,
971 .init_val = 0x0000,
972 .ro_mask = 0xFFFF,
973 .emu_mask = 0xF9C8,
974 .init = xen_pt_common_reg_init,
975 .u.w.read = xen_pt_word_reg_read,
976 .u.w.write = xen_pt_word_reg_write,
977 },
978 /* PCI Power Management Control/Status reg */
979 {
980 .offset = PCI_PM_CTRL,
981 .size = 2,
982 .init_val = 0x0008,
983 .ro_mask = 0xE1FC,
d61bb248 984 .emu_mask = 0x810B,
93d7ae8e 985 .init = xen_pt_common_reg_init,
d61bb248 986 .u.w.read = xen_pt_word_reg_read,
93d7ae8e
AK		 987 .u.w.write = xen_pt_pmcsr_reg_write,
988 },
989 {
990 .size = 0,
991 },
992};
993
994
3854ca57
JY		 995/********************************
996 * MSI Capability
997 */
998
999/* Helper */
7611dae8
JB		 1000#define xen_pt_msi_check_type(offset, flags, what) \
1001 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1002 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
3854ca57
JY		 1003
1004/* Message Control register */
1005static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
1006 XenPTRegInfo *reg, uint32_t real_offset,
1007 uint32_t *data)
1008{
1009 PCIDevice *d = &s->dev;
1010 XenPTMSI *msi = s->msi;
1011 uint16_t reg_field = 0;
1012
1013 /* use I/O device register's value as initial value */
1014 reg_field = pci_get_word(d->config + real_offset);
1015
1016 if (reg_field & PCI_MSI_FLAGS_ENABLE) {
1017 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n");
1018 xen_host_pci_set_word(&s->real_device, real_offset,
1019 reg_field & ~PCI_MSI_FLAGS_ENABLE);
1020 }
1021 msi->flags |= reg_field;
1022 msi->ctrl_offset = real_offset;
1023 msi->initialized = false;
1024 msi->mapped = false;
1025
1026 *data = reg->init_val;
1027 return 0;
1028}
1029static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
1030 XenPTReg *cfg_entry, uint16_t *val,
1031 uint16_t dev_value, uint16_t valid_mask)
1032{
1033 XenPTRegInfo *reg = cfg_entry->reg;
1034 XenPTMSI *msi = s->msi;
1035 uint16_t writable_mask = 0;
0e7ef221 1036 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
3854ca57
JY		 1037
1038 /* Currently no support for multi-vector */
1039 if (*val & PCI_MSI_FLAGS_QSIZE) {
1040 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val);
1041 }
1042
1043 /* modify emulate register */
1044 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1045 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1046 msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE;
1047
1048 /* create value for writing to I/O device register */
3854ca57
JY		 1049 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1050
1051 /* update MSI */
d1d35cf4 1052 if (*val & PCI_MSI_FLAGS_ENABLE) {
3854ca57
JY		 1053 /* setup MSI pirq for the first time */
1054 if (!msi->initialized) {
1055 /* Init physical one */
1056 XEN_PT_LOG(&s->dev, "setup MSI\n");
1057 if (xen_pt_msi_setup(s)) {
1058 /* We do not broadcast the error to the framework code, so
1059 * that MSI errors are contained in MSI emulation code and
1060 * QEMU can go on running.
1061 * Guest MSI would be actually not working.
1062 */
1063 *val &= ~PCI_MSI_FLAGS_ENABLE;
1064 XEN_PT_WARN(&s->dev, "Can not map MSI.\n");
1065 return 0;
1066 }
1067 if (xen_pt_msi_update(s)) {
1068 *val &= ~PCI_MSI_FLAGS_ENABLE;
1069 XEN_PT_WARN(&s->dev, "Can not bind MSI\n");
1070 return 0;
1071 }
1072 msi->initialized = true;
1073 msi->mapped = true;
1074 }
1075 msi->flags |= PCI_MSI_FLAGS_ENABLE;
c976437c
ZD		 1076 } else if (msi->mapped) {
1077 xen_pt_msi_disable(s);
3854ca57
JY		 1078 }
1079
3854ca57
JY		 1080 return 0;
1081}
1082
1083/* initialize Message Upper Address register */
1084static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s,
1085 XenPTRegInfo *reg, uint32_t real_offset,
1086 uint32_t *data)
1087{
1088 /* no need to initialize in case of 32 bit type */
1089 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1090 *data = XEN_PT_INVALID_REG;
1091 } else {
1092 *data = reg->init_val;
1093 }
1094
1095 return 0;
1096}
1097/* this function will be called twice (for 32 bit and 64 bit type) */
1098/* initialize Message Data register */
1099static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
1100 XenPTRegInfo *reg, uint32_t real_offset,
1101 uint32_t *data)
1102{
1103 uint32_t flags = s->msi->flags;
1104 uint32_t offset = reg->offset;
1105
1106 /* check the offset whether matches the type or not */
7611dae8
JB		 1107 if (xen_pt_msi_check_type(offset, flags, DATA)) {
1108 *data = reg->init_val;
1109 } else {
1110 *data = XEN_PT_INVALID_REG;
1111 }
1112 return 0;
1113}
1114
1115/* this function will be called twice (for 32 bit and 64 bit type) */
1116/* initialize Mask register */
1117static int xen_pt_mask_reg_init(XenPCIPassthroughState *s,
1118 XenPTRegInfo *reg, uint32_t real_offset,
1119 uint32_t *data)
1120{
1121 uint32_t flags = s->msi->flags;
1122
1123 /* check the offset whether matches the type or not */
1124 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1125 *data = XEN_PT_INVALID_REG;
1126 } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) {
1127 *data = reg->init_val;
1128 } else {
1129 *data = XEN_PT_INVALID_REG;
1130 }
1131 return 0;
1132}
1133
1134/* this function will be called twice (for 32 bit and 64 bit type) */
1135/* initialize Pending register */
1136static int xen_pt_pending_reg_init(XenPCIPassthroughState *s,
1137 XenPTRegInfo *reg, uint32_t real_offset,
1138 uint32_t *data)
1139{
1140 uint32_t flags = s->msi->flags;
1141
1142 /* check the offset whether matches the type or not */
1143 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1144 *data = XEN_PT_INVALID_REG;
1145 } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) {
3854ca57
JY		 1146 *data = reg->init_val;
1147 } else {
1148 *data = XEN_PT_INVALID_REG;
1149 }
1150 return 0;
1151}
1152
1153/* write Message Address register */
1154static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s,
1155 XenPTReg *cfg_entry, uint32_t *val,
1156 uint32_t dev_value, uint32_t valid_mask)
1157{
1158 XenPTRegInfo *reg = cfg_entry->reg;
1159 uint32_t writable_mask = 0;
3854ca57
JY		 1160 uint32_t old_addr = cfg_entry->data;
1161
1162 /* modify emulate register */
1163 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1164 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1165 s->msi->addr_lo = cfg_entry->data;
1166
1167 /* create value for writing to I/O device register */
0e7ef221 1168 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
3854ca57
JY		 1169
1170 /* update MSI */
1171 if (cfg_entry->data != old_addr) {
1172 if (s->msi->mapped) {
1173 xen_pt_msi_update(s);
1174 }
1175 }
1176
1177 return 0;
1178}
1179/* write Message Upper Address register */
1180static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s,
1181 XenPTReg *cfg_entry, uint32_t *val,
1182 uint32_t dev_value, uint32_t valid_mask)
1183{
1184 XenPTRegInfo *reg = cfg_entry->reg;
1185 uint32_t writable_mask = 0;
3854ca57
JY		 1186 uint32_t old_addr = cfg_entry->data;
1187
1188 /* check whether the type is 64 bit or not */
1189 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1190 XEN_PT_ERR(&s->dev,
1191 "Can't write to the upper address without 64 bit support\n");
1192 return -1;
1193 }
1194
1195 /* modify emulate register */
1196 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1197 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1198 /* update the msi_info too */
1199 s->msi->addr_hi = cfg_entry->data;
1200
1201 /* create value for writing to I/O device register */
0e7ef221 1202 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
3854ca57
JY		 1203
1204 /* update MSI */
1205 if (cfg_entry->data != old_addr) {
1206 if (s->msi->mapped) {
1207 xen_pt_msi_update(s);
1208 }
1209 }
1210
1211 return 0;
1212}
1213
1214
1215/* this function will be called twice (for 32 bit and 64 bit type) */
1216/* write Message Data register */
1217static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
1218 XenPTReg *cfg_entry, uint16_t *val,
1219 uint16_t dev_value, uint16_t valid_mask)
1220{
1221 XenPTRegInfo *reg = cfg_entry->reg;
1222 XenPTMSI *msi = s->msi;
1223 uint16_t writable_mask = 0;
3854ca57
JY		 1224 uint16_t old_data = cfg_entry->data;
1225 uint32_t offset = reg->offset;
1226
1227 /* check the offset whether matches the type or not */
7611dae8 1228 if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) {
3854ca57
JY		 1229 /* exit I/O emulator */
1230 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
1231 return -1;
1232 }
1233
1234 /* modify emulate register */
1235 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1236 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1237 /* update the msi_info too */
1238 msi->data = cfg_entry->data;
1239
1240 /* create value for writing to I/O device register */
0e7ef221 1241 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0);
3854ca57
JY		 1242
1243 /* update MSI */
1244 if (cfg_entry->data != old_data) {
1245 if (msi->mapped) {
1246 xen_pt_msi_update(s);
1247 }
1248 }
1249
1250 return 0;
1251}
1252
0546b8c2 1253/* MSI Capability Structure reg static information table */
3854ca57
JY		 1254static XenPTRegInfo xen_pt_emu_reg_msi[] = {
1255 /* Next Pointer reg */
1256 {
1257 .offset = PCI_CAP_LIST_NEXT,
1258 .size = 1,
1259 .init_val = 0x00,
1260 .ro_mask = 0xFF,
1261 .emu_mask = 0xFF,
1262 .init = xen_pt_ptr_reg_init,
1263 .u.b.read = xen_pt_byte_reg_read,
1264 .u.b.write = xen_pt_byte_reg_write,
1265 },
1266 /* Message Control reg */
1267 {
1268 .offset = PCI_MSI_FLAGS,
1269 .size = 2,
1270 .init_val = 0x0000,
1271 .ro_mask = 0xFF8E,
d1d35cf4 1272 .emu_mask = 0x017E,
3854ca57
JY		 1273 .init = xen_pt_msgctrl_reg_init,
1274 .u.w.read = xen_pt_word_reg_read,
1275 .u.w.write = xen_pt_msgctrl_reg_write,
1276 },
1277 /* Message Address reg */
1278 {
1279 .offset = PCI_MSI_ADDRESS_LO,
1280 .size = 4,
1281 .init_val = 0x00000000,
1282 .ro_mask = 0x00000003,
1283 .emu_mask = 0xFFFFFFFF,
3854ca57
JY		 1284 .init = xen_pt_common_reg_init,
1285 .u.dw.read = xen_pt_long_reg_read,
1286 .u.dw.write = xen_pt_msgaddr32_reg_write,
1287 },
1288 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1289 {
1290 .offset = PCI_MSI_ADDRESS_HI,
1291 .size = 4,
1292 .init_val = 0x00000000,
1293 .ro_mask = 0x00000000,
1294 .emu_mask = 0xFFFFFFFF,
3854ca57
JY		 1295 .init = xen_pt_msgaddr64_reg_init,
1296 .u.dw.read = xen_pt_long_reg_read,
1297 .u.dw.write = xen_pt_msgaddr64_reg_write,
1298 },
1299 /* Message Data reg (16 bits of data for 32-bit devices) */
1300 {
1301 .offset = PCI_MSI_DATA_32,
1302 .size = 2,
1303 .init_val = 0x0000,
1304 .ro_mask = 0x0000,
1305 .emu_mask = 0xFFFF,
3854ca57
JY		 1306 .init = xen_pt_msgdata_reg_init,
1307 .u.w.read = xen_pt_word_reg_read,
1308 .u.w.write = xen_pt_msgdata_reg_write,
1309 },
1310 /* Message Data reg (16 bits of data for 64-bit devices) */
1311 {
1312 .offset = PCI_MSI_DATA_64,
1313 .size = 2,
1314 .init_val = 0x0000,
1315 .ro_mask = 0x0000,
1316 .emu_mask = 0xFFFF,
3854ca57
JY		 1317 .init = xen_pt_msgdata_reg_init,
1318 .u.w.read = xen_pt_word_reg_read,
1319 .u.w.write = xen_pt_msgdata_reg_write,
1320 },
7611dae8
JB		 1321 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1322 {
1323 .offset = PCI_MSI_MASK_32,
1324 .size = 4,
1325 .init_val = 0x00000000,
1326 .ro_mask = 0xFFFFFFFF,
1327 .emu_mask = 0xFFFFFFFF,
1328 .init = xen_pt_mask_reg_init,
1329 .u.dw.read = xen_pt_long_reg_read,
1330 .u.dw.write = xen_pt_long_reg_write,
1331 },
1332 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1333 {
1334 .offset = PCI_MSI_MASK_64,
1335 .size = 4,
1336 .init_val = 0x00000000,
1337 .ro_mask = 0xFFFFFFFF,
1338 .emu_mask = 0xFFFFFFFF,
1339 .init = xen_pt_mask_reg_init,
1340 .u.dw.read = xen_pt_long_reg_read,
1341 .u.dw.write = xen_pt_long_reg_write,
1342 },
1343 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1344 {
1345 .offset = PCI_MSI_MASK_32 + 4,
1346 .size = 4,
1347 .init_val = 0x00000000,
1348 .ro_mask = 0xFFFFFFFF,
1349 .emu_mask = 0x00000000,
1350 .init = xen_pt_pending_reg_init,
1351 .u.dw.read = xen_pt_long_reg_read,
1352 .u.dw.write = xen_pt_long_reg_write,
1353 },
1354 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1355 {
1356 .offset = PCI_MSI_MASK_64 + 4,
1357 .size = 4,
1358 .init_val = 0x00000000,
1359 .ro_mask = 0xFFFFFFFF,
1360 .emu_mask = 0x00000000,
1361 .init = xen_pt_pending_reg_init,
1362 .u.dw.read = xen_pt_long_reg_read,
1363 .u.dw.write = xen_pt_long_reg_write,
1364 },
3854ca57
JY		 1365 {
1366 .size = 0,
1367 },
1368};
1369
1370
1371/**************************************
1372 * MSI-X Capability
1373 */
1374
1375/* Message Control register for MSI-X */
1376static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
1377 XenPTRegInfo *reg, uint32_t real_offset,
1378 uint32_t *data)
1379{
1380 PCIDevice *d = &s->dev;
1381 uint16_t reg_field = 0;
1382
1383 /* use I/O device register's value as initial value */
1384 reg_field = pci_get_word(d->config + real_offset);
1385
1386 if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
1387 XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
1388 xen_host_pci_set_word(&s->real_device, real_offset,
1389 reg_field & ~PCI_MSIX_FLAGS_ENABLE);
1390 }
1391
1392 s->msix->ctrl_offset = real_offset;
1393
1394 *data = reg->init_val;
1395 return 0;
1396}
1397static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
1398 XenPTReg *cfg_entry, uint16_t *val,
1399 uint16_t dev_value, uint16_t valid_mask)
1400{
1401 XenPTRegInfo *reg = cfg_entry->reg;
1402 uint16_t writable_mask = 0;
0e7ef221 1403 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask);
3854ca57
JY		 1404 int debug_msix_enabled_old;
1405
1406 /* modify emulate register */
1407 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1408 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1409
1410 /* create value for writing to I/O device register */
3854ca57
JY		 1411 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1412
1413 /* update MSI-X */
1414 if ((*val & PCI_MSIX_FLAGS_ENABLE)
1415 && !(*val & PCI_MSIX_FLAGS_MASKALL)) {
1416 xen_pt_msix_update(s);
c976437c
ZD		 1417 } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {
1418 xen_pt_msix_disable(s);
3854ca57
JY		 1419 }
1420
1421 debug_msix_enabled_old = s->msix->enabled;
1422 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
1423 if (s->msix->enabled != debug_msix_enabled_old) {
1424 XEN_PT_LOG(&s->dev, "%s MSI-X\n",
1425 s->msix->enabled ? "enable" : "disable");
1426 }
1427
1428 return 0;
1429}
1430
0546b8c2 1431/* MSI-X Capability Structure reg static information table */
3854ca57
JY		 1432static XenPTRegInfo xen_pt_emu_reg_msix[] = {
1433 /* Next Pointer reg */
1434 {
1435 .offset = PCI_CAP_LIST_NEXT,
1436 .size = 1,
1437 .init_val = 0x00,
1438 .ro_mask = 0xFF,
1439 .emu_mask = 0xFF,
1440 .init = xen_pt_ptr_reg_init,
1441 .u.b.read = xen_pt_byte_reg_read,
1442 .u.b.write = xen_pt_byte_reg_write,
1443 },
1444 /* Message Control reg */
1445 {
1446 .offset = PCI_MSI_FLAGS,
1447 .size = 2,
1448 .init_val = 0x0000,
1449 .ro_mask = 0x3FFF,
1450 .emu_mask = 0x0000,
1451 .init = xen_pt_msixctrl_reg_init,
1452 .u.w.read = xen_pt_word_reg_read,
1453 .u.w.write = xen_pt_msixctrl_reg_write,
1454 },
1455 {
1456 .size = 0,
1457 },
1458};
1459
1460
93d7ae8e
AK		 1461/****************************
1462 * Capabilities
1463 */
1464
1465/* capability structure register group size functions */
1466
1467static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s,
1468 const XenPTRegGroupInfo *grp_reg,
1469 uint32_t base_offset, uint8_t *size)
1470{
1471 *size = grp_reg->grp_size;
1472 return 0;
1473}
1474/* get Vendor Specific Capability Structure register group size */
1475static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
1476 const XenPTRegGroupInfo *grp_reg,
1477 uint32_t base_offset, uint8_t *size)
1478{
1479 *size = pci_get_byte(s->dev.config + base_offset + 0x02);
1480 return 0;
1481}
1482/* get PCI Express Capability Structure register group size */
1483static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
1484 const XenPTRegGroupInfo *grp_reg,
1485 uint32_t base_offset, uint8_t *size)
1486{
1487 PCIDevice *d = &s->dev;
1488 uint8_t version = get_capability_version(s, base_offset);
1489 uint8_t type = get_device_type(s, base_offset);
1490 uint8_t pcie_size = 0;
1491
1492
1493 /* calculate size depend on capability version and device/port type */
1494 /* in case of PCI Express Base Specification Rev 1.x */
1495 if (version == 1) {
1496 /* The PCI Express Capabilities, Device Capabilities, and Device
1497 * Status/Control registers are required for all PCI Express devices.
1498 * The Link Capabilities and Link Status/Control are required for all
1499 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1500 * are not required to implement registers other than those listed
1501 * above and terminate the capability structure.
1502 */
1503 switch (type) {
1504 case PCI_EXP_TYPE_ENDPOINT:
1505 case PCI_EXP_TYPE_LEG_END:
1506 pcie_size = 0x14;
1507 break;
1508 case PCI_EXP_TYPE_RC_END:
1509 /* has no link */
1510 pcie_size = 0x0C;
1511 break;
1512 /* only EndPoint passthrough is supported */
1513 case PCI_EXP_TYPE_ROOT_PORT:
1514 case PCI_EXP_TYPE_UPSTREAM:
1515 case PCI_EXP_TYPE_DOWNSTREAM:
1516 case PCI_EXP_TYPE_PCI_BRIDGE:
1517 case PCI_EXP_TYPE_PCIE_BRIDGE:
1518 case PCI_EXP_TYPE_RC_EC:
1519 default:
1520 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1521 return -1;
1522 }
1523 }
1524 /* in case of PCI Express Base Specification Rev 2.0 */
1525 else if (version == 2) {
1526 switch (type) {
1527 case PCI_EXP_TYPE_ENDPOINT:
1528 case PCI_EXP_TYPE_LEG_END:
1529 case PCI_EXP_TYPE_RC_END:
1530 /* For Functions that do not implement the registers,
1531 * these spaces must be hardwired to 0b.
1532 */
1533 pcie_size = 0x3C;
1534 break;
1535 /* only EndPoint passthrough is supported */
1536 case PCI_EXP_TYPE_ROOT_PORT:
1537 case PCI_EXP_TYPE_UPSTREAM:
1538 case PCI_EXP_TYPE_DOWNSTREAM:
1539 case PCI_EXP_TYPE_PCI_BRIDGE:
1540 case PCI_EXP_TYPE_PCIE_BRIDGE:
1541 case PCI_EXP_TYPE_RC_EC:
1542 default:
1543 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1544 return -1;
1545 }
1546 } else {
1547 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version);
1548 return -1;
1549 }
1550
1551 *size = pcie_size;
1552 return 0;
1553}
3854ca57
JY		 1554/* get MSI Capability Structure register group size */
1555static int xen_pt_msi_size_init(XenPCIPassthroughState *s,
1556 const XenPTRegGroupInfo *grp_reg,
1557 uint32_t base_offset, uint8_t *size)
1558{
1559 PCIDevice *d = &s->dev;
1560 uint16_t msg_ctrl = 0;
1561 uint8_t msi_size = 0xa;
1562
1563 msg_ctrl = pci_get_word(d->config + (base_offset + PCI_MSI_FLAGS));
1564
1565 /* check if 64-bit address is capable of per-vector masking */
1566 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) {
1567 msi_size += 4;
1568 }
1569 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) {
1570 msi_size += 10;
1571 }
1572
1573 s->msi = g_new0(XenPTMSI, 1);
1574 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
1575
1576 *size = msi_size;
1577 return 0;
1578}
1579/* get MSI-X Capability Structure register group size */
1580static int xen_pt_msix_size_init(XenPCIPassthroughState *s,
1581 const XenPTRegGroupInfo *grp_reg,
1582 uint32_t base_offset, uint8_t *size)
1583{
1584 int rc = 0;
1585
1586 rc = xen_pt_msix_init(s, base_offset);
1587
1588 if (rc < 0) {
1589 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n");
1590 return rc;
1591 }
1592
1593 *size = grp_reg->grp_size;
1594 return 0;
1595}
1596
93d7ae8e
AK		 1597
1598static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
1599 /* Header Type0 reg group */
1600 {
1601 .grp_id = 0xFF,
1602 .grp_type = XEN_PT_GRP_TYPE_EMU,
1603 .grp_size = 0x40,
1604 .size_init = xen_pt_reg_grp_size_init,
1605 .emu_regs = xen_pt_emu_reg_header0,
1606 },
1607 /* PCI PowerManagement Capability reg group */
1608 {
1609 .grp_id = PCI_CAP_ID_PM,
1610 .grp_type = XEN_PT_GRP_TYPE_EMU,
1611 .grp_size = PCI_PM_SIZEOF,
1612 .size_init = xen_pt_reg_grp_size_init,
1613 .emu_regs = xen_pt_emu_reg_pm,
1614 },
1615 /* AGP Capability Structure reg group */
1616 {
1617 .grp_id = PCI_CAP_ID_AGP,
1618 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1619 .grp_size = 0x30,
1620 .size_init = xen_pt_reg_grp_size_init,
1621 },
1622 /* Vital Product Data Capability Structure reg group */
1623 {
1624 .grp_id = PCI_CAP_ID_VPD,
1625 .grp_type = XEN_PT_GRP_TYPE_EMU,
1626 .grp_size = 0x08,
1627 .size_init = xen_pt_reg_grp_size_init,
1628 .emu_regs = xen_pt_emu_reg_vpd,
1629 },
1630 /* Slot Identification reg group */
1631 {
1632 .grp_id = PCI_CAP_ID_SLOTID,
1633 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1634 .grp_size = 0x04,
1635 .size_init = xen_pt_reg_grp_size_init,
1636 },
3854ca57
JY		 1637 /* MSI Capability Structure reg group */
1638 {
1639 .grp_id = PCI_CAP_ID_MSI,
1640 .grp_type = XEN_PT_GRP_TYPE_EMU,
1641 .grp_size = 0xFF,
1642 .size_init = xen_pt_msi_size_init,
1643 .emu_regs = xen_pt_emu_reg_msi,
1644 },
93d7ae8e
AK		 1645 /* PCI-X Capabilities List Item reg group */
1646 {
1647 .grp_id = PCI_CAP_ID_PCIX,
1648 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1649 .grp_size = 0x18,
1650 .size_init = xen_pt_reg_grp_size_init,
1651 },
1652 /* Vendor Specific Capability Structure reg group */
1653 {
1654 .grp_id = PCI_CAP_ID_VNDR,
1655 .grp_type = XEN_PT_GRP_TYPE_EMU,
1656 .grp_size = 0xFF,
1657 .size_init = xen_pt_vendor_size_init,
1658 .emu_regs = xen_pt_emu_reg_vendor,
1659 },
1660 /* SHPC Capability List Item reg group */
1661 {
1662 .grp_id = PCI_CAP_ID_SHPC,
1663 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1664 .grp_size = 0x08,
1665 .size_init = xen_pt_reg_grp_size_init,
1666 },
1667 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1668 {
1669 .grp_id = PCI_CAP_ID_SSVID,
1670 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1671 .grp_size = 0x08,
1672 .size_init = xen_pt_reg_grp_size_init,
1673 },
1674 /* AGP 8x Capability Structure reg group */
1675 {
1676 .grp_id = PCI_CAP_ID_AGP3,
1677 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1678 .grp_size = 0x30,
1679 .size_init = xen_pt_reg_grp_size_init,
1680 },
1681 /* PCI Express Capability Structure reg group */
1682 {
1683 .grp_id = PCI_CAP_ID_EXP,
1684 .grp_type = XEN_PT_GRP_TYPE_EMU,
1685 .grp_size = 0xFF,
1686 .size_init = xen_pt_pcie_size_init,
1687 .emu_regs = xen_pt_emu_reg_pcie,
1688 },
3854ca57
JY		 1689 /* MSI-X Capability Structure reg group */
1690 {
1691 .grp_id = PCI_CAP_ID_MSIX,
1692 .grp_type = XEN_PT_GRP_TYPE_EMU,
1693 .grp_size = 0x0C,
1694 .size_init = xen_pt_msix_size_init,
1695 .emu_regs = xen_pt_emu_reg_msix,
1696 },
93d7ae8e
AK		 1697 {
1698 .grp_size = 0,
1699 },
1700};
1701
1702/* initialize Capabilities Pointer or Next Pointer register */
1703static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s,
1704 XenPTRegInfo *reg, uint32_t real_offset,
1705 uint32_t *data)
1706{
1707 int i;
1708 uint8_t *config = s->dev.config;
1709 uint32_t reg_field = pci_get_byte(config + real_offset);
1710 uint8_t cap_id = 0;
1711
1712 /* find capability offset */
1713 while (reg_field) {
1714 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1715 if (xen_pt_hide_dev_cap(&s->real_device,
1716 xen_pt_emu_reg_grps[i].grp_id)) {
1717 continue;
1718 }
1719
1720 cap_id = pci_get_byte(config + reg_field + PCI_CAP_LIST_ID);
1721 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) {
1722 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1723 goto out;
1724 }
1725 /* ignore the 0 hardwired capability, find next one */
1726 break;
1727 }
1728 }
1729
1730 /* next capability */
1731 reg_field = pci_get_byte(config + reg_field + PCI_CAP_LIST_NEXT);
1732 }
1733
1734out:
1735 *data = reg_field;
1736 return 0;
1737}
1738
1739
1740/*************
1741 * Main
1742 */
1743
1744static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap)
1745{
1746 uint8_t id;
1747 unsigned max_cap = PCI_CAP_MAX;
1748 uint8_t pos = PCI_CAPABILITY_LIST;
1749 uint8_t status = 0;
1750
1751 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) {
1752 return 0;
1753 }
1754 if ((status & PCI_STATUS_CAP_LIST) == 0) {
1755 return 0;
1756 }
1757
1758 while (max_cap--) {
1759 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) {
1760 break;
1761 }
1762 if (pos < PCI_CONFIG_HEADER_SIZE) {
1763 break;
1764 }
1765
1766 pos &= ~3;
1767 if (xen_host_pci_get_byte(&s->real_device,
1768 pos + PCI_CAP_LIST_ID, &id)) {
1769 break;
1770 }
1771
1772 if (id == 0xff) {
1773 break;
1774 }
1775 if (id == cap) {
1776 return pos;
1777 }
1778
1779 pos += PCI_CAP_LIST_NEXT;
1780 }
1781 return 0;
1782}
1783
1784static int xen_pt_config_reg_init(XenPCIPassthroughState *s,
1785 XenPTRegGroup *reg_grp, XenPTRegInfo *reg)
1786{
1787 XenPTReg *reg_entry;
1788 uint32_t data = 0;
1789 int rc = 0;
1790
1791 reg_entry = g_new0(XenPTReg, 1);
1792 reg_entry->reg = reg;
1793
1794 if (reg->init) {
1795 /* initialize emulate register */
1796 rc = reg->init(s, reg_entry->reg,
1797 reg_grp->base_offset + reg->offset, &data);
1798 if (rc < 0) {
c5633d99 1799 g_free(reg_entry);
93d7ae8e
AK		 1800 return rc;
1801 }
1802 if (data == XEN_PT_INVALID_REG) {
1803 /* free unused BAR register entry */
c5633d99 1804 g_free(reg_entry);
93d7ae8e
AK		 1805 return 0;
1806 }
1807 /* set register value */
1808 reg_entry->data = data;
1809 }
1810 /* list add register entry */
1811 QLIST_INSERT_HEAD(&reg_grp->reg_tbl_list, reg_entry, entries);
1812
1813 return 0;
1814}
1815
1816int xen_pt_config_init(XenPCIPassthroughState *s)
1817{
1818 int i, rc;
1819
1820 QLIST_INIT(&s->reg_grps);
1821
1822 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1823 uint32_t reg_grp_offset = 0;
1824 XenPTRegGroup *reg_grp_entry = NULL;
1825
1826 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF) {
1827 if (xen_pt_hide_dev_cap(&s->real_device,
1828 xen_pt_emu_reg_grps[i].grp_id)) {
1829 continue;
1830 }
1831
1832 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id);
1833
1834 if (!reg_grp_offset) {
1835 continue;
1836 }
1837 }
1838
1839 reg_grp_entry = g_new0(XenPTRegGroup, 1);
1840 QLIST_INIT(&reg_grp_entry->reg_tbl_list);
1841 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
1842
1843 reg_grp_entry->base_offset = reg_grp_offset;
1844 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i;
1845 if (xen_pt_emu_reg_grps[i].size_init) {
1846 /* get register group size */
1847 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp,
1848 reg_grp_offset,
1849 &reg_grp_entry->size);
1850 if (rc < 0) {
1851 xen_pt_config_delete(s);
1852 return rc;
1853 }
1854 }
1855
1856 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1857 if (xen_pt_emu_reg_grps[i].emu_regs) {
1858 int j = 0;
1859 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs;
1860 /* initialize capability register */
1861 for (j = 0; regs->size != 0; j++, regs++) {
1862 /* initialize capability register */
1863 rc = xen_pt_config_reg_init(s, reg_grp_entry, regs);
1864 if (rc < 0) {
1865 xen_pt_config_delete(s);
1866 return rc;
1867 }
1868 }
1869 }
1870 }
1871 }
1872
1873 return 0;
1874}
1875
1876/* delete all emulate register */
1877void xen_pt_config_delete(XenPCIPassthroughState *s)
1878{
1879 struct XenPTRegGroup *reg_group, *next_grp;
1880 struct XenPTReg *reg, *next_reg;
1881
3854ca57
JY		 1882 /* free MSI/MSI-X info table */
1883 if (s->msix) {
1884 xen_pt_msix_delete(s);
1885 }
1886 if (s->msi) {
1887 g_free(s->msi);
1888 }
1889
93d7ae8e
AK		 1890 /* free all register group entry */
1891 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) {
1892 /* free all register entry */
1893 QLIST_FOREACH_SAFE(reg, &reg_group->reg_tbl_list, entries, next_reg) {
1894 QLIST_REMOVE(reg, entries);
1895 g_free(reg);
1896 }
1897
1898 QLIST_REMOVE(reg_group, entries);
1899 g_free(reg_group);
1900 }
1901}
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