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trace: [linux-user] Commandline arguments to control tracing
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31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a 18 */
d39594e9 19#include "qemu/osdep.h"
67a1de0d 20#include "qemu-version.h"
edf8e2af 21#include <sys/syscall.h>
703e0e89 22#include <sys/resource.h>
31e31b8a 23
daa76aa4 24#include "qapi/error.h"
3ef693a0 25#include "qemu.h"
f348b6d1 26#include "qemu/path.h"
6533dd6e 27#include "qemu/config-file.h"
f348b6d1
VB		 28#include "qemu/cutils.h"
29#include "qemu/help_option.h"
2b41f10e 30#include "cpu.h"
63c91552 31#include "exec/exec-all.h"
9002ec79 32#include "tcg.h"
1de7afc9
PB		 33#include "qemu/timer.h"
34#include "qemu/envlist.h"
d8fd2954 35#include "elf.h"
508127e2 36#include "exec/log.h"
6533dd6e
LV		 37#include "trace/control.h"
38#include "glib-compat.h"
04a6dfeb 39
d088d664
AJ		 40char *exec_path;
41
1b530a6d 42int singlestep;
8cb76755
SW		 43static const char *filename;
44static const char *argv0;
45static int gdbstub_port;
46static envlist_t *envlist;
51fb256a 47static const char *cpu_model;
379f6698
PB		 48unsigned long mmap_min_addr;
49unsigned long guest_base;
50int have_guest_base;
120a9848
PB		 51
52#define EXCP_DUMP(env, fmt, ...) \
53do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61} while (0)
62
288e65b9
AG		 63#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64/*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
314992b1
AG		 71# ifdef TARGET_MIPS
72/* MIPS only supports 31 bits of virtual address space for user space */
73unsigned long reserved_va = 0x77000000;
74# else
288e65b9 75unsigned long reserved_va = 0xf7000000;
314992b1 76# endif
288e65b9 77#else
68a1c816 78unsigned long reserved_va;
379f6698 79#endif
1b530a6d 80
d03f9c32 81static void usage(int exitcode);
fc9c5412 82
7ee2822c 83static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 84const char *qemu_uname_release;
586314f2 85
9de5e440
FB		 86/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
703e0e89 89unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 90
91void gemu_log(const char *fmt, ...)
92{
93 va_list ap;
94
95 va_start(ap, fmt);
96 vfprintf(stderr, fmt, ap);
97 va_end(ap);
98}
99
8fcd3692 100#if defined(TARGET_I386)
05390248 101int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 102{
103 return -1;
104}
8fcd3692 105#endif
92ccca6a 106
d5975363
PB		 107/***********************************************************/
108/* Helper routines for implementing atomic operations. */
109
110/* To implement exclusive operations we force all cpus to syncronise.
111 We don't require a full sync, only that no cpus are executing guest code.
112 The alternative is to map target atomic ops onto host equivalents,
113 which requires quite a lot of per host/target work. */
c2764719 114static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 115static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
116static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
117static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
118static int pending_cpus;
119
120/* Make sure everything is in a consistent state for calling fork(). */
121void fork_start(void)
122{
677ef623 123 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 124 pthread_mutex_lock(&exclusive_lock);
d032d1b4 125 mmap_fork_start();
d5975363
PB		 126}
127
128void fork_end(int child)
129{
d032d1b4 130 mmap_fork_end(child);
d5975363 131 if (child) {
bdc44640 132 CPUState *cpu, *next_cpu;
d5975363
PB		 133 /* Child processes created by fork() only have a single thread.
134 Discard information about the parent threads. */
bdc44640
AF		 135 CPU_FOREACH_SAFE(cpu, next_cpu) {
136 if (cpu != thread_cpu) {
014628a7 137 QTAILQ_REMOVE(&cpus, cpu, node);
bdc44640
AF		 138 }
139 }
d5975363
PB		 140 pending_cpus = 0;
141 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 142 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 143 pthread_cond_init(&exclusive_cond, NULL);
144 pthread_cond_init(&exclusive_resume, NULL);
677ef623 145 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
f7ec7f7b 146 gdbserver_fork(thread_cpu);
d5975363
PB		 147 } else {
148 pthread_mutex_unlock(&exclusive_lock);
677ef623 149 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 150 }
d5975363
PB		 151}
152
153/* Wait for pending exclusive operations to complete. The exclusive lock
154 must be held. */
155static inline void exclusive_idle(void)
156{
157 while (pending_cpus) {
158 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
159 }
160}
161
162/* Start an exclusive operation.
8642c1b8 163 Must only be called from outside cpu_exec. */
d5975363
PB		 164static inline void start_exclusive(void)
165{
0315c31c
AF		 166 CPUState *other_cpu;
167
d5975363
PB		 168 pthread_mutex_lock(&exclusive_lock);
169 exclusive_idle();
170
171 pending_cpus = 1;
172 /* Make all other cpus stop executing. */
bdc44640 173 CPU_FOREACH(other_cpu) {
0315c31c 174 if (other_cpu->running) {
d5975363 175 pending_cpus++;
60a3e17a 176 cpu_exit(other_cpu);
d5975363
PB		 177 }
178 }
179 if (pending_cpus > 1) {
180 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
181 }
182}
183
184/* Finish an exclusive operation. */
f7e61b22 185static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 186{
187 pending_cpus = 0;
188 pthread_cond_broadcast(&exclusive_resume);
189 pthread_mutex_unlock(&exclusive_lock);
190}
191
192/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 193static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 194{
195 pthread_mutex_lock(&exclusive_lock);
196 exclusive_idle();
0315c31c 197 cpu->running = true;
d5975363
PB		 198 pthread_mutex_unlock(&exclusive_lock);
199}
200
201/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 202static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 203{
204 pthread_mutex_lock(&exclusive_lock);
0315c31c 205 cpu->running = false;
d5975363
PB		 206 if (pending_cpus > 1) {
207 pending_cpus--;
208 if (pending_cpus == 1) {
209 pthread_cond_signal(&exclusive_cond);
210 }
211 }
212 exclusive_idle();
213 pthread_mutex_unlock(&exclusive_lock);
214}
c2764719
PB		 215
216void cpu_list_lock(void)
217{
218 pthread_mutex_lock(&cpu_list_mutex);
219}
220
221void cpu_list_unlock(void)
222{
223 pthread_mutex_unlock(&cpu_list_mutex);
224}
d5975363
PB		 225
226
a541f297
FB		 227#ifdef TARGET_I386
228/***********************************************************/
229/* CPUX86 core interface */
230
28ab0e2e
FB		 231uint64_t cpu_get_tsc(CPUX86State *env)
232{
4a7428c5 233 return cpu_get_host_ticks();
28ab0e2e
FB		 234}
235
5fafdf24 236static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 237 int flags)
6dbad63e 238{
f4beb510 239 unsigned int e1, e2;
53a5960a 240 uint32_t *p;
6dbad63e
FB		 241 e1 = (addr << 16) | (limit & 0xffff);
242 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 243 e2 |= flags;
53a5960a 244 p = ptr;
d538e8f5 245 p[0] = tswap32(e1);
246 p[1] = tswap32(e2);
f4beb510
FB		 247}
248
e441570f 249static uint64_t *idt_table;
eb38c52c 250#ifdef TARGET_X86_64
d2fd1af7
FB		 251static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
252 uint64_t addr, unsigned int sel)
f4beb510 253{
4dbc422b 254 uint32_t *p, e1, e2;
f4beb510
FB		 255 e1 = (addr & 0xffff) | (sel << 16);
256 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 257 p = ptr;
4dbc422b
FB		 258 p[0] = tswap32(e1);
259 p[1] = tswap32(e2);
260 p[2] = tswap32(addr >> 32);
261 p[3] = 0;
6dbad63e 262}
d2fd1af7
FB		 263/* only dpl matters as we do only user space emulation */
264static void set_idt(int n, unsigned int dpl)
265{
266 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
267}
268#else
d2fd1af7
FB		 269static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
270 uint32_t addr, unsigned int sel)
271{
4dbc422b 272 uint32_t *p, e1, e2;
d2fd1af7
FB		 273 e1 = (addr & 0xffff) | (sel << 16);
274 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
275 p = ptr;
4dbc422b
FB		 276 p[0] = tswap32(e1);
277 p[1] = tswap32(e2);
d2fd1af7
FB		 278}
279
f4beb510
FB		 280/* only dpl matters as we do only user space emulation */
281static void set_idt(int n, unsigned int dpl)
282{
283 set_gate(idt_table + n, 0, dpl, 0, 0);
284}
d2fd1af7 285#endif
31e31b8a 286
89e957e7 287void cpu_loop(CPUX86State *env)
1b6b029e 288{
db6b81d4 289 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 290 int trapnr;
992f48a0 291 abi_ulong pc;
0284b03b 292 abi_ulong ret;
c227f099 293 target_siginfo_t info;
851e67a1 294
1b6b029e 295 for(;;) {
b040bc9c 296 cpu_exec_start(cs);
8642c1b8 297 trapnr = cpu_exec(cs);
b040bc9c 298 cpu_exec_end(cs);
bc8a22cc 299 switch(trapnr) {
f4beb510 300 case 0x80:
d2fd1af7 301 /* linux syscall from int $0x80 */
0284b03b
TB		 302 ret = do_syscall(env,
303 env->regs[R_EAX],
304 env->regs[R_EBX],
305 env->regs[R_ECX],
306 env->regs[R_EDX],
307 env->regs[R_ESI],
308 env->regs[R_EDI],
309 env->regs[R_EBP],
310 0, 0);
311 if (ret == -TARGET_ERESTARTSYS) {
312 env->eip -= 2;
313 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
314 env->regs[R_EAX] = ret;
315 }
f4beb510 316 break;
d2fd1af7
FB		 317#ifndef TARGET_ABI32
318 case EXCP_SYSCALL:
5ba18547 319 /* linux syscall from syscall instruction */
0284b03b
TB		 320 ret = do_syscall(env,
321 env->regs[R_EAX],
322 env->regs[R_EDI],
323 env->regs[R_ESI],
324 env->regs[R_EDX],
325 env->regs[10],
326 env->regs[8],
327 env->regs[9],
328 0, 0);
329 if (ret == -TARGET_ERESTARTSYS) {
330 env->eip -= 2;
331 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
332 env->regs[R_EAX] = ret;
333 }
d2fd1af7
FB		 334 break;
335#endif
f4beb510
FB		 336 case EXCP0B_NOSEG:
337 case EXCP0C_STACK:
a86b3c64 338 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 339 info.si_errno = 0;
340 info.si_code = TARGET_SI_KERNEL;
341 info._sifields._sigfault._addr = 0;
624f7979 342 queue_signal(env, info.si_signo, &info);
f4beb510 343 break;
1b6b029e 344 case EXCP0D_GPF:
d2fd1af7 345 /* XXX: potential problem if ABI32 */
84409ddb 346#ifndef TARGET_X86_64
851e67a1 347 if (env->eflags & VM_MASK) {
89e957e7 348 handle_vm86_fault(env);
84409ddb
JM		 349 } else
350#endif
351 {
a86b3c64 352 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 353 info.si_errno = 0;
354 info.si_code = TARGET_SI_KERNEL;
355 info._sifields._sigfault._addr = 0;
624f7979 356 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 357 }
358 break;
b689bc57 359 case EXCP0E_PAGE:
a86b3c64 360 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 361 info.si_errno = 0;
362 if (!(env->error_code & 1))
363 info.si_code = TARGET_SEGV_MAPERR;
364 else
365 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 366 info._sifields._sigfault._addr = env->cr[2];
624f7979 367 queue_signal(env, info.si_signo, &info);
b689bc57 368 break;
9de5e440 369 case EXCP00_DIVZ:
84409ddb 370#ifndef TARGET_X86_64
bc8a22cc 371 if (env->eflags & VM_MASK) {
447db213 372 handle_vm86_trap(env, trapnr);
84409ddb
JM		 373 } else
374#endif
375 {
bc8a22cc 376 /* division by zero */
a86b3c64 377 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 378 info.si_errno = 0;
379 info.si_code = TARGET_FPE_INTDIV;
380 info._sifields._sigfault._addr = env->eip;
624f7979 381 queue_signal(env, info.si_signo, &info);
bc8a22cc 382 }
9de5e440 383 break;
01df040b 384 case EXCP01_DB:
447db213 385 case EXCP03_INT3:
84409ddb 386#ifndef TARGET_X86_64
447db213
FB		 387 if (env->eflags & VM_MASK) {
388 handle_vm86_trap(env, trapnr);
84409ddb
JM		 389 } else
390#endif
391 {
a86b3c64 392 info.si_signo = TARGET_SIGTRAP;
447db213 393 info.si_errno = 0;
01df040b 394 if (trapnr == EXCP01_DB) {
447db213
FB		 395 info.si_code = TARGET_TRAP_BRKPT;
396 info._sifields._sigfault._addr = env->eip;
397 } else {
398 info.si_code = TARGET_SI_KERNEL;
399 info._sifields._sigfault._addr = 0;
400 }
624f7979 401 queue_signal(env, info.si_signo, &info);
447db213
FB		 402 }
403 break;
9de5e440
FB		 404 case EXCP04_INTO:
405 case EXCP05_BOUND:
84409ddb 406#ifndef TARGET_X86_64
bc8a22cc 407 if (env->eflags & VM_MASK) {
447db213 408 handle_vm86_trap(env, trapnr);
84409ddb
JM		 409 } else
410#endif
411 {
a86b3c64 412 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 413 info.si_errno = 0;
b689bc57 414 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 415 info._sifields._sigfault._addr = 0;
624f7979 416 queue_signal(env, info.si_signo, &info);
bc8a22cc 417 }
9de5e440
FB		 418 break;
419 case EXCP06_ILLOP:
a86b3c64 420 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 421 info.si_errno = 0;
422 info.si_code = TARGET_ILL_ILLOPN;
423 info._sifields._sigfault._addr = env->eip;
624f7979 424 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 425 break;
426 case EXCP_INTERRUPT:
427 /* just indicate that signals should be handled asap */
428 break;
1fddef4b
FB		 429 case EXCP_DEBUG:
430 {
431 int sig;
432
db6b81d4 433 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 434 if (sig)
435 {
436 info.si_signo = sig;
437 info.si_errno = 0;
438 info.si_code = TARGET_TRAP_BRKPT;
624f7979 439 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 440 }
441 }
442 break;
1b6b029e 443 default:
970a87a6 444 pc = env->segs[R_CS].base + env->eip;
120a9848
PB		 445 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
446 (long)pc, trapnr);
1b6b029e
FB		 447 abort();
448 }
66fb9763 449 process_pending_signals(env);
1b6b029e
FB		 450 }
451}
b346ff46
FB		 452#endif
453
454#ifdef TARGET_ARM
455
49017bd8 456#define get_user_code_u32(x, gaddr, env) \
d8fd2954 457 ({ abi_long __r = get_user_u32((x), (gaddr)); \
f9fd40eb 458 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 459 (x) = bswap32(x); \
460 } \
461 __r; \
462 })
463
49017bd8 464#define get_user_code_u16(x, gaddr, env) \
d8fd2954 465 ({ abi_long __r = get_user_u16((x), (gaddr)); \
f9fd40eb 466 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 467 (x) = bswap16(x); \
468 } \
469 __r; \
470 })
471
c3ae85fc
PB		 472#define get_user_data_u32(x, gaddr, env) \
473 ({ abi_long __r = get_user_u32((x), (gaddr)); \
474 if (!__r && arm_cpu_bswap_data(env)) { \
475 (x) = bswap32(x); \
476 } \
477 __r; \
478 })
479
480#define get_user_data_u16(x, gaddr, env) \
481 ({ abi_long __r = get_user_u16((x), (gaddr)); \
482 if (!__r && arm_cpu_bswap_data(env)) { \
483 (x) = bswap16(x); \
484 } \
485 __r; \
486 })
487
488#define put_user_data_u32(x, gaddr, env) \
489 ({ typeof(x) __x = (x); \
490 if (arm_cpu_bswap_data(env)) { \
491 __x = bswap32(__x); \
492 } \
493 put_user_u32(__x, (gaddr)); \
494 })
495
496#define put_user_data_u16(x, gaddr, env) \
497 ({ typeof(x) __x = (x); \
498 if (arm_cpu_bswap_data(env)) { \
499 __x = bswap16(__x); \
500 } \
501 put_user_u16(__x, (gaddr)); \
502 })
503
1861c454
PM		 504#ifdef TARGET_ABI32
505/* Commpage handling -- there is no commpage for AArch64 */
506
97cc7560
DDAG		 507/*
508 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
509 * Input:
510 * r0 = pointer to oldval
511 * r1 = pointer to newval
512 * r2 = pointer to target value
513 *
514 * Output:
515 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
516 * C set if *ptr was changed, clear if no exchange happened
517 *
518 * Note segv's in kernel helpers are a bit tricky, we can set the
519 * data address sensibly but the PC address is just the entry point.
520 */
521static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
522{
523 uint64_t oldval, newval, val;
524 uint32_t addr, cpsr;
525 target_siginfo_t info;
526
527 /* Based on the 32 bit code in do_kernel_trap */
528
529 /* XXX: This only works between threads, not between processes.
530 It's probably possible to implement this with native host
531 operations. However things like ldrex/strex are much harder so
532 there's not much point trying. */
533 start_exclusive();
534 cpsr = cpsr_read(env);
535 addr = env->regs[2];
536
537 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 538 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 539 goto segv;
540 };
541
542 if (get_user_u64(newval, env->regs[1])) {
abf1172f 543 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 544 goto segv;
545 };
546
547 if (get_user_u64(val, addr)) {
abf1172f 548 env->exception.vaddress = addr;
97cc7560
DDAG		 549 goto segv;
550 }
551
552 if (val == oldval) {
553 val = newval;
554
555 if (put_user_u64(val, addr)) {
abf1172f 556 env->exception.vaddress = addr;
97cc7560
DDAG		 557 goto segv;
558 };
559
560 env->regs[0] = 0;
561 cpsr |= CPSR_C;
562 } else {
563 env->regs[0] = -1;
564 cpsr &= ~CPSR_C;
565 }
50866ba5 566 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
97cc7560
DDAG		 567 end_exclusive();
568 return;
569
570segv:
571 end_exclusive();
572 /* We get the PC of the entry address - which is as good as anything,
573 on a real kernel what you get depends on which mode it uses. */
a86b3c64 574 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 575 info.si_errno = 0;
576 /* XXX: check env->error_code */
577 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 578 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 579 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 580}
581
fbb4a2e3
PB		 582/* Handle a jump to the kernel code page. */
583static int
584do_kernel_trap(CPUARMState *env)
585{
586 uint32_t addr;
587 uint32_t cpsr;
588 uint32_t val;
589
590 switch (env->regs[15]) {
591 case 0xffff0fa0: /* __kernel_memory_barrier */
592 /* ??? No-op. Will need to do better for SMP. */
593 break;
594 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 595 /* XXX: This only works between threads, not between processes.
596 It's probably possible to implement this with native host
597 operations. However things like ldrex/strex are much harder so
598 there's not much point trying. */
599 start_exclusive();
fbb4a2e3
PB		 600 cpsr = cpsr_read(env);
601 addr = env->regs[2];
602 /* FIXME: This should SEGV if the access fails. */
603 if (get_user_u32(val, addr))
604 val = ~env->regs[0];
605 if (val == env->regs[0]) {
606 val = env->regs[1];
607 /* FIXME: Check for segfaults. */
608 put_user_u32(val, addr);
609 env->regs[0] = 0;
610 cpsr |= CPSR_C;
611 } else {
612 env->regs[0] = -1;
613 cpsr &= ~CPSR_C;
614 }
50866ba5 615 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
d5975363 616 end_exclusive();
fbb4a2e3
PB		 617 break;
618 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 619 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 620 break;
97cc7560
DDAG		 621 case 0xffff0f60: /* __kernel_cmpxchg64 */
622 arm_kernel_cmpxchg64_helper(env);
623 break;
624
fbb4a2e3
PB		 625 default:
626 return 1;
627 }
628 /* Jump back to the caller. */
629 addr = env->regs[14];
630 if (addr & 1) {
631 env->thumb = 1;
632 addr &= ~1;
633 }
634 env->regs[15] = addr;
635
636 return 0;
637}
638
fa2ef212 639/* Store exclusive handling for AArch32 */
426f5abc
PB		 640static int do_strex(CPUARMState *env)
641{
03d05e2d 642 uint64_t val;
426f5abc
PB		 643 int size;
644 int rc = 1;
645 int segv = 0;
646 uint32_t addr;
647 start_exclusive();
03d05e2d 648 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 649 goto fail;
650 }
03d05e2d
PM		 651 /* We know we're always AArch32 so the address is in uint32_t range
652 * unless it was the -1 exclusive-monitor-lost value (which won't
653 * match exclusive_test above).
654 */
655 assert(extract64(env->exclusive_addr, 32, 32) == 0);
656 addr = env->exclusive_addr;
426f5abc
PB		 657 size = env->exclusive_info & 0xf;
658 switch (size) {
659 case 0:
660 segv = get_user_u8(val, addr);
661 break;
662 case 1:
c3ae85fc 663 segv = get_user_data_u16(val, addr, env);
426f5abc
PB		 664 break;
665 case 2:
666 case 3:
c3ae85fc 667 segv = get_user_data_u32(val, addr, env);
426f5abc 668 break;
f7001a3b
AJ		 669 default:
670 abort();
426f5abc
PB		 671 }
672 if (segv) {
abf1172f 673 env->exception.vaddress = addr;
426f5abc
PB		 674 goto done;
675 }
426f5abc 676 if (size == 3) {
03d05e2d 677 uint32_t valhi;
c3ae85fc 678 segv = get_user_data_u32(valhi, addr + 4, env);
426f5abc 679 if (segv) {
abf1172f 680 env->exception.vaddress = addr + 4;
426f5abc
PB		 681 goto done;
682 }
c3ae85fc
PB		 683 if (arm_cpu_bswap_data(env)) {
684 val = deposit64((uint64_t)valhi, 32, 32, val);
685 } else {
686 val = deposit64(val, 32, 32, valhi);
687 }
426f5abc 688 }
03d05e2d
PM		 689 if (val != env->exclusive_val) {
690 goto fail;
691 }
692
426f5abc
PB		 693 val = env->regs[(env->exclusive_info >> 8) & 0xf];
694 switch (size) {
695 case 0:
696 segv = put_user_u8(val, addr);
697 break;
698 case 1:
c3ae85fc 699 segv = put_user_data_u16(val, addr, env);
426f5abc
PB		 700 break;
701 case 2:
702 case 3:
c3ae85fc 703 segv = put_user_data_u32(val, addr, env);
426f5abc
PB		 704 break;
705 }
706 if (segv) {
abf1172f 707 env->exception.vaddress = addr;
426f5abc
PB		 708 goto done;
709 }
710 if (size == 3) {
711 val = env->regs[(env->exclusive_info >> 12) & 0xf];
c3ae85fc 712 segv = put_user_data_u32(val, addr + 4, env);
426f5abc 713 if (segv) {
abf1172f 714 env->exception.vaddress = addr + 4;
426f5abc
PB		 715 goto done;
716 }
717 }
718 rc = 0;
719fail:
725b8a69 720 env->regs[15] += 4;
426f5abc
PB		 721 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
722done:
723 end_exclusive();
724 return segv;
725}
726
b346ff46
FB		 727void cpu_loop(CPUARMState *env)
728{
0315c31c 729 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 730 int trapnr;
731 unsigned int n, insn;
c227f099 732 target_siginfo_t info;
b5ff1b31 733 uint32_t addr;
f0267ef7 734 abi_ulong ret;
3b46e624 735
b346ff46 736 for(;;) {
0315c31c 737 cpu_exec_start(cs);
8642c1b8 738 trapnr = cpu_exec(cs);
0315c31c 739 cpu_exec_end(cs);
b346ff46
FB		 740 switch(trapnr) {
741 case EXCP_UDEF:
c6981055 742 {
0429a971 743 TaskState *ts = cs->opaque;
c6981055 744 uint32_t opcode;
6d9a42be 745 int rc;
c6981055
FB		 746
747 /* we handle the FPU emulation here, as Linux */
748 /* we get the opcode */
2f619698 749 /* FIXME - what to do if get_user() fails? */
49017bd8 750 get_user_code_u32(opcode, env->regs[15], env);
3b46e624 751
6d9a42be
AJ		 752 rc = EmulateAll(opcode, &ts->fpa, env);
753 if (rc == 0) { /* illegal instruction */
a86b3c64 754 info.si_signo = TARGET_SIGILL;
c6981055
FB		 755 info.si_errno = 0;
756 info.si_code = TARGET_ILL_ILLOPN;
757 info._sifields._sigfault._addr = env->regs[15];
624f7979 758 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 759 } else if (rc < 0) { /* FP exception */
760 int arm_fpe=0;
761
762 /* translate softfloat flags to FPSR flags */
763 if (-rc & float_flag_invalid)
764 arm_fpe |= BIT_IOC;
765 if (-rc & float_flag_divbyzero)
766 arm_fpe |= BIT_DZC;
767 if (-rc & float_flag_overflow)
768 arm_fpe |= BIT_OFC;
769 if (-rc & float_flag_underflow)
770 arm_fpe |= BIT_UFC;
771 if (-rc & float_flag_inexact)
772 arm_fpe |= BIT_IXC;
773
774 FPSR fpsr = ts->fpa.fpsr;
775 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
776
777 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 778 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 779 info.si_errno = 0;
780
781 /* ordered by priority, least first */
782 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
783 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
784 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
785 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
786 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
787
788 info._sifields._sigfault._addr = env->regs[15];
624f7979 789 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 790 } else {
791 env->regs[15] += 4;
792 }
793
794 /* accumulate unenabled exceptions */
795 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
796 fpsr |= BIT_IXC;
797 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
798 fpsr |= BIT_UFC;
799 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
800 fpsr |= BIT_OFC;
801 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
802 fpsr |= BIT_DZC;
803 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
804 fpsr |= BIT_IOC;
805 ts->fpa.fpsr=fpsr;
806 } else { /* everything OK */
c6981055
FB		 807 /* increment PC */
808 env->regs[15] += 4;
809 }
810 }
b346ff46
FB		 811 break;
812 case EXCP_SWI:
06c949e6 813 case EXCP_BKPT:
b346ff46 814 {
ce4defa0 815 env->eabi = 1;
b346ff46 816 /* system call */
06c949e6
PB		 817 if (trapnr == EXCP_BKPT) {
818 if (env->thumb) {
2f619698 819 /* FIXME - what to do if get_user() fails? */
49017bd8 820 get_user_code_u16(insn, env->regs[15], env);
06c949e6
PB		 821 n = insn & 0xff;
822 env->regs[15] += 2;
823 } else {
2f619698 824 /* FIXME - what to do if get_user() fails? */
49017bd8 825 get_user_code_u32(insn, env->regs[15], env);
06c949e6
PB		 826 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
827 env->regs[15] += 4;
828 }
192c7bd9 829 } else {
06c949e6 830 if (env->thumb) {
2f619698 831 /* FIXME - what to do if get_user() fails? */
49017bd8 832 get_user_code_u16(insn, env->regs[15] - 2, env);
06c949e6
PB		 833 n = insn & 0xff;
834 } else {
2f619698 835 /* FIXME - what to do if get_user() fails? */
49017bd8 836 get_user_code_u32(insn, env->regs[15] - 4, env);
06c949e6
PB		 837 n = insn & 0xffffff;
838 }
192c7bd9
FB		 839 }
840
6f1f31c0 841 if (n == ARM_NR_cacheflush) {
dcfd14b3 842 /* nop */
a4f81979
FB		 843 } else if (n == ARM_NR_semihosting
844 || n == ARM_NR_thumb_semihosting) {
845 env->regs[0] = do_arm_semihosting (env);
3a1363ac 846 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 847 /* linux syscall */
ce4defa0 848 if (env->thumb || n == 0) {
192c7bd9
FB		 849 n = env->regs[7];
850 } else {
851 n -= ARM_SYSCALL_BASE;
ce4defa0 852 env->eabi = 0;
192c7bd9 853 }
fbb4a2e3
PB		 854 if ( n > ARM_NR_BASE) {
855 switch (n) {
856 case ARM_NR_cacheflush:
dcfd14b3 857 /* nop */
fbb4a2e3
PB		 858 break;
859 case ARM_NR_set_tls:
860 cpu_set_tls(env, env->regs[0]);
861 env->regs[0] = 0;
862 break;
d5355087
HL		 863 case ARM_NR_breakpoint:
864 env->regs[15] -= env->thumb ? 2 : 4;
865 goto excp_debug;
fbb4a2e3
PB		 866 default:
867 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
868 n);
869 env->regs[0] = -TARGET_ENOSYS;
870 break;
871 }
872 } else {
f0267ef7
TB		 873 ret = do_syscall(env,
874 n,
875 env->regs[0],
876 env->regs[1],
877 env->regs[2],
878 env->regs[3],
879 env->regs[4],
880 env->regs[5],
881 0, 0);
882 if (ret == -TARGET_ERESTARTSYS) {
883 env->regs[15] -= env->thumb ? 2 : 4;
884 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
885 env->regs[0] = ret;
886 }
fbb4a2e3 887 }
b346ff46
FB		 888 } else {
889 goto error;
890 }
891 }
892 break;
43fff238
FB		 893 case EXCP_INTERRUPT:
894 /* just indicate that signals should be handled asap */
895 break;
abf1172f
PM		 896 case EXCP_STREX:
897 if (!do_strex(env)) {
898 break;
899 }
900 /* fall through for segv */
68016c62
FB		 901 case EXCP_PREFETCH_ABORT:
902 case EXCP_DATA_ABORT:
abf1172f 903 addr = env->exception.vaddress;
68016c62 904 {
a86b3c64 905 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 906 info.si_errno = 0;
907 /* XXX: check env->error_code */
908 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 909 info._sifields._sigfault._addr = addr;
624f7979 910 queue_signal(env, info.si_signo, &info);
68016c62
FB		 911 }
912 break;
1fddef4b 913 case EXCP_DEBUG:
d5355087 914 excp_debug:
1fddef4b
FB		 915 {
916 int sig;
917
db6b81d4 918 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 919 if (sig)
920 {
921 info.si_signo = sig;
922 info.si_errno = 0;
923 info.si_code = TARGET_TRAP_BRKPT;
624f7979 924 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 925 }
926 }
927 break;
fbb4a2e3
PB		 928 case EXCP_KERNEL_TRAP:
929 if (do_kernel_trap(env))
930 goto error;
931 break;
f911e0a3
PM		 932 case EXCP_YIELD:
933 /* nothing to do here for user-mode, just resume guest code */
934 break;
b346ff46
FB		 935 default:
936 error:
120a9848 937 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
b346ff46
FB		 938 abort();
939 }
940 process_pending_signals(env);
941 }
942}
943
1861c454
PM		 944#else
945
fa2ef212
MM		 946/*
947 * Handle AArch64 store-release exclusive
948 *
949 * rs = gets the status result of store exclusive
950 * rt = is the register that is stored
951 * rt2 = is the second register store (in STP)
952 *
953 */
954static int do_strex_a64(CPUARMState *env)
955{
956 uint64_t val;
957 int size;
958 bool is_pair;
959 int rc = 1;
960 int segv = 0;
961 uint64_t addr;
962 int rs, rt, rt2;
963
964 start_exclusive();
965 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
966 size = extract32(env->exclusive_info, 0, 2);
967 is_pair = extract32(env->exclusive_info, 2, 1);
968 rs = extract32(env->exclusive_info, 4, 5);
969 rt = extract32(env->exclusive_info, 9, 5);
970 rt2 = extract32(env->exclusive_info, 14, 5);
971
972 addr = env->exclusive_addr;
973
974 if (addr != env->exclusive_test) {
975 goto finish;
976 }
977
978 switch (size) {
979 case 0:
980 segv = get_user_u8(val, addr);
981 break;
982 case 1:
983 segv = get_user_u16(val, addr);
984 break;
985 case 2:
986 segv = get_user_u32(val, addr);
987 break;
988 case 3:
989 segv = get_user_u64(val, addr);
990 break;
991 default:
992 abort();
993 }
994 if (segv) {
abf1172f 995 env->exception.vaddress = addr;
fa2ef212
MM		 996 goto error;
997 }
998 if (val != env->exclusive_val) {
999 goto finish;
1000 }
1001 if (is_pair) {
1002 if (size == 2) {
1003 segv = get_user_u32(val, addr + 4);
1004 } else {
1005 segv = get_user_u64(val, addr + 8);
1006 }
1007 if (segv) {
abf1172f 1008 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1009 goto error;
1010 }
1011 if (val != env->exclusive_high) {
1012 goto finish;
1013 }
1014 }
2ea5a2ca
JG		 1015 /* handle the zero register */
1016 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 1017 switch (size) {
1018 case 0:
1019 segv = put_user_u8(val, addr);
1020 break;
1021 case 1:
1022 segv = put_user_u16(val, addr);
1023 break;
1024 case 2:
1025 segv = put_user_u32(val, addr);
1026 break;
1027 case 3:
1028 segv = put_user_u64(val, addr);
1029 break;
1030 }
1031 if (segv) {
1032 goto error;
1033 }
1034 if (is_pair) {
2ea5a2ca
JG		 1035 /* handle the zero register */
1036 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 1037 if (size == 2) {
1038 segv = put_user_u32(val, addr + 4);
1039 } else {
1040 segv = put_user_u64(val, addr + 8);
1041 }
1042 if (segv) {
abf1172f 1043 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1044 goto error;
1045 }
1046 }
1047 rc = 0;
1048finish:
1049 env->pc += 4;
1050 /* rs == 31 encodes a write to the ZR, thus throwing away
1051 * the status return. This is rather silly but valid.
1052 */
1053 if (rs < 31) {
1054 env->xregs[rs] = rc;
1055 }
1056error:
1057 /* instruction faulted, PC does not advance */
1058 /* either way a strex releases any exclusive lock we have */
1059 env->exclusive_addr = -1;
1060 end_exclusive();
1061 return segv;
1062}
1063
1861c454
PM		 1064/* AArch64 main loop */
1065void cpu_loop(CPUARMState *env)
1066{
1067 CPUState *cs = CPU(arm_env_get_cpu(env));
1068 int trapnr, sig;
f0267ef7 1069 abi_long ret;
1861c454 1070 target_siginfo_t info;
1861c454
PM		 1071
1072 for (;;) {
1073 cpu_exec_start(cs);
8642c1b8 1074 trapnr = cpu_exec(cs);
1861c454
PM		 1075 cpu_exec_end(cs);
1076
1077 switch (trapnr) {
1078 case EXCP_SWI:
f0267ef7
TB		 1079 ret = do_syscall(env,
1080 env->xregs[8],
1081 env->xregs[0],
1082 env->xregs[1],
1083 env->xregs[2],
1084 env->xregs[3],
1085 env->xregs[4],
1086 env->xregs[5],
1087 0, 0);
1088 if (ret == -TARGET_ERESTARTSYS) {
1089 env->pc -= 4;
1090 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1091 env->xregs[0] = ret;
1092 }
1861c454
PM		 1093 break;
1094 case EXCP_INTERRUPT:
1095 /* just indicate that signals should be handled asap */
1096 break;
1097 case EXCP_UDEF:
a86b3c64 1098 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1099 info.si_errno = 0;
1100 info.si_code = TARGET_ILL_ILLOPN;
1101 info._sifields._sigfault._addr = env->pc;
1102 queue_signal(env, info.si_signo, &info);
1103 break;
abf1172f
PM		 1104 case EXCP_STREX:
1105 if (!do_strex_a64(env)) {
1106 break;
1107 }
1108 /* fall through for segv */
1861c454 1109 case EXCP_PREFETCH_ABORT:
1861c454 1110 case EXCP_DATA_ABORT:
a86b3c64 1111 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1112 info.si_errno = 0;
1113 /* XXX: check env->error_code */
1114 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1115 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1116 queue_signal(env, info.si_signo, &info);
1117 break;
1118 case EXCP_DEBUG:
1119 case EXCP_BKPT:
1120 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1121 if (sig) {
1122 info.si_signo = sig;
1123 info.si_errno = 0;
1124 info.si_code = TARGET_TRAP_BRKPT;
1125 queue_signal(env, info.si_signo, &info);
1126 }
1127 break;
8012c84f
PM		 1128 case EXCP_SEMIHOST:
1129 env->xregs[0] = do_arm_semihosting(env);
1130 break;
f911e0a3
PM		 1131 case EXCP_YIELD:
1132 /* nothing to do here for user-mode, just resume guest code */
1133 break;
1861c454 1134 default:
120a9848 1135 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1861c454
PM		 1136 abort();
1137 }
1138 process_pending_signals(env);
fa2ef212
MM		 1139 /* Exception return on AArch64 always clears the exclusive monitor,
1140 * so any return to running guest code implies this.
1141 * A strex (successful or otherwise) also clears the monitor, so
1142 * we don't need to specialcase EXCP_STREX.
1143 */
1144 env->exclusive_addr = -1;
1861c454
PM		 1145 }
1146}
1147#endif /* ndef TARGET_ABI32 */
1148
b346ff46 1149#endif
1b6b029e 1150
d2fbca94
GX		 1151#ifdef TARGET_UNICORE32
1152
05390248 1153void cpu_loop(CPUUniCore32State *env)
d2fbca94 1154{
0315c31c 1155 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1156 int trapnr;
1157 unsigned int n, insn;
1158 target_siginfo_t info;
1159
1160 for (;;) {
0315c31c 1161 cpu_exec_start(cs);
8642c1b8 1162 trapnr = cpu_exec(cs);
0315c31c 1163 cpu_exec_end(cs);
d2fbca94
GX		 1164 switch (trapnr) {
1165 case UC32_EXCP_PRIV:
1166 {
1167 /* system call */
1168 get_user_u32(insn, env->regs[31] - 4);
1169 n = insn & 0xffffff;
1170
1171 if (n >= UC32_SYSCALL_BASE) {
1172 /* linux syscall */
1173 n -= UC32_SYSCALL_BASE;
1174 if (n == UC32_SYSCALL_NR_set_tls) {
1175 cpu_set_tls(env, env->regs[0]);
1176 env->regs[0] = 0;
1177 } else {
256cb6af 1178 abi_long ret = do_syscall(env,
d2fbca94
GX		 1179 n,
1180 env->regs[0],
1181 env->regs[1],
1182 env->regs[2],
1183 env->regs[3],
1184 env->regs[4],
5945cfcb
PM		 1185 env->regs[5],
1186 0, 0);
256cb6af
TB		 1187 if (ret == -TARGET_ERESTARTSYS) {
1188 env->regs[31] -= 4;
1189 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1190 env->regs[0] = ret;
1191 }
d2fbca94
GX		 1192 }
1193 } else {
1194 goto error;
1195 }
1196 }
1197 break;
d48813dd
GX		 1198 case UC32_EXCP_DTRAP:
1199 case UC32_EXCP_ITRAP:
a86b3c64 1200 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1201 info.si_errno = 0;
1202 /* XXX: check env->error_code */
1203 info.si_code = TARGET_SEGV_MAPERR;
1204 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1205 queue_signal(env, info.si_signo, &info);
1206 break;
1207 case EXCP_INTERRUPT:
1208 /* just indicate that signals should be handled asap */
1209 break;
1210 case EXCP_DEBUG:
1211 {
1212 int sig;
1213
db6b81d4 1214 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1215 if (sig) {
1216 info.si_signo = sig;
1217 info.si_errno = 0;
1218 info.si_code = TARGET_TRAP_BRKPT;
1219 queue_signal(env, info.si_signo, &info);
1220 }
1221 }
1222 break;
1223 default:
1224 goto error;
1225 }
1226 process_pending_signals(env);
1227 }
1228
1229error:
120a9848 1230 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
d2fbca94
GX		 1231 abort();
1232}
1233#endif
1234
93ac68bc 1235#ifdef TARGET_SPARC
ed23fbd9 1236#define SPARC64_STACK_BIAS 2047
93ac68bc 1237
060366c5
FB		 1238//#define DEBUG_WIN
1239
2623cbaf
FB		 1240/* WARNING: dealing with register windows _is_ complicated. More info
1241 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1242static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1243{
1a14026e 1244 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1245 /* wrap handling : if cwp is on the last window, then we use the
1246 registers 'after' the end */
1a14026e
BS		 1247 if (index < 8 && env->cwp == env->nwindows - 1)
1248 index += 16 * env->nwindows;
060366c5
FB		 1249 return index;
1250}
1251
2623cbaf
FB		 1252/* save the register window 'cwp1' */
1253static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1254{
2623cbaf 1255 unsigned int i;
992f48a0 1256 abi_ulong sp_ptr;
3b46e624 1257
53a5960a 1258 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1259#ifdef TARGET_SPARC64
1260 if (sp_ptr & 3)
1261 sp_ptr += SPARC64_STACK_BIAS;
1262#endif
060366c5 1263#if defined(DEBUG_WIN)
2daf0284
BS		 1264 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1265 sp_ptr, cwp1);
060366c5 1266#endif
2623cbaf 1267 for(i = 0; i < 16; i++) {
2f619698
FB		 1268 /* FIXME - what to do if put_user() fails? */
1269 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1270 sp_ptr += sizeof(abi_ulong);
2623cbaf 1271 }
060366c5
FB		 1272}
1273
1274static void save_window(CPUSPARCState *env)
1275{
5ef54116 1276#ifndef TARGET_SPARC64
2623cbaf 1277 unsigned int new_wim;
1a14026e
BS		 1278 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1279 ((1LL << env->nwindows) - 1);
1280 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1281 env->wim = new_wim;
5ef54116 1282#else
1a14026e 1283 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1284 env->cansave++;
1285 env->canrestore--;
1286#endif
060366c5
FB		 1287}
1288
1289static void restore_window(CPUSPARCState *env)
1290{
eda52953
BS		 1291#ifndef TARGET_SPARC64
1292 unsigned int new_wim;
1293#endif
1294 unsigned int i, cwp1;
992f48a0 1295 abi_ulong sp_ptr;
3b46e624 1296
eda52953 1297#ifndef TARGET_SPARC64
1a14026e
BS		 1298 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1299 ((1LL << env->nwindows) - 1);
eda52953 1300#endif
3b46e624 1301
060366c5 1302 /* restore the invalid window */
1a14026e 1303 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1304 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1305#ifdef TARGET_SPARC64
1306 if (sp_ptr & 3)
1307 sp_ptr += SPARC64_STACK_BIAS;
1308#endif
060366c5 1309#if defined(DEBUG_WIN)
2daf0284
BS		 1310 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1311 sp_ptr, cwp1);
060366c5 1312#endif
2623cbaf 1313 for(i = 0; i < 16; i++) {
2f619698
FB		 1314 /* FIXME - what to do if get_user() fails? */
1315 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1316 sp_ptr += sizeof(abi_ulong);
2623cbaf 1317 }
5ef54116
FB		 1318#ifdef TARGET_SPARC64
1319 env->canrestore++;
1a14026e
BS		 1320 if (env->cleanwin < env->nwindows - 1)
1321 env->cleanwin++;
5ef54116 1322 env->cansave--;
eda52953
BS		 1323#else
1324 env->wim = new_wim;
5ef54116 1325#endif
060366c5
FB		 1326}
1327
1328static void flush_windows(CPUSPARCState *env)
1329{
1330 int offset, cwp1;
2623cbaf
FB		 1331
1332 offset = 1;
060366c5
FB		 1333 for(;;) {
1334 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1335 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1336#ifndef TARGET_SPARC64
060366c5
FB		 1337 if (env->wim & (1 << cwp1))
1338 break;
eda52953
BS		 1339#else
1340 if (env->canrestore == 0)
1341 break;
1342 env->cansave++;
1343 env->canrestore--;
1344#endif
2623cbaf 1345 save_window_offset(env, cwp1);
060366c5
FB		 1346 offset++;
1347 }
1a14026e 1348 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1349#ifndef TARGET_SPARC64
1350 /* set wim so that restore will reload the registers */
2623cbaf 1351 env->wim = 1 << cwp1;
eda52953 1352#endif
2623cbaf
FB		 1353#if defined(DEBUG_WIN)
1354 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1355#endif
2623cbaf 1356}
060366c5 1357
93ac68bc
FB		 1358void cpu_loop (CPUSPARCState *env)
1359{
878096ee 1360 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1361 int trapnr;
1362 abi_long ret;
c227f099 1363 target_siginfo_t info;
3b46e624 1364
060366c5 1365 while (1) {
b040bc9c 1366 cpu_exec_start(cs);
8642c1b8 1367 trapnr = cpu_exec(cs);
b040bc9c 1368 cpu_exec_end(cs);
3b46e624 1369
20132b96
RH		 1370 /* Compute PSR before exposing state. */
1371 if (env->cc_op != CC_OP_FLAGS) {
1372 cpu_get_psr(env);
1373 }
1374
060366c5 1375 switch (trapnr) {
5ef54116 1376#ifndef TARGET_SPARC64
5fafdf24 1377 case 0x88:
060366c5 1378 case 0x90:
5ef54116 1379#else
cb33da57 1380 case 0x110:
5ef54116
FB		 1381 case 0x16d:
1382#endif
060366c5 1383 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1384 env->regwptr[0], env->regwptr[1],
1385 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1386 env->regwptr[4], env->regwptr[5],
1387 0, 0);
c0bea68f
TB		 1388 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1389 break;
1390 }
2cc20260 1391 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1392#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1393 env->xcc |= PSR_CARRY;
1394#else
060366c5 1395 env->psr |= PSR_CARRY;
27908725 1396#endif
060366c5
FB		 1397 ret = -ret;
1398 } else {
992f48a0 1399#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1400 env->xcc &= ~PSR_CARRY;
1401#else
060366c5 1402 env->psr &= ~PSR_CARRY;
27908725 1403#endif
060366c5
FB		 1404 }
1405 env->regwptr[0] = ret;
1406 /* next instruction */
1407 env->pc = env->npc;
1408 env->npc = env->npc + 4;
1409 break;
1410 case 0x83: /* flush windows */
992f48a0
BS		 1411#ifdef TARGET_ABI32
1412 case 0x103:
1413#endif
2623cbaf 1414 flush_windows(env);
060366c5
FB		 1415 /* next instruction */
1416 env->pc = env->npc;
1417 env->npc = env->npc + 4;
1418 break;
3475187d 1419#ifndef TARGET_SPARC64
060366c5
FB		 1420 case TT_WIN_OVF: /* window overflow */
1421 save_window(env);
1422 break;
1423 case TT_WIN_UNF: /* window underflow */
1424 restore_window(env);
1425 break;
61ff6f58
FB		 1426 case TT_TFAULT:
1427 case TT_DFAULT:
1428 {
59f7182f 1429 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1430 info.si_errno = 0;
1431 /* XXX: check env->error_code */
1432 info.si_code = TARGET_SEGV_MAPERR;
1433 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1434 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1435 }
1436 break;
3475187d 1437#else
5ef54116
FB		 1438 case TT_SPILL: /* window overflow */
1439 save_window(env);
1440 break;
1441 case TT_FILL: /* window underflow */
1442 restore_window(env);
1443 break;
7f84a729
BS		 1444 case TT_TFAULT:
1445 case TT_DFAULT:
1446 {
59f7182f 1447 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1448 info.si_errno = 0;
1449 /* XXX: check env->error_code */
1450 info.si_code = TARGET_SEGV_MAPERR;
1451 if (trapnr == TT_DFAULT)
1452 info._sifields._sigfault._addr = env->dmmuregs[4];
1453 else
8194f35a 1454 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1455 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1456 }
1457 break;
27524dc3 1458#ifndef TARGET_ABI32
5bfb56b2
BS		 1459 case 0x16e:
1460 flush_windows(env);
1461 sparc64_get_context(env);
1462 break;
1463 case 0x16f:
1464 flush_windows(env);
1465 sparc64_set_context(env);
1466 break;
27524dc3 1467#endif
3475187d 1468#endif
48dc41eb
FB		 1469 case EXCP_INTERRUPT:
1470 /* just indicate that signals should be handled asap */
1471 break;
75f22e4e
RH		 1472 case TT_ILL_INSN:
1473 {
1474 info.si_signo = TARGET_SIGILL;
1475 info.si_errno = 0;
1476 info.si_code = TARGET_ILL_ILLOPC;
1477 info._sifields._sigfault._addr = env->pc;
1478 queue_signal(env, info.si_signo, &info);
1479 }
1480 break;
1fddef4b
FB		 1481 case EXCP_DEBUG:
1482 {
1483 int sig;
1484
db6b81d4 1485 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1486 if (sig)
1487 {
1488 info.si_signo = sig;
1489 info.si_errno = 0;
1490 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1491 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1492 }
1493 }
1494 break;
060366c5
FB		 1495 default:
1496 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1497 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 1498 exit(EXIT_FAILURE);
060366c5
FB		 1499 }
1500 process_pending_signals (env);
1501 }
93ac68bc
FB		 1502}
1503
1504#endif
1505
67867308 1506#ifdef TARGET_PPC
05390248 1507static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1508{
4a7428c5 1509 return cpu_get_host_ticks();
9fddaa0c 1510}
3b46e624 1511
05390248 1512uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1513{
e3ea6529 1514 return cpu_ppc_get_tb(env);
9fddaa0c 1515}
3b46e624 1516
05390248 1517uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1518{
1519 return cpu_ppc_get_tb(env) >> 32;
1520}
3b46e624 1521
05390248 1522uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1523{
b711de95 1524 return cpu_ppc_get_tb(env);
9fddaa0c 1525}
5fafdf24 1526
05390248 1527uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1528{
a062e36c 1529 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1530}
76a66253 1531
05390248 1532uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1533__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1534
05390248 1535uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1536{
76a66253 1537 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1538}
76a66253 1539
a750fc0b 1540/* XXX: to be fixed */
73b01960 1541int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1542{
1543 return -1;
1544}
1545
73b01960 1546int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1547{
1548 return -1;
1549}
1550
56f066bb
NF		 1551static int do_store_exclusive(CPUPPCState *env)
1552{
1553 target_ulong addr;
1554 target_ulong page_addr;
e22c357b 1555 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1556 int flags;
1557 int segv = 0;
1558
1559 addr = env->reserve_ea;
1560 page_addr = addr & TARGET_PAGE_MASK;
1561 start_exclusive();
1562 mmap_lock();
1563 flags = page_get_flags(page_addr);
1564 if ((flags & PAGE_READ) == 0) {
1565 segv = 1;
1566 } else {
1567 int reg = env->reserve_info & 0x1f;
4b1daa72 1568 int size = env->reserve_info >> 5;
56f066bb
NF		 1569 int stored = 0;
1570
1571 if (addr == env->reserve_addr) {
1572 switch (size) {
1573 case 1: segv = get_user_u8(val, addr); break;
1574 case 2: segv = get_user_u16(val, addr); break;
1575 case 4: segv = get_user_u32(val, addr); break;
1576#if defined(TARGET_PPC64)
1577 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1578 case 16: {
1579 segv = get_user_u64(val, addr);
1580 if (!segv) {
1581 segv = get_user_u64(val2, addr + 8);
1582 }
1583 break;
1584 }
56f066bb
NF		 1585#endif
1586 default: abort();
1587 }
1588 if (!segv && val == env->reserve_val) {
1589 val = env->gpr[reg];
1590 switch (size) {
1591 case 1: segv = put_user_u8(val, addr); break;
1592 case 2: segv = put_user_u16(val, addr); break;
1593 case 4: segv = put_user_u32(val, addr); break;
1594#if defined(TARGET_PPC64)
1595 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1596 case 16: {
1597 if (val2 == env->reserve_val2) {
e22c357b
DK		 1598 if (msr_le) {
1599 val2 = val;
1600 val = env->gpr[reg+1];
1601 } else {
1602 val2 = env->gpr[reg+1];
1603 }
27b95bfe
TM		 1604 segv = put_user_u64(val, addr);
1605 if (!segv) {
1606 segv = put_user_u64(val2, addr + 8);
1607 }
1608 }
1609 break;
1610 }
56f066bb
NF		 1611#endif
1612 default: abort();
1613 }
1614 if (!segv) {
1615 stored = 1;
1616 }
1617 }
1618 }
1619 env->crf[0] = (stored << 1) | xer_so;
1620 env->reserve_addr = (target_ulong)-1;
1621 }
1622 if (!segv) {
1623 env->nip += 4;
1624 }
1625 mmap_unlock();
1626 end_exclusive();
1627 return segv;
1628}
1629
67867308
FB		 1630void cpu_loop(CPUPPCState *env)
1631{
0315c31c 1632 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1633 target_siginfo_t info;
61190b14 1634 int trapnr;
9e0e2f96 1635 target_ulong ret;
3b46e624 1636
67867308 1637 for(;;) {
0315c31c 1638 cpu_exec_start(cs);
8642c1b8 1639 trapnr = cpu_exec(cs);
0315c31c 1640 cpu_exec_end(cs);
67867308 1641 switch(trapnr) {
e1833e1f
JM		 1642 case POWERPC_EXCP_NONE:
1643 /* Just go on */
67867308 1644 break;
e1833e1f 1645 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1646 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1647 "Aborting\n");
61190b14 1648 break;
e1833e1f 1649 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1650 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1651 "Aborting\n");
1652 break;
1653 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1654 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1655 env->spr[SPR_DAR]);
1656 /* XXX: check this. Seems bugged */
2be0071f
FB		 1657 switch (env->error_code & 0xFF000000) {
1658 case 0x40000000:
61190b14
FB		 1659 info.si_signo = TARGET_SIGSEGV;
1660 info.si_errno = 0;
1661 info.si_code = TARGET_SEGV_MAPERR;
1662 break;
2be0071f 1663 case 0x04000000:
61190b14
FB		 1664 info.si_signo = TARGET_SIGILL;
1665 info.si_errno = 0;
1666 info.si_code = TARGET_ILL_ILLADR;
1667 break;
2be0071f 1668 case 0x08000000:
61190b14
FB		 1669 info.si_signo = TARGET_SIGSEGV;
1670 info.si_errno = 0;
1671 info.si_code = TARGET_SEGV_ACCERR;
1672 break;
61190b14
FB		 1673 default:
1674 /* Let's send a regular segfault... */
e1833e1f
JM		 1675 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1676 env->error_code);
61190b14
FB		 1677 info.si_signo = TARGET_SIGSEGV;
1678 info.si_errno = 0;
1679 info.si_code = TARGET_SEGV_MAPERR;
1680 break;
1681 }
67867308 1682 info._sifields._sigfault._addr = env->nip;
624f7979 1683 queue_signal(env, info.si_signo, &info);
67867308 1684 break;
e1833e1f 1685 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1686 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1687 "\n", env->spr[SPR_SRR0]);
e1833e1f 1688 /* XXX: check this */
2be0071f
FB		 1689 switch (env->error_code & 0xFF000000) {
1690 case 0x40000000:
61190b14 1691 info.si_signo = TARGET_SIGSEGV;
67867308 1692 info.si_errno = 0;
61190b14
FB		 1693 info.si_code = TARGET_SEGV_MAPERR;
1694 break;
2be0071f
FB		 1695 case 0x10000000:
1696 case 0x08000000:
61190b14
FB		 1697 info.si_signo = TARGET_SIGSEGV;
1698 info.si_errno = 0;
1699 info.si_code = TARGET_SEGV_ACCERR;
1700 break;
1701 default:
1702 /* Let's send a regular segfault... */
e1833e1f
JM		 1703 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1704 env->error_code);
61190b14
FB		 1705 info.si_signo = TARGET_SIGSEGV;
1706 info.si_errno = 0;
1707 info.si_code = TARGET_SEGV_MAPERR;
1708 break;
1709 }
1710 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1711 queue_signal(env, info.si_signo, &info);
67867308 1712 break;
e1833e1f 1713 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1714 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1715 "Aborting\n");
1716 break;
1717 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1718 EXCP_DUMP(env, "Unaligned memory access\n");
1719 /* XXX: check this */
61190b14 1720 info.si_signo = TARGET_SIGBUS;
67867308 1721 info.si_errno = 0;
61190b14 1722 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1723 info._sifields._sigfault._addr = env->nip;
624f7979 1724 queue_signal(env, info.si_signo, &info);
67867308 1725 break;
e1833e1f 1726 case POWERPC_EXCP_PROGRAM: /* Program exception */
9b2fadda 1727 case POWERPC_EXCP_HV_EMU: /* HV emulation */
e1833e1f 1728 /* XXX: check this */
61190b14 1729 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1730 case POWERPC_EXCP_FP:
1731 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1732 info.si_signo = TARGET_SIGFPE;
1733 info.si_errno = 0;
1734 switch (env->error_code & 0xF) {
e1833e1f 1735 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1736 info.si_code = TARGET_FPE_FLTOVF;
1737 break;
e1833e1f 1738 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1739 info.si_code = TARGET_FPE_FLTUND;
1740 break;
e1833e1f
JM		 1741 case POWERPC_EXCP_FP_ZX:
1742 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1743 info.si_code = TARGET_FPE_FLTDIV;
1744 break;
e1833e1f 1745 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1746 info.si_code = TARGET_FPE_FLTRES;
1747 break;
e1833e1f 1748 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1749 info.si_code = TARGET_FPE_FLTINV;
1750 break;
7c58044c 1751 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1752 case POWERPC_EXCP_FP_VXISI:
1753 case POWERPC_EXCP_FP_VXIDI:
1754 case POWERPC_EXCP_FP_VXIMZ:
1755 case POWERPC_EXCP_FP_VXVC:
1756 case POWERPC_EXCP_FP_VXSQRT:
1757 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1758 info.si_code = TARGET_FPE_FLTSUB;
1759 break;
1760 default:
e1833e1f
JM		 1761 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1762 env->error_code);
1763 break;
61190b14 1764 }
e1833e1f
JM		 1765 break;
1766 case POWERPC_EXCP_INVAL:
1767 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1768 info.si_signo = TARGET_SIGILL;
1769 info.si_errno = 0;
1770 switch (env->error_code & 0xF) {
e1833e1f 1771 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1772 info.si_code = TARGET_ILL_ILLOPC;
1773 break;
e1833e1f 1774 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1775 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1776 break;
e1833e1f 1777 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1778 info.si_code = TARGET_ILL_PRVREG;
1779 break;
e1833e1f 1780 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1781 info.si_code = TARGET_ILL_COPROC;
1782 break;
1783 default:
e1833e1f
JM		 1784 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1785 env->error_code & 0xF);
61190b14
FB		 1786 info.si_code = TARGET_ILL_ILLADR;
1787 break;
1788 }
1789 break;
e1833e1f
JM		 1790 case POWERPC_EXCP_PRIV:
1791 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1792 info.si_signo = TARGET_SIGILL;
1793 info.si_errno = 0;
1794 switch (env->error_code & 0xF) {
e1833e1f 1795 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1796 info.si_code = TARGET_ILL_PRVOPC;
1797 break;
e1833e1f 1798 case POWERPC_EXCP_PRIV_REG:
61190b14 1799 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1800 break;
61190b14 1801 default:
e1833e1f
JM		 1802 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1803 env->error_code & 0xF);
61190b14
FB		 1804 info.si_code = TARGET_ILL_PRVOPC;
1805 break;
1806 }
1807 break;
e1833e1f 1808 case POWERPC_EXCP_TRAP:
a47dddd7 1809 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1810 break;
61190b14
FB		 1811 default:
1812 /* Should not happen ! */
a47dddd7 1813 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1814 env->error_code);
1815 break;
61190b14
FB		 1816 }
1817 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1818 queue_signal(env, info.si_signo, &info);
67867308 1819 break;
e1833e1f
JM		 1820 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1821 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1822 info.si_signo = TARGET_SIGILL;
67867308 1823 info.si_errno = 0;
61190b14
FB		 1824 info.si_code = TARGET_ILL_COPROC;
1825 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1826 queue_signal(env, info.si_signo, &info);
67867308 1827 break;
e1833e1f 1828 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1829 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1830 "Aborting\n");
61190b14 1831 break;
e1833e1f
JM		 1832 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1833 EXCP_DUMP(env, "No APU instruction allowed\n");
1834 info.si_signo = TARGET_SIGILL;
1835 info.si_errno = 0;
1836 info.si_code = TARGET_ILL_COPROC;
1837 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1838 queue_signal(env, info.si_signo, &info);
61190b14 1839 break;
e1833e1f 1840 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1841 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1842 "Aborting\n");
61190b14 1843 break;
e1833e1f 1844 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1845 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1846 "Aborting\n");
1847 break;
1848 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1849 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1850 "Aborting\n");
1851 break;
1852 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1853 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1854 "Aborting\n");
1855 break;
1856 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1857 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1858 "Aborting\n");
1859 break;
e1833e1f
JM		 1860 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1861 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1862 info.si_signo = TARGET_SIGILL;
1863 info.si_errno = 0;
1864 info.si_code = TARGET_ILL_COPROC;
1865 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1866 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1867 break;
1868 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1869 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1870 break;
1871 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1872 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1873 break;
1874 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1875 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1876 break;
1877 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1878 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1879 "Aborting\n");
1880 break;
1881 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1882 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1883 "Aborting\n");
1884 break;
1885 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1886 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1887 "Aborting\n");
1888 break;
e1833e1f 1889 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1890 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1891 "Aborting\n");
1892 break;
1893 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1894 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1895 "while in user mode. Aborting\n");
1896 break;
e85e7c6e 1897 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1898 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1899 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1900 "while in user mode. Aborting\n");
1901 break;
e1833e1f
JM		 1902 case POWERPC_EXCP_TRACE: /* Trace exception */
1903 /* Nothing to do:
1904 * we use this exception to emulate step-by-step execution mode.
1905 */
1906 break;
e85e7c6e 1907 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1908 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1909 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1910 "while in user mode. Aborting\n");
1911 break;
1912 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1913 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1914 "while in user mode. Aborting\n");
1915 break;
1916 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1917 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1918 "while in user mode. Aborting\n");
1919 break;
1920 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1921 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1922 "while in user mode. Aborting\n");
1923 break;
e1833e1f
JM		 1924 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1925 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1926 info.si_signo = TARGET_SIGILL;
1927 info.si_errno = 0;
1928 info.si_code = TARGET_ILL_COPROC;
1929 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1930 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1931 break;
1932 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1933 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1934 "while in user mode. Aborting\n");
1935 break;
1936 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1937 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1938 "Aborting\n");
1939 break;
1940 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1941 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1942 "Aborting\n");
1943 break;
1944 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1945 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1946 break;
1947 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1948 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1949 "while in user-mode. Aborting");
1950 break;
1951 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1952 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1953 "Aborting");
1954 break;
1955 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1956 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1957 "Aborting");
1958 break;
1959 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1960 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1961 break;
1962 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1963 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1964 "not handled\n");
1965 break;
1966 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1967 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1968 "Aborting\n");
1969 break;
1970 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1971 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1972 "Aborting\n");
1973 break;
1974 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1975 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1976 break;
1977 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1978 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1979 break;
1980 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1981 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1982 break;
1983 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1984 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1985 "Aborting\n");
1986 break;
1987 case POWERPC_EXCP_STOP: /* stop translation */
1988 /* We did invalidate the instruction cache. Go on */
1989 break;
1990 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1991 /* We just stopped because of a branch. Go on */
1992 break;
1993 case POWERPC_EXCP_SYSCALL_USER:
1994 /* system call in user-mode emulation */
1995 /* WARNING:
1996 * PPC ABI uses overflow flag in cr0 to signal an error
1997 * in syscalls.
1998 */
e1833e1f
JM		 1999 env->crf[0] &= ~0x1;
2000 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
2001 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 2002 env->gpr[8], 0, 0);
6db9d00e
TB		 2003 if (ret == -TARGET_ERESTARTSYS) {
2004 env->nip -= 4;
2005 break;
2006 }
9e0e2f96 2007 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 2008 /* Returning from a successful sigreturn syscall.
2009 Avoid corrupting register state. */
2010 break;
2011 }
9e0e2f96 2012 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 2013 env->crf[0] |= 0x1;
2014 ret = -ret;
61190b14 2015 }
e1833e1f 2016 env->gpr[3] = ret;
e1833e1f 2017 break;
56f066bb
NF		 2018 case POWERPC_EXCP_STCX:
2019 if (do_store_exclusive(env)) {
2020 info.si_signo = TARGET_SIGSEGV;
2021 info.si_errno = 0;
2022 info.si_code = TARGET_SEGV_MAPERR;
2023 info._sifields._sigfault._addr = env->nip;
2024 queue_signal(env, info.si_signo, &info);
2025 }
2026 break;
71f75756
AJ		 2027 case EXCP_DEBUG:
2028 {
2029 int sig;
2030
db6b81d4 2031 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 2032 if (sig) {
2033 info.si_signo = sig;
2034 info.si_errno = 0;
2035 info.si_code = TARGET_TRAP_BRKPT;
2036 queue_signal(env, info.si_signo, &info);
2037 }
2038 }
2039 break;
56ba31ff
JM		 2040 case EXCP_INTERRUPT:
2041 /* just indicate that signals should be handled asap */
2042 break;
e1833e1f 2043 default:
a47dddd7 2044 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 2045 break;
67867308
FB		 2046 }
2047 process_pending_signals(env);
2048 }
2049}
2050#endif
2051
048f6b4d
FB		 2052#ifdef TARGET_MIPS
2053
ff4f7382
RH		 2054# ifdef TARGET_ABI_MIPSO32
2055# define MIPS_SYS(name, args) args,
048f6b4d 2056static const uint8_t mips_syscall_args[] = {
29fb0f25 2057 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 2058 MIPS_SYS(sys_exit , 1)
2059 MIPS_SYS(sys_fork , 0)
2060 MIPS_SYS(sys_read , 3)
2061 MIPS_SYS(sys_write , 3)
2062 MIPS_SYS(sys_open , 3) /* 4005 */
2063 MIPS_SYS(sys_close , 1)
2064 MIPS_SYS(sys_waitpid , 3)
2065 MIPS_SYS(sys_creat , 2)
2066 MIPS_SYS(sys_link , 2)
2067 MIPS_SYS(sys_unlink , 1) /* 4010 */
2068 MIPS_SYS(sys_execve , 0)
2069 MIPS_SYS(sys_chdir , 1)
2070 MIPS_SYS(sys_time , 1)
2071 MIPS_SYS(sys_mknod , 3)
2072 MIPS_SYS(sys_chmod , 2) /* 4015 */
2073 MIPS_SYS(sys_lchown , 3)
2074 MIPS_SYS(sys_ni_syscall , 0)
2075 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2076 MIPS_SYS(sys_lseek , 3)
2077 MIPS_SYS(sys_getpid , 0) /* 4020 */
2078 MIPS_SYS(sys_mount , 5)
868e34d7 2079 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2080 MIPS_SYS(sys_setuid , 1)
2081 MIPS_SYS(sys_getuid , 0)
2082 MIPS_SYS(sys_stime , 1) /* 4025 */
2083 MIPS_SYS(sys_ptrace , 4)
2084 MIPS_SYS(sys_alarm , 1)
2085 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2086 MIPS_SYS(sys_pause , 0)
2087 MIPS_SYS(sys_utime , 2) /* 4030 */
2088 MIPS_SYS(sys_ni_syscall , 0)
2089 MIPS_SYS(sys_ni_syscall , 0)
2090 MIPS_SYS(sys_access , 2)
2091 MIPS_SYS(sys_nice , 1)
2092 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2093 MIPS_SYS(sys_sync , 0)
2094 MIPS_SYS(sys_kill , 2)
2095 MIPS_SYS(sys_rename , 2)
2096 MIPS_SYS(sys_mkdir , 2)
2097 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2098 MIPS_SYS(sys_dup , 1)
2099 MIPS_SYS(sys_pipe , 0)
2100 MIPS_SYS(sys_times , 1)
2101 MIPS_SYS(sys_ni_syscall , 0)
2102 MIPS_SYS(sys_brk , 1) /* 4045 */
2103 MIPS_SYS(sys_setgid , 1)
2104 MIPS_SYS(sys_getgid , 0)
2105 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2106 MIPS_SYS(sys_geteuid , 0)
2107 MIPS_SYS(sys_getegid , 0) /* 4050 */
2108 MIPS_SYS(sys_acct , 0)
868e34d7 2109 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2110 MIPS_SYS(sys_ni_syscall , 0)
2111 MIPS_SYS(sys_ioctl , 3)
2112 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2113 MIPS_SYS(sys_ni_syscall , 2)
2114 MIPS_SYS(sys_setpgid , 2)
2115 MIPS_SYS(sys_ni_syscall , 0)
2116 MIPS_SYS(sys_olduname , 1)
2117 MIPS_SYS(sys_umask , 1) /* 4060 */
2118 MIPS_SYS(sys_chroot , 1)
2119 MIPS_SYS(sys_ustat , 2)
2120 MIPS_SYS(sys_dup2 , 2)
2121 MIPS_SYS(sys_getppid , 0)
2122 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2123 MIPS_SYS(sys_setsid , 0)
2124 MIPS_SYS(sys_sigaction , 3)
2125 MIPS_SYS(sys_sgetmask , 0)
2126 MIPS_SYS(sys_ssetmask , 1)
2127 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2128 MIPS_SYS(sys_setregid , 2)
2129 MIPS_SYS(sys_sigsuspend , 0)
2130 MIPS_SYS(sys_sigpending , 1)
2131 MIPS_SYS(sys_sethostname , 2)
2132 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2133 MIPS_SYS(sys_getrlimit , 2)
2134 MIPS_SYS(sys_getrusage , 2)
2135 MIPS_SYS(sys_gettimeofday, 2)
2136 MIPS_SYS(sys_settimeofday, 2)
2137 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2138 MIPS_SYS(sys_setgroups , 2)
2139 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2140 MIPS_SYS(sys_symlink , 2)
2141 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2142 MIPS_SYS(sys_readlink , 3) /* 4085 */
2143 MIPS_SYS(sys_uselib , 1)
2144 MIPS_SYS(sys_swapon , 2)
2145 MIPS_SYS(sys_reboot , 3)
2146 MIPS_SYS(old_readdir , 3)
2147 MIPS_SYS(old_mmap , 6) /* 4090 */
2148 MIPS_SYS(sys_munmap , 2)
2149 MIPS_SYS(sys_truncate , 2)
2150 MIPS_SYS(sys_ftruncate , 2)
2151 MIPS_SYS(sys_fchmod , 2)
2152 MIPS_SYS(sys_fchown , 3) /* 4095 */
2153 MIPS_SYS(sys_getpriority , 2)
2154 MIPS_SYS(sys_setpriority , 3)
2155 MIPS_SYS(sys_ni_syscall , 0)
2156 MIPS_SYS(sys_statfs , 2)
2157 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2158 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2159 MIPS_SYS(sys_socketcall , 2)
2160 MIPS_SYS(sys_syslog , 3)
2161 MIPS_SYS(sys_setitimer , 3)
2162 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2163 MIPS_SYS(sys_newstat , 2)
2164 MIPS_SYS(sys_newlstat , 2)
2165 MIPS_SYS(sys_newfstat , 2)
2166 MIPS_SYS(sys_uname , 1)
2167 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2168 MIPS_SYS(sys_vhangup , 0)
2169 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2170 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2171 MIPS_SYS(sys_wait4 , 4)
2172 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2173 MIPS_SYS(sys_sysinfo , 1)
2174 MIPS_SYS(sys_ipc , 6)
2175 MIPS_SYS(sys_fsync , 1)
2176 MIPS_SYS(sys_sigreturn , 0)
18113962 2177 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2178 MIPS_SYS(sys_setdomainname, 2)
2179 MIPS_SYS(sys_newuname , 1)
2180 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2181 MIPS_SYS(sys_adjtimex , 1)
2182 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2183 MIPS_SYS(sys_sigprocmask , 3)
2184 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2185 MIPS_SYS(sys_init_module , 5)
2186 MIPS_SYS(sys_delete_module, 1)
2187 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2188 MIPS_SYS(sys_quotactl , 0)
2189 MIPS_SYS(sys_getpgid , 1)
2190 MIPS_SYS(sys_fchdir , 1)
2191 MIPS_SYS(sys_bdflush , 2)
2192 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2193 MIPS_SYS(sys_personality , 1)
2194 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2195 MIPS_SYS(sys_setfsuid , 1)
2196 MIPS_SYS(sys_setfsgid , 1)
2197 MIPS_SYS(sys_llseek , 5) /* 4140 */
2198 MIPS_SYS(sys_getdents , 3)
2199 MIPS_SYS(sys_select , 5)
2200 MIPS_SYS(sys_flock , 2)
2201 MIPS_SYS(sys_msync , 3)
2202 MIPS_SYS(sys_readv , 3) /* 4145 */
2203 MIPS_SYS(sys_writev , 3)
2204 MIPS_SYS(sys_cacheflush , 3)
2205 MIPS_SYS(sys_cachectl , 3)
2206 MIPS_SYS(sys_sysmips , 4)
2207 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2208 MIPS_SYS(sys_getsid , 1)
2209 MIPS_SYS(sys_fdatasync , 0)
2210 MIPS_SYS(sys_sysctl , 1)
2211 MIPS_SYS(sys_mlock , 2)
2212 MIPS_SYS(sys_munlock , 2) /* 4155 */
2213 MIPS_SYS(sys_mlockall , 1)
2214 MIPS_SYS(sys_munlockall , 0)
2215 MIPS_SYS(sys_sched_setparam, 2)
2216 MIPS_SYS(sys_sched_getparam, 2)
2217 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2218 MIPS_SYS(sys_sched_getscheduler, 1)
2219 MIPS_SYS(sys_sched_yield , 0)
2220 MIPS_SYS(sys_sched_get_priority_max, 1)
2221 MIPS_SYS(sys_sched_get_priority_min, 1)
2222 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2223 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2224 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2225 MIPS_SYS(sys_accept , 3)
2226 MIPS_SYS(sys_bind , 3)
2227 MIPS_SYS(sys_connect , 3) /* 4170 */
2228 MIPS_SYS(sys_getpeername , 3)
2229 MIPS_SYS(sys_getsockname , 3)
2230 MIPS_SYS(sys_getsockopt , 5)
2231 MIPS_SYS(sys_listen , 2)
2232 MIPS_SYS(sys_recv , 4) /* 4175 */
2233 MIPS_SYS(sys_recvfrom , 6)
2234 MIPS_SYS(sys_recvmsg , 3)
2235 MIPS_SYS(sys_send , 4)
2236 MIPS_SYS(sys_sendmsg , 3)
2237 MIPS_SYS(sys_sendto , 6) /* 4180 */
2238 MIPS_SYS(sys_setsockopt , 5)
2239 MIPS_SYS(sys_shutdown , 2)
2240 MIPS_SYS(sys_socket , 3)
2241 MIPS_SYS(sys_socketpair , 4)
2242 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2243 MIPS_SYS(sys_getresuid , 3)
2244 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2245 MIPS_SYS(sys_poll , 3)
2246 MIPS_SYS(sys_nfsservctl , 3)
2247 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2248 MIPS_SYS(sys_getresgid , 3)
2249 MIPS_SYS(sys_prctl , 5)
2250 MIPS_SYS(sys_rt_sigreturn, 0)
2251 MIPS_SYS(sys_rt_sigaction, 4)
2252 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2253 MIPS_SYS(sys_rt_sigpending, 2)
2254 MIPS_SYS(sys_rt_sigtimedwait, 4)
2255 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2256 MIPS_SYS(sys_rt_sigsuspend, 0)
2257 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2258 MIPS_SYS(sys_pwrite64 , 6)
2259 MIPS_SYS(sys_chown , 3)
2260 MIPS_SYS(sys_getcwd , 2)
2261 MIPS_SYS(sys_capget , 2)
2262 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2263 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2264 MIPS_SYS(sys_sendfile , 4)
2265 MIPS_SYS(sys_ni_syscall , 0)
2266 MIPS_SYS(sys_ni_syscall , 0)
2267 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2268 MIPS_SYS(sys_truncate64 , 4)
2269 MIPS_SYS(sys_ftruncate64 , 4)
2270 MIPS_SYS(sys_stat64 , 2)
2271 MIPS_SYS(sys_lstat64 , 2)
2272 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2273 MIPS_SYS(sys_pivot_root , 2)
2274 MIPS_SYS(sys_mincore , 3)
2275 MIPS_SYS(sys_madvise , 3)
2276 MIPS_SYS(sys_getdents64 , 3)
2277 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2278 MIPS_SYS(sys_ni_syscall , 0)
2279 MIPS_SYS(sys_gettid , 0)
2280 MIPS_SYS(sys_readahead , 5)
2281 MIPS_SYS(sys_setxattr , 5)
2282 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2283 MIPS_SYS(sys_fsetxattr , 5)
2284 MIPS_SYS(sys_getxattr , 4)
2285 MIPS_SYS(sys_lgetxattr , 4)
2286 MIPS_SYS(sys_fgetxattr , 4)
2287 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2288 MIPS_SYS(sys_llistxattr , 3)
2289 MIPS_SYS(sys_flistxattr , 3)
2290 MIPS_SYS(sys_removexattr , 2)
2291 MIPS_SYS(sys_lremovexattr, 2)
2292 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2293 MIPS_SYS(sys_tkill , 2)
2294 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2295 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2296 MIPS_SYS(sys_sched_setaffinity, 3)
2297 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2298 MIPS_SYS(sys_io_setup , 2)
2299 MIPS_SYS(sys_io_destroy , 1)
2300 MIPS_SYS(sys_io_getevents, 5)
2301 MIPS_SYS(sys_io_submit , 3)
2302 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2303 MIPS_SYS(sys_exit_group , 1)
2304 MIPS_SYS(sys_lookup_dcookie, 3)
2305 MIPS_SYS(sys_epoll_create, 1)
2306 MIPS_SYS(sys_epoll_ctl , 4)
2307 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2308 MIPS_SYS(sys_remap_file_pages, 5)
2309 MIPS_SYS(sys_set_tid_address, 1)
2310 MIPS_SYS(sys_restart_syscall, 0)
2311 MIPS_SYS(sys_fadvise64_64, 7)
2312 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2313 MIPS_SYS(sys_fstatfs64 , 2)
2314 MIPS_SYS(sys_timer_create, 3)
2315 MIPS_SYS(sys_timer_settime, 4)
2316 MIPS_SYS(sys_timer_gettime, 2)
2317 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2318 MIPS_SYS(sys_timer_delete, 1)
2319 MIPS_SYS(sys_clock_settime, 2)
2320 MIPS_SYS(sys_clock_gettime, 2)
2321 MIPS_SYS(sys_clock_getres, 2)
2322 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2323 MIPS_SYS(sys_tgkill , 3)
2324 MIPS_SYS(sys_utimes , 2)
2325 MIPS_SYS(sys_mbind , 4)
2326 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2327 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2328 MIPS_SYS(sys_mq_open , 4)
2329 MIPS_SYS(sys_mq_unlink , 1)
2330 MIPS_SYS(sys_mq_timedsend, 5)
2331 MIPS_SYS(sys_mq_timedreceive, 5)
2332 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2333 MIPS_SYS(sys_mq_getsetattr, 3)
2334 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2335 MIPS_SYS(sys_waitid , 4)
2336 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2337 MIPS_SYS(sys_add_key , 5)
388bb21a 2338 MIPS_SYS(sys_request_key, 4)
048f6b4d 2339 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2340 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2341 MIPS_SYS(sys_inotify_init, 0)
2342 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2343 MIPS_SYS(sys_inotify_rm_watch, 2)
2344 MIPS_SYS(sys_migrate_pages, 4)
2345 MIPS_SYS(sys_openat, 4)
2346 MIPS_SYS(sys_mkdirat, 3)
2347 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2348 MIPS_SYS(sys_fchownat, 5)
2349 MIPS_SYS(sys_futimesat, 3)
2350 MIPS_SYS(sys_fstatat64, 4)
2351 MIPS_SYS(sys_unlinkat, 3)
2352 MIPS_SYS(sys_renameat, 4) /* 4295 */
2353 MIPS_SYS(sys_linkat, 5)
2354 MIPS_SYS(sys_symlinkat, 3)
2355 MIPS_SYS(sys_readlinkat, 4)
2356 MIPS_SYS(sys_fchmodat, 3)
2357 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2358 MIPS_SYS(sys_pselect6, 6)
2359 MIPS_SYS(sys_ppoll, 5)
2360 MIPS_SYS(sys_unshare, 1)
b0932e06 2361 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2362 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2363 MIPS_SYS(sys_tee, 4)
2364 MIPS_SYS(sys_vmsplice, 4)
2365 MIPS_SYS(sys_move_pages, 6)
2366 MIPS_SYS(sys_set_robust_list, 2)
2367 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2368 MIPS_SYS(sys_kexec_load, 4)
2369 MIPS_SYS(sys_getcpu, 3)
2370 MIPS_SYS(sys_epoll_pwait, 6)
2371 MIPS_SYS(sys_ioprio_set, 3)
2372 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2373 MIPS_SYS(sys_utimensat, 4)
2374 MIPS_SYS(sys_signalfd, 3)
2375 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2376 MIPS_SYS(sys_eventfd, 1)
2377 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2378 MIPS_SYS(sys_timerfd_create, 2)
2379 MIPS_SYS(sys_timerfd_gettime, 2)
2380 MIPS_SYS(sys_timerfd_settime, 4)
2381 MIPS_SYS(sys_signalfd4, 4)
2382 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2383 MIPS_SYS(sys_epoll_create1, 1)
2384 MIPS_SYS(sys_dup3, 3)
2385 MIPS_SYS(sys_pipe2, 2)
2386 MIPS_SYS(sys_inotify_init1, 1)
2387 MIPS_SYS(sys_preadv, 6) /* 4330 */
2388 MIPS_SYS(sys_pwritev, 6)
2389 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2390 MIPS_SYS(sys_perf_event_open, 5)
2391 MIPS_SYS(sys_accept4, 4)
2392 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2393 MIPS_SYS(sys_fanotify_init, 2)
2394 MIPS_SYS(sys_fanotify_mark, 6)
2395 MIPS_SYS(sys_prlimit64, 4)
2396 MIPS_SYS(sys_name_to_handle_at, 5)
2397 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2398 MIPS_SYS(sys_clock_adjtime, 2)
2399 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2400};
ff4f7382
RH		 2401# undef MIPS_SYS
2402# endif /* O32 */
048f6b4d 2403
590bc601
PB		 2404static int do_store_exclusive(CPUMIPSState *env)
2405{
2406 target_ulong addr;
2407 target_ulong page_addr;
2408 target_ulong val;
2409 int flags;
2410 int segv = 0;
2411 int reg;
2412 int d;
2413
5499b6ff 2414 addr = env->lladdr;
590bc601
PB		 2415 page_addr = addr & TARGET_PAGE_MASK;
2416 start_exclusive();
2417 mmap_lock();
2418 flags = page_get_flags(page_addr);
2419 if ((flags & PAGE_READ) == 0) {
2420 segv = 1;
2421 } else {
2422 reg = env->llreg & 0x1f;
2423 d = (env->llreg & 0x20) != 0;
2424 if (d) {
2425 segv = get_user_s64(val, addr);
2426 } else {
2427 segv = get_user_s32(val, addr);
2428 }
2429 if (!segv) {
2430 if (val != env->llval) {
2431 env->active_tc.gpr[reg] = 0;
2432 } else {
2433 if (d) {
2434 segv = put_user_u64(env->llnewval, addr);
2435 } else {
2436 segv = put_user_u32(env->llnewval, addr);
2437 }
2438 if (!segv) {
2439 env->active_tc.gpr[reg] = 1;
2440 }
2441 }
2442 }
2443 }
5499b6ff 2444 env->lladdr = -1;
590bc601
PB		 2445 if (!segv) {
2446 env->active_tc.PC += 4;
2447 }
2448 mmap_unlock();
2449 end_exclusive();
2450 return segv;
2451}
2452
54b2f42c
MI		 2453/* Break codes */
2454enum {
2455 BRK_OVERFLOW = 6,
2456 BRK_DIVZERO = 7
2457};
2458
2459static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2460 unsigned int code)
2461{
2462 int ret = -1;
2463
2464 switch (code) {
2465 case BRK_OVERFLOW:
2466 case BRK_DIVZERO:
2467 info->si_signo = TARGET_SIGFPE;
2468 info->si_errno = 0;
2469 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2470 queue_signal(env, info->si_signo, &*info);
2471 ret = 0;
2472 break;
2473 default:
b51910ba
PJ		 2474 info->si_signo = TARGET_SIGTRAP;
2475 info->si_errno = 0;
2476 queue_signal(env, info->si_signo, &*info);
2477 ret = 0;
54b2f42c
MI		 2478 break;
2479 }
2480
2481 return ret;
2482}
2483
048f6b4d
FB		 2484void cpu_loop(CPUMIPSState *env)
2485{
0315c31c 2486 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2487 target_siginfo_t info;
ff4f7382
RH		 2488 int trapnr;
2489 abi_long ret;
2490# ifdef TARGET_ABI_MIPSO32
048f6b4d 2491 unsigned int syscall_num;
ff4f7382 2492# endif
048f6b4d
FB		 2493
2494 for(;;) {
0315c31c 2495 cpu_exec_start(cs);
8642c1b8 2496 trapnr = cpu_exec(cs);
0315c31c 2497 cpu_exec_end(cs);
048f6b4d
FB		 2498 switch(trapnr) {
2499 case EXCP_SYSCALL:
b5dc7732 2500 env->active_tc.PC += 4;
ff4f7382
RH		 2501# ifdef TARGET_ABI_MIPSO32
2502 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2503 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2504 ret = -TARGET_ENOSYS;
388bb21a
TS		 2505 } else {
2506 int nb_args;
992f48a0
BS		 2507 abi_ulong sp_reg;
2508 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2509
2510 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2511 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2512 switch (nb_args) {
2513 /* these arguments are taken from the stack */
94c19610
ACH		 2514 case 8:
2515 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2516 goto done_syscall;
2517 }
2518 case 7:
2519 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2520 goto done_syscall;
2521 }
2522 case 6:
2523 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2524 goto done_syscall;
2525 }
2526 case 5:
2527 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2528 goto done_syscall;
2529 }
388bb21a
TS		 2530 default:
2531 break;
048f6b4d 2532 }
b5dc7732
TS		 2533 ret = do_syscall(env, env->active_tc.gpr[2],
2534 env->active_tc.gpr[4],
2535 env->active_tc.gpr[5],
2536 env->active_tc.gpr[6],
2537 env->active_tc.gpr[7],
5945cfcb 2538 arg5, arg6, arg7, arg8);
388bb21a 2539 }
94c19610 2540done_syscall:
ff4f7382
RH		 2541# else
2542 ret = do_syscall(env, env->active_tc.gpr[2],
2543 env->active_tc.gpr[4], env->active_tc.gpr[5],
2544 env->active_tc.gpr[6], env->active_tc.gpr[7],
2545 env->active_tc.gpr[8], env->active_tc.gpr[9],
2546 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2547# endif /* O32 */
2eb3ae27
TB		 2548 if (ret == -TARGET_ERESTARTSYS) {
2549 env->active_tc.PC -= 4;
2550 break;
2551 }
0b1bcb00
PB		 2552 if (ret == -TARGET_QEMU_ESIGRETURN) {
2553 /* Returning from a successful sigreturn syscall.
2554 Avoid clobbering register state. */
2555 break;
2556 }
ff4f7382 2557 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2558 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2559 ret = -ret;
2560 } else {
b5dc7732 2561 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2562 }
b5dc7732 2563 env->active_tc.gpr[2] = ret;
048f6b4d 2564 break;
ca7c2b1b
TS		 2565 case EXCP_TLBL:
2566 case EXCP_TLBS:
e6e5bd2d
WT		 2567 case EXCP_AdEL:
2568 case EXCP_AdES:
e4474235
PB		 2569 info.si_signo = TARGET_SIGSEGV;
2570 info.si_errno = 0;
2571 /* XXX: check env->error_code */
2572 info.si_code = TARGET_SEGV_MAPERR;
2573 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2574 queue_signal(env, info.si_signo, &info);
2575 break;
6900e84b 2576 case EXCP_CpU:
048f6b4d 2577 case EXCP_RI:
bc1ad2de
FB		 2578 info.si_signo = TARGET_SIGILL;
2579 info.si_errno = 0;
2580 info.si_code = 0;
624f7979 2581 queue_signal(env, info.si_signo, &info);
048f6b4d 2582 break;
106ec879
FB		 2583 case EXCP_INTERRUPT:
2584 /* just indicate that signals should be handled asap */
2585 break;
d08b2a28
PB		 2586 case EXCP_DEBUG:
2587 {
2588 int sig;
2589
db6b81d4 2590 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2591 if (sig)
2592 {
2593 info.si_signo = sig;
2594 info.si_errno = 0;
2595 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2596 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2597 }
2598 }
2599 break;
590bc601
PB		 2600 case EXCP_SC:
2601 if (do_store_exclusive(env)) {
2602 info.si_signo = TARGET_SIGSEGV;
2603 info.si_errno = 0;
2604 info.si_code = TARGET_SEGV_MAPERR;
2605 info._sifields._sigfault._addr = env->active_tc.PC;
2606 queue_signal(env, info.si_signo, &info);
2607 }
2608 break;
853c3240
JL		 2609 case EXCP_DSPDIS:
2610 info.si_signo = TARGET_SIGILL;
2611 info.si_errno = 0;
2612 info.si_code = TARGET_ILL_ILLOPC;
2613 queue_signal(env, info.si_signo, &info);
2614 break;
54b2f42c
MI		 2615 /* The code below was inspired by the MIPS Linux kernel trap
2616 * handling code in arch/mips/kernel/traps.c.
2617 */
2618 case EXCP_BREAK:
2619 {
2620 abi_ulong trap_instr;
2621 unsigned int code;
2622
a0333817
KCY		 2623 if (env->hflags & MIPS_HFLAG_M16) {
2624 if (env->insn_flags & ASE_MICROMIPS) {
2625 /* microMIPS mode */
1308c464
KCY		 2626 ret = get_user_u16(trap_instr, env->active_tc.PC);
2627 if (ret != 0) {
2628 goto error;
2629 }
a0333817 2630
1308c464
KCY		 2631 if ((trap_instr >> 10) == 0x11) {
2632 /* 16-bit instruction */
2633 code = trap_instr & 0xf;
2634 } else {
2635 /* 32-bit instruction */
2636 abi_ulong instr_lo;
2637
2638 ret = get_user_u16(instr_lo,
2639 env->active_tc.PC + 2);
2640 if (ret != 0) {
2641 goto error;
2642 }
2643 trap_instr = (trap_instr << 16) | instr_lo;
2644 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2645 /* Unfortunately, microMIPS also suffers from
2646 the old assembler bug... */
2647 if (code >= (1 << 10)) {
2648 code >>= 10;
2649 }
2650 }
a0333817
KCY		 2651 } else {
2652 /* MIPS16e mode */
2653 ret = get_user_u16(trap_instr, env->active_tc.PC);
2654 if (ret != 0) {
2655 goto error;
2656 }
2657 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2658 }
2659 } else {
f01a361b 2660 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2661 if (ret != 0) {
2662 goto error;
2663 }
54b2f42c 2664
1308c464
KCY		 2665 /* As described in the original Linux kernel code, the
2666 * below checks on 'code' are to work around an old
2667 * assembly bug.
2668 */
2669 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2670 if (code >= (1 << 10)) {
2671 code >>= 10;
2672 }
54b2f42c
MI		 2673 }
2674
2675 if (do_break(env, &info, code) != 0) {
2676 goto error;
2677 }
2678 }
2679 break;
2680 case EXCP_TRAP:
2681 {
2682 abi_ulong trap_instr;
2683 unsigned int code = 0;
2684
a0333817
KCY		 2685 if (env->hflags & MIPS_HFLAG_M16) {
2686 /* microMIPS mode */
2687 abi_ulong instr[2];
2688
2689 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2690 get_user_u16(instr[1], env->active_tc.PC + 2);
2691
2692 trap_instr = (instr[0] << 16) | instr[1];
2693 } else {
f01a361b 2694 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2695 }
2696
54b2f42c
MI		 2697 if (ret != 0) {
2698 goto error;
2699 }
2700
2701 /* The immediate versions don't provide a code. */
2702 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2703 if (env->hflags & MIPS_HFLAG_M16) {
2704 /* microMIPS mode */
2705 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2706 } else {
2707 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2708 }
54b2f42c
MI		 2709 }
2710
2711 if (do_break(env, &info, code) != 0) {
2712 goto error;
2713 }
2714 }
2715 break;
048f6b4d 2716 default:
54b2f42c 2717error:
120a9848 2718 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
048f6b4d
FB		 2719 abort();
2720 }
2721 process_pending_signals(env);
2722 }
2723}
2724#endif
2725
d962783e
JL		 2726#ifdef TARGET_OPENRISC
2727
2728void cpu_loop(CPUOpenRISCState *env)
2729{
878096ee 2730 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e 2731 int trapnr, gdbsig;
7fe7231a 2732 abi_long ret;
d962783e
JL		 2733
2734 for (;;) {
b040bc9c 2735 cpu_exec_start(cs);
8642c1b8 2736 trapnr = cpu_exec(cs);
b040bc9c 2737 cpu_exec_end(cs);
d962783e
JL		 2738 gdbsig = 0;
2739
2740 switch (trapnr) {
2741 case EXCP_RESET:
120a9848 2742 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
4d1275c2 2743 exit(EXIT_FAILURE);
d962783e
JL		 2744 break;
2745 case EXCP_BUSERR:
120a9848 2746 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2747 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2748 break;
2749 case EXCP_DPF:
2750 case EXCP_IPF:
878096ee 2751 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2752 gdbsig = TARGET_SIGSEGV;
2753 break;
2754 case EXCP_TICK:
120a9848 2755 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
d962783e
JL		 2756 break;
2757 case EXCP_ALIGN:
120a9848 2758 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
a86b3c64 2759 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2760 break;
2761 case EXCP_ILLEGAL:
120a9848 2762 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2763 gdbsig = TARGET_SIGILL;
d962783e
JL		 2764 break;
2765 case EXCP_INT:
120a9848 2766 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
d962783e
JL		 2767 break;
2768 case EXCP_DTLBMISS:
2769 case EXCP_ITLBMISS:
120a9848 2770 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
d962783e
JL		 2771 break;
2772 case EXCP_RANGE:
120a9848 2773 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
a86b3c64 2774 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2775 break;
2776 case EXCP_SYSCALL:
2777 env->pc += 4; /* 0xc00; */
7fe7231a
TB		 2778 ret = do_syscall(env,
2779 env->gpr[11], /* return value */
2780 env->gpr[3], /* r3 - r7 are params */
2781 env->gpr[4],
2782 env->gpr[5],
2783 env->gpr[6],
2784 env->gpr[7],
2785 env->gpr[8], 0, 0);
2786 if (ret == -TARGET_ERESTARTSYS) {
2787 env->pc -= 4;
2788 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2789 env->gpr[11] = ret;
2790 }
d962783e
JL		 2791 break;
2792 case EXCP_FPE:
120a9848 2793 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
d962783e
JL		 2794 break;
2795 case EXCP_TRAP:
120a9848 2796 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
a86b3c64 2797 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2798 break;
2799 case EXCP_NR:
120a9848 2800 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
d962783e
JL		 2801 break;
2802 default:
120a9848 2803 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
d962783e 2804 trapnr);
d962783e
JL		 2805 gdbsig = TARGET_SIGILL;
2806 break;
2807 }
2808 if (gdbsig) {
db6b81d4 2809 gdb_handlesig(cs, gdbsig);
d962783e 2810 if (gdbsig != TARGET_SIGTRAP) {
4d1275c2 2811 exit(EXIT_FAILURE);
d962783e
JL		 2812 }
2813 }
2814
2815 process_pending_signals(env);
2816 }
2817}
2818
2819#endif /* TARGET_OPENRISC */
2820
fdf9b3e8 2821#ifdef TARGET_SH4
05390248 2822void cpu_loop(CPUSH4State *env)
fdf9b3e8 2823{
878096ee 2824 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2825 int trapnr, ret;
c227f099 2826 target_siginfo_t info;
3b46e624 2827
fdf9b3e8 2828 while (1) {
b040bc9c 2829 cpu_exec_start(cs);
8642c1b8 2830 trapnr = cpu_exec(cs);
b040bc9c 2831 cpu_exec_end(cs);
3b46e624 2832
fdf9b3e8
FB		 2833 switch (trapnr) {
2834 case 0x160:
0b6d3ae0 2835 env->pc += 2;
5fafdf24
TS		 2836 ret = do_syscall(env,
2837 env->gregs[3],
2838 env->gregs[4],
2839 env->gregs[5],
2840 env->gregs[6],
2841 env->gregs[7],
2842 env->gregs[0],
5945cfcb
PM		 2843 env->gregs[1],
2844 0, 0);
ba412496
TB		 2845 if (ret == -TARGET_ERESTARTSYS) {
2846 env->pc -= 2;
2847 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2848 env->gregs[0] = ret;
2849 }
fdf9b3e8 2850 break;
c3b5bc8a
TS		 2851 case EXCP_INTERRUPT:
2852 /* just indicate that signals should be handled asap */
2853 break;
355fb23d
PB		 2854 case EXCP_DEBUG:
2855 {
2856 int sig;
2857
db6b81d4 2858 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2859 if (sig)
2860 {
2861 info.si_signo = sig;
2862 info.si_errno = 0;
2863 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2864 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2865 }
2866 }
2867 break;
c3b5bc8a
TS		 2868 case 0xa0:
2869 case 0xc0:
a86b3c64 2870 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2871 info.si_errno = 0;
2872 info.si_code = TARGET_SEGV_MAPERR;
2873 info._sifields._sigfault._addr = env->tea;
624f7979 2874 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2875 break;
2876
fdf9b3e8
FB		 2877 default:
2878 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2879 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2880 exit(EXIT_FAILURE);
fdf9b3e8
FB		 2881 }
2882 process_pending_signals (env);
2883 }
2884}
2885#endif
2886
48733d19 2887#ifdef TARGET_CRIS
05390248 2888void cpu_loop(CPUCRISState *env)
48733d19 2889{
878096ee 2890 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2891 int trapnr, ret;
c227f099 2892 target_siginfo_t info;
48733d19
TS		 2893
2894 while (1) {
b040bc9c 2895 cpu_exec_start(cs);
8642c1b8 2896 trapnr = cpu_exec(cs);
b040bc9c 2897 cpu_exec_end(cs);
48733d19
TS		 2898 switch (trapnr) {
2899 case 0xaa:
2900 {
a86b3c64 2901 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2902 info.si_errno = 0;
2903 /* XXX: check env->error_code */
2904 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2905 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2906 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2907 }
2908 break;
b6d3abda
EI		 2909 case EXCP_INTERRUPT:
2910 /* just indicate that signals should be handled asap */
2911 break;
48733d19
TS		 2912 case EXCP_BREAK:
2913 ret = do_syscall(env,
2914 env->regs[9],
2915 env->regs[10],
2916 env->regs[11],
2917 env->regs[12],
2918 env->regs[13],
2919 env->pregs[7],
5945cfcb
PM		 2920 env->pregs[11],
2921 0, 0);
62050865
TB		 2922 if (ret == -TARGET_ERESTARTSYS) {
2923 env->pc -= 2;
2924 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2925 env->regs[10] = ret;
2926 }
48733d19
TS		 2927 break;
2928 case EXCP_DEBUG:
2929 {
2930 int sig;
2931
db6b81d4 2932 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2933 if (sig)
2934 {
2935 info.si_signo = sig;
2936 info.si_errno = 0;
2937 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2938 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2939 }
2940 }
2941 break;
2942 default:
2943 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2944 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2945 exit(EXIT_FAILURE);
48733d19
TS		 2946 }
2947 process_pending_signals (env);
2948 }
2949}
2950#endif
2951
b779e29e 2952#ifdef TARGET_MICROBLAZE
05390248 2953void cpu_loop(CPUMBState *env)
b779e29e 2954{
878096ee 2955 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2956 int trapnr, ret;
c227f099 2957 target_siginfo_t info;
b779e29e
EI		 2958
2959 while (1) {
b040bc9c 2960 cpu_exec_start(cs);
8642c1b8 2961 trapnr = cpu_exec(cs);
b040bc9c 2962 cpu_exec_end(cs);
b779e29e
EI		 2963 switch (trapnr) {
2964 case 0xaa:
2965 {
a86b3c64 2966 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2967 info.si_errno = 0;
2968 /* XXX: check env->error_code */
2969 info.si_code = TARGET_SEGV_MAPERR;
2970 info._sifields._sigfault._addr = 0;
2971 queue_signal(env, info.si_signo, &info);
2972 }
2973 break;
2974 case EXCP_INTERRUPT:
2975 /* just indicate that signals should be handled asap */
2976 break;
2977 case EXCP_BREAK:
2978 /* Return address is 4 bytes after the call. */
2979 env->regs[14] += 4;
d7dce494 2980 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2981 ret = do_syscall(env,
2982 env->regs[12],
2983 env->regs[5],
2984 env->regs[6],
2985 env->regs[7],
2986 env->regs[8],
2987 env->regs[9],
5945cfcb
PM		 2988 env->regs[10],
2989 0, 0);
4134ecfe
TB		 2990 if (ret == -TARGET_ERESTARTSYS) {
2991 /* Wind back to before the syscall. */
2992 env->sregs[SR_PC] -= 4;
2993 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2994 env->regs[3] = ret;
2995 }
d7749ab7
PM		 2996 /* All syscall exits result in guest r14 being equal to the
2997 * PC we return to, because the kernel syscall exit "rtbd" does
2998 * this. (This is true even for sigreturn(); note that r14 is
2999 * not a userspace-usable register, as the kernel may clobber it
3000 * at any point.)
3001 */
3002 env->regs[14] = env->sregs[SR_PC];
b779e29e 3003 break;
b76da7e3
EI		 3004 case EXCP_HW_EXCP:
3005 env->regs[17] = env->sregs[SR_PC] + 4;
3006 if (env->iflags & D_FLAG) {
3007 env->sregs[SR_ESR] |= 1 << 12;
3008 env->sregs[SR_PC] -= 4;
b4916d7b 3009 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 3010 }
3011
3012 env->iflags &= ~(IMM_FLAG | D_FLAG);
3013
3014 switch (env->sregs[SR_ESR] & 31) {
22a78d64 3015 case ESR_EC_DIVZERO:
a86b3c64 3016 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 3017 info.si_errno = 0;
3018 info.si_code = TARGET_FPE_FLTDIV;
3019 info._sifields._sigfault._addr = 0;
3020 queue_signal(env, info.si_signo, &info);
3021 break;
b76da7e3 3022 case ESR_EC_FPU:
a86b3c64 3023 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 3024 info.si_errno = 0;
3025 if (env->sregs[SR_FSR] & FSR_IO) {
3026 info.si_code = TARGET_FPE_FLTINV;
3027 }
3028 if (env->sregs[SR_FSR] & FSR_DZ) {
3029 info.si_code = TARGET_FPE_FLTDIV;
3030 }
3031 info._sifields._sigfault._addr = 0;
3032 queue_signal(env, info.si_signo, &info);
3033 break;
3034 default:
3035 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 3036 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 3037 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3038 exit(EXIT_FAILURE);
b76da7e3
EI		 3039 break;
3040 }
3041 break;
b779e29e
EI		 3042 case EXCP_DEBUG:
3043 {
3044 int sig;
3045
db6b81d4 3046 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 3047 if (sig)
3048 {
3049 info.si_signo = sig;
3050 info.si_errno = 0;
3051 info.si_code = TARGET_TRAP_BRKPT;
3052 queue_signal(env, info.si_signo, &info);
3053 }
3054 }
3055 break;
3056 default:
3057 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3058 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3059 exit(EXIT_FAILURE);
b779e29e
EI		 3060 }
3061 process_pending_signals (env);
3062 }
3063}
3064#endif
3065
e6e5906b
PB		 3066#ifdef TARGET_M68K
3067
3068void cpu_loop(CPUM68KState *env)
3069{
878096ee 3070 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 3071 int trapnr;
3072 unsigned int n;
c227f099 3073 target_siginfo_t info;
0429a971 3074 TaskState *ts = cs->opaque;
3b46e624 3075
e6e5906b 3076 for(;;) {
b040bc9c 3077 cpu_exec_start(cs);
8642c1b8 3078 trapnr = cpu_exec(cs);
b040bc9c 3079 cpu_exec_end(cs);
e6e5906b
PB		 3080 switch(trapnr) {
3081 case EXCP_ILLEGAL:
3082 {
3083 if (ts->sim_syscalls) {
3084 uint16_t nr;
d8d5119c 3085 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 3086 env->pc += 4;
3087 do_m68k_simcall(env, nr);
3088 } else {
3089 goto do_sigill;
3090 }
3091 }
3092 break;
a87295e8 3093 case EXCP_HALT_INSN:
e6e5906b 3094 /* Semihosing syscall. */
a87295e8 3095 env->pc += 4;
e6e5906b
PB		 3096 do_m68k_semihosting(env, env->dregs[0]);
3097 break;
3098 case EXCP_LINEA:
3099 case EXCP_LINEF:
3100 case EXCP_UNSUPPORTED:
3101 do_sigill:
a86b3c64 3102 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3103 info.si_errno = 0;
3104 info.si_code = TARGET_ILL_ILLOPN;
3105 info._sifields._sigfault._addr = env->pc;
624f7979 3106 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3107 break;
3108 case EXCP_TRAP0:
3109 {
7ccb84a9 3110 abi_long ret;
e6e5906b
PB		 3111 ts->sim_syscalls = 0;
3112 n = env->dregs[0];
3113 env->pc += 2;
7ccb84a9
TB		 3114 ret = do_syscall(env,
3115 n,
3116 env->dregs[1],
3117 env->dregs[2],
3118 env->dregs[3],
3119 env->dregs[4],
3120 env->dregs[5],
3121 env->aregs[0],
3122 0, 0);
3123 if (ret == -TARGET_ERESTARTSYS) {
3124 env->pc -= 2;
3125 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3126 env->dregs[0] = ret;
3127 }
e6e5906b
PB		 3128 }
3129 break;
3130 case EXCP_INTERRUPT:
3131 /* just indicate that signals should be handled asap */
3132 break;
3133 case EXCP_ACCESS:
3134 {
a86b3c64 3135 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3136 info.si_errno = 0;
3137 /* XXX: check env->error_code */
3138 info.si_code = TARGET_SEGV_MAPERR;
3139 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3140 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3141 }
3142 break;
3143 case EXCP_DEBUG:
3144 {
3145 int sig;
3146
db6b81d4 3147 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3148 if (sig)
3149 {
3150 info.si_signo = sig;
3151 info.si_errno = 0;
3152 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3153 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3154 }
3155 }
3156 break;
3157 default:
120a9848 3158 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
e6e5906b
PB		 3159 abort();
3160 }
3161 process_pending_signals(env);
3162 }
3163}
3164#endif /* TARGET_M68K */
3165
7a3148a9 3166#ifdef TARGET_ALPHA
6910b8f6
RH		 3167static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3168{
3169 target_ulong addr, val, tmp;
3170 target_siginfo_t info;
3171 int ret = 0;
3172
3173 addr = env->lock_addr;
3174 tmp = env->lock_st_addr;
3175 env->lock_addr = -1;
3176 env->lock_st_addr = 0;
3177
3178 start_exclusive();
3179 mmap_lock();
3180
3181 if (addr == tmp) {
3182 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3183 goto do_sigsegv;
3184 }
3185
3186 if (val == env->lock_value) {
3187 tmp = env->ir[reg];
3188 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3189 goto do_sigsegv;
3190 }
3191 ret = 1;
3192 }
3193 }
3194 env->ir[reg] = ret;
3195 env->pc += 4;
3196
3197 mmap_unlock();
3198 end_exclusive();
3199 return;
3200
3201 do_sigsegv:
3202 mmap_unlock();
3203 end_exclusive();
3204
3205 info.si_signo = TARGET_SIGSEGV;
3206 info.si_errno = 0;
3207 info.si_code = TARGET_SEGV_MAPERR;
3208 info._sifields._sigfault._addr = addr;
3209 queue_signal(env, TARGET_SIGSEGV, &info);
3210}
3211
05390248 3212void cpu_loop(CPUAlphaState *env)
7a3148a9 3213{
878096ee 3214 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3215 int trapnr;
c227f099 3216 target_siginfo_t info;
6049f4f8 3217 abi_long sysret;
3b46e624 3218
7a3148a9 3219 while (1) {
b040bc9c 3220 cpu_exec_start(cs);
8642c1b8 3221 trapnr = cpu_exec(cs);
b040bc9c 3222 cpu_exec_end(cs);
3b46e624 3223
ac316ca4
RH		 3224 /* All of the traps imply a transition through PALcode, which
3225 implies an REI instruction has been executed. Which means
3226 that the intr_flag should be cleared. */
3227 env->intr_flag = 0;
3228
7a3148a9
JM		 3229 switch (trapnr) {
3230 case EXCP_RESET:
3231 fprintf(stderr, "Reset requested. Exit\n");
4d1275c2 3232 exit(EXIT_FAILURE);
7a3148a9
JM		 3233 break;
3234 case EXCP_MCHK:
3235 fprintf(stderr, "Machine check exception. Exit\n");
4d1275c2 3236 exit(EXIT_FAILURE);
7a3148a9 3237 break;
07b6c13b
RH		 3238 case EXCP_SMP_INTERRUPT:
3239 case EXCP_CLK_INTERRUPT:
3240 case EXCP_DEV_INTERRUPT:
5fafdf24 3241 fprintf(stderr, "External interrupt. Exit\n");
4d1275c2 3242 exit(EXIT_FAILURE);
7a3148a9 3243 break;
07b6c13b 3244 case EXCP_MMFAULT:
6910b8f6 3245 env->lock_addr = -1;
6049f4f8
RH		 3246 info.si_signo = TARGET_SIGSEGV;
3247 info.si_errno = 0;
129d8aa5 3248 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3249 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3250 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3251 queue_signal(env, info.si_signo, &info);
7a3148a9 3252 break;
7a3148a9 3253 case EXCP_UNALIGN:
6910b8f6 3254 env->lock_addr = -1;
6049f4f8
RH		 3255 info.si_signo = TARGET_SIGBUS;
3256 info.si_errno = 0;
3257 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3258 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3259 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3260 break;
3261 case EXCP_OPCDEC:
6049f4f8 3262 do_sigill:
6910b8f6 3263 env->lock_addr = -1;
6049f4f8
RH		 3264 info.si_signo = TARGET_SIGILL;
3265 info.si_errno = 0;
3266 info.si_code = TARGET_ILL_ILLOPC;
3267 info._sifields._sigfault._addr = env->pc;
3268 queue_signal(env, info.si_signo, &info);
7a3148a9 3269 break;
07b6c13b
RH		 3270 case EXCP_ARITH:
3271 env->lock_addr = -1;
3272 info.si_signo = TARGET_SIGFPE;
3273 info.si_errno = 0;
3274 info.si_code = TARGET_FPE_FLTINV;
3275 info._sifields._sigfault._addr = env->pc;
3276 queue_signal(env, info.si_signo, &info);
3277 break;
7a3148a9 3278 case EXCP_FEN:
6049f4f8 3279 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3280 break;
07b6c13b 3281 case EXCP_CALL_PAL:
6910b8f6 3282 env->lock_addr = -1;
07b6c13b 3283 switch (env->error_code) {
6049f4f8
RH		 3284 case 0x80:
3285 /* BPT */
3286 info.si_signo = TARGET_SIGTRAP;
3287 info.si_errno = 0;
3288 info.si_code = TARGET_TRAP_BRKPT;
3289 info._sifields._sigfault._addr = env->pc;
3290 queue_signal(env, info.si_signo, &info);
3291 break;
3292 case 0x81:
3293 /* BUGCHK */
3294 info.si_signo = TARGET_SIGTRAP;
3295 info.si_errno = 0;
3296 info.si_code = 0;
3297 info._sifields._sigfault._addr = env->pc;
3298 queue_signal(env, info.si_signo, &info);
3299 break;
3300 case 0x83:
3301 /* CALLSYS */
3302 trapnr = env->ir[IR_V0];
3303 sysret = do_syscall(env, trapnr,
3304 env->ir[IR_A0], env->ir[IR_A1],
3305 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3306 env->ir[IR_A4], env->ir[IR_A5],
3307 0, 0);
338c858c
TB		 3308 if (sysret == -TARGET_ERESTARTSYS) {
3309 env->pc -= 4;
3310 break;
3311 }
3312 if (sysret == -TARGET_QEMU_ESIGRETURN) {
a5b3b13b
RH		 3313 break;
3314 }
3315 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3316 to how this is handled internal to Linux kernel.
3317 (Ab)use trapnr temporarily as boolean indicating error. */
3318 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3319 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3320 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3321 break;
3322 case 0x86:
3323 /* IMB */
3324 /* ??? We can probably elide the code using page_unprotect
3325 that is checking for self-modifying code. Instead we
3326 could simply call tb_flush here. Until we work out the
3327 changes required to turn off the extra write protection,
3328 this can be a no-op. */
3329 break;
3330 case 0x9E:
3331 /* RDUNIQUE */
3332 /* Handled in the translator for usermode. */
3333 abort();
3334 case 0x9F:
3335 /* WRUNIQUE */
3336 /* Handled in the translator for usermode. */
3337 abort();
3338 case 0xAA:
3339 /* GENTRAP */
3340 info.si_signo = TARGET_SIGFPE;
3341 switch (env->ir[IR_A0]) {
3342 case TARGET_GEN_INTOVF:
3343 info.si_code = TARGET_FPE_INTOVF;
3344 break;
3345 case TARGET_GEN_INTDIV:
3346 info.si_code = TARGET_FPE_INTDIV;
3347 break;
3348 case TARGET_GEN_FLTOVF:
3349 info.si_code = TARGET_FPE_FLTOVF;
3350 break;
3351 case TARGET_GEN_FLTUND:
3352 info.si_code = TARGET_FPE_FLTUND;
3353 break;
3354 case TARGET_GEN_FLTINV:
3355 info.si_code = TARGET_FPE_FLTINV;
3356 break;
3357 case TARGET_GEN_FLTINE:
3358 info.si_code = TARGET_FPE_FLTRES;
3359 break;
3360 case TARGET_GEN_ROPRAND:
3361 info.si_code = 0;
3362 break;
3363 default:
3364 info.si_signo = TARGET_SIGTRAP;
3365 info.si_code = 0;
3366 break;
3367 }
3368 info.si_errno = 0;
3369 info._sifields._sigfault._addr = env->pc;
3370 queue_signal(env, info.si_signo, &info);
3371 break;
3372 default:
3373 goto do_sigill;
3374 }
7a3148a9 3375 break;
7a3148a9 3376 case EXCP_DEBUG:
db6b81d4 3377 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3378 if (info.si_signo) {
6910b8f6 3379 env->lock_addr = -1;
6049f4f8
RH		 3380 info.si_errno = 0;
3381 info.si_code = TARGET_TRAP_BRKPT;
3382 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3383 }
3384 break;
6910b8f6
RH		 3385 case EXCP_STL_C:
3386 case EXCP_STQ_C:
3387 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3388 break;
d0f20495
RH		 3389 case EXCP_INTERRUPT:
3390 /* Just indicate that signals should be handled asap. */
3391 break;
7a3148a9
JM		 3392 default:
3393 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3394 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3395 exit(EXIT_FAILURE);
7a3148a9
JM		 3396 }
3397 process_pending_signals (env);
3398 }
3399}
3400#endif /* TARGET_ALPHA */
3401
a4c075f1
UH		 3402#ifdef TARGET_S390X
3403void cpu_loop(CPUS390XState *env)
3404{
878096ee 3405 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3406 int trapnr, n, sig;
a4c075f1 3407 target_siginfo_t info;
d5a103cd 3408 target_ulong addr;
47405ab6 3409 abi_long ret;
a4c075f1
UH		 3410
3411 while (1) {
b040bc9c 3412 cpu_exec_start(cs);
8642c1b8 3413 trapnr = cpu_exec(cs);
b040bc9c 3414 cpu_exec_end(cs);
a4c075f1
UH		 3415 switch (trapnr) {
3416 case EXCP_INTERRUPT:
d5a103cd 3417 /* Just indicate that signals should be handled asap. */
a4c075f1 3418 break;
a4c075f1 3419
d5a103cd
RH		 3420 case EXCP_SVC:
3421 n = env->int_svc_code;
3422 if (!n) {
3423 /* syscalls > 255 */
3424 n = env->regs[1];
a4c075f1 3425 }
d5a103cd 3426 env->psw.addr += env->int_svc_ilen;
47405ab6
TB		 3427 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3428 env->regs[4], env->regs[5],
3429 env->regs[6], env->regs[7], 0, 0);
3430 if (ret == -TARGET_ERESTARTSYS) {
3431 env->psw.addr -= env->int_svc_ilen;
3432 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3433 env->regs[2] = ret;
3434 }
a4c075f1 3435 break;
d5a103cd
RH		 3436
3437 case EXCP_DEBUG:
db6b81d4 3438 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3439 if (sig) {
3440 n = TARGET_TRAP_BRKPT;
3441 goto do_signal_pc;
a4c075f1
UH		 3442 }
3443 break;
d5a103cd
RH		 3444 case EXCP_PGM:
3445 n = env->int_pgm_code;
3446 switch (n) {
3447 case PGM_OPERATION:
3448 case PGM_PRIVILEGED:
a86b3c64 3449 sig = TARGET_SIGILL;
d5a103cd
RH		 3450 n = TARGET_ILL_ILLOPC;
3451 goto do_signal_pc;
3452 case PGM_PROTECTION:
3453 case PGM_ADDRESSING:
a86b3c64 3454 sig = TARGET_SIGSEGV;
a4c075f1 3455 /* XXX: check env->error_code */
d5a103cd
RH		 3456 n = TARGET_SEGV_MAPERR;
3457 addr = env->__excp_addr;
3458 goto do_signal;
3459 case PGM_EXECUTE:
3460 case PGM_SPECIFICATION:
3461 case PGM_SPECIAL_OP:
3462 case PGM_OPERAND:
3463 do_sigill_opn:
a86b3c64 3464 sig = TARGET_SIGILL;
d5a103cd
RH		 3465 n = TARGET_ILL_ILLOPN;
3466 goto do_signal_pc;
3467
3468 case PGM_FIXPT_OVERFLOW:
a86b3c64 3469 sig = TARGET_SIGFPE;
d5a103cd
RH		 3470 n = TARGET_FPE_INTOVF;
3471 goto do_signal_pc;
3472 case PGM_FIXPT_DIVIDE:
a86b3c64 3473 sig = TARGET_SIGFPE;
d5a103cd
RH		 3474 n = TARGET_FPE_INTDIV;
3475 goto do_signal_pc;
3476
3477 case PGM_DATA:
3478 n = (env->fpc >> 8) & 0xff;
3479 if (n == 0xff) {
3480 /* compare-and-trap */
3481 goto do_sigill_opn;
3482 } else {
3483 /* An IEEE exception, simulated or otherwise. */
3484 if (n & 0x80) {
3485 n = TARGET_FPE_FLTINV;
3486 } else if (n & 0x40) {
3487 n = TARGET_FPE_FLTDIV;
3488 } else if (n & 0x20) {
3489 n = TARGET_FPE_FLTOVF;
3490 } else if (n & 0x10) {
3491 n = TARGET_FPE_FLTUND;
3492 } else if (n & 0x08) {
3493 n = TARGET_FPE_FLTRES;
3494 } else {
3495 /* ??? Quantum exception; BFP, DFP error. */
3496 goto do_sigill_opn;
3497 }
a86b3c64 3498 sig = TARGET_SIGFPE;
d5a103cd
RH		 3499 goto do_signal_pc;
3500 }
3501
3502 default:
3503 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3504 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3505 exit(EXIT_FAILURE);
a4c075f1
UH		 3506 }
3507 break;
d5a103cd
RH		 3508
3509 do_signal_pc:
3510 addr = env->psw.addr;
3511 do_signal:
3512 info.si_signo = sig;
3513 info.si_errno = 0;
3514 info.si_code = n;
3515 info._sifields._sigfault._addr = addr;
3516 queue_signal(env, info.si_signo, &info);
a4c075f1 3517 break;
d5a103cd 3518
a4c075f1 3519 default:
d5a103cd 3520 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3521 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3522 exit(EXIT_FAILURE);
a4c075f1
UH		 3523 }
3524 process_pending_signals (env);
3525 }
3526}
3527
3528#endif /* TARGET_S390X */
3529
b16189b2
CG		 3530#ifdef TARGET_TILEGX
3531
b16189b2
CG		 3532static void gen_sigill_reg(CPUTLGState *env)
3533{
3534 target_siginfo_t info;
3535
3536 info.si_signo = TARGET_SIGILL;
3537 info.si_errno = 0;
3538 info.si_code = TARGET_ILL_PRVREG;
3539 info._sifields._sigfault._addr = env->pc;
3540 queue_signal(env, info.si_signo, &info);
3541}
3542
a0577d2a 3543static void do_signal(CPUTLGState *env, int signo, int sigcode)
dd8070d8
CG		 3544{
3545 target_siginfo_t info;
3546
a0577d2a 3547 info.si_signo = signo;
dd8070d8 3548 info.si_errno = 0;
dd8070d8 3549 info._sifields._sigfault._addr = env->pc;
a0577d2a
RH		 3550
3551 if (signo == TARGET_SIGSEGV) {
3552 /* The passed in sigcode is a dummy; check for a page mapping
3553 and pass either MAPERR or ACCERR. */
3554 target_ulong addr = env->excaddr;
3555 info._sifields._sigfault._addr = addr;
3556 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3557 sigcode = TARGET_SEGV_MAPERR;
3558 } else {
3559 sigcode = TARGET_SEGV_ACCERR;
3560 }
3561 }
3562 info.si_code = sigcode;
3563
dd8070d8
CG		 3564 queue_signal(env, info.si_signo, &info);
3565}
3566
a0577d2a
RH		 3567static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3568{
3569 env->excaddr = addr;
3570 do_signal(env, TARGET_SIGSEGV, 0);
3571}
3572
0583b233
RH		 3573static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3574{
3575 if (unlikely(reg >= TILEGX_R_COUNT)) {
3576 switch (reg) {
3577 case TILEGX_R_SN:
3578 case TILEGX_R_ZERO:
3579 return;
3580 case TILEGX_R_IDN0:
3581 case TILEGX_R_IDN1:
3582 case TILEGX_R_UDN0:
3583 case TILEGX_R_UDN1:
3584 case TILEGX_R_UDN2:
3585 case TILEGX_R_UDN3:
3586 gen_sigill_reg(env);
3587 return;
3588 default:
3589 g_assert_not_reached();
3590 }
3591 }
3592 env->regs[reg] = val;
3593}
3594
3595/*
3596 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3597 * memory at the address held in the first source register. If the values are
3598 * not equal, then no memory operation is performed. If the values are equal,
3599 * the 8-byte quantity from the second source register is written into memory
3600 * at the address held in the first source register. In either case, the result
3601 * of the instruction is the value read from memory. The compare and write to
3602 * memory are atomic and thus can be used for synchronization purposes. This
3603 * instruction only operates for addresses aligned to a 8-byte boundary.
3604 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3605 *
3606 * Functional Description (64-bit)
3607 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3608 * rf[Dest] = memVal;
3609 * if (memVal == SPR[CmpValueSPR])
3610 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3611 *
3612 * Functional Description (32-bit)
3613 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3614 * rf[Dest] = memVal;
3615 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3616 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3617 *
3618 *
3619 * This function also processes exch and exch4 which need not process SPR.
3620 */
3621static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3622{
3623 target_ulong addr;
3624 target_long val, sprval;
3625
3626 start_exclusive();
3627
3628 addr = env->atomic_srca;
3629 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3630 goto sigsegv_maperr;
3631 }
3632
3633 if (cmp) {
3634 if (quad) {
3635 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3636 } else {
3637 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3638 }
3639 }
3640
3641 if (!cmp || val == sprval) {
3642 target_long valb = env->atomic_srcb;
3643 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3644 goto sigsegv_maperr;
3645 }
3646 }
3647
3648 set_regval(env, env->atomic_dstr, val);
3649 end_exclusive();
3650 return;
3651
3652 sigsegv_maperr:
3653 end_exclusive();
3654 gen_sigsegv_maperr(env, addr);
3655}
3656
3657static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3658{
3659 int8_t write = 1;
3660 target_ulong addr;
3661 target_long val, valb;
3662
3663 start_exclusive();
3664
3665 addr = env->atomic_srca;
3666 valb = env->atomic_srcb;
3667 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3668 goto sigsegv_maperr;
3669 }
3670
3671 switch (trapnr) {
3672 case TILEGX_EXCP_OPCODE_FETCHADD:
3673 case TILEGX_EXCP_OPCODE_FETCHADD4:
3674 valb += val;
3675 break;
3676 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3677 valb += val;
3678 if (valb < 0) {
3679 write = 0;
3680 }
3681 break;
3682 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3683 valb += val;
3684 if ((int32_t)valb < 0) {
3685 write = 0;
3686 }
3687 break;
3688 case TILEGX_EXCP_OPCODE_FETCHAND:
3689 case TILEGX_EXCP_OPCODE_FETCHAND4:
3690 valb &= val;
3691 break;
3692 case TILEGX_EXCP_OPCODE_FETCHOR:
3693 case TILEGX_EXCP_OPCODE_FETCHOR4:
3694 valb |= val;
3695 break;
3696 default:
3697 g_assert_not_reached();
3698 }
3699
3700 if (write) {
3701 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3702 goto sigsegv_maperr;
3703 }
3704 }
3705
3706 set_regval(env, env->atomic_dstr, val);
3707 end_exclusive();
3708 return;
3709
3710 sigsegv_maperr:
3711 end_exclusive();
3712 gen_sigsegv_maperr(env, addr);
3713}
3714
b16189b2
CG		 3715void cpu_loop(CPUTLGState *env)
3716{
3717 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3718 int trapnr;
3719
3720 while (1) {
3721 cpu_exec_start(cs);
8642c1b8 3722 trapnr = cpu_exec(cs);
b16189b2
CG		 3723 cpu_exec_end(cs);
3724 switch (trapnr) {
3725 case TILEGX_EXCP_SYSCALL:
a9175169
PM		 3726 {
3727 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3728 env->regs[0], env->regs[1],
3729 env->regs[2], env->regs[3],
3730 env->regs[4], env->regs[5],
3731 env->regs[6], env->regs[7]);
3732 if (ret == -TARGET_ERESTARTSYS) {
3733 env->pc -= 8;
3734 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3735 env->regs[TILEGX_R_RE] = ret;
3736 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3737 }
b16189b2 3738 break;
a9175169 3739 }
0583b233
RH		 3740 case TILEGX_EXCP_OPCODE_EXCH:
3741 do_exch(env, true, false);
3742 break;
3743 case TILEGX_EXCP_OPCODE_EXCH4:
3744 do_exch(env, false, false);
3745 break;
3746 case TILEGX_EXCP_OPCODE_CMPEXCH:
3747 do_exch(env, true, true);
3748 break;
3749 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3750 do_exch(env, false, true);
3751 break;
3752 case TILEGX_EXCP_OPCODE_FETCHADD:
3753 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3754 case TILEGX_EXCP_OPCODE_FETCHAND:
3755 case TILEGX_EXCP_OPCODE_FETCHOR:
3756 do_fetch(env, trapnr, true);
3757 break;
3758 case TILEGX_EXCP_OPCODE_FETCHADD4:
3759 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3760 case TILEGX_EXCP_OPCODE_FETCHAND4:
3761 case TILEGX_EXCP_OPCODE_FETCHOR4:
3762 do_fetch(env, trapnr, false);
3763 break;
dd8070d8 3764 case TILEGX_EXCP_SIGNAL:
a0577d2a 3765 do_signal(env, env->signo, env->sigcode);
dd8070d8 3766 break;
b16189b2
CG		 3767 case TILEGX_EXCP_REG_IDN_ACCESS:
3768 case TILEGX_EXCP_REG_UDN_ACCESS:
3769 gen_sigill_reg(env);
3770 break;
3771 default:
3772 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3773 g_assert_not_reached();
3774 }
3775 process_pending_signals(env);
3776 }
3777}
3778
3779#endif
3780
a2247f8e 3781THREAD CPUState *thread_cpu;
59faf6d6 3782
edf8e2af
MW		 3783void task_settid(TaskState *ts)
3784{
3785 if (ts->ts_tid == 0) {
edf8e2af 3786 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3787 }
3788}
3789
3790void stop_all_tasks(void)
3791{
3792 /*
3793 * We trust that when using NPTL, start_exclusive()
3794 * handles thread stopping correctly.
3795 */
3796 start_exclusive();
3797}
3798
c3a92833 3799/* Assumes contents are already zeroed. */
624f7979
PB		 3800void init_task_state(TaskState *ts)
3801{
624f7979 3802 ts->used = 1;
624f7979 3803}
fc9c5412 3804
30ba0ee5
AF		 3805CPUArchState *cpu_copy(CPUArchState *env)
3806{
ff4700b0 3807 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3808 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3809 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3810 CPUBreakpoint *bp;
3811 CPUWatchpoint *wp;
30ba0ee5
AF		 3812
3813 /* Reset non arch specific state */
75a34036 3814 cpu_reset(new_cpu);
30ba0ee5
AF		 3815
3816 memcpy(new_env, env, sizeof(CPUArchState));
3817
3818 /* Clone all break/watchpoints.
3819 Note: Once we support ptrace with hw-debug register access, make sure
3820 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3821 QTAILQ_INIT(&new_cpu->breakpoints);
3822 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3823 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3824 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3825 }
ff4700b0 3826 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3827 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3828 }
30ba0ee5
AF		 3829
3830 return new_env;
3831}
3832
fc9c5412
JS		 3833static void handle_arg_help(const char *arg)
3834{
4d1275c2 3835 usage(EXIT_SUCCESS);
fc9c5412
JS		 3836}
3837
3838static void handle_arg_log(const char *arg)
3839{
3840 int mask;
fc9c5412 3841
4fde1eba 3842 mask = qemu_str_to_log_mask(arg);
fc9c5412 3843 if (!mask) {
59a6fa6e 3844 qemu_print_log_usage(stdout);
4d1275c2 3845 exit(EXIT_FAILURE);
fc9c5412 3846 }
f2937a33 3847 qemu_log_needs_buffers();
24537a01 3848 qemu_set_log(mask);
fc9c5412
JS		 3849}
3850
50171d42
CWR		 3851static void handle_arg_log_filename(const char *arg)
3852{
daa76aa4 3853 qemu_set_log_filename(arg, &error_fatal);
50171d42
CWR		 3854}
3855
fc9c5412
JS		 3856static void handle_arg_set_env(const char *arg)
3857{
3858 char *r, *p, *token;
3859 r = p = strdup(arg);
3860 while ((token = strsep(&p, ",")) != NULL) {
3861 if (envlist_setenv(envlist, token) != 0) {
4d1275c2 3862 usage(EXIT_FAILURE);
fc9c5412
JS		 3863 }
3864 }
3865 free(r);
3866}
3867
3868static void handle_arg_unset_env(const char *arg)
3869{
3870 char *r, *p, *token;
3871 r = p = strdup(arg);
3872 while ((token = strsep(&p, ",")) != NULL) {
3873 if (envlist_unsetenv(envlist, token) != 0) {
4d1275c2 3874 usage(EXIT_FAILURE);
fc9c5412
JS		 3875 }
3876 }
3877 free(r);
3878}
3879
3880static void handle_arg_argv0(const char *arg)
3881{
3882 argv0 = strdup(arg);
3883}
3884
3885static void handle_arg_stack_size(const char *arg)
3886{
3887 char *p;
3888 guest_stack_size = strtoul(arg, &p, 0);
3889 if (guest_stack_size == 0) {
4d1275c2 3890 usage(EXIT_FAILURE);
fc9c5412
JS		 3891 }
3892
3893 if (*p == 'M') {
3894 guest_stack_size *= 1024 * 1024;
3895 } else if (*p == 'k' || *p == 'K') {
3896 guest_stack_size *= 1024;
3897 }
3898}
3899
3900static void handle_arg_ld_prefix(const char *arg)
3901{
3902 interp_prefix = strdup(arg);
3903}
3904
3905static void handle_arg_pagesize(const char *arg)
3906{
3907 qemu_host_page_size = atoi(arg);
3908 if (qemu_host_page_size == 0 ||
3909 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3910 fprintf(stderr, "page size must be a power of two\n");
4d1275c2 3911 exit(EXIT_FAILURE);
fc9c5412
JS		 3912 }
3913}
3914
c5e4a5a9
MR		 3915static void handle_arg_randseed(const char *arg)
3916{
3917 unsigned long long seed;
3918
3919 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3920 fprintf(stderr, "Invalid seed number: %s\n", arg);
4d1275c2 3921 exit(EXIT_FAILURE);
c5e4a5a9
MR		 3922 }
3923 srand(seed);
3924}
3925
fc9c5412
JS		 3926static void handle_arg_gdb(const char *arg)
3927{
3928 gdbstub_port = atoi(arg);
3929}
3930
3931static void handle_arg_uname(const char *arg)
3932{
3933 qemu_uname_release = strdup(arg);
3934}
3935
3936static void handle_arg_cpu(const char *arg)
3937{
3938 cpu_model = strdup(arg);
c8057f95 3939 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3940 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3941#if defined(cpu_list)
3942 cpu_list(stdout, &fprintf);
fc9c5412 3943#endif
4d1275c2 3944 exit(EXIT_FAILURE);
fc9c5412
JS		 3945 }
3946}
3947
fc9c5412
JS		 3948static void handle_arg_guest_base(const char *arg)
3949{
3950 guest_base = strtol(arg, NULL, 0);
3951 have_guest_base = 1;
3952}
3953
3954static void handle_arg_reserved_va(const char *arg)
3955{
3956 char *p;
3957 int shift = 0;
3958 reserved_va = strtoul(arg, &p, 0);
3959 switch (*p) {
3960 case 'k':
3961 case 'K':
3962 shift = 10;
3963 break;
3964 case 'M':
3965 shift = 20;
3966 break;
3967 case 'G':
3968 shift = 30;
3969 break;
3970 }
3971 if (shift) {
3972 unsigned long unshifted = reserved_va;
3973 p++;
3974 reserved_va <<= shift;
3975 if (((reserved_va >> shift) != unshifted)
3976#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3977 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3978#endif
3979 ) {
3980 fprintf(stderr, "Reserved virtual address too big\n");
4d1275c2 3981 exit(EXIT_FAILURE);
fc9c5412
JS		 3982 }
3983 }
3984 if (*p) {
3985 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4d1275c2 3986 exit(EXIT_FAILURE);
fc9c5412
JS		 3987 }
3988}
fc9c5412
JS		 3989
3990static void handle_arg_singlestep(const char *arg)
3991{
3992 singlestep = 1;
3993}
3994
3995static void handle_arg_strace(const char *arg)
3996{
3997 do_strace = 1;
3998}
3999
4000static void handle_arg_version(const char *arg)
4001{
2e59915d 4002 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 4003 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
4d1275c2 4004 exit(EXIT_SUCCESS);
fc9c5412
JS		 4005}
4006
6533dd6e
LV		 4007static char *trace_file;
4008static void handle_arg_trace(const char *arg)
4009{
4010 g_free(trace_file);
4011 trace_file = trace_opt_parse(arg);
4012}
4013
fc9c5412
JS		 4014struct qemu_argument {
4015 const char *argv;
4016 const char *env;
4017 bool has_arg;
4018 void (*handle_opt)(const char *arg);
4019 const char *example;
4020 const char *help;
4021};
4022
42644cee 4023static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 4024 {"h", "", false, handle_arg_help,
4025 "", "print this help"},
daaf8c8e
MI		 4026 {"help", "", false, handle_arg_help,
4027 "", ""},
fc9c5412
JS		 4028 {"g", "QEMU_GDB", true, handle_arg_gdb,
4029 "port", "wait gdb connection to 'port'"},
4030 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4031 "path", "set the elf interpreter prefix to 'path'"},
4032 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4033 "size", "set the stack size to 'size' bytes"},
4034 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 4035 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 4036 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4037 "var=value", "sets targets environment variable (see below)"},
4038 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4039 "var", "unsets targets environment variable (see below)"},
4040 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4041 "argv0", "forces target process argv[0] to be 'argv0'"},
4042 {"r", "QEMU_UNAME", true, handle_arg_uname,
4043 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 4044 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4045 "address", "set guest_base address to 'address'"},
4046 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4047 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 4048 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 4049 "item[,...]", "enable logging of specified items "
4050 "(use '-d help' for a list of items)"},
50171d42 4051 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 4052 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 4053 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4054 "pagesize", "set the host page size to 'pagesize'"},
4055 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4056 "", "run in singlestep mode"},
4057 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4058 "", "log system calls"},
c5e4a5a9
MR		 4059 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4060 "", "Seed for pseudo-random number generator"},
6533dd6e
LV		 4061 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4062 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
fc9c5412 4063 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 4064 "", "display version information and exit"},
fc9c5412
JS		 4065 {NULL, NULL, false, NULL, NULL, NULL}
4066};
4067
d03f9c32 4068static void usage(int exitcode)
fc9c5412 4069{
42644cee 4070 const struct qemu_argument *arginfo;
fc9c5412
JS		 4071 int maxarglen;
4072 int maxenvlen;
4073
2e59915d
PB		 4074 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4075 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 4076 "\n"
4077 "Options and associated environment variables:\n"
4078 "\n");
4079
63ec54d7
PM		 4080 /* Calculate column widths. We must always have at least enough space
4081 * for the column header.
4082 */
4083 maxarglen = strlen("Argument");
4084 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 4085
4086 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 4087 int arglen = strlen(arginfo->argv);
4088 if (arginfo->has_arg) {
4089 arglen += strlen(arginfo->example) + 1;
4090 }
fc9c5412
JS		 4091 if (strlen(arginfo->env) > maxenvlen) {
4092 maxenvlen = strlen(arginfo->env);
4093 }
63ec54d7
PM		 4094 if (arglen > maxarglen) {
4095 maxarglen = arglen;
fc9c5412
JS		 4096 }
4097 }
4098
63ec54d7
PM		 4099 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4100 maxenvlen, "Env-variable");
fc9c5412
JS		 4101
4102 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4103 if (arginfo->has_arg) {
4104 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 4105 (int)(maxarglen - strlen(arginfo->argv) - 1),
4106 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 4107 } else {
63ec54d7 4108 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 4109 maxenvlen, arginfo->env,
4110 arginfo->help);
4111 }
4112 }
4113
4114 printf("\n"
4115 "Defaults:\n"
4116 "QEMU_LD_PREFIX = %s\n"
989b697d 4117 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 4118 interp_prefix,
989b697d 4119 guest_stack_size);
fc9c5412
JS		 4120
4121 printf("\n"
4122 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4123 "QEMU_UNSET_ENV environment variables to set and unset\n"
4124 "environment variables for the target process.\n"
4125 "It is possible to provide several variables by separating them\n"
4126 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4127 "provide the -E and -U options multiple times.\n"
4128 "The following lines are equivalent:\n"
4129 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4130 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4131 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4132 "Note that if you provide several changes to a single variable\n"
4133 "the last change will stay in effect.\n");
4134
d03f9c32 4135 exit(exitcode);
fc9c5412
JS		 4136}
4137
4138static int parse_args(int argc, char **argv)
4139{
4140 const char *r;
4141 int optind;
42644cee 4142 const struct qemu_argument *arginfo;
fc9c5412
JS		 4143
4144 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4145 if (arginfo->env == NULL) {
4146 continue;
4147 }
4148
4149 r = getenv(arginfo->env);
4150 if (r != NULL) {
4151 arginfo->handle_opt(r);
4152 }
4153 }
4154
4155 optind = 1;
4156 for (;;) {
4157 if (optind >= argc) {
4158 break;
4159 }
4160 r = argv[optind];
4161 if (r[0] != '-') {
4162 break;
4163 }
4164 optind++;
4165 r++;
4166 if (!strcmp(r, "-")) {
4167 break;
4168 }
ba02577c
MI		 4169 /* Treat --foo the same as -foo. */
4170 if (r[0] == '-') {
4171 r++;
4172 }
fc9c5412
JS		 4173
4174 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4175 if (!strcmp(r, arginfo->argv)) {
fc9c5412 4176 if (arginfo->has_arg) {
1386d4c0 4177 if (optind >= argc) {
138940bf
MI		 4178 (void) fprintf(stderr,
4179 "qemu: missing argument for option '%s'\n", r);
4d1275c2 4180 exit(EXIT_FAILURE);
1386d4c0
PM		 4181 }
4182 arginfo->handle_opt(argv[optind]);
fc9c5412 4183 optind++;
1386d4c0
PM		 4184 } else {
4185 arginfo->handle_opt(NULL);
fc9c5412 4186 }
fc9c5412
JS		 4187 break;
4188 }
4189 }
4190
4191 /* no option matched the current argv */
4192 if (arginfo->handle_opt == NULL) {
138940bf 4193 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4d1275c2 4194 exit(EXIT_FAILURE);
fc9c5412
JS		 4195 }
4196 }
4197
4198 if (optind >= argc) {
138940bf 4199 (void) fprintf(stderr, "qemu: no user program specified\n");
4d1275c2 4200 exit(EXIT_FAILURE);
fc9c5412
JS		 4201 }
4202
4203 filename = argv[optind];
4204 exec_path = argv[optind];
4205
4206 return optind;
4207}
4208
902b3d5c 4209int main(int argc, char **argv, char **envp)
31e31b8a 4210{
01ffc75b 4211 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 4212 struct image_info info1, *info = &info1;
edf8e2af 4213 struct linux_binprm bprm;
48e15fc2 4214 TaskState *ts;
9349b4f9 4215 CPUArchState *env;
db6b81d4 4216 CPUState *cpu;
586314f2 4217 int optind;
04a6dfeb 4218 char **target_environ, **wrk;
7d8cec95
AJ		 4219 char **target_argv;
4220 int target_argc;
7d8cec95 4221 int i;
fd4d81dd 4222 int ret;
03cfd8fa 4223 int execfd;
b12b6a18 4224
ce008c1f
AF		 4225 module_call_init(MODULE_INIT_QOM);
4226
04a6dfeb
AJ		 4227 if ((envlist = envlist_create()) == NULL) {
4228 (void) fprintf(stderr, "Unable to allocate envlist\n");
4d1275c2 4229 exit(EXIT_FAILURE);
04a6dfeb
AJ		 4230 }
4231
4232 /* add current environment into the list */
4233 for (wrk = environ; *wrk != NULL; wrk++) {
4234 (void) envlist_setenv(envlist, *wrk);
4235 }
4236
703e0e89
RH		 4237 /* Read the stack limit from the kernel. If it's "unlimited",
4238 then we can do little else besides use the default. */
4239 {
4240 struct rlimit lim;
4241 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 4242 && lim.rlim_cur != RLIM_INFINITY
4243 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 4244 guest_stack_size = lim.rlim_cur;
4245 }
4246 }
4247
b1f9be31 4248 cpu_model = NULL;
b5ec5ce0 4249
c5e4a5a9
MR		 4250 srand(time(NULL));
4251
6533dd6e
LV		 4252 qemu_add_opts(&qemu_trace_opts);
4253
fc9c5412 4254 optind = parse_args(argc, argv);
586314f2 4255
6533dd6e
LV		 4256 if (!trace_init_backends()) {
4257 exit(1);
4258 }
4259 trace_init_file(trace_file);
4260
31e31b8a 4261 /* Zero out regs */
01ffc75b 4262 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4263
4264 /* Zero out image_info */
4265 memset(info, 0, sizeof(struct image_info));
4266
edf8e2af
MW		 4267 memset(&bprm, 0, sizeof (bprm));
4268
74cd30b8
FB		 4269 /* Scan interp_prefix dir for replacement files. */
4270 init_paths(interp_prefix);
4271
4a24a758
PM		 4272 init_qemu_uname_release();
4273
46027c07 4274 if (cpu_model == NULL) {
aaed909a 4275#if defined(TARGET_I386)
46027c07
FB		 4276#ifdef TARGET_X86_64
4277 cpu_model = "qemu64";
4278#else
4279 cpu_model = "qemu32";
4280#endif
aaed909a 4281#elif defined(TARGET_ARM)
088ab16c 4282 cpu_model = "any";
d2fbca94
GX		 4283#elif defined(TARGET_UNICORE32)
4284 cpu_model = "any";
aaed909a
FB		 4285#elif defined(TARGET_M68K)
4286 cpu_model = "any";
4287#elif defined(TARGET_SPARC)
4288#ifdef TARGET_SPARC64
4289 cpu_model = "TI UltraSparc II";
4290#else
4291 cpu_model = "Fujitsu MB86904";
46027c07 4292#endif
aaed909a
FB		 4293#elif defined(TARGET_MIPS)
4294#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4295 cpu_model = "5KEf";
aaed909a
FB		 4296#else
4297 cpu_model = "24Kf";
4298#endif
d962783e
JL		 4299#elif defined TARGET_OPENRISC
4300 cpu_model = "or1200";
aaed909a 4301#elif defined(TARGET_PPC)
a74029f6 4302# ifdef TARGET_PPC64
de3f1b98 4303 cpu_model = "POWER8";
a74029f6 4304# else
aaed909a 4305 cpu_model = "750";
a74029f6 4306# endif
91c45a38
RH		 4307#elif defined TARGET_SH4
4308 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4309#else
4310 cpu_model = "any";
4311#endif
4312 }
d5ab9713 4313 tcg_exec_init(0);
83fb7adf
FB		 4314 /* NOTE: we need to init the CPU at this stage to get
4315 qemu_host_page_size */
2994fd96
EH		 4316 cpu = cpu_init(cpu_model);
4317 if (!cpu) {
aaed909a 4318 fprintf(stderr, "Unable to find CPU definition\n");
4d1275c2 4319 exit(EXIT_FAILURE);
aaed909a 4320 }
2994fd96 4321 env = cpu->env_ptr;
0ac46af3 4322 cpu_reset(cpu);
b55a37c9 4323
db6b81d4 4324 thread_cpu = cpu;
3b46e624 4325
b6741956
FB		 4326 if (getenv("QEMU_STRACE")) {
4327 do_strace = 1;
b92c47c1
TS		 4328 }
4329
c5e4a5a9
MR		 4330 if (getenv("QEMU_RAND_SEED")) {
4331 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4332 }
4333
04a6dfeb
AJ		 4334 target_environ = envlist_to_environ(envlist, NULL);
4335 envlist_free(envlist);
b12b6a18 4336
379f6698
PB		 4337 /*
4338 * Now that page sizes are configured in cpu_init() we can do
4339 * proper page alignment for guest_base.
4340 */
4341 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4342
806d1021
MI		 4343 if (reserved_va || have_guest_base) {
4344 guest_base = init_guest_space(guest_base, reserved_va, 0,
4345 have_guest_base);
4346 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4347 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4348 "space for use as guest address space (check your virtual "
4349 "memory ulimit setting or reserve less using -R option)\n",
4350 reserved_va);
4d1275c2 4351 exit(EXIT_FAILURE);
68a1c816 4352 }
97cc7560 4353
806d1021
MI		 4354 if (reserved_va) {
4355 mmap_next_start = reserved_va;
97cc7560
DDAG		 4356 }
4357 }
379f6698
PB		 4358
4359 /*
4360 * Read in mmap_min_addr kernel parameter. This value is used
4361 * When loading the ELF image to determine whether guest_base
14f24e14 4362 * is needed. It is also used in mmap_find_vma.
379f6698 4363 */
14f24e14 4364 {
379f6698
PB		 4365 FILE *fp;
4366
4367 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4368 unsigned long tmp;
4369 if (fscanf(fp, "%lu", &tmp) == 1) {
4370 mmap_min_addr = tmp;
13829020 4371 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
379f6698
PB		 4372 }
4373 fclose(fp);
4374 }
4375 }
379f6698 4376
7d8cec95
AJ		 4377 /*
4378 * Prepare copy of argv vector for target.
4379 */
4380 target_argc = argc - optind;
4381 target_argv = calloc(target_argc + 1, sizeof (char *));
4382 if (target_argv == NULL) {
4383 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4d1275c2 4384 exit(EXIT_FAILURE);
7d8cec95
AJ		 4385 }
4386
4387 /*
4388 * If argv0 is specified (using '-0' switch) we replace
4389 * argv[0] pointer with the given one.
4390 */
4391 i = 0;
4392 if (argv0 != NULL) {
4393 target_argv[i++] = strdup(argv0);
4394 }
4395 for (; i < target_argc; i++) {
4396 target_argv[i] = strdup(argv[optind + i]);
4397 }
4398 target_argv[target_argc] = NULL;
4399
c78d65e8 4400 ts = g_new0(TaskState, 1);
edf8e2af
MW		 4401 init_task_state(ts);
4402 /* build Task State */
4403 ts->info = info;
4404 ts->bprm = &bprm;
0429a971 4405 cpu->opaque = ts;
edf8e2af
MW		 4406 task_settid(ts);
4407
0b959cf5
RH		 4408 execfd = qemu_getauxval(AT_EXECFD);
4409 if (execfd == 0) {
03cfd8fa 4410 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4411 if (execfd < 0) {
4412 printf("Error while loading %s: %s\n", filename, strerror(errno));
4d1275c2 4413 _exit(EXIT_FAILURE);
0b959cf5 4414 }
03cfd8fa
LV		 4415 }
4416
4417 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4418 info, &bprm);
4419 if (ret != 0) {
885c1d10 4420 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4d1275c2 4421 _exit(EXIT_FAILURE);
b12b6a18
TS		 4422 }
4423
4424 for (wrk = target_environ; *wrk; wrk++) {
4425 free(*wrk);
31e31b8a 4426 }
3b46e624 4427
b12b6a18
TS		 4428 free(target_environ);
4429
13829020 4430 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
379f6698 4431 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4432 log_page_dump();
4433
4434 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4435 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4436 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4437 info->start_code);
4438 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4439 info->start_data);
4440 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4441 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4442 info->start_stack);
4443 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4444 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4445 }
31e31b8a 4446
53a5960a 4447 target_set_brk(info->brk);
31e31b8a 4448 syscall_init();
66fb9763 4449 signal_init();
31e31b8a 4450
9002ec79
RH		 4451 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4452 generating the prologue until now so that the prologue can take
4453 the real value of GUEST_BASE into account. */
4454 tcg_prologue_init(&tcg_ctx);
9002ec79 4455
b346ff46 4456#if defined(TARGET_I386)
3802ce26 4457 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4458 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4459 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4460 env->cr[4] |= CR4_OSFXSR_MASK;
4461 env->hflags |= HF_OSFXSR_MASK;
4462 }
d2fd1af7 4463#ifndef TARGET_ABI32
4dbc422b 4464 /* enable 64 bit mode if possible */
0514ef2f 4465 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b 4466 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4d1275c2 4467 exit(EXIT_FAILURE);
4dbc422b 4468 }
d2fd1af7 4469 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4470 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4471 env->hflags |= HF_LMA_MASK;
4472#endif
1bde465e 4473
415e561f
FB		 4474 /* flags setup : we activate the IRQs by default as in user mode */
4475 env->eflags |= IF_MASK;
3b46e624 4476
6dbad63e 4477 /* linux register setup */
d2fd1af7 4478#ifndef TARGET_ABI32
84409ddb
JM		 4479 env->regs[R_EAX] = regs->rax;
4480 env->regs[R_EBX] = regs->rbx;
4481 env->regs[R_ECX] = regs->rcx;
4482 env->regs[R_EDX] = regs->rdx;
4483 env->regs[R_ESI] = regs->rsi;
4484 env->regs[R_EDI] = regs->rdi;
4485 env->regs[R_EBP] = regs->rbp;
4486 env->regs[R_ESP] = regs->rsp;
4487 env->eip = regs->rip;
4488#else
0ecfa993
FB		 4489 env->regs[R_EAX] = regs->eax;
4490 env->regs[R_EBX] = regs->ebx;
4491 env->regs[R_ECX] = regs->ecx;
4492 env->regs[R_EDX] = regs->edx;
4493 env->regs[R_ESI] = regs->esi;
4494 env->regs[R_EDI] = regs->edi;
4495 env->regs[R_EBP] = regs->ebp;
4496 env->regs[R_ESP] = regs->esp;
dab2ed99 4497 env->eip = regs->eip;
84409ddb 4498#endif
31e31b8a 4499
f4beb510 4500 /* linux interrupt setup */
e441570f
AZ		 4501#ifndef TARGET_ABI32
4502 env->idt.limit = 511;
4503#else
4504 env->idt.limit = 255;
4505#endif
4506 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4507 PROT_READ|PROT_WRITE,
4508 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4509 idt_table = g2h(env->idt.base);
f4beb510
FB		 4510 set_idt(0, 0);
4511 set_idt(1, 0);
4512 set_idt(2, 0);
4513 set_idt(3, 3);
4514 set_idt(4, 3);
ec95da6c 4515 set_idt(5, 0);
f4beb510
FB		 4516 set_idt(6, 0);
4517 set_idt(7, 0);
4518 set_idt(8, 0);
4519 set_idt(9, 0);
4520 set_idt(10, 0);
4521 set_idt(11, 0);
4522 set_idt(12, 0);
4523 set_idt(13, 0);
4524 set_idt(14, 0);
4525 set_idt(15, 0);
4526 set_idt(16, 0);
4527 set_idt(17, 0);
4528 set_idt(18, 0);
4529 set_idt(19, 0);
4530 set_idt(0x80, 3);
4531
6dbad63e 4532 /* linux segment setup */
8d18e893
FB		 4533 {
4534 uint64_t *gdt_table;
e441570f
AZ		 4535 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4536 PROT_READ|PROT_WRITE,
4537 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4538 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4539 gdt_table = g2h(env->gdt.base);
d2fd1af7 4540#ifdef TARGET_ABI32
8d18e893
FB		 4541 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4542 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4543 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4544#else
4545 /* 64 bit code segment */
4546 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4547 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4548 DESC_L_MASK |
4549 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4550#endif
8d18e893
FB		 4551 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4552 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4553 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4554 }
6dbad63e 4555 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4556 cpu_x86_load_seg(env, R_SS, __USER_DS);
4557#ifdef TARGET_ABI32
6dbad63e
FB		 4558 cpu_x86_load_seg(env, R_DS, __USER_DS);
4559 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4560 cpu_x86_load_seg(env, R_FS, __USER_DS);
4561 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4562 /* This hack makes Wine work... */
4563 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4564#else
4565 cpu_x86_load_seg(env, R_DS, 0);
4566 cpu_x86_load_seg(env, R_ES, 0);
4567 cpu_x86_load_seg(env, R_FS, 0);
4568 cpu_x86_load_seg(env, R_GS, 0);
4569#endif
99033cae
AG		 4570#elif defined(TARGET_AARCH64)
4571 {
4572 int i;
4573
4574 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4575 fprintf(stderr,
4576 "The selected ARM CPU does not support 64 bit mode\n");
4d1275c2 4577 exit(EXIT_FAILURE);
99033cae
AG		 4578 }
4579
4580 for (i = 0; i < 31; i++) {
4581 env->xregs[i] = regs->regs[i];
4582 }
4583 env->pc = regs->pc;
4584 env->xregs[31] = regs->sp;
4585 }
b346ff46
FB		 4586#elif defined(TARGET_ARM)
4587 {
4588 int i;
ae087923
PM		 4589 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4590 CPSRWriteByInstr);
b346ff46
FB		 4591 for(i = 0; i < 16; i++) {
4592 env->regs[i] = regs->uregs[i];
4593 }
f9fd40eb 4594#ifdef TARGET_WORDS_BIGENDIAN
d8fd2954
PB		 4595 /* Enable BE8. */
4596 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4597 && (info->elf_flags & EF_ARM_BE8)) {
9c5a7460
PC		 4598 env->uncached_cpsr |= CPSR_E;
4599 env->cp15.sctlr_el[1] |= SCTLR_E0E;
f9fd40eb
PB		 4600 } else {
4601 env->cp15.sctlr_el[1] |= SCTLR_B;
d8fd2954 4602 }
f9fd40eb 4603#endif
b346ff46 4604 }
d2fbca94
GX		 4605#elif defined(TARGET_UNICORE32)
4606 {
4607 int i;
4608 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4609 for (i = 0; i < 32; i++) {
4610 env->regs[i] = regs->uregs[i];
4611 }
4612 }
93ac68bc 4613#elif defined(TARGET_SPARC)
060366c5
FB		 4614 {
4615 int i;
4616 env->pc = regs->pc;
4617 env->npc = regs->npc;
4618 env->y = regs->y;
4619 for(i = 0; i < 8; i++)
4620 env->gregs[i] = regs->u_regs[i];
4621 for(i = 0; i < 8; i++)
4622 env->regwptr[i] = regs->u_regs[i + 8];
4623 }
67867308
FB		 4624#elif defined(TARGET_PPC)
4625 {
4626 int i;
3fc6c082 4627
0411a972
JM		 4628#if defined(TARGET_PPC64)
4629#if defined(TARGET_ABI32)
4630 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4631#else
0411a972
JM		 4632 env->msr |= (target_ulong)1 << MSR_SF;
4633#endif
84409ddb 4634#endif
67867308
FB		 4635 env->nip = regs->nip;
4636 for(i = 0; i < 32; i++) {
4637 env->gpr[i] = regs->gpr[i];
4638 }
4639 }
e6e5906b
PB		 4640#elif defined(TARGET_M68K)
4641 {
e6e5906b
PB		 4642 env->pc = regs->pc;
4643 env->dregs[0] = regs->d0;
4644 env->dregs[1] = regs->d1;
4645 env->dregs[2] = regs->d2;
4646 env->dregs[3] = regs->d3;
4647 env->dregs[4] = regs->d4;
4648 env->dregs[5] = regs->d5;
4649 env->dregs[6] = regs->d6;
4650 env->dregs[7] = regs->d7;
4651 env->aregs[0] = regs->a0;
4652 env->aregs[1] = regs->a1;
4653 env->aregs[2] = regs->a2;
4654 env->aregs[3] = regs->a3;
4655 env->aregs[4] = regs->a4;
4656 env->aregs[5] = regs->a5;
4657 env->aregs[6] = regs->a6;
4658 env->aregs[7] = regs->usp;
4659 env->sr = regs->sr;
4660 ts->sim_syscalls = 1;
4661 }
b779e29e
EI		 4662#elif defined(TARGET_MICROBLAZE)
4663 {
4664 env->regs[0] = regs->r0;
4665 env->regs[1] = regs->r1;
4666 env->regs[2] = regs->r2;
4667 env->regs[3] = regs->r3;
4668 env->regs[4] = regs->r4;
4669 env->regs[5] = regs->r5;
4670 env->regs[6] = regs->r6;
4671 env->regs[7] = regs->r7;
4672 env->regs[8] = regs->r8;
4673 env->regs[9] = regs->r9;
4674 env->regs[10] = regs->r10;
4675 env->regs[11] = regs->r11;
4676 env->regs[12] = regs->r12;
4677 env->regs[13] = regs->r13;
4678 env->regs[14] = regs->r14;
4679 env->regs[15] = regs->r15;
4680 env->regs[16] = regs->r16;
4681 env->regs[17] = regs->r17;
4682 env->regs[18] = regs->r18;
4683 env->regs[19] = regs->r19;
4684 env->regs[20] = regs->r20;
4685 env->regs[21] = regs->r21;
4686 env->regs[22] = regs->r22;
4687 env->regs[23] = regs->r23;
4688 env->regs[24] = regs->r24;
4689 env->regs[25] = regs->r25;
4690 env->regs[26] = regs->r26;
4691 env->regs[27] = regs->r27;
4692 env->regs[28] = regs->r28;
4693 env->regs[29] = regs->r29;
4694 env->regs[30] = regs->r30;
4695 env->regs[31] = regs->r31;
4696 env->sregs[SR_PC] = regs->pc;
4697 }
048f6b4d
FB		 4698#elif defined(TARGET_MIPS)
4699 {
4700 int i;
4701
4702 for(i = 0; i < 32; i++) {
b5dc7732 4703 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4704 }
0fddbbf2
NF		 4705 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4706 if (regs->cp0_epc & 1) {
4707 env->hflags |= MIPS_HFLAG_M16;
4708 }
599bc5e8
AM		 4709 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4710 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4711 if ((env->active_fpu.fcr31_rw_bitmask &
4712 (1 << FCR31_NAN2008)) == 0) {
4713 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4714 exit(1);
4715 }
4716 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4717 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4718 } else {
4719 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4720 }
4721 restore_snan_bit_mode(env);
4722 }
048f6b4d 4723 }
d962783e
JL		 4724#elif defined(TARGET_OPENRISC)
4725 {
4726 int i;
4727
4728 for (i = 0; i < 32; i++) {
4729 env->gpr[i] = regs->gpr[i];
4730 }
4731
4732 env->sr = regs->sr;
4733 env->pc = regs->pc;
4734 }
fdf9b3e8
FB		 4735#elif defined(TARGET_SH4)
4736 {
4737 int i;
4738
4739 for(i = 0; i < 16; i++) {
4740 env->gregs[i] = regs->regs[i];
4741 }
4742 env->pc = regs->pc;
4743 }
7a3148a9
JM		 4744#elif defined(TARGET_ALPHA)
4745 {
4746 int i;
4747
4748 for(i = 0; i < 28; i++) {
992f48a0 4749 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4750 }
dad081ee 4751 env->ir[IR_SP] = regs->usp;
7a3148a9 4752 env->pc = regs->pc;
7a3148a9 4753 }
48733d19
TS		 4754#elif defined(TARGET_CRIS)
4755 {
4756 env->regs[0] = regs->r0;
4757 env->regs[1] = regs->r1;
4758 env->regs[2] = regs->r2;
4759 env->regs[3] = regs->r3;
4760 env->regs[4] = regs->r4;
4761 env->regs[5] = regs->r5;
4762 env->regs[6] = regs->r6;
4763 env->regs[7] = regs->r7;
4764 env->regs[8] = regs->r8;
4765 env->regs[9] = regs->r9;
4766 env->regs[10] = regs->r10;
4767 env->regs[11] = regs->r11;
4768 env->regs[12] = regs->r12;
4769 env->regs[13] = regs->r13;
4770 env->regs[14] = info->start_stack;
4771 env->regs[15] = regs->acr;
4772 env->pc = regs->erp;
4773 }
a4c075f1
UH		 4774#elif defined(TARGET_S390X)
4775 {
4776 int i;
4777 for (i = 0; i < 16; i++) {
4778 env->regs[i] = regs->gprs[i];
4779 }
4780 env->psw.mask = regs->psw.mask;
4781 env->psw.addr = regs->psw.addr;
4782 }
b16189b2
CG		 4783#elif defined(TARGET_TILEGX)
4784 {
4785 int i;
4786 for (i = 0; i < TILEGX_R_COUNT; i++) {
4787 env->regs[i] = regs->regs[i];
4788 }
4789 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4790 env->spregs[i] = 0;
4791 }
4792 env->pc = regs->pc;
4793 }
b346ff46
FB		 4794#else
4795#error unsupported target CPU
4796#endif
31e31b8a 4797
d2fbca94 4798#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4799 ts->stack_base = info->start_stack;
4800 ts->heap_base = info->brk;
4801 /* This will be filled in on the first SYS_HEAPINFO call. */
4802 ts->heap_limit = 0;
4803#endif
4804
74c33bed 4805 if (gdbstub_port) {
ff7a981a
PM		 4806 if (gdbserver_start(gdbstub_port) < 0) {
4807 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4808 gdbstub_port);
4d1275c2 4809 exit(EXIT_FAILURE);
ff7a981a 4810 }
db6b81d4 4811 gdb_handlesig(cpu, 0);
1fddef4b 4812 }
1b6b029e
FB		 4813 cpu_loop(env);
4814 /* never exits */
31e31b8a
FB		 4815 return 0;
4816}
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