]> Git Repo - qemu.git/blame - linux-user/main.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
alpha-linux-user: Fill in SI_CODE for SIGSEGV.
[qemu.git] / linux-user / main.c
CommitLineData
31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a
FB		 18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <stdarg.h>
04369ff2 22#include <string.h>
31e31b8a 23#include <errno.h>
0ecfa993 24#include <unistd.h>
e441570f 25#include <sys/mman.h>
edf8e2af 26#include <sys/syscall.h>
703e0e89 27#include <sys/resource.h>
31e31b8a 28
3ef693a0 29#include "qemu.h"
ca10f867 30#include "qemu-common.h"
902b3d5c 31#include "cache-utils.h"
d5975363
PB		 32/* For tb_lock */
33#include "exec-all.h"
9002ec79 34#include "tcg.h"
29e922b6 35#include "qemu-timer.h"
04a6dfeb
AJ		 36#include "envlist.h"
37
3ef693a0 38#define DEBUG_LOGFILE "/tmp/qemu.log"
586314f2 39
d088d664
AJ		 40char *exec_path;
41
1b530a6d 42int singlestep;
379f6698 43unsigned long mmap_min_addr;
14f24e14 44#if defined(CONFIG_USE_GUEST_BASE)
379f6698
PB		 45unsigned long guest_base;
46int have_guest_base;
47#endif
1b530a6d 48
74cd30b8 49static const char *interp_prefix = CONFIG_QEMU_PREFIX;
c5937220 50const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
586314f2 51
9de5e440
FB		 52/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
53 we allocate a bigger stack. Need a better solution, for example
54 by remapping the process stack directly at the right place */
703e0e89 55unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 56
57void gemu_log(const char *fmt, ...)
58{
59 va_list ap;
60
61 va_start(ap, fmt);
62 vfprintf(stderr, fmt, ap);
63 va_end(ap);
64}
65
8fcd3692 66#if defined(TARGET_I386)
a541f297 67int cpu_get_pic_interrupt(CPUState *env)
92ccca6a
FB		 68{
69 return -1;
70}
8fcd3692 71#endif
92ccca6a 72
28ab0e2e
FB		 73/* timers for rdtsc */
74
1dce7c3c 75#if 0
28ab0e2e
FB		 76
77static uint64_t emu_time;
78
79int64_t cpu_get_real_ticks(void)
80{
81 return emu_time++;
82}
83
84#endif
85
2f7bb878 86#if defined(CONFIG_USE_NPTL)
d5975363
PB		 87/***********************************************************/
88/* Helper routines for implementing atomic operations. */
89
90/* To implement exclusive operations we force all cpus to syncronise.
91 We don't require a full sync, only that no cpus are executing guest code.
92 The alternative is to map target atomic ops onto host equivalents,
93 which requires quite a lot of per host/target work. */
c2764719 94static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 95static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
96static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
97static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
98static int pending_cpus;
99
100/* Make sure everything is in a consistent state for calling fork(). */
101void fork_start(void)
102{
d5975363
PB		 103 pthread_mutex_lock(&tb_lock);
104 pthread_mutex_lock(&exclusive_lock);
d032d1b4 105 mmap_fork_start();
d5975363
PB		 106}
107
108void fork_end(int child)
109{
d032d1b4 110 mmap_fork_end(child);
d5975363
PB		 111 if (child) {
112 /* Child processes created by fork() only have a single thread.
113 Discard information about the parent threads. */
114 first_cpu = thread_env;
115 thread_env->next_cpu = NULL;
116 pending_cpus = 0;
117 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 118 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 119 pthread_cond_init(&exclusive_cond, NULL);
120 pthread_cond_init(&exclusive_resume, NULL);
121 pthread_mutex_init(&tb_lock, NULL);
2b1319c8 122 gdbserver_fork(thread_env);
d5975363
PB		 123 } else {
124 pthread_mutex_unlock(&exclusive_lock);
125 pthread_mutex_unlock(&tb_lock);
126 }
d5975363
PB		 127}
128
129/* Wait for pending exclusive operations to complete. The exclusive lock
130 must be held. */
131static inline void exclusive_idle(void)
132{
133 while (pending_cpus) {
134 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
135 }
136}
137
138/* Start an exclusive operation.
139 Must only be called from outside cpu_arm_exec. */
140static inline void start_exclusive(void)
141{
142 CPUState *other;
143 pthread_mutex_lock(&exclusive_lock);
144 exclusive_idle();
145
146 pending_cpus = 1;
147 /* Make all other cpus stop executing. */
148 for (other = first_cpu; other; other = other->next_cpu) {
149 if (other->running) {
150 pending_cpus++;
3098dba0 151 cpu_exit(other);
d5975363
PB		 152 }
153 }
154 if (pending_cpus > 1) {
155 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
156 }
157}
158
159/* Finish an exclusive operation. */
160static inline void end_exclusive(void)
161{
162 pending_cpus = 0;
163 pthread_cond_broadcast(&exclusive_resume);
164 pthread_mutex_unlock(&exclusive_lock);
165}
166
167/* Wait for exclusive ops to finish, and begin cpu execution. */
168static inline void cpu_exec_start(CPUState *env)
169{
170 pthread_mutex_lock(&exclusive_lock);
171 exclusive_idle();
172 env->running = 1;
173 pthread_mutex_unlock(&exclusive_lock);
174}
175
176/* Mark cpu as not executing, and release pending exclusive ops. */
177static inline void cpu_exec_end(CPUState *env)
178{
179 pthread_mutex_lock(&exclusive_lock);
180 env->running = 0;
181 if (pending_cpus > 1) {
182 pending_cpus--;
183 if (pending_cpus == 1) {
184 pthread_cond_signal(&exclusive_cond);
185 }
186 }
187 exclusive_idle();
188 pthread_mutex_unlock(&exclusive_lock);
189}
c2764719
PB		 190
191void cpu_list_lock(void)
192{
193 pthread_mutex_lock(&cpu_list_mutex);
194}
195
196void cpu_list_unlock(void)
197{
198 pthread_mutex_unlock(&cpu_list_mutex);
199}
2f7bb878 200#else /* if !CONFIG_USE_NPTL */
d5975363
PB		 201/* These are no-ops because we are not threadsafe. */
202static inline void cpu_exec_start(CPUState *env)
203{
204}
205
206static inline void cpu_exec_end(CPUState *env)
207{
208}
209
210static inline void start_exclusive(void)
211{
212}
213
214static inline void end_exclusive(void)
215{
216}
217
218void fork_start(void)
219{
220}
221
222void fork_end(int child)
223{
2b1319c8
AJ		 224 if (child) {
225 gdbserver_fork(thread_env);
226 }
d5975363 227}
c2764719
PB		 228
229void cpu_list_lock(void)
230{
231}
232
233void cpu_list_unlock(void)
234{
235}
d5975363
PB		 236#endif
237
238
a541f297
FB		 239#ifdef TARGET_I386
240/***********************************************************/
241/* CPUX86 core interface */
242
02a1602e
FB		 243void cpu_smm_update(CPUState *env)
244{
245}
246
28ab0e2e
FB		 247uint64_t cpu_get_tsc(CPUX86State *env)
248{
249 return cpu_get_real_ticks();
250}
251
5fafdf24 252static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 253 int flags)
6dbad63e 254{
f4beb510 255 unsigned int e1, e2;
53a5960a 256 uint32_t *p;
6dbad63e
FB		 257 e1 = (addr << 16) | (limit & 0xffff);
258 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 259 e2 |= flags;
53a5960a 260 p = ptr;
d538e8f5 261 p[0] = tswap32(e1);
262 p[1] = tswap32(e2);
f4beb510
FB		 263}
264
e441570f 265static uint64_t *idt_table;
eb38c52c 266#ifdef TARGET_X86_64
d2fd1af7
FB		 267static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
268 uint64_t addr, unsigned int sel)
f4beb510 269{
4dbc422b 270 uint32_t *p, e1, e2;
f4beb510
FB		 271 e1 = (addr & 0xffff) | (sel << 16);
272 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 273 p = ptr;
4dbc422b
FB		 274 p[0] = tswap32(e1);
275 p[1] = tswap32(e2);
276 p[2] = tswap32(addr >> 32);
277 p[3] = 0;
6dbad63e 278}
d2fd1af7
FB		 279/* only dpl matters as we do only user space emulation */
280static void set_idt(int n, unsigned int dpl)
281{
282 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
283}
284#else
d2fd1af7
FB		 285static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
286 uint32_t addr, unsigned int sel)
287{
4dbc422b 288 uint32_t *p, e1, e2;
d2fd1af7
FB		 289 e1 = (addr & 0xffff) | (sel << 16);
290 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
291 p = ptr;
4dbc422b
FB		 292 p[0] = tswap32(e1);
293 p[1] = tswap32(e2);
d2fd1af7
FB		 294}
295
f4beb510
FB		 296/* only dpl matters as we do only user space emulation */
297static void set_idt(int n, unsigned int dpl)
298{
299 set_gate(idt_table + n, 0, dpl, 0, 0);
300}
d2fd1af7 301#endif
31e31b8a 302
89e957e7 303void cpu_loop(CPUX86State *env)
1b6b029e 304{
bc8a22cc 305 int trapnr;
992f48a0 306 abi_ulong pc;
c227f099 307 target_siginfo_t info;
851e67a1 308
1b6b029e 309 for(;;) {
bc8a22cc 310 trapnr = cpu_x86_exec(env);
bc8a22cc 311 switch(trapnr) {
f4beb510 312 case 0x80:
d2fd1af7 313 /* linux syscall from int $0x80 */
5fafdf24
TS		 314 env->regs[R_EAX] = do_syscall(env,
315 env->regs[R_EAX],
f4beb510
FB		 316 env->regs[R_EBX],
317 env->regs[R_ECX],
318 env->regs[R_EDX],
319 env->regs[R_ESI],
320 env->regs[R_EDI],
321 env->regs[R_EBP]);
322 break;
d2fd1af7
FB		 323#ifndef TARGET_ABI32
324 case EXCP_SYSCALL:
325 /* linux syscall from syscall intruction */
326 env->regs[R_EAX] = do_syscall(env,
327 env->regs[R_EAX],
328 env->regs[R_EDI],
329 env->regs[R_ESI],
330 env->regs[R_EDX],
331 env->regs[10],
332 env->regs[8],
333 env->regs[9]);
334 env->eip = env->exception_next_eip;
335 break;
336#endif
f4beb510
FB		 337 case EXCP0B_NOSEG:
338 case EXCP0C_STACK:
339 info.si_signo = SIGBUS;
340 info.si_errno = 0;
341 info.si_code = TARGET_SI_KERNEL;
342 info._sifields._sigfault._addr = 0;
624f7979 343 queue_signal(env, info.si_signo, &info);
f4beb510 344 break;
1b6b029e 345 case EXCP0D_GPF:
d2fd1af7 346 /* XXX: potential problem if ABI32 */
84409ddb 347#ifndef TARGET_X86_64
851e67a1 348 if (env->eflags & VM_MASK) {
89e957e7 349 handle_vm86_fault(env);
84409ddb
JM		 350 } else
351#endif
352 {
f4beb510
FB		 353 info.si_signo = SIGSEGV;
354 info.si_errno = 0;
355 info.si_code = TARGET_SI_KERNEL;
356 info._sifields._sigfault._addr = 0;
624f7979 357 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 358 }
359 break;
b689bc57
FB		 360 case EXCP0E_PAGE:
361 info.si_signo = SIGSEGV;
362 info.si_errno = 0;
363 if (!(env->error_code & 1))
364 info.si_code = TARGET_SEGV_MAPERR;
365 else
366 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 367 info._sifields._sigfault._addr = env->cr[2];
624f7979 368 queue_signal(env, info.si_signo, &info);
b689bc57 369 break;
9de5e440 370 case EXCP00_DIVZ:
84409ddb 371#ifndef TARGET_X86_64
bc8a22cc 372 if (env->eflags & VM_MASK) {
447db213 373 handle_vm86_trap(env, trapnr);
84409ddb
JM		 374 } else
375#endif
376 {
bc8a22cc
FB		 377 /* division by zero */
378 info.si_signo = SIGFPE;
379 info.si_errno = 0;
380 info.si_code = TARGET_FPE_INTDIV;
381 info._sifields._sigfault._addr = env->eip;
624f7979 382 queue_signal(env, info.si_signo, &info);
bc8a22cc 383 }
9de5e440 384 break;
01df040b 385 case EXCP01_DB:
447db213 386 case EXCP03_INT3:
84409ddb 387#ifndef TARGET_X86_64
447db213
FB		 388 if (env->eflags & VM_MASK) {
389 handle_vm86_trap(env, trapnr);
84409ddb
JM		 390 } else
391#endif
392 {
447db213
FB		 393 info.si_signo = SIGTRAP;
394 info.si_errno = 0;
01df040b 395 if (trapnr == EXCP01_DB) {
447db213
FB		 396 info.si_code = TARGET_TRAP_BRKPT;
397 info._sifields._sigfault._addr = env->eip;
398 } else {
399 info.si_code = TARGET_SI_KERNEL;
400 info._sifields._sigfault._addr = 0;
401 }
624f7979 402 queue_signal(env, info.si_signo, &info);
447db213
FB		 403 }
404 break;
9de5e440
FB		 405 case EXCP04_INTO:
406 case EXCP05_BOUND:
84409ddb 407#ifndef TARGET_X86_64
bc8a22cc 408 if (env->eflags & VM_MASK) {
447db213 409 handle_vm86_trap(env, trapnr);
84409ddb
JM		 410 } else
411#endif
412 {
bc8a22cc
FB		 413 info.si_signo = SIGSEGV;
414 info.si_errno = 0;
b689bc57 415 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 416 info._sifields._sigfault._addr = 0;
624f7979 417 queue_signal(env, info.si_signo, &info);
bc8a22cc 418 }
9de5e440
FB		 419 break;
420 case EXCP06_ILLOP:
421 info.si_signo = SIGILL;
422 info.si_errno = 0;
423 info.si_code = TARGET_ILL_ILLOPN;
424 info._sifields._sigfault._addr = env->eip;
624f7979 425 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 426 break;
427 case EXCP_INTERRUPT:
428 /* just indicate that signals should be handled asap */
429 break;
1fddef4b
FB		 430 case EXCP_DEBUG:
431 {
432 int sig;
433
434 sig = gdb_handlesig (env, TARGET_SIGTRAP);
435 if (sig)
436 {
437 info.si_signo = sig;
438 info.si_errno = 0;
439 info.si_code = TARGET_TRAP_BRKPT;
624f7979 440 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 441 }
442 }
443 break;
1b6b029e 444 default:
970a87a6 445 pc = env->segs[R_CS].base + env->eip;
5fafdf24 446 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
bc8a22cc 447 (long)pc, trapnr);
1b6b029e
FB		 448 abort();
449 }
66fb9763 450 process_pending_signals(env);
1b6b029e
FB		 451 }
452}
b346ff46
FB		 453#endif
454
455#ifdef TARGET_ARM
456
992f48a0 457static void arm_cache_flush(abi_ulong start, abi_ulong last)
6f1f31c0 458{
992f48a0 459 abi_ulong addr, last1;
6f1f31c0
FB		 460
461 if (last < start)
462 return;
463 addr = start;
464 for(;;) {
465 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
466 if (last1 > last)
467 last1 = last;
468 tb_invalidate_page_range(addr, last1 + 1);
469 if (last1 == last)
470 break;
471 addr = last1 + 1;
472 }
473}
474
fbb4a2e3
PB		 475/* Handle a jump to the kernel code page. */
476static int
477do_kernel_trap(CPUARMState *env)
478{
479 uint32_t addr;
480 uint32_t cpsr;
481 uint32_t val;
482
483 switch (env->regs[15]) {
484 case 0xffff0fa0: /* __kernel_memory_barrier */
485 /* ??? No-op. Will need to do better for SMP. */
486 break;
487 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 488 /* XXX: This only works between threads, not between processes.
489 It's probably possible to implement this with native host
490 operations. However things like ldrex/strex are much harder so
491 there's not much point trying. */
492 start_exclusive();
fbb4a2e3
PB		 493 cpsr = cpsr_read(env);
494 addr = env->regs[2];
495 /* FIXME: This should SEGV if the access fails. */
496 if (get_user_u32(val, addr))
497 val = ~env->regs[0];
498 if (val == env->regs[0]) {
499 val = env->regs[1];
500 /* FIXME: Check for segfaults. */
501 put_user_u32(val, addr);
502 env->regs[0] = 0;
503 cpsr |= CPSR_C;
504 } else {
505 env->regs[0] = -1;
506 cpsr &= ~CPSR_C;
507 }
508 cpsr_write(env, cpsr, CPSR_C);
d5975363 509 end_exclusive();
fbb4a2e3
PB		 510 break;
511 case 0xffff0fe0: /* __kernel_get_tls */
512 env->regs[0] = env->cp15.c13_tls2;
513 break;
514 default:
515 return 1;
516 }
517 /* Jump back to the caller. */
518 addr = env->regs[14];
519 if (addr & 1) {
520 env->thumb = 1;
521 addr &= ~1;
522 }
523 env->regs[15] = addr;
524
525 return 0;
526}
527
426f5abc
PB		 528static int do_strex(CPUARMState *env)
529{
530 uint32_t val;
531 int size;
532 int rc = 1;
533 int segv = 0;
534 uint32_t addr;
535 start_exclusive();
536 addr = env->exclusive_addr;
537 if (addr != env->exclusive_test) {
538 goto fail;
539 }
540 size = env->exclusive_info & 0xf;
541 switch (size) {
542 case 0:
543 segv = get_user_u8(val, addr);
544 break;
545 case 1:
546 segv = get_user_u16(val, addr);
547 break;
548 case 2:
549 case 3:
550 segv = get_user_u32(val, addr);
551 break;
f7001a3b
AJ		 552 default:
553 abort();
426f5abc
PB		 554 }
555 if (segv) {
556 env->cp15.c6_data = addr;
557 goto done;
558 }
559 if (val != env->exclusive_val) {
560 goto fail;
561 }
562 if (size == 3) {
563 segv = get_user_u32(val, addr + 4);
564 if (segv) {
565 env->cp15.c6_data = addr + 4;
566 goto done;
567 }
568 if (val != env->exclusive_high) {
569 goto fail;
570 }
571 }
572 val = env->regs[(env->exclusive_info >> 8) & 0xf];
573 switch (size) {
574 case 0:
575 segv = put_user_u8(val, addr);
576 break;
577 case 1:
578 segv = put_user_u16(val, addr);
579 break;
580 case 2:
581 case 3:
582 segv = put_user_u32(val, addr);
583 break;
584 }
585 if (segv) {
586 env->cp15.c6_data = addr;
587 goto done;
588 }
589 if (size == 3) {
590 val = env->regs[(env->exclusive_info >> 12) & 0xf];
591 segv = put_user_u32(val, addr);
592 if (segv) {
593 env->cp15.c6_data = addr + 4;
594 goto done;
595 }
596 }
597 rc = 0;
598fail:
725b8a69 599 env->regs[15] += 4;
426f5abc
PB		 600 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
601done:
602 end_exclusive();
603 return segv;
604}
605
b346ff46
FB		 606void cpu_loop(CPUARMState *env)
607{
608 int trapnr;
609 unsigned int n, insn;
c227f099 610 target_siginfo_t info;
b5ff1b31 611 uint32_t addr;
3b46e624 612
b346ff46 613 for(;;) {
d5975363 614 cpu_exec_start(env);
b346ff46 615 trapnr = cpu_arm_exec(env);
d5975363 616 cpu_exec_end(env);
b346ff46
FB		 617 switch(trapnr) {
618 case EXCP_UDEF:
c6981055
FB		 619 {
620 TaskState *ts = env->opaque;
621 uint32_t opcode;
6d9a42be 622 int rc;
c6981055
FB		 623
624 /* we handle the FPU emulation here, as Linux */
625 /* we get the opcode */
2f619698
FB		 626 /* FIXME - what to do if get_user() fails? */
627 get_user_u32(opcode, env->regs[15]);
3b46e624 628
6d9a42be
AJ		 629 rc = EmulateAll(opcode, &ts->fpa, env);
630 if (rc == 0) { /* illegal instruction */
c6981055
FB		 631 info.si_signo = SIGILL;
632 info.si_errno = 0;
633 info.si_code = TARGET_ILL_ILLOPN;
634 info._sifields._sigfault._addr = env->regs[15];
624f7979 635 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 636 } else if (rc < 0) { /* FP exception */
637 int arm_fpe=0;
638
639 /* translate softfloat flags to FPSR flags */
640 if (-rc & float_flag_invalid)
641 arm_fpe |= BIT_IOC;
642 if (-rc & float_flag_divbyzero)
643 arm_fpe |= BIT_DZC;
644 if (-rc & float_flag_overflow)
645 arm_fpe |= BIT_OFC;
646 if (-rc & float_flag_underflow)
647 arm_fpe |= BIT_UFC;
648 if (-rc & float_flag_inexact)
649 arm_fpe |= BIT_IXC;
650
651 FPSR fpsr = ts->fpa.fpsr;
652 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
653
654 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
655 info.si_signo = SIGFPE;
656 info.si_errno = 0;
657
658 /* ordered by priority, least first */
659 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
660 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
661 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
662 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
663 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
664
665 info._sifields._sigfault._addr = env->regs[15];
624f7979 666 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 667 } else {
668 env->regs[15] += 4;
669 }
670
671 /* accumulate unenabled exceptions */
672 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
673 fpsr |= BIT_IXC;
674 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
675 fpsr |= BIT_UFC;
676 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
677 fpsr |= BIT_OFC;
678 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
679 fpsr |= BIT_DZC;
680 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
681 fpsr |= BIT_IOC;
682 ts->fpa.fpsr=fpsr;
683 } else { /* everything OK */
c6981055
FB		 684 /* increment PC */
685 env->regs[15] += 4;
686 }
687 }
b346ff46
FB		 688 break;
689 case EXCP_SWI:
06c949e6 690 case EXCP_BKPT:
b346ff46 691 {
ce4defa0 692 env->eabi = 1;
b346ff46 693 /* system call */
06c949e6
PB		 694 if (trapnr == EXCP_BKPT) {
695 if (env->thumb) {
2f619698
FB		 696 /* FIXME - what to do if get_user() fails? */
697 get_user_u16(insn, env->regs[15]);
06c949e6
PB		 698 n = insn & 0xff;
699 env->regs[15] += 2;
700 } else {
2f619698
FB		 701 /* FIXME - what to do if get_user() fails? */
702 get_user_u32(insn, env->regs[15]);
06c949e6
PB		 703 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
704 env->regs[15] += 4;
705 }
192c7bd9 706 } else {
06c949e6 707 if (env->thumb) {
2f619698
FB		 708 /* FIXME - what to do if get_user() fails? */
709 get_user_u16(insn, env->regs[15] - 2);
06c949e6
PB		 710 n = insn & 0xff;
711 } else {
2f619698
FB		 712 /* FIXME - what to do if get_user() fails? */
713 get_user_u32(insn, env->regs[15] - 4);
06c949e6
PB		 714 n = insn & 0xffffff;
715 }
192c7bd9
FB		 716 }
717
6f1f31c0
FB		 718 if (n == ARM_NR_cacheflush) {
719 arm_cache_flush(env->regs[0], env->regs[1]);
a4f81979
FB		 720 } else if (n == ARM_NR_semihosting
721 || n == ARM_NR_thumb_semihosting) {
722 env->regs[0] = do_arm_semihosting (env);
ce4defa0 723 } else if (n == 0 || n >= ARM_SYSCALL_BASE
192c7bd9 724 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
b346ff46 725 /* linux syscall */
ce4defa0 726 if (env->thumb || n == 0) {
192c7bd9
FB		 727 n = env->regs[7];
728 } else {
729 n -= ARM_SYSCALL_BASE;
ce4defa0 730 env->eabi = 0;
192c7bd9 731 }
fbb4a2e3
PB		 732 if ( n > ARM_NR_BASE) {
733 switch (n) {
734 case ARM_NR_cacheflush:
735 arm_cache_flush(env->regs[0], env->regs[1]);
736 break;
737 case ARM_NR_set_tls:
738 cpu_set_tls(env, env->regs[0]);
739 env->regs[0] = 0;
740 break;
741 default:
742 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
743 n);
744 env->regs[0] = -TARGET_ENOSYS;
745 break;
746 }
747 } else {
748 env->regs[0] = do_syscall(env,
749 n,
750 env->regs[0],
751 env->regs[1],
752 env->regs[2],
753 env->regs[3],
754 env->regs[4],
755 env->regs[5]);
756 }
b346ff46
FB		 757 } else {
758 goto error;
759 }
760 }
761 break;
43fff238
FB		 762 case EXCP_INTERRUPT:
763 /* just indicate that signals should be handled asap */
764 break;
68016c62 765 case EXCP_PREFETCH_ABORT:
eae473c1 766 addr = env->cp15.c6_insn;
b5ff1b31 767 goto do_segv;
68016c62 768 case EXCP_DATA_ABORT:
eae473c1 769 addr = env->cp15.c6_data;
b5ff1b31
FB		 770 goto do_segv;
771 do_segv:
68016c62
FB		 772 {
773 info.si_signo = SIGSEGV;
774 info.si_errno = 0;
775 /* XXX: check env->error_code */
776 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 777 info._sifields._sigfault._addr = addr;
624f7979 778 queue_signal(env, info.si_signo, &info);
68016c62
FB		 779 }
780 break;
1fddef4b
FB		 781 case EXCP_DEBUG:
782 {
783 int sig;
784
785 sig = gdb_handlesig (env, TARGET_SIGTRAP);
786 if (sig)
787 {
788 info.si_signo = sig;
789 info.si_errno = 0;
790 info.si_code = TARGET_TRAP_BRKPT;
624f7979 791 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 792 }
793 }
794 break;
fbb4a2e3
PB		 795 case EXCP_KERNEL_TRAP:
796 if (do_kernel_trap(env))
797 goto error;
798 break;
426f5abc
PB		 799 case EXCP_STREX:
800 if (do_strex(env)) {
801 addr = env->cp15.c6_data;
802 goto do_segv;
803 }
e9273455 804 break;
b346ff46
FB		 805 default:
806 error:
5fafdf24 807 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
b346ff46 808 trapnr);
7fe48483 809 cpu_dump_state(env, stderr, fprintf, 0);
b346ff46
FB		 810 abort();
811 }
812 process_pending_signals(env);
813 }
814}
815
816#endif
1b6b029e 817
93ac68bc 818#ifdef TARGET_SPARC
ed23fbd9 819#define SPARC64_STACK_BIAS 2047
93ac68bc 820
060366c5
FB		 821//#define DEBUG_WIN
822
2623cbaf
FB		 823/* WARNING: dealing with register windows _is_ complicated. More info
824 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 825static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
826{
1a14026e 827 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 828 /* wrap handling : if cwp is on the last window, then we use the
829 registers 'after' the end */
1a14026e
BS		 830 if (index < 8 && env->cwp == env->nwindows - 1)
831 index += 16 * env->nwindows;
060366c5
FB		 832 return index;
833}
834
2623cbaf
FB		 835/* save the register window 'cwp1' */
836static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 837{
2623cbaf 838 unsigned int i;
992f48a0 839 abi_ulong sp_ptr;
3b46e624 840
53a5960a 841 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 842#ifdef TARGET_SPARC64
843 if (sp_ptr & 3)
844 sp_ptr += SPARC64_STACK_BIAS;
845#endif
060366c5 846#if defined(DEBUG_WIN)
2daf0284
BS		 847 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
848 sp_ptr, cwp1);
060366c5 849#endif
2623cbaf 850 for(i = 0; i < 16; i++) {
2f619698
FB		 851 /* FIXME - what to do if put_user() fails? */
852 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 853 sp_ptr += sizeof(abi_ulong);
2623cbaf 854 }
060366c5
FB		 855}
856
857static void save_window(CPUSPARCState *env)
858{
5ef54116 859#ifndef TARGET_SPARC64
2623cbaf 860 unsigned int new_wim;
1a14026e
BS		 861 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
862 ((1LL << env->nwindows) - 1);
863 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 864 env->wim = new_wim;
5ef54116 865#else
1a14026e 866 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 867 env->cansave++;
868 env->canrestore--;
869#endif
060366c5
FB		 870}
871
872static void restore_window(CPUSPARCState *env)
873{
eda52953
BS		 874#ifndef TARGET_SPARC64
875 unsigned int new_wim;
876#endif
877 unsigned int i, cwp1;
992f48a0 878 abi_ulong sp_ptr;
3b46e624 879
eda52953 880#ifndef TARGET_SPARC64
1a14026e
BS		 881 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
882 ((1LL << env->nwindows) - 1);
eda52953 883#endif
3b46e624 884
060366c5 885 /* restore the invalid window */
1a14026e 886 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 887 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 888#ifdef TARGET_SPARC64
889 if (sp_ptr & 3)
890 sp_ptr += SPARC64_STACK_BIAS;
891#endif
060366c5 892#if defined(DEBUG_WIN)
2daf0284
BS		 893 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
894 sp_ptr, cwp1);
060366c5 895#endif
2623cbaf 896 for(i = 0; i < 16; i++) {
2f619698
FB		 897 /* FIXME - what to do if get_user() fails? */
898 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 899 sp_ptr += sizeof(abi_ulong);
2623cbaf 900 }
5ef54116
FB		 901#ifdef TARGET_SPARC64
902 env->canrestore++;
1a14026e
BS		 903 if (env->cleanwin < env->nwindows - 1)
904 env->cleanwin++;
5ef54116 905 env->cansave--;
eda52953
BS		 906#else
907 env->wim = new_wim;
5ef54116 908#endif
060366c5
FB		 909}
910
911static void flush_windows(CPUSPARCState *env)
912{
913 int offset, cwp1;
2623cbaf
FB		 914
915 offset = 1;
060366c5
FB		 916 for(;;) {
917 /* if restore would invoke restore_window(), then we can stop */
1a14026e 918 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 919#ifndef TARGET_SPARC64
060366c5
FB		 920 if (env->wim & (1 << cwp1))
921 break;
eda52953
BS		 922#else
923 if (env->canrestore == 0)
924 break;
925 env->cansave++;
926 env->canrestore--;
927#endif
2623cbaf 928 save_window_offset(env, cwp1);
060366c5
FB		 929 offset++;
930 }
1a14026e 931 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 932#ifndef TARGET_SPARC64
933 /* set wim so that restore will reload the registers */
2623cbaf 934 env->wim = 1 << cwp1;
eda52953 935#endif
2623cbaf
FB		 936#if defined(DEBUG_WIN)
937 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 938#endif
2623cbaf 939}
060366c5 940
93ac68bc
FB		 941void cpu_loop (CPUSPARCState *env)
942{
2cc20260
RH		 943 int trapnr;
944 abi_long ret;
c227f099 945 target_siginfo_t info;
3b46e624 946
060366c5
FB		 947 while (1) {
948 trapnr = cpu_sparc_exec (env);
3b46e624 949
060366c5 950 switch (trapnr) {
5ef54116 951#ifndef TARGET_SPARC64
5fafdf24 952 case 0x88:
060366c5 953 case 0x90:
5ef54116 954#else
cb33da57 955 case 0x110:
5ef54116
FB		 956 case 0x16d:
957#endif
060366c5 958 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 959 env->regwptr[0], env->regwptr[1],
960 env->regwptr[2], env->regwptr[3],
060366c5 961 env->regwptr[4], env->regwptr[5]);
2cc20260 962 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 963#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 964 env->xcc |= PSR_CARRY;
965#else
060366c5 966 env->psr |= PSR_CARRY;
27908725 967#endif
060366c5
FB		 968 ret = -ret;
969 } else {
992f48a0 970#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 971 env->xcc &= ~PSR_CARRY;
972#else
060366c5 973 env->psr &= ~PSR_CARRY;
27908725 974#endif
060366c5
FB		 975 }
976 env->regwptr[0] = ret;
977 /* next instruction */
978 env->pc = env->npc;
979 env->npc = env->npc + 4;
980 break;
981 case 0x83: /* flush windows */
992f48a0
BS		 982#ifdef TARGET_ABI32
983 case 0x103:
984#endif
2623cbaf 985 flush_windows(env);
060366c5
FB		 986 /* next instruction */
987 env->pc = env->npc;
988 env->npc = env->npc + 4;
989 break;
3475187d 990#ifndef TARGET_SPARC64
060366c5
FB		 991 case TT_WIN_OVF: /* window overflow */
992 save_window(env);
993 break;
994 case TT_WIN_UNF: /* window underflow */
995 restore_window(env);
996 break;
61ff6f58
FB		 997 case TT_TFAULT:
998 case TT_DFAULT:
999 {
1000 info.si_signo = SIGSEGV;
1001 info.si_errno = 0;
1002 /* XXX: check env->error_code */
1003 info.si_code = TARGET_SEGV_MAPERR;
1004 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1005 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1006 }
1007 break;
3475187d 1008#else
5ef54116
FB		 1009 case TT_SPILL: /* window overflow */
1010 save_window(env);
1011 break;
1012 case TT_FILL: /* window underflow */
1013 restore_window(env);
1014 break;
7f84a729
BS		 1015 case TT_TFAULT:
1016 case TT_DFAULT:
1017 {
1018 info.si_signo = SIGSEGV;
1019 info.si_errno = 0;
1020 /* XXX: check env->error_code */
1021 info.si_code = TARGET_SEGV_MAPERR;
1022 if (trapnr == TT_DFAULT)
1023 info._sifields._sigfault._addr = env->dmmuregs[4];
1024 else
8194f35a 1025 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1026 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1027 }
1028 break;
27524dc3 1029#ifndef TARGET_ABI32
5bfb56b2
BS		 1030 case 0x16e:
1031 flush_windows(env);
1032 sparc64_get_context(env);
1033 break;
1034 case 0x16f:
1035 flush_windows(env);
1036 sparc64_set_context(env);
1037 break;
27524dc3 1038#endif
3475187d 1039#endif
48dc41eb
FB		 1040 case EXCP_INTERRUPT:
1041 /* just indicate that signals should be handled asap */
1042 break;
1fddef4b
FB		 1043 case EXCP_DEBUG:
1044 {
1045 int sig;
1046
1047 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1048 if (sig)
1049 {
1050 info.si_signo = sig;
1051 info.si_errno = 0;
1052 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1053 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1054 }
1055 }
1056 break;
060366c5
FB		 1057 default:
1058 printf ("Unhandled trap: 0x%x\n", trapnr);
7fe48483 1059 cpu_dump_state(env, stderr, fprintf, 0);
060366c5
FB		 1060 exit (1);
1061 }
1062 process_pending_signals (env);
1063 }
93ac68bc
FB		 1064}
1065
1066#endif
1067
67867308 1068#ifdef TARGET_PPC
9fddaa0c
FB		 1069static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1070{
1071 /* TO FIX */
1072 return 0;
1073}
3b46e624 1074
e3ea6529 1075uint64_t cpu_ppc_load_tbl (CPUState *env)
9fddaa0c 1076{
e3ea6529 1077 return cpu_ppc_get_tb(env);
9fddaa0c 1078}
3b46e624 1079
9fddaa0c
FB		 1080uint32_t cpu_ppc_load_tbu (CPUState *env)
1081{
1082 return cpu_ppc_get_tb(env) >> 32;
1083}
3b46e624 1084
b711de95 1085uint64_t cpu_ppc_load_atbl (CPUState *env)
9fddaa0c 1086{
b711de95 1087 return cpu_ppc_get_tb(env);
9fddaa0c 1088}
5fafdf24 1089
a062e36c 1090uint32_t cpu_ppc_load_atbu (CPUState *env)
9fddaa0c 1091{
a062e36c 1092 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1093}
76a66253 1094
76a66253
JM		 1095uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1096__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1097
76a66253 1098uint32_t cpu_ppc601_load_rtcl (CPUState *env)
9fddaa0c 1099{
76a66253 1100 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1101}
76a66253 1102
a750fc0b 1103/* XXX: to be fixed */
73b01960 1104int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1105{
1106 return -1;
1107}
1108
73b01960 1109int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1110{
1111 return -1;
1112}
1113
001faf32
BS		 1114#define EXCP_DUMP(env, fmt, ...) \
1115do { \
1116 fprintf(stderr, fmt , ## __VA_ARGS__); \
1117 cpu_dump_state(env, stderr, fprintf, 0); \
1118 qemu_log(fmt, ## __VA_ARGS__); \
430c7ec7 1119 if (logfile) \
1120 log_cpu_state(env, 0); \
e1833e1f
JM		 1121} while (0)
1122
56f066bb
NF		 1123static int do_store_exclusive(CPUPPCState *env)
1124{
1125 target_ulong addr;
1126 target_ulong page_addr;
1127 target_ulong val;
1128 int flags;
1129 int segv = 0;
1130
1131 addr = env->reserve_ea;
1132 page_addr = addr & TARGET_PAGE_MASK;
1133 start_exclusive();
1134 mmap_lock();
1135 flags = page_get_flags(page_addr);
1136 if ((flags & PAGE_READ) == 0) {
1137 segv = 1;
1138 } else {
1139 int reg = env->reserve_info & 0x1f;
1140 int size = (env->reserve_info >> 5) & 0xf;
1141 int stored = 0;
1142
1143 if (addr == env->reserve_addr) {
1144 switch (size) {
1145 case 1: segv = get_user_u8(val, addr); break;
1146 case 2: segv = get_user_u16(val, addr); break;
1147 case 4: segv = get_user_u32(val, addr); break;
1148#if defined(TARGET_PPC64)
1149 case 8: segv = get_user_u64(val, addr); break;
1150#endif
1151 default: abort();
1152 }
1153 if (!segv && val == env->reserve_val) {
1154 val = env->gpr[reg];
1155 switch (size) {
1156 case 1: segv = put_user_u8(val, addr); break;
1157 case 2: segv = put_user_u16(val, addr); break;
1158 case 4: segv = put_user_u32(val, addr); break;
1159#if defined(TARGET_PPC64)
1160 case 8: segv = put_user_u64(val, addr); break;
1161#endif
1162 default: abort();
1163 }
1164 if (!segv) {
1165 stored = 1;
1166 }
1167 }
1168 }
1169 env->crf[0] = (stored << 1) | xer_so;
1170 env->reserve_addr = (target_ulong)-1;
1171 }
1172 if (!segv) {
1173 env->nip += 4;
1174 }
1175 mmap_unlock();
1176 end_exclusive();
1177 return segv;
1178}
1179
67867308
FB		 1180void cpu_loop(CPUPPCState *env)
1181{
c227f099 1182 target_siginfo_t info;
61190b14
FB		 1183 int trapnr;
1184 uint32_t ret;
3b46e624 1185
67867308 1186 for(;;) {
56f066bb 1187 cpu_exec_start(env);
67867308 1188 trapnr = cpu_ppc_exec(env);
56f066bb 1189 cpu_exec_end(env);
67867308 1190 switch(trapnr) {
e1833e1f
JM		 1191 case POWERPC_EXCP_NONE:
1192 /* Just go on */
67867308 1193 break;
e1833e1f
JM		 1194 case POWERPC_EXCP_CRITICAL: /* Critical input */
1195 cpu_abort(env, "Critical interrupt while in user mode. "
1196 "Aborting\n");
61190b14 1197 break;
e1833e1f
JM		 1198 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1199 cpu_abort(env, "Machine check exception while in user mode. "
1200 "Aborting\n");
1201 break;
1202 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1203 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1204 env->spr[SPR_DAR]);
1205 /* XXX: check this. Seems bugged */
2be0071f
FB		 1206 switch (env->error_code & 0xFF000000) {
1207 case 0x40000000:
61190b14
FB		 1208 info.si_signo = TARGET_SIGSEGV;
1209 info.si_errno = 0;
1210 info.si_code = TARGET_SEGV_MAPERR;
1211 break;
2be0071f 1212 case 0x04000000:
61190b14
FB		 1213 info.si_signo = TARGET_SIGILL;
1214 info.si_errno = 0;
1215 info.si_code = TARGET_ILL_ILLADR;
1216 break;
2be0071f 1217 case 0x08000000:
61190b14
FB		 1218 info.si_signo = TARGET_SIGSEGV;
1219 info.si_errno = 0;
1220 info.si_code = TARGET_SEGV_ACCERR;
1221 break;
61190b14
FB		 1222 default:
1223 /* Let's send a regular segfault... */
e1833e1f
JM		 1224 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1225 env->error_code);
61190b14
FB		 1226 info.si_signo = TARGET_SIGSEGV;
1227 info.si_errno = 0;
1228 info.si_code = TARGET_SEGV_MAPERR;
1229 break;
1230 }
67867308 1231 info._sifields._sigfault._addr = env->nip;
624f7979 1232 queue_signal(env, info.si_signo, &info);
67867308 1233 break;
e1833e1f 1234 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1235 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1236 "\n", env->spr[SPR_SRR0]);
e1833e1f 1237 /* XXX: check this */
2be0071f
FB		 1238 switch (env->error_code & 0xFF000000) {
1239 case 0x40000000:
61190b14 1240 info.si_signo = TARGET_SIGSEGV;
67867308 1241 info.si_errno = 0;
61190b14
FB		 1242 info.si_code = TARGET_SEGV_MAPERR;
1243 break;
2be0071f
FB		 1244 case 0x10000000:
1245 case 0x08000000:
61190b14
FB		 1246 info.si_signo = TARGET_SIGSEGV;
1247 info.si_errno = 0;
1248 info.si_code = TARGET_SEGV_ACCERR;
1249 break;
1250 default:
1251 /* Let's send a regular segfault... */
e1833e1f
JM		 1252 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1253 env->error_code);
61190b14
FB		 1254 info.si_signo = TARGET_SIGSEGV;
1255 info.si_errno = 0;
1256 info.si_code = TARGET_SEGV_MAPERR;
1257 break;
1258 }
1259 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1260 queue_signal(env, info.si_signo, &info);
67867308 1261 break;
e1833e1f
JM		 1262 case POWERPC_EXCP_EXTERNAL: /* External input */
1263 cpu_abort(env, "External interrupt while in user mode. "
1264 "Aborting\n");
1265 break;
1266 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1267 EXCP_DUMP(env, "Unaligned memory access\n");
1268 /* XXX: check this */
61190b14 1269 info.si_signo = TARGET_SIGBUS;
67867308 1270 info.si_errno = 0;
61190b14
FB		 1271 info.si_code = TARGET_BUS_ADRALN;
1272 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1273 queue_signal(env, info.si_signo, &info);
67867308 1274 break;
e1833e1f
JM		 1275 case POWERPC_EXCP_PROGRAM: /* Program exception */
1276 /* XXX: check this */
61190b14 1277 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1278 case POWERPC_EXCP_FP:
1279 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1280 info.si_signo = TARGET_SIGFPE;
1281 info.si_errno = 0;
1282 switch (env->error_code & 0xF) {
e1833e1f 1283 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1284 info.si_code = TARGET_FPE_FLTOVF;
1285 break;
e1833e1f 1286 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1287 info.si_code = TARGET_FPE_FLTUND;
1288 break;
e1833e1f
JM		 1289 case POWERPC_EXCP_FP_ZX:
1290 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1291 info.si_code = TARGET_FPE_FLTDIV;
1292 break;
e1833e1f 1293 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1294 info.si_code = TARGET_FPE_FLTRES;
1295 break;
e1833e1f 1296 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1297 info.si_code = TARGET_FPE_FLTINV;
1298 break;
7c58044c 1299 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1300 case POWERPC_EXCP_FP_VXISI:
1301 case POWERPC_EXCP_FP_VXIDI:
1302 case POWERPC_EXCP_FP_VXIMZ:
1303 case POWERPC_EXCP_FP_VXVC:
1304 case POWERPC_EXCP_FP_VXSQRT:
1305 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1306 info.si_code = TARGET_FPE_FLTSUB;
1307 break;
1308 default:
e1833e1f
JM		 1309 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1310 env->error_code);
1311 break;
61190b14 1312 }
e1833e1f
JM		 1313 break;
1314 case POWERPC_EXCP_INVAL:
1315 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1316 info.si_signo = TARGET_SIGILL;
1317 info.si_errno = 0;
1318 switch (env->error_code & 0xF) {
e1833e1f 1319 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1320 info.si_code = TARGET_ILL_ILLOPC;
1321 break;
e1833e1f 1322 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1323 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1324 break;
e1833e1f 1325 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1326 info.si_code = TARGET_ILL_PRVREG;
1327 break;
e1833e1f 1328 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1329 info.si_code = TARGET_ILL_COPROC;
1330 break;
1331 default:
e1833e1f
JM		 1332 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1333 env->error_code & 0xF);
61190b14
FB		 1334 info.si_code = TARGET_ILL_ILLADR;
1335 break;
1336 }
1337 break;
e1833e1f
JM		 1338 case POWERPC_EXCP_PRIV:
1339 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1340 info.si_signo = TARGET_SIGILL;
1341 info.si_errno = 0;
1342 switch (env->error_code & 0xF) {
e1833e1f 1343 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1344 info.si_code = TARGET_ILL_PRVOPC;
1345 break;
e1833e1f 1346 case POWERPC_EXCP_PRIV_REG:
61190b14 1347 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1348 break;
61190b14 1349 default:
e1833e1f
JM		 1350 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1351 env->error_code & 0xF);
61190b14
FB		 1352 info.si_code = TARGET_ILL_PRVOPC;
1353 break;
1354 }
1355 break;
e1833e1f
JM		 1356 case POWERPC_EXCP_TRAP:
1357 cpu_abort(env, "Tried to call a TRAP\n");
1358 break;
61190b14
FB		 1359 default:
1360 /* Should not happen ! */
e1833e1f
JM		 1361 cpu_abort(env, "Unknown program exception (%02x)\n",
1362 env->error_code);
1363 break;
61190b14
FB		 1364 }
1365 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1366 queue_signal(env, info.si_signo, &info);
67867308 1367 break;
e1833e1f
JM		 1368 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1369 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1370 info.si_signo = TARGET_SIGILL;
67867308 1371 info.si_errno = 0;
61190b14
FB		 1372 info.si_code = TARGET_ILL_COPROC;
1373 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1374 queue_signal(env, info.si_signo, &info);
67867308 1375 break;
e1833e1f
JM		 1376 case POWERPC_EXCP_SYSCALL: /* System call exception */
1377 cpu_abort(env, "Syscall exception while in user mode. "
1378 "Aborting\n");
61190b14 1379 break;
e1833e1f
JM		 1380 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1381 EXCP_DUMP(env, "No APU instruction allowed\n");
1382 info.si_signo = TARGET_SIGILL;
1383 info.si_errno = 0;
1384 info.si_code = TARGET_ILL_COPROC;
1385 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1386 queue_signal(env, info.si_signo, &info);
61190b14 1387 break;
e1833e1f
JM		 1388 case POWERPC_EXCP_DECR: /* Decrementer exception */
1389 cpu_abort(env, "Decrementer interrupt while in user mode. "
1390 "Aborting\n");
61190b14 1391 break;
e1833e1f
JM		 1392 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1393 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1394 "Aborting\n");
1395 break;
1396 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1397 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1398 "Aborting\n");
1399 break;
1400 case POWERPC_EXCP_DTLB: /* Data TLB error */
1401 cpu_abort(env, "Data TLB exception while in user mode. "
1402 "Aborting\n");
1403 break;
1404 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1405 cpu_abort(env, "Instruction TLB exception while in user mode. "
1406 "Aborting\n");
1407 break;
e1833e1f
JM		 1408 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1409 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1410 info.si_signo = TARGET_SIGILL;
1411 info.si_errno = 0;
1412 info.si_code = TARGET_ILL_COPROC;
1413 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1414 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1415 break;
1416 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1417 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1418 break;
1419 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1420 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1421 break;
1422 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1423 cpu_abort(env, "Performance monitor exception not handled\n");
1424 break;
1425 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1426 cpu_abort(env, "Doorbell interrupt while in user mode. "
1427 "Aborting\n");
1428 break;
1429 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1430 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1431 "Aborting\n");
1432 break;
1433 case POWERPC_EXCP_RESET: /* System reset exception */
1434 cpu_abort(env, "Reset interrupt while in user mode. "
1435 "Aborting\n");
1436 break;
e1833e1f
JM		 1437 case POWERPC_EXCP_DSEG: /* Data segment exception */
1438 cpu_abort(env, "Data segment exception while in user mode. "
1439 "Aborting\n");
1440 break;
1441 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1442 cpu_abort(env, "Instruction segment exception "
1443 "while in user mode. Aborting\n");
1444 break;
e85e7c6e 1445 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1446 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1447 cpu_abort(env, "Hypervisor decrementer interrupt "
1448 "while in user mode. Aborting\n");
1449 break;
e1833e1f
JM		 1450 case POWERPC_EXCP_TRACE: /* Trace exception */
1451 /* Nothing to do:
1452 * we use this exception to emulate step-by-step execution mode.
1453 */
1454 break;
e85e7c6e 1455 /* PowerPC 64 with hypervisor mode support */
e1833e1f
JM		 1456 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1457 cpu_abort(env, "Hypervisor data storage exception "
1458 "while in user mode. Aborting\n");
1459 break;
1460 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1461 cpu_abort(env, "Hypervisor instruction storage exception "
1462 "while in user mode. Aborting\n");
1463 break;
1464 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1465 cpu_abort(env, "Hypervisor data segment exception "
1466 "while in user mode. Aborting\n");
1467 break;
1468 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1469 cpu_abort(env, "Hypervisor instruction segment exception "
1470 "while in user mode. Aborting\n");
1471 break;
e1833e1f
JM		 1472 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1473 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1474 info.si_signo = TARGET_SIGILL;
1475 info.si_errno = 0;
1476 info.si_code = TARGET_ILL_COPROC;
1477 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1478 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1479 break;
1480 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1481 cpu_abort(env, "Programable interval timer interrupt "
1482 "while in user mode. Aborting\n");
1483 break;
1484 case POWERPC_EXCP_IO: /* IO error exception */
1485 cpu_abort(env, "IO error exception while in user mode. "
1486 "Aborting\n");
1487 break;
1488 case POWERPC_EXCP_RUNM: /* Run mode exception */
1489 cpu_abort(env, "Run mode exception while in user mode. "
1490 "Aborting\n");
1491 break;
1492 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1493 cpu_abort(env, "Emulation trap exception not handled\n");
1494 break;
1495 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1496 cpu_abort(env, "Instruction fetch TLB exception "
1497 "while in user-mode. Aborting");
1498 break;
1499 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1500 cpu_abort(env, "Data load TLB exception while in user-mode. "
1501 "Aborting");
1502 break;
1503 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1504 cpu_abort(env, "Data store TLB exception while in user-mode. "
1505 "Aborting");
1506 break;
1507 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1508 cpu_abort(env, "Floating-point assist exception not handled\n");
1509 break;
1510 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1511 cpu_abort(env, "Instruction address breakpoint exception "
1512 "not handled\n");
1513 break;
1514 case POWERPC_EXCP_SMI: /* System management interrupt */
1515 cpu_abort(env, "System management interrupt while in user mode. "
1516 "Aborting\n");
1517 break;
1518 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1519 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1520 "Aborting\n");
1521 break;
1522 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1523 cpu_abort(env, "Performance monitor exception not handled\n");
1524 break;
1525 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1526 cpu_abort(env, "Vector assist exception not handled\n");
1527 break;
1528 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1529 cpu_abort(env, "Soft patch exception not handled\n");
1530 break;
1531 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1532 cpu_abort(env, "Maintenance exception while in user mode. "
1533 "Aborting\n");
1534 break;
1535 case POWERPC_EXCP_STOP: /* stop translation */
1536 /* We did invalidate the instruction cache. Go on */
1537 break;
1538 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1539 /* We just stopped because of a branch. Go on */
1540 break;
1541 case POWERPC_EXCP_SYSCALL_USER:
1542 /* system call in user-mode emulation */
1543 /* WARNING:
1544 * PPC ABI uses overflow flag in cr0 to signal an error
1545 * in syscalls.
1546 */
1547#if 0
1548 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1549 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1550#endif
1551 env->crf[0] &= ~0x1;
1552 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1553 env->gpr[5], env->gpr[6], env->gpr[7],
1554 env->gpr[8]);
bcd4933a
NF		 1555 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) {
1556 /* Returning from a successful sigreturn syscall.
1557 Avoid corrupting register state. */
1558 break;
1559 }
e1833e1f
JM		 1560 if (ret > (uint32_t)(-515)) {
1561 env->crf[0] |= 0x1;
1562 ret = -ret;
61190b14 1563 }
e1833e1f
JM		 1564 env->gpr[3] = ret;
1565#if 0
1566 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1567#endif
1568 break;
56f066bb
NF		 1569 case POWERPC_EXCP_STCX:
1570 if (do_store_exclusive(env)) {
1571 info.si_signo = TARGET_SIGSEGV;
1572 info.si_errno = 0;
1573 info.si_code = TARGET_SEGV_MAPERR;
1574 info._sifields._sigfault._addr = env->nip;
1575 queue_signal(env, info.si_signo, &info);
1576 }
1577 break;
71f75756
AJ		 1578 case EXCP_DEBUG:
1579 {
1580 int sig;
1581
1582 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1583 if (sig) {
1584 info.si_signo = sig;
1585 info.si_errno = 0;
1586 info.si_code = TARGET_TRAP_BRKPT;
1587 queue_signal(env, info.si_signo, &info);
1588 }
1589 }
1590 break;
56ba31ff
JM		 1591 case EXCP_INTERRUPT:
1592 /* just indicate that signals should be handled asap */
1593 break;
e1833e1f
JM		 1594 default:
1595 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1596 break;
67867308
FB		 1597 }
1598 process_pending_signals(env);
1599 }
1600}
1601#endif
1602
048f6b4d
FB		 1603#ifdef TARGET_MIPS
1604
1605#define MIPS_SYS(name, args) args,
1606
1607static const uint8_t mips_syscall_args[] = {
1608 MIPS_SYS(sys_syscall , 0) /* 4000 */
1609 MIPS_SYS(sys_exit , 1)
1610 MIPS_SYS(sys_fork , 0)
1611 MIPS_SYS(sys_read , 3)
1612 MIPS_SYS(sys_write , 3)
1613 MIPS_SYS(sys_open , 3) /* 4005 */
1614 MIPS_SYS(sys_close , 1)
1615 MIPS_SYS(sys_waitpid , 3)
1616 MIPS_SYS(sys_creat , 2)
1617 MIPS_SYS(sys_link , 2)
1618 MIPS_SYS(sys_unlink , 1) /* 4010 */
1619 MIPS_SYS(sys_execve , 0)
1620 MIPS_SYS(sys_chdir , 1)
1621 MIPS_SYS(sys_time , 1)
1622 MIPS_SYS(sys_mknod , 3)
1623 MIPS_SYS(sys_chmod , 2) /* 4015 */
1624 MIPS_SYS(sys_lchown , 3)
1625 MIPS_SYS(sys_ni_syscall , 0)
1626 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1627 MIPS_SYS(sys_lseek , 3)
1628 MIPS_SYS(sys_getpid , 0) /* 4020 */
1629 MIPS_SYS(sys_mount , 5)
1630 MIPS_SYS(sys_oldumount , 1)
1631 MIPS_SYS(sys_setuid , 1)
1632 MIPS_SYS(sys_getuid , 0)
1633 MIPS_SYS(sys_stime , 1) /* 4025 */
1634 MIPS_SYS(sys_ptrace , 4)
1635 MIPS_SYS(sys_alarm , 1)
1636 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1637 MIPS_SYS(sys_pause , 0)
1638 MIPS_SYS(sys_utime , 2) /* 4030 */
1639 MIPS_SYS(sys_ni_syscall , 0)
1640 MIPS_SYS(sys_ni_syscall , 0)
1641 MIPS_SYS(sys_access , 2)
1642 MIPS_SYS(sys_nice , 1)
1643 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1644 MIPS_SYS(sys_sync , 0)
1645 MIPS_SYS(sys_kill , 2)
1646 MIPS_SYS(sys_rename , 2)
1647 MIPS_SYS(sys_mkdir , 2)
1648 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1649 MIPS_SYS(sys_dup , 1)
1650 MIPS_SYS(sys_pipe , 0)
1651 MIPS_SYS(sys_times , 1)
1652 MIPS_SYS(sys_ni_syscall , 0)
1653 MIPS_SYS(sys_brk , 1) /* 4045 */
1654 MIPS_SYS(sys_setgid , 1)
1655 MIPS_SYS(sys_getgid , 0)
1656 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1657 MIPS_SYS(sys_geteuid , 0)
1658 MIPS_SYS(sys_getegid , 0) /* 4050 */
1659 MIPS_SYS(sys_acct , 0)
1660 MIPS_SYS(sys_umount , 2)
1661 MIPS_SYS(sys_ni_syscall , 0)
1662 MIPS_SYS(sys_ioctl , 3)
1663 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1664 MIPS_SYS(sys_ni_syscall , 2)
1665 MIPS_SYS(sys_setpgid , 2)
1666 MIPS_SYS(sys_ni_syscall , 0)
1667 MIPS_SYS(sys_olduname , 1)
1668 MIPS_SYS(sys_umask , 1) /* 4060 */
1669 MIPS_SYS(sys_chroot , 1)
1670 MIPS_SYS(sys_ustat , 2)
1671 MIPS_SYS(sys_dup2 , 2)
1672 MIPS_SYS(sys_getppid , 0)
1673 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1674 MIPS_SYS(sys_setsid , 0)
1675 MIPS_SYS(sys_sigaction , 3)
1676 MIPS_SYS(sys_sgetmask , 0)
1677 MIPS_SYS(sys_ssetmask , 1)
1678 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1679 MIPS_SYS(sys_setregid , 2)
1680 MIPS_SYS(sys_sigsuspend , 0)
1681 MIPS_SYS(sys_sigpending , 1)
1682 MIPS_SYS(sys_sethostname , 2)
1683 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1684 MIPS_SYS(sys_getrlimit , 2)
1685 MIPS_SYS(sys_getrusage , 2)
1686 MIPS_SYS(sys_gettimeofday, 2)
1687 MIPS_SYS(sys_settimeofday, 2)
1688 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1689 MIPS_SYS(sys_setgroups , 2)
1690 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1691 MIPS_SYS(sys_symlink , 2)
1692 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1693 MIPS_SYS(sys_readlink , 3) /* 4085 */
1694 MIPS_SYS(sys_uselib , 1)
1695 MIPS_SYS(sys_swapon , 2)
1696 MIPS_SYS(sys_reboot , 3)
1697 MIPS_SYS(old_readdir , 3)
1698 MIPS_SYS(old_mmap , 6) /* 4090 */
1699 MIPS_SYS(sys_munmap , 2)
1700 MIPS_SYS(sys_truncate , 2)
1701 MIPS_SYS(sys_ftruncate , 2)
1702 MIPS_SYS(sys_fchmod , 2)
1703 MIPS_SYS(sys_fchown , 3) /* 4095 */
1704 MIPS_SYS(sys_getpriority , 2)
1705 MIPS_SYS(sys_setpriority , 3)
1706 MIPS_SYS(sys_ni_syscall , 0)
1707 MIPS_SYS(sys_statfs , 2)
1708 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1709 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1710 MIPS_SYS(sys_socketcall , 2)
1711 MIPS_SYS(sys_syslog , 3)
1712 MIPS_SYS(sys_setitimer , 3)
1713 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1714 MIPS_SYS(sys_newstat , 2)
1715 MIPS_SYS(sys_newlstat , 2)
1716 MIPS_SYS(sys_newfstat , 2)
1717 MIPS_SYS(sys_uname , 1)
1718 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1719 MIPS_SYS(sys_vhangup , 0)
1720 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1721 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1722 MIPS_SYS(sys_wait4 , 4)
1723 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1724 MIPS_SYS(sys_sysinfo , 1)
1725 MIPS_SYS(sys_ipc , 6)
1726 MIPS_SYS(sys_fsync , 1)
1727 MIPS_SYS(sys_sigreturn , 0)
18113962 1728 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 1729 MIPS_SYS(sys_setdomainname, 2)
1730 MIPS_SYS(sys_newuname , 1)
1731 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1732 MIPS_SYS(sys_adjtimex , 1)
1733 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1734 MIPS_SYS(sys_sigprocmask , 3)
1735 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1736 MIPS_SYS(sys_init_module , 5)
1737 MIPS_SYS(sys_delete_module, 1)
1738 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1739 MIPS_SYS(sys_quotactl , 0)
1740 MIPS_SYS(sys_getpgid , 1)
1741 MIPS_SYS(sys_fchdir , 1)
1742 MIPS_SYS(sys_bdflush , 2)
1743 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1744 MIPS_SYS(sys_personality , 1)
1745 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1746 MIPS_SYS(sys_setfsuid , 1)
1747 MIPS_SYS(sys_setfsgid , 1)
1748 MIPS_SYS(sys_llseek , 5) /* 4140 */
1749 MIPS_SYS(sys_getdents , 3)
1750 MIPS_SYS(sys_select , 5)
1751 MIPS_SYS(sys_flock , 2)
1752 MIPS_SYS(sys_msync , 3)
1753 MIPS_SYS(sys_readv , 3) /* 4145 */
1754 MIPS_SYS(sys_writev , 3)
1755 MIPS_SYS(sys_cacheflush , 3)
1756 MIPS_SYS(sys_cachectl , 3)
1757 MIPS_SYS(sys_sysmips , 4)
1758 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1759 MIPS_SYS(sys_getsid , 1)
1760 MIPS_SYS(sys_fdatasync , 0)
1761 MIPS_SYS(sys_sysctl , 1)
1762 MIPS_SYS(sys_mlock , 2)
1763 MIPS_SYS(sys_munlock , 2) /* 4155 */
1764 MIPS_SYS(sys_mlockall , 1)
1765 MIPS_SYS(sys_munlockall , 0)
1766 MIPS_SYS(sys_sched_setparam, 2)
1767 MIPS_SYS(sys_sched_getparam, 2)
1768 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1769 MIPS_SYS(sys_sched_getscheduler, 1)
1770 MIPS_SYS(sys_sched_yield , 0)
1771 MIPS_SYS(sys_sched_get_priority_max, 1)
1772 MIPS_SYS(sys_sched_get_priority_min, 1)
1773 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1774 MIPS_SYS(sys_nanosleep, 2)
1775 MIPS_SYS(sys_mremap , 4)
1776 MIPS_SYS(sys_accept , 3)
1777 MIPS_SYS(sys_bind , 3)
1778 MIPS_SYS(sys_connect , 3) /* 4170 */
1779 MIPS_SYS(sys_getpeername , 3)
1780 MIPS_SYS(sys_getsockname , 3)
1781 MIPS_SYS(sys_getsockopt , 5)
1782 MIPS_SYS(sys_listen , 2)
1783 MIPS_SYS(sys_recv , 4) /* 4175 */
1784 MIPS_SYS(sys_recvfrom , 6)
1785 MIPS_SYS(sys_recvmsg , 3)
1786 MIPS_SYS(sys_send , 4)
1787 MIPS_SYS(sys_sendmsg , 3)
1788 MIPS_SYS(sys_sendto , 6) /* 4180 */
1789 MIPS_SYS(sys_setsockopt , 5)
1790 MIPS_SYS(sys_shutdown , 2)
1791 MIPS_SYS(sys_socket , 3)
1792 MIPS_SYS(sys_socketpair , 4)
1793 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1794 MIPS_SYS(sys_getresuid , 3)
1795 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1796 MIPS_SYS(sys_poll , 3)
1797 MIPS_SYS(sys_nfsservctl , 3)
1798 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1799 MIPS_SYS(sys_getresgid , 3)
1800 MIPS_SYS(sys_prctl , 5)
1801 MIPS_SYS(sys_rt_sigreturn, 0)
1802 MIPS_SYS(sys_rt_sigaction, 4)
1803 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1804 MIPS_SYS(sys_rt_sigpending, 2)
1805 MIPS_SYS(sys_rt_sigtimedwait, 4)
1806 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1807 MIPS_SYS(sys_rt_sigsuspend, 0)
1808 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1809 MIPS_SYS(sys_pwrite64 , 6)
1810 MIPS_SYS(sys_chown , 3)
1811 MIPS_SYS(sys_getcwd , 2)
1812 MIPS_SYS(sys_capget , 2)
1813 MIPS_SYS(sys_capset , 2) /* 4205 */
1814 MIPS_SYS(sys_sigaltstack , 0)
1815 MIPS_SYS(sys_sendfile , 4)
1816 MIPS_SYS(sys_ni_syscall , 0)
1817 MIPS_SYS(sys_ni_syscall , 0)
1818 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1819 MIPS_SYS(sys_truncate64 , 4)
1820 MIPS_SYS(sys_ftruncate64 , 4)
1821 MIPS_SYS(sys_stat64 , 2)
1822 MIPS_SYS(sys_lstat64 , 2)
1823 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1824 MIPS_SYS(sys_pivot_root , 2)
1825 MIPS_SYS(sys_mincore , 3)
1826 MIPS_SYS(sys_madvise , 3)
1827 MIPS_SYS(sys_getdents64 , 3)
1828 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1829 MIPS_SYS(sys_ni_syscall , 0)
1830 MIPS_SYS(sys_gettid , 0)
1831 MIPS_SYS(sys_readahead , 5)
1832 MIPS_SYS(sys_setxattr , 5)
1833 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1834 MIPS_SYS(sys_fsetxattr , 5)
1835 MIPS_SYS(sys_getxattr , 4)
1836 MIPS_SYS(sys_lgetxattr , 4)
1837 MIPS_SYS(sys_fgetxattr , 4)
1838 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1839 MIPS_SYS(sys_llistxattr , 3)
1840 MIPS_SYS(sys_flistxattr , 3)
1841 MIPS_SYS(sys_removexattr , 2)
1842 MIPS_SYS(sys_lremovexattr, 2)
1843 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1844 MIPS_SYS(sys_tkill , 2)
1845 MIPS_SYS(sys_sendfile64 , 5)
1846 MIPS_SYS(sys_futex , 2)
1847 MIPS_SYS(sys_sched_setaffinity, 3)
1848 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1849 MIPS_SYS(sys_io_setup , 2)
1850 MIPS_SYS(sys_io_destroy , 1)
1851 MIPS_SYS(sys_io_getevents, 5)
1852 MIPS_SYS(sys_io_submit , 3)
1853 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1854 MIPS_SYS(sys_exit_group , 1)
1855 MIPS_SYS(sys_lookup_dcookie, 3)
1856 MIPS_SYS(sys_epoll_create, 1)
1857 MIPS_SYS(sys_epoll_ctl , 4)
1858 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1859 MIPS_SYS(sys_remap_file_pages, 5)
1860 MIPS_SYS(sys_set_tid_address, 1)
1861 MIPS_SYS(sys_restart_syscall, 0)
1862 MIPS_SYS(sys_fadvise64_64, 7)
1863 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1864 MIPS_SYS(sys_fstatfs64 , 2)
1865 MIPS_SYS(sys_timer_create, 3)
1866 MIPS_SYS(sys_timer_settime, 4)
1867 MIPS_SYS(sys_timer_gettime, 2)
1868 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1869 MIPS_SYS(sys_timer_delete, 1)
1870 MIPS_SYS(sys_clock_settime, 2)
1871 MIPS_SYS(sys_clock_gettime, 2)
1872 MIPS_SYS(sys_clock_getres, 2)
1873 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1874 MIPS_SYS(sys_tgkill , 3)
1875 MIPS_SYS(sys_utimes , 2)
1876 MIPS_SYS(sys_mbind , 4)
1877 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1878 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1879 MIPS_SYS(sys_mq_open , 4)
1880 MIPS_SYS(sys_mq_unlink , 1)
1881 MIPS_SYS(sys_mq_timedsend, 5)
1882 MIPS_SYS(sys_mq_timedreceive, 5)
1883 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1884 MIPS_SYS(sys_mq_getsetattr, 3)
1885 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1886 MIPS_SYS(sys_waitid , 4)
1887 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1888 MIPS_SYS(sys_add_key , 5)
388bb21a 1889 MIPS_SYS(sys_request_key, 4)
048f6b4d 1890 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 1891 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 1892 MIPS_SYS(sys_inotify_init, 0)
1893 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1894 MIPS_SYS(sys_inotify_rm_watch, 2)
1895 MIPS_SYS(sys_migrate_pages, 4)
1896 MIPS_SYS(sys_openat, 4)
1897 MIPS_SYS(sys_mkdirat, 3)
1898 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1899 MIPS_SYS(sys_fchownat, 5)
1900 MIPS_SYS(sys_futimesat, 3)
1901 MIPS_SYS(sys_fstatat64, 4)
1902 MIPS_SYS(sys_unlinkat, 3)
1903 MIPS_SYS(sys_renameat, 4) /* 4295 */
1904 MIPS_SYS(sys_linkat, 5)
1905 MIPS_SYS(sys_symlinkat, 3)
1906 MIPS_SYS(sys_readlinkat, 4)
1907 MIPS_SYS(sys_fchmodat, 3)
1908 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1909 MIPS_SYS(sys_pselect6, 6)
1910 MIPS_SYS(sys_ppoll, 5)
1911 MIPS_SYS(sys_unshare, 1)
1912 MIPS_SYS(sys_splice, 4)
1913 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1914 MIPS_SYS(sys_tee, 4)
1915 MIPS_SYS(sys_vmsplice, 4)
1916 MIPS_SYS(sys_move_pages, 6)
1917 MIPS_SYS(sys_set_robust_list, 2)
1918 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1919 MIPS_SYS(sys_kexec_load, 4)
1920 MIPS_SYS(sys_getcpu, 3)
1921 MIPS_SYS(sys_epoll_pwait, 6)
1922 MIPS_SYS(sys_ioprio_set, 3)
1923 MIPS_SYS(sys_ioprio_get, 2)
048f6b4d
FB		 1924};
1925
1926#undef MIPS_SYS
1927
590bc601
PB		 1928static int do_store_exclusive(CPUMIPSState *env)
1929{
1930 target_ulong addr;
1931 target_ulong page_addr;
1932 target_ulong val;
1933 int flags;
1934 int segv = 0;
1935 int reg;
1936 int d;
1937
5499b6ff 1938 addr = env->lladdr;
590bc601
PB		 1939 page_addr = addr & TARGET_PAGE_MASK;
1940 start_exclusive();
1941 mmap_lock();
1942 flags = page_get_flags(page_addr);
1943 if ((flags & PAGE_READ) == 0) {
1944 segv = 1;
1945 } else {
1946 reg = env->llreg & 0x1f;
1947 d = (env->llreg & 0x20) != 0;
1948 if (d) {
1949 segv = get_user_s64(val, addr);
1950 } else {
1951 segv = get_user_s32(val, addr);
1952 }
1953 if (!segv) {
1954 if (val != env->llval) {
1955 env->active_tc.gpr[reg] = 0;
1956 } else {
1957 if (d) {
1958 segv = put_user_u64(env->llnewval, addr);
1959 } else {
1960 segv = put_user_u32(env->llnewval, addr);
1961 }
1962 if (!segv) {
1963 env->active_tc.gpr[reg] = 1;
1964 }
1965 }
1966 }
1967 }
5499b6ff 1968 env->lladdr = -1;
590bc601
PB		 1969 if (!segv) {
1970 env->active_tc.PC += 4;
1971 }
1972 mmap_unlock();
1973 end_exclusive();
1974 return segv;
1975}
1976
048f6b4d
FB		 1977void cpu_loop(CPUMIPSState *env)
1978{
c227f099 1979 target_siginfo_t info;
388bb21a 1980 int trapnr, ret;
048f6b4d 1981 unsigned int syscall_num;
048f6b4d
FB		 1982
1983 for(;;) {
590bc601 1984 cpu_exec_start(env);
048f6b4d 1985 trapnr = cpu_mips_exec(env);
590bc601 1986 cpu_exec_end(env);
048f6b4d
FB		 1987 switch(trapnr) {
1988 case EXCP_SYSCALL:
b5dc7732
TS		 1989 syscall_num = env->active_tc.gpr[2] - 4000;
1990 env->active_tc.PC += 4;
388bb21a
TS		 1991 if (syscall_num >= sizeof(mips_syscall_args)) {
1992 ret = -ENOSYS;
1993 } else {
1994 int nb_args;
992f48a0
BS		 1995 abi_ulong sp_reg;
1996 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 1997
1998 nb_args = mips_syscall_args[syscall_num];
b5dc7732 1999 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2000 switch (nb_args) {
2001 /* these arguments are taken from the stack */
2f619698
FB		 2002 /* FIXME - what to do if get_user() fails? */
2003 case 8: get_user_ual(arg8, sp_reg + 28);
2004 case 7: get_user_ual(arg7, sp_reg + 24);
2005 case 6: get_user_ual(arg6, sp_reg + 20);
2006 case 5: get_user_ual(arg5, sp_reg + 16);
388bb21a
TS		 2007 default:
2008 break;
048f6b4d 2009 }
b5dc7732
TS		 2010 ret = do_syscall(env, env->active_tc.gpr[2],
2011 env->active_tc.gpr[4],
2012 env->active_tc.gpr[5],
2013 env->active_tc.gpr[6],
2014 env->active_tc.gpr[7],
388bb21a
TS		 2015 arg5, arg6/*, arg7, arg8*/);
2016 }
0b1bcb00
PB		 2017 if (ret == -TARGET_QEMU_ESIGRETURN) {
2018 /* Returning from a successful sigreturn syscall.
2019 Avoid clobbering register state. */
2020 break;
2021 }
388bb21a 2022 if ((unsigned int)ret >= (unsigned int)(-1133)) {
b5dc7732 2023 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2024 ret = -ret;
2025 } else {
b5dc7732 2026 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2027 }
b5dc7732 2028 env->active_tc.gpr[2] = ret;
048f6b4d 2029 break;
ca7c2b1b
TS		 2030 case EXCP_TLBL:
2031 case EXCP_TLBS:
e4474235
PB		 2032 info.si_signo = TARGET_SIGSEGV;
2033 info.si_errno = 0;
2034 /* XXX: check env->error_code */
2035 info.si_code = TARGET_SEGV_MAPERR;
2036 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2037 queue_signal(env, info.si_signo, &info);
2038 break;
6900e84b 2039 case EXCP_CpU:
048f6b4d 2040 case EXCP_RI:
bc1ad2de
FB		 2041 info.si_signo = TARGET_SIGILL;
2042 info.si_errno = 0;
2043 info.si_code = 0;
624f7979 2044 queue_signal(env, info.si_signo, &info);
048f6b4d 2045 break;
106ec879
FB		 2046 case EXCP_INTERRUPT:
2047 /* just indicate that signals should be handled asap */
2048 break;
d08b2a28
PB		 2049 case EXCP_DEBUG:
2050 {
2051 int sig;
2052
2053 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2054 if (sig)
2055 {
2056 info.si_signo = sig;
2057 info.si_errno = 0;
2058 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2059 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2060 }
2061 }
2062 break;
590bc601
PB		 2063 case EXCP_SC:
2064 if (do_store_exclusive(env)) {
2065 info.si_signo = TARGET_SIGSEGV;
2066 info.si_errno = 0;
2067 info.si_code = TARGET_SEGV_MAPERR;
2068 info._sifields._sigfault._addr = env->active_tc.PC;
2069 queue_signal(env, info.si_signo, &info);
2070 }
2071 break;
048f6b4d
FB		 2072 default:
2073 // error:
5fafdf24 2074 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
048f6b4d
FB		 2075 trapnr);
2076 cpu_dump_state(env, stderr, fprintf, 0);
2077 abort();
2078 }
2079 process_pending_signals(env);
2080 }
2081}
2082#endif
2083
fdf9b3e8
FB		 2084#ifdef TARGET_SH4
2085void cpu_loop (CPUState *env)
2086{
2087 int trapnr, ret;
c227f099 2088 target_siginfo_t info;
3b46e624 2089
fdf9b3e8
FB		 2090 while (1) {
2091 trapnr = cpu_sh4_exec (env);
3b46e624 2092
fdf9b3e8
FB		 2093 switch (trapnr) {
2094 case 0x160:
0b6d3ae0 2095 env->pc += 2;
5fafdf24
TS		 2096 ret = do_syscall(env,
2097 env->gregs[3],
2098 env->gregs[4],
2099 env->gregs[5],
2100 env->gregs[6],
2101 env->gregs[7],
2102 env->gregs[0],
fca743f3 2103 env->gregs[1]);
9c2a9ea1 2104 env->gregs[0] = ret;
fdf9b3e8 2105 break;
c3b5bc8a
TS		 2106 case EXCP_INTERRUPT:
2107 /* just indicate that signals should be handled asap */
2108 break;
355fb23d
PB		 2109 case EXCP_DEBUG:
2110 {
2111 int sig;
2112
2113 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2114 if (sig)
2115 {
2116 info.si_signo = sig;
2117 info.si_errno = 0;
2118 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2119 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2120 }
2121 }
2122 break;
c3b5bc8a
TS		 2123 case 0xa0:
2124 case 0xc0:
2125 info.si_signo = SIGSEGV;
2126 info.si_errno = 0;
2127 info.si_code = TARGET_SEGV_MAPERR;
2128 info._sifields._sigfault._addr = env->tea;
624f7979 2129 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2130 break;
2131
fdf9b3e8
FB		 2132 default:
2133 printf ("Unhandled trap: 0x%x\n", trapnr);
2134 cpu_dump_state(env, stderr, fprintf, 0);
2135 exit (1);
2136 }
2137 process_pending_signals (env);
2138 }
2139}
2140#endif
2141
48733d19
TS		 2142#ifdef TARGET_CRIS
2143void cpu_loop (CPUState *env)
2144{
2145 int trapnr, ret;
c227f099 2146 target_siginfo_t info;
48733d19
TS		 2147
2148 while (1) {
2149 trapnr = cpu_cris_exec (env);
2150 switch (trapnr) {
2151 case 0xaa:
2152 {
2153 info.si_signo = SIGSEGV;
2154 info.si_errno = 0;
2155 /* XXX: check env->error_code */
2156 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2157 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2158 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2159 }
2160 break;
b6d3abda
EI		 2161 case EXCP_INTERRUPT:
2162 /* just indicate that signals should be handled asap */
2163 break;
48733d19
TS		 2164 case EXCP_BREAK:
2165 ret = do_syscall(env,
2166 env->regs[9],
2167 env->regs[10],
2168 env->regs[11],
2169 env->regs[12],
2170 env->regs[13],
2171 env->pregs[7],
2172 env->pregs[11]);
2173 env->regs[10] = ret;
48733d19
TS		 2174 break;
2175 case EXCP_DEBUG:
2176 {
2177 int sig;
2178
2179 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2180 if (sig)
2181 {
2182 info.si_signo = sig;
2183 info.si_errno = 0;
2184 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2185 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2186 }
2187 }
2188 break;
2189 default:
2190 printf ("Unhandled trap: 0x%x\n", trapnr);
2191 cpu_dump_state(env, stderr, fprintf, 0);
2192 exit (1);
2193 }
2194 process_pending_signals (env);
2195 }
2196}
2197#endif
2198
b779e29e
EI		 2199#ifdef TARGET_MICROBLAZE
2200void cpu_loop (CPUState *env)
2201{
2202 int trapnr, ret;
c227f099 2203 target_siginfo_t info;
b779e29e
EI		 2204
2205 while (1) {
2206 trapnr = cpu_mb_exec (env);
2207 switch (trapnr) {
2208 case 0xaa:
2209 {
2210 info.si_signo = SIGSEGV;
2211 info.si_errno = 0;
2212 /* XXX: check env->error_code */
2213 info.si_code = TARGET_SEGV_MAPERR;
2214 info._sifields._sigfault._addr = 0;
2215 queue_signal(env, info.si_signo, &info);
2216 }
2217 break;
2218 case EXCP_INTERRUPT:
2219 /* just indicate that signals should be handled asap */
2220 break;
2221 case EXCP_BREAK:
2222 /* Return address is 4 bytes after the call. */
2223 env->regs[14] += 4;
2224 ret = do_syscall(env,
2225 env->regs[12],
2226 env->regs[5],
2227 env->regs[6],
2228 env->regs[7],
2229 env->regs[8],
2230 env->regs[9],
2231 env->regs[10]);
2232 env->regs[3] = ret;
2233 env->sregs[SR_PC] = env->regs[14];
2234 break;
2235 case EXCP_DEBUG:
2236 {
2237 int sig;
2238
2239 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2240 if (sig)
2241 {
2242 info.si_signo = sig;
2243 info.si_errno = 0;
2244 info.si_code = TARGET_TRAP_BRKPT;
2245 queue_signal(env, info.si_signo, &info);
2246 }
2247 }
2248 break;
2249 default:
2250 printf ("Unhandled trap: 0x%x\n", trapnr);
2251 cpu_dump_state(env, stderr, fprintf, 0);
2252 exit (1);
2253 }
2254 process_pending_signals (env);
2255 }
2256}
2257#endif
2258
e6e5906b
PB		 2259#ifdef TARGET_M68K
2260
2261void cpu_loop(CPUM68KState *env)
2262{
2263 int trapnr;
2264 unsigned int n;
c227f099 2265 target_siginfo_t info;
e6e5906b 2266 TaskState *ts = env->opaque;
3b46e624 2267
e6e5906b
PB		 2268 for(;;) {
2269 trapnr = cpu_m68k_exec(env);
2270 switch(trapnr) {
2271 case EXCP_ILLEGAL:
2272 {
2273 if (ts->sim_syscalls) {
2274 uint16_t nr;
2275 nr = lduw(env->pc + 2);
2276 env->pc += 4;
2277 do_m68k_simcall(env, nr);
2278 } else {
2279 goto do_sigill;
2280 }
2281 }
2282 break;
a87295e8 2283 case EXCP_HALT_INSN:
e6e5906b 2284 /* Semihosing syscall. */
a87295e8 2285 env->pc += 4;
e6e5906b
PB		 2286 do_m68k_semihosting(env, env->dregs[0]);
2287 break;
2288 case EXCP_LINEA:
2289 case EXCP_LINEF:
2290 case EXCP_UNSUPPORTED:
2291 do_sigill:
2292 info.si_signo = SIGILL;
2293 info.si_errno = 0;
2294 info.si_code = TARGET_ILL_ILLOPN;
2295 info._sifields._sigfault._addr = env->pc;
624f7979 2296 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2297 break;
2298 case EXCP_TRAP0:
2299 {
2300 ts->sim_syscalls = 0;
2301 n = env->dregs[0];
2302 env->pc += 2;
5fafdf24
TS		 2303 env->dregs[0] = do_syscall(env,
2304 n,
e6e5906b
PB		 2305 env->dregs[1],
2306 env->dregs[2],
2307 env->dregs[3],
2308 env->dregs[4],
2309 env->dregs[5],
bb7ec043 2310 env->aregs[0]);
e6e5906b
PB		 2311 }
2312 break;
2313 case EXCP_INTERRUPT:
2314 /* just indicate that signals should be handled asap */
2315 break;
2316 case EXCP_ACCESS:
2317 {
2318 info.si_signo = SIGSEGV;
2319 info.si_errno = 0;
2320 /* XXX: check env->error_code */
2321 info.si_code = TARGET_SEGV_MAPERR;
2322 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 2323 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2324 }
2325 break;
2326 case EXCP_DEBUG:
2327 {
2328 int sig;
2329
2330 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2331 if (sig)
2332 {
2333 info.si_signo = sig;
2334 info.si_errno = 0;
2335 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2336 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 2337 }
2338 }
2339 break;
2340 default:
5fafdf24 2341 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
e6e5906b
PB		 2342 trapnr);
2343 cpu_dump_state(env, stderr, fprintf, 0);
2344 abort();
2345 }
2346 process_pending_signals(env);
2347 }
2348}
2349#endif /* TARGET_M68K */
2350
7a3148a9 2351#ifdef TARGET_ALPHA
6910b8f6
RH		 2352static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2353{
2354 target_ulong addr, val, tmp;
2355 target_siginfo_t info;
2356 int ret = 0;
2357
2358 addr = env->lock_addr;
2359 tmp = env->lock_st_addr;
2360 env->lock_addr = -1;
2361 env->lock_st_addr = 0;
2362
2363 start_exclusive();
2364 mmap_lock();
2365
2366 if (addr == tmp) {
2367 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2368 goto do_sigsegv;
2369 }
2370
2371 if (val == env->lock_value) {
2372 tmp = env->ir[reg];
2373 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2374 goto do_sigsegv;
2375 }
2376 ret = 1;
2377 }
2378 }
2379 env->ir[reg] = ret;
2380 env->pc += 4;
2381
2382 mmap_unlock();
2383 end_exclusive();
2384 return;
2385
2386 do_sigsegv:
2387 mmap_unlock();
2388 end_exclusive();
2389
2390 info.si_signo = TARGET_SIGSEGV;
2391 info.si_errno = 0;
2392 info.si_code = TARGET_SEGV_MAPERR;
2393 info._sifields._sigfault._addr = addr;
2394 queue_signal(env, TARGET_SIGSEGV, &info);
2395}
2396
7a3148a9
JM		 2397void cpu_loop (CPUState *env)
2398{
e96efcfc 2399 int trapnr;
c227f099 2400 target_siginfo_t info;
6049f4f8 2401 abi_long sysret;
3b46e624 2402
7a3148a9
JM		 2403 while (1) {
2404 trapnr = cpu_alpha_exec (env);
3b46e624 2405
ac316ca4
RH		 2406 /* All of the traps imply a transition through PALcode, which
2407 implies an REI instruction has been executed. Which means
2408 that the intr_flag should be cleared. */
2409 env->intr_flag = 0;
2410
7a3148a9
JM		 2411 switch (trapnr) {
2412 case EXCP_RESET:
2413 fprintf(stderr, "Reset requested. Exit\n");
2414 exit(1);
2415 break;
2416 case EXCP_MCHK:
2417 fprintf(stderr, "Machine check exception. Exit\n");
2418 exit(1);
2419 break;
2420 case EXCP_ARITH:
6910b8f6 2421 env->lock_addr = -1;
6049f4f8
RH		 2422 info.si_signo = TARGET_SIGFPE;
2423 info.si_errno = 0;
2424 info.si_code = TARGET_FPE_FLTINV;
2425 info._sifields._sigfault._addr = env->pc;
2426 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2427 break;
2428 case EXCP_HW_INTERRUPT:
5fafdf24 2429 fprintf(stderr, "External interrupt. Exit\n");
7a3148a9
JM		 2430 exit(1);
2431 break;
2432 case EXCP_DFAULT:
6910b8f6 2433 env->lock_addr = -1;
6049f4f8
RH		 2434 info.si_signo = TARGET_SIGSEGV;
2435 info.si_errno = 0;
0be1d07c
RH		 2436 info.si_code = (page_get_flags(env->ipr[IPR_EXC_ADDR]) & PAGE_VALID
2437 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
1b6bd8c7 2438 info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR];
6049f4f8 2439 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2440 break;
2441 case EXCP_DTB_MISS_PAL:
2442 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2443 exit(1);
2444 break;
2445 case EXCP_ITB_MISS:
2446 fprintf(stderr, "MMU instruction TLB miss\n");
2447 exit(1);
2448 break;
2449 case EXCP_ITB_ACV:
2450 fprintf(stderr, "MMU instruction access violation\n");
2451 exit(1);
2452 break;
2453 case EXCP_DTB_MISS_NATIVE:
2454 fprintf(stderr, "MMU data TLB miss\n");
2455 exit(1);
2456 break;
2457 case EXCP_UNALIGN:
6910b8f6 2458 env->lock_addr = -1;
6049f4f8
RH		 2459 info.si_signo = TARGET_SIGBUS;
2460 info.si_errno = 0;
2461 info.si_code = TARGET_BUS_ADRALN;
1b6bd8c7 2462 info._sifields._sigfault._addr = env->ipr[IPR_EXC_ADDR];
6049f4f8 2463 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2464 break;
2465 case EXCP_OPCDEC:
6049f4f8 2466 do_sigill:
6910b8f6 2467 env->lock_addr = -1;
6049f4f8
RH		 2468 info.si_signo = TARGET_SIGILL;
2469 info.si_errno = 0;
2470 info.si_code = TARGET_ILL_ILLOPC;
2471 info._sifields._sigfault._addr = env->pc;
2472 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2473 break;
2474 case EXCP_FEN:
6049f4f8 2475 /* No-op. Linux simply re-enables the FPU. */
7a3148a9
JM		 2476 break;
2477 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
6910b8f6 2478 env->lock_addr = -1;
6049f4f8
RH		 2479 switch ((trapnr >> 6) | 0x80) {
2480 case 0x80:
2481 /* BPT */
2482 info.si_signo = TARGET_SIGTRAP;
2483 info.si_errno = 0;
2484 info.si_code = TARGET_TRAP_BRKPT;
2485 info._sifields._sigfault._addr = env->pc;
2486 queue_signal(env, info.si_signo, &info);
2487 break;
2488 case 0x81:
2489 /* BUGCHK */
2490 info.si_signo = TARGET_SIGTRAP;
2491 info.si_errno = 0;
2492 info.si_code = 0;
2493 info._sifields._sigfault._addr = env->pc;
2494 queue_signal(env, info.si_signo, &info);
2495 break;
2496 case 0x83:
2497 /* CALLSYS */
2498 trapnr = env->ir[IR_V0];
2499 sysret = do_syscall(env, trapnr,
2500 env->ir[IR_A0], env->ir[IR_A1],
2501 env->ir[IR_A2], env->ir[IR_A3],
2502 env->ir[IR_A4], env->ir[IR_A5]);
a5b3b13b
RH		 2503 if (trapnr == TARGET_NR_sigreturn
2504 || trapnr == TARGET_NR_rt_sigreturn) {
2505 break;
2506 }
2507 /* Syscall writes 0 to V0 to bypass error check, similar
2508 to how this is handled internal to Linux kernel. */
2509 if (env->ir[IR_V0] == 0) {
2510 env->ir[IR_V0] = sysret;
2511 } else {
6049f4f8
RH		 2512 env->ir[IR_V0] = (sysret < 0 ? -sysret : sysret);
2513 env->ir[IR_A3] = (sysret < 0);
2514 }
2515 break;
2516 case 0x86:
2517 /* IMB */
2518 /* ??? We can probably elide the code using page_unprotect
2519 that is checking for self-modifying code. Instead we
2520 could simply call tb_flush here. Until we work out the
2521 changes required to turn off the extra write protection,
2522 this can be a no-op. */
2523 break;
2524 case 0x9E:
2525 /* RDUNIQUE */
2526 /* Handled in the translator for usermode. */
2527 abort();
2528 case 0x9F:
2529 /* WRUNIQUE */
2530 /* Handled in the translator for usermode. */
2531 abort();
2532 case 0xAA:
2533 /* GENTRAP */
2534 info.si_signo = TARGET_SIGFPE;
2535 switch (env->ir[IR_A0]) {
2536 case TARGET_GEN_INTOVF:
2537 info.si_code = TARGET_FPE_INTOVF;
2538 break;
2539 case TARGET_GEN_INTDIV:
2540 info.si_code = TARGET_FPE_INTDIV;
2541 break;
2542 case TARGET_GEN_FLTOVF:
2543 info.si_code = TARGET_FPE_FLTOVF;
2544 break;
2545 case TARGET_GEN_FLTUND:
2546 info.si_code = TARGET_FPE_FLTUND;
2547 break;
2548 case TARGET_GEN_FLTINV:
2549 info.si_code = TARGET_FPE_FLTINV;
2550 break;
2551 case TARGET_GEN_FLTINE:
2552 info.si_code = TARGET_FPE_FLTRES;
2553 break;
2554 case TARGET_GEN_ROPRAND:
2555 info.si_code = 0;
2556 break;
2557 default:
2558 info.si_signo = TARGET_SIGTRAP;
2559 info.si_code = 0;
2560 break;
2561 }
2562 info.si_errno = 0;
2563 info._sifields._sigfault._addr = env->pc;
2564 queue_signal(env, info.si_signo, &info);
2565 break;
2566 default:
2567 goto do_sigill;
2568 }
7a3148a9
JM		 2569 break;
2570 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
6049f4f8 2571 goto do_sigill;
7a3148a9 2572 case EXCP_DEBUG:
6049f4f8
RH		 2573 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
2574 if (info.si_signo) {
6910b8f6 2575 env->lock_addr = -1;
6049f4f8
RH		 2576 info.si_errno = 0;
2577 info.si_code = TARGET_TRAP_BRKPT;
2578 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 2579 }
2580 break;
6910b8f6
RH		 2581 case EXCP_STL_C:
2582 case EXCP_STQ_C:
2583 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
2584 break;
7a3148a9
JM		 2585 default:
2586 printf ("Unhandled trap: 0x%x\n", trapnr);
2587 cpu_dump_state(env, stderr, fprintf, 0);
2588 exit (1);
2589 }
2590 process_pending_signals (env);
2591 }
2592}
2593#endif /* TARGET_ALPHA */
2594
8fcd3692 2595static void usage(void)
31e31b8a 2596{
4a19f1ec 2597 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
68d0f70e 2598 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
b346ff46 2599 "Linux CPU emulator (compiled for %s emulation)\n"
d691f669 2600 "\n"
68d0f70e 2601 "Standard options:\n"
b12b6a18
TS		 2602 "-h print this help\n"
2603 "-g port wait gdb connection to port\n"
2604 "-L path set the elf interpreter prefix (default=%s)\n"
2605 "-s size set the stack size in bytes (default=%ld)\n"
2606 "-cpu model select CPU (-cpu ? for list)\n"
2607 "-drop-ld-preload drop LD_PRELOAD for target process\n"
04a6dfeb
AJ		 2608 "-E var=value sets/modifies targets environment variable(s)\n"
2609 "-U var unsets targets environment variable(s)\n"
7d8cec95 2610 "-0 argv0 forces target process argv[0] to be argv0\n"
379f6698
PB		 2611#if defined(CONFIG_USE_GUEST_BASE)
2612 "-B address set guest_base address to address\n"
2613#endif
54936004 2614 "\n"
68d0f70e 2615 "Debug options:\n"
6f1f31c0 2616 "-d options activate log (logfile=%s)\n"
b6741956 2617 "-p pagesize set the host page size to 'pagesize'\n"
1b530a6d 2618 "-singlestep always run in singlestep mode\n"
b01bcae6
AZ		 2619 "-strace log system calls\n"
2620 "\n"
68d0f70e 2621 "Environment variables:\n"
b01bcae6
AZ		 2622 "QEMU_STRACE Print system calls and arguments similar to the\n"
2623 " 'strace' program. Enable by setting to any value.\n"
04a6dfeb
AJ		 2624 "You can use -E and -U options to set/unset environment variables\n"
2625 "for target process. It is possible to provide several variables\n"
2626 "by repeating the option. For example:\n"
2627 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2628 "Note that if you provide several changes to single variable\n"
2629 "last change will stay in effect.\n"
b01bcae6 2630 ,
b346ff46 2631 TARGET_ARCH,
5fafdf24 2632 interp_prefix,
703e0e89 2633 guest_stack_size,
54936004 2634 DEBUG_LOGFILE);
2d18e637 2635 exit(1);
31e31b8a
FB		 2636}
2637
d5975363 2638THREAD CPUState *thread_env;
59faf6d6 2639
edf8e2af
MW		 2640void task_settid(TaskState *ts)
2641{
2642 if (ts->ts_tid == 0) {
2f7bb878 2643#ifdef CONFIG_USE_NPTL
edf8e2af
MW		 2644 ts->ts_tid = (pid_t)syscall(SYS_gettid);
2645#else
2646 /* when no threads are used, tid becomes pid */
2647 ts->ts_tid = getpid();
2648#endif
2649 }
2650}
2651
2652void stop_all_tasks(void)
2653{
2654 /*
2655 * We trust that when using NPTL, start_exclusive()
2656 * handles thread stopping correctly.
2657 */
2658 start_exclusive();
2659}
2660
c3a92833 2661/* Assumes contents are already zeroed. */
624f7979
PB		 2662void init_task_state(TaskState *ts)
2663{
2664 int i;
2665
624f7979
PB		 2666 ts->used = 1;
2667 ts->first_free = ts->sigqueue_table;
2668 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2669 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2670 }
2671 ts->sigqueue_table[i].next = NULL;
2672}
2673
902b3d5c 2674int main(int argc, char **argv, char **envp)
31e31b8a
FB		 2675{
2676 const char *filename;
b1f9be31 2677 const char *cpu_model;
01ffc75b 2678 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 2679 struct image_info info1, *info = &info1;
edf8e2af 2680 struct linux_binprm bprm;
851e67a1 2681 TaskState ts1, *ts = &ts1;
b346ff46 2682 CPUState *env;
586314f2 2683 int optind;
d691f669 2684 const char *r;
74c33bed 2685 int gdbstub_port = 0;
04a6dfeb 2686 char **target_environ, **wrk;
7d8cec95
AJ		 2687 char **target_argv;
2688 int target_argc;
04a6dfeb 2689 envlist_t *envlist = NULL;
7d8cec95
AJ		 2690 const char *argv0 = NULL;
2691 int i;
fd4d81dd 2692 int ret;
b12b6a18 2693
31e31b8a 2694 if (argc <= 1)
44de1b33 2695 usage();
f801f97e 2696
902b3d5c 2697 qemu_cache_utils_init(envp);
2698
cc38b844
FB		 2699 /* init debug */
2700 cpu_set_log_filename(DEBUG_LOGFILE);
2701
04a6dfeb
AJ		 2702 if ((envlist = envlist_create()) == NULL) {
2703 (void) fprintf(stderr, "Unable to allocate envlist\n");
2704 exit(1);
2705 }
2706
2707 /* add current environment into the list */
2708 for (wrk = environ; *wrk != NULL; wrk++) {
2709 (void) envlist_setenv(envlist, *wrk);
2710 }
2711
703e0e89
RH		 2712 /* Read the stack limit from the kernel. If it's "unlimited",
2713 then we can do little else besides use the default. */
2714 {
2715 struct rlimit lim;
2716 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 2717 && lim.rlim_cur != RLIM_INFINITY
2718 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 2719 guest_stack_size = lim.rlim_cur;
2720 }
2721 }
2722
b1f9be31 2723 cpu_model = NULL;
b5ec5ce0 2724#if defined(cpudef_setup)
2725 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
2726#endif
2727
586314f2 2728 optind = 1;
d691f669
FB		 2729 for(;;) {
2730 if (optind >= argc)
2731 break;
2732 r = argv[optind];
2733 if (r[0] != '-')
2734 break;
586314f2 2735 optind++;
d691f669
FB		 2736 r++;
2737 if (!strcmp(r, "-")) {
2738 break;
2739 } else if (!strcmp(r, "d")) {
e19e89a5 2740 int mask;
c7cd6a37 2741 const CPULogItem *item;
6f1f31c0
FB		 2742
2743 if (optind >= argc)
2744 break;
3b46e624 2745
6f1f31c0
FB		 2746 r = argv[optind++];
2747 mask = cpu_str_to_log_mask(r);
e19e89a5
FB		 2748 if (!mask) {
2749 printf("Log items (comma separated):\n");
2750 for(item = cpu_log_items; item->mask != 0; item++) {
2751 printf("%-10s %s\n", item->name, item->help);
2752 }
2753 exit(1);
2754 }
2755 cpu_set_log(mask);
04a6dfeb
AJ		 2756 } else if (!strcmp(r, "E")) {
2757 r = argv[optind++];
2758 if (envlist_setenv(envlist, r) != 0)
2759 usage();
2760 } else if (!strcmp(r, "U")) {
2761 r = argv[optind++];
2762 if (envlist_unsetenv(envlist, r) != 0)
2763 usage();
7d8cec95
AJ		 2764 } else if (!strcmp(r, "0")) {
2765 r = argv[optind++];
2766 argv0 = r;
d691f669 2767 } else if (!strcmp(r, "s")) {
491150db
AJ		 2768 if (optind >= argc)
2769 break;
d691f669 2770 r = argv[optind++];
703e0e89
RH		 2771 guest_stack_size = strtoul(r, (char **)&r, 0);
2772 if (guest_stack_size == 0)
44de1b33 2773 usage();
d691f669 2774 if (*r == 'M')
703e0e89 2775 guest_stack_size *= 1024 * 1024;
d691f669 2776 else if (*r == 'k' || *r == 'K')
703e0e89 2777 guest_stack_size *= 1024;
d691f669
FB		 2778 } else if (!strcmp(r, "L")) {
2779 interp_prefix = argv[optind++];
54936004 2780 } else if (!strcmp(r, "p")) {
491150db
AJ		 2781 if (optind >= argc)
2782 break;
83fb7adf
FB		 2783 qemu_host_page_size = atoi(argv[optind++]);
2784 if (qemu_host_page_size == 0 ||
2785 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
54936004
FB		 2786 fprintf(stderr, "page size must be a power of two\n");
2787 exit(1);
2788 }
1fddef4b 2789 } else if (!strcmp(r, "g")) {
491150db
AJ		 2790 if (optind >= argc)
2791 break;
74c33bed 2792 gdbstub_port = atoi(argv[optind++]);
c5937220
PB		 2793 } else if (!strcmp(r, "r")) {
2794 qemu_uname_release = argv[optind++];
b1f9be31
JM		 2795 } else if (!strcmp(r, "cpu")) {
2796 cpu_model = argv[optind++];
491150db 2797 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
c732abe2 2798/* XXX: implement xxx_cpu_list for targets that still miss it */
b5ec5ce0 2799#if defined(cpu_list_id)
2800 cpu_list_id(stdout, &fprintf, "");
b1f9be31 2801#endif
2d18e637 2802 exit(1);
b1f9be31 2803 }
379f6698
PB		 2804#if defined(CONFIG_USE_GUEST_BASE)
2805 } else if (!strcmp(r, "B")) {
2806 guest_base = strtol(argv[optind++], NULL, 0);
2807 have_guest_base = 1;
2808#endif
b12b6a18 2809 } else if (!strcmp(r, "drop-ld-preload")) {
04a6dfeb 2810 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
1b530a6d
AJ		 2811 } else if (!strcmp(r, "singlestep")) {
2812 singlestep = 1;
b6741956
FB		 2813 } else if (!strcmp(r, "strace")) {
2814 do_strace = 1;
5fafdf24 2815 } else
c6981055 2816 {
d691f669
FB		 2817 usage();
2818 }
586314f2 2819 }
d691f669
FB		 2820 if (optind >= argc)
2821 usage();
586314f2 2822 filename = argv[optind];
d088d664 2823 exec_path = argv[optind];
586314f2 2824
31e31b8a 2825 /* Zero out regs */
01ffc75b 2826 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 2827
2828 /* Zero out image_info */
2829 memset(info, 0, sizeof(struct image_info));
2830
edf8e2af
MW		 2831 memset(&bprm, 0, sizeof (bprm));
2832
74cd30b8
FB		 2833 /* Scan interp_prefix dir for replacement files. */
2834 init_paths(interp_prefix);
2835
46027c07 2836 if (cpu_model == NULL) {
aaed909a 2837#if defined(TARGET_I386)
46027c07
FB		 2838#ifdef TARGET_X86_64
2839 cpu_model = "qemu64";
2840#else
2841 cpu_model = "qemu32";
2842#endif
aaed909a 2843#elif defined(TARGET_ARM)
088ab16c 2844 cpu_model = "any";
aaed909a
FB		 2845#elif defined(TARGET_M68K)
2846 cpu_model = "any";
2847#elif defined(TARGET_SPARC)
2848#ifdef TARGET_SPARC64
2849 cpu_model = "TI UltraSparc II";
2850#else
2851 cpu_model = "Fujitsu MB86904";
46027c07 2852#endif
aaed909a
FB		 2853#elif defined(TARGET_MIPS)
2854#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2855 cpu_model = "20Kc";
2856#else
2857 cpu_model = "24Kf";
2858#endif
2859#elif defined(TARGET_PPC)
7ded4f52 2860#ifdef TARGET_PPC64
f7177937 2861 cpu_model = "970fx";
7ded4f52 2862#else
aaed909a 2863 cpu_model = "750";
7ded4f52 2864#endif
aaed909a
FB		 2865#else
2866 cpu_model = "any";
2867#endif
2868 }
26a5f13b 2869 cpu_exec_init_all(0);
83fb7adf
FB		 2870 /* NOTE: we need to init the CPU at this stage to get
2871 qemu_host_page_size */
aaed909a
FB		 2872 env = cpu_init(cpu_model);
2873 if (!env) {
2874 fprintf(stderr, "Unable to find CPU definition\n");
2875 exit(1);
2876 }
b55a37c9
BS		 2877#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
2878 cpu_reset(env);
2879#endif
2880
d5975363 2881 thread_env = env;
3b46e624 2882
b6741956
FB		 2883 if (getenv("QEMU_STRACE")) {
2884 do_strace = 1;
b92c47c1
TS		 2885 }
2886
04a6dfeb
AJ		 2887 target_environ = envlist_to_environ(envlist, NULL);
2888 envlist_free(envlist);
b12b6a18 2889
379f6698
PB		 2890#if defined(CONFIG_USE_GUEST_BASE)
2891 /*
2892 * Now that page sizes are configured in cpu_init() we can do
2893 * proper page alignment for guest_base.
2894 */
2895 guest_base = HOST_PAGE_ALIGN(guest_base);
14f24e14 2896#endif /* CONFIG_USE_GUEST_BASE */
379f6698
PB		 2897
2898 /*
2899 * Read in mmap_min_addr kernel parameter. This value is used
2900 * When loading the ELF image to determine whether guest_base
14f24e14 2901 * is needed. It is also used in mmap_find_vma.
379f6698 2902 */
14f24e14 2903 {
379f6698
PB		 2904 FILE *fp;
2905
2906 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
2907 unsigned long tmp;
2908 if (fscanf(fp, "%lu", &tmp) == 1) {
2909 mmap_min_addr = tmp;
2910 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
2911 }
2912 fclose(fp);
2913 }
2914 }
379f6698 2915
7d8cec95
AJ		 2916 /*
2917 * Prepare copy of argv vector for target.
2918 */
2919 target_argc = argc - optind;
2920 target_argv = calloc(target_argc + 1, sizeof (char *));
2921 if (target_argv == NULL) {
2922 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
2923 exit(1);
2924 }
2925
2926 /*
2927 * If argv0 is specified (using '-0' switch) we replace
2928 * argv[0] pointer with the given one.
2929 */
2930 i = 0;
2931 if (argv0 != NULL) {
2932 target_argv[i++] = strdup(argv0);
2933 }
2934 for (; i < target_argc; i++) {
2935 target_argv[i] = strdup(argv[optind + i]);
2936 }
2937 target_argv[target_argc] = NULL;
2938
edf8e2af
MW		 2939 memset(ts, 0, sizeof(TaskState));
2940 init_task_state(ts);
2941 /* build Task State */
2942 ts->info = info;
2943 ts->bprm = &bprm;
2944 env->opaque = ts;
2945 task_settid(ts);
2946
fd4d81dd
AP		 2947 ret = loader_exec(filename, target_argv, target_environ, regs,
2948 info, &bprm);
2949 if (ret != 0) {
2950 printf("Error %d while loading %s\n", ret, filename);
b12b6a18
TS		 2951 _exit(1);
2952 }
2953
7d8cec95
AJ		 2954 for (i = 0; i < target_argc; i++) {
2955 free(target_argv[i]);
2956 }
2957 free(target_argv);
2958
b12b6a18
TS		 2959 for (wrk = target_environ; *wrk; wrk++) {
2960 free(*wrk);
31e31b8a 2961 }
3b46e624 2962
b12b6a18
TS		 2963 free(target_environ);
2964
2e77eac6 2965 if (qemu_log_enabled()) {
379f6698
PB		 2966#if defined(CONFIG_USE_GUEST_BASE)
2967 qemu_log("guest_base 0x%lx\n", guest_base);
2968#endif
2e77eac6
BS		 2969 log_page_dump();
2970
2971 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2972 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2973 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
2974 info->start_code);
2975 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
2976 info->start_data);
2977 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2978 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
2979 info->start_stack);
2980 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2981 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2982 }
31e31b8a 2983
53a5960a 2984 target_set_brk(info->brk);
31e31b8a 2985 syscall_init();
66fb9763 2986 signal_init();
31e31b8a 2987
9002ec79
RH		 2988#if defined(CONFIG_USE_GUEST_BASE)
2989 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
2990 generating the prologue until now so that the prologue can take
2991 the real value of GUEST_BASE into account. */
2992 tcg_prologue_init(&tcg_ctx);
2993#endif
2994
b346ff46 2995#if defined(TARGET_I386)
2e255c6b
FB		 2996 cpu_x86_set_cpl(env, 3);
2997
3802ce26 2998 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
1bde465e
FB		 2999 env->hflags |= HF_PE_MASK;
3000 if (env->cpuid_features & CPUID_SSE) {
3001 env->cr[4] |= CR4_OSFXSR_MASK;
3002 env->hflags |= HF_OSFXSR_MASK;
3003 }
d2fd1af7 3004#ifndef TARGET_ABI32
4dbc422b
FB		 3005 /* enable 64 bit mode if possible */
3006 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
3007 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3008 exit(1);
3009 }
d2fd1af7 3010 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 3011 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 3012 env->hflags |= HF_LMA_MASK;
3013#endif
1bde465e 3014
415e561f
FB		 3015 /* flags setup : we activate the IRQs by default as in user mode */
3016 env->eflags |= IF_MASK;
3b46e624 3017
6dbad63e 3018 /* linux register setup */
d2fd1af7 3019#ifndef TARGET_ABI32
84409ddb
JM		 3020 env->regs[R_EAX] = regs->rax;
3021 env->regs[R_EBX] = regs->rbx;
3022 env->regs[R_ECX] = regs->rcx;
3023 env->regs[R_EDX] = regs->rdx;
3024 env->regs[R_ESI] = regs->rsi;
3025 env->regs[R_EDI] = regs->rdi;
3026 env->regs[R_EBP] = regs->rbp;
3027 env->regs[R_ESP] = regs->rsp;
3028 env->eip = regs->rip;
3029#else
0ecfa993
FB		 3030 env->regs[R_EAX] = regs->eax;
3031 env->regs[R_EBX] = regs->ebx;
3032 env->regs[R_ECX] = regs->ecx;
3033 env->regs[R_EDX] = regs->edx;
3034 env->regs[R_ESI] = regs->esi;
3035 env->regs[R_EDI] = regs->edi;
3036 env->regs[R_EBP] = regs->ebp;
3037 env->regs[R_ESP] = regs->esp;
dab2ed99 3038 env->eip = regs->eip;
84409ddb 3039#endif
31e31b8a 3040
f4beb510 3041 /* linux interrupt setup */
e441570f
AZ		 3042#ifndef TARGET_ABI32
3043 env->idt.limit = 511;
3044#else
3045 env->idt.limit = 255;
3046#endif
3047 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3048 PROT_READ|PROT_WRITE,
3049 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3050 idt_table = g2h(env->idt.base);
f4beb510
FB		 3051 set_idt(0, 0);
3052 set_idt(1, 0);
3053 set_idt(2, 0);
3054 set_idt(3, 3);
3055 set_idt(4, 3);
ec95da6c 3056 set_idt(5, 0);
f4beb510
FB		 3057 set_idt(6, 0);
3058 set_idt(7, 0);
3059 set_idt(8, 0);
3060 set_idt(9, 0);
3061 set_idt(10, 0);
3062 set_idt(11, 0);
3063 set_idt(12, 0);
3064 set_idt(13, 0);
3065 set_idt(14, 0);
3066 set_idt(15, 0);
3067 set_idt(16, 0);
3068 set_idt(17, 0);
3069 set_idt(18, 0);
3070 set_idt(19, 0);
3071 set_idt(0x80, 3);
3072
6dbad63e 3073 /* linux segment setup */
8d18e893
FB		 3074 {
3075 uint64_t *gdt_table;
e441570f
AZ		 3076 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3077 PROT_READ|PROT_WRITE,
3078 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 3079 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 3080 gdt_table = g2h(env->gdt.base);
d2fd1af7 3081#ifdef TARGET_ABI32
8d18e893
FB		 3082 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3083 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3084 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 3085#else
3086 /* 64 bit code segment */
3087 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3088 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3089 DESC_L_MASK |
3090 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3091#endif
8d18e893
FB		 3092 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3093 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3094 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3095 }
6dbad63e 3096 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 3097 cpu_x86_load_seg(env, R_SS, __USER_DS);
3098#ifdef TARGET_ABI32
6dbad63e
FB		 3099 cpu_x86_load_seg(env, R_DS, __USER_DS);
3100 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 3101 cpu_x86_load_seg(env, R_FS, __USER_DS);
3102 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 3103 /* This hack makes Wine work... */
3104 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 3105#else
3106 cpu_x86_load_seg(env, R_DS, 0);
3107 cpu_x86_load_seg(env, R_ES, 0);
3108 cpu_x86_load_seg(env, R_FS, 0);
3109 cpu_x86_load_seg(env, R_GS, 0);
3110#endif
b346ff46
FB		 3111#elif defined(TARGET_ARM)
3112 {
3113 int i;
b5ff1b31 3114 cpsr_write(env, regs->uregs[16], 0xffffffff);
b346ff46
FB		 3115 for(i = 0; i < 16; i++) {
3116 env->regs[i] = regs->uregs[i];
3117 }
b346ff46 3118 }
93ac68bc 3119#elif defined(TARGET_SPARC)
060366c5
FB		 3120 {
3121 int i;
3122 env->pc = regs->pc;
3123 env->npc = regs->npc;
3124 env->y = regs->y;
3125 for(i = 0; i < 8; i++)
3126 env->gregs[i] = regs->u_regs[i];
3127 for(i = 0; i < 8; i++)
3128 env->regwptr[i] = regs->u_regs[i + 8];
3129 }
67867308
FB		 3130#elif defined(TARGET_PPC)
3131 {
3132 int i;
3fc6c082 3133
0411a972
JM		 3134#if defined(TARGET_PPC64)
3135#if defined(TARGET_ABI32)
3136 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 3137#else
0411a972
JM		 3138 env->msr |= (target_ulong)1 << MSR_SF;
3139#endif
84409ddb 3140#endif
67867308
FB		 3141 env->nip = regs->nip;
3142 for(i = 0; i < 32; i++) {
3143 env->gpr[i] = regs->gpr[i];
3144 }
3145 }
e6e5906b
PB		 3146#elif defined(TARGET_M68K)
3147 {
e6e5906b
PB		 3148 env->pc = regs->pc;
3149 env->dregs[0] = regs->d0;
3150 env->dregs[1] = regs->d1;
3151 env->dregs[2] = regs->d2;
3152 env->dregs[3] = regs->d3;
3153 env->dregs[4] = regs->d4;
3154 env->dregs[5] = regs->d5;
3155 env->dregs[6] = regs->d6;
3156 env->dregs[7] = regs->d7;
3157 env->aregs[0] = regs->a0;
3158 env->aregs[1] = regs->a1;
3159 env->aregs[2] = regs->a2;
3160 env->aregs[3] = regs->a3;
3161 env->aregs[4] = regs->a4;
3162 env->aregs[5] = regs->a5;
3163 env->aregs[6] = regs->a6;
3164 env->aregs[7] = regs->usp;
3165 env->sr = regs->sr;
3166 ts->sim_syscalls = 1;
3167 }
b779e29e
EI		 3168#elif defined(TARGET_MICROBLAZE)
3169 {
3170 env->regs[0] = regs->r0;
3171 env->regs[1] = regs->r1;
3172 env->regs[2] = regs->r2;
3173 env->regs[3] = regs->r3;
3174 env->regs[4] = regs->r4;
3175 env->regs[5] = regs->r5;
3176 env->regs[6] = regs->r6;
3177 env->regs[7] = regs->r7;
3178 env->regs[8] = regs->r8;
3179 env->regs[9] = regs->r9;
3180 env->regs[10] = regs->r10;
3181 env->regs[11] = regs->r11;
3182 env->regs[12] = regs->r12;
3183 env->regs[13] = regs->r13;
3184 env->regs[14] = regs->r14;
3185 env->regs[15] = regs->r15;
3186 env->regs[16] = regs->r16;
3187 env->regs[17] = regs->r17;
3188 env->regs[18] = regs->r18;
3189 env->regs[19] = regs->r19;
3190 env->regs[20] = regs->r20;
3191 env->regs[21] = regs->r21;
3192 env->regs[22] = regs->r22;
3193 env->regs[23] = regs->r23;
3194 env->regs[24] = regs->r24;
3195 env->regs[25] = regs->r25;
3196 env->regs[26] = regs->r26;
3197 env->regs[27] = regs->r27;
3198 env->regs[28] = regs->r28;
3199 env->regs[29] = regs->r29;
3200 env->regs[30] = regs->r30;
3201 env->regs[31] = regs->r31;
3202 env->sregs[SR_PC] = regs->pc;
3203 }
048f6b4d
FB		 3204#elif defined(TARGET_MIPS)
3205 {
3206 int i;
3207
3208 for(i = 0; i < 32; i++) {
b5dc7732 3209 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 3210 }
b5dc7732 3211 env->active_tc.PC = regs->cp0_epc;
048f6b4d 3212 }
fdf9b3e8
FB		 3213#elif defined(TARGET_SH4)
3214 {
3215 int i;
3216
3217 for(i = 0; i < 16; i++) {
3218 env->gregs[i] = regs->regs[i];
3219 }
3220 env->pc = regs->pc;
3221 }
7a3148a9
JM		 3222#elif defined(TARGET_ALPHA)
3223 {
3224 int i;
3225
3226 for(i = 0; i < 28; i++) {
992f48a0 3227 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 3228 }
dad081ee 3229 env->ir[IR_SP] = regs->usp;
7a3148a9 3230 env->pc = regs->pc;
7a3148a9 3231 }
48733d19
TS		 3232#elif defined(TARGET_CRIS)
3233 {
3234 env->regs[0] = regs->r0;
3235 env->regs[1] = regs->r1;
3236 env->regs[2] = regs->r2;
3237 env->regs[3] = regs->r3;
3238 env->regs[4] = regs->r4;
3239 env->regs[5] = regs->r5;
3240 env->regs[6] = regs->r6;
3241 env->regs[7] = regs->r7;
3242 env->regs[8] = regs->r8;
3243 env->regs[9] = regs->r9;
3244 env->regs[10] = regs->r10;
3245 env->regs[11] = regs->r11;
3246 env->regs[12] = regs->r12;
3247 env->regs[13] = regs->r13;
3248 env->regs[14] = info->start_stack;
3249 env->regs[15] = regs->acr;
3250 env->pc = regs->erp;
3251 }
b346ff46
FB		 3252#else
3253#error unsupported target CPU
3254#endif
31e31b8a 3255
a87295e8
PB		 3256#if defined(TARGET_ARM) || defined(TARGET_M68K)
3257 ts->stack_base = info->start_stack;
3258 ts->heap_base = info->brk;
3259 /* This will be filled in on the first SYS_HEAPINFO call. */
3260 ts->heap_limit = 0;
3261#endif
3262
74c33bed
FB		 3263 if (gdbstub_port) {
3264 gdbserver_start (gdbstub_port);
1fddef4b
FB		 3265 gdb_handlesig(env, 0);
3266 }
1b6b029e
FB		 3267 cpu_loop(env);
3268 /* never exits */
31e31b8a
FB		 3269 return 0;
3270}
Empty description
This page took 0.869756 seconds and 4 git commands to generate.