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Commit | Line | Data |
---|---|---|
31e31b8a | 1 | /* |
93ac68bc | 2 | * qemu user main |
5fafdf24 | 3 | * |
68d0f70e | 4 | * Copyright (c) 2003-2008 Fabrice Bellard |
31e31b8a FB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
31e31b8a | 18 | */ |
d39594e9 | 19 | #include "qemu/osdep.h" |
e441570f | 20 | #include <sys/mman.h> |
edf8e2af | 21 | #include <sys/syscall.h> |
703e0e89 | 22 | #include <sys/resource.h> |
31e31b8a | 23 | |
3ef693a0 | 24 | #include "qemu.h" |
f348b6d1 VB |
25 | #include "qemu/path.h" |
26 | #include "qemu/cutils.h" | |
27 | #include "qemu/help_option.h" | |
2b41f10e | 28 | #include "cpu.h" |
63c91552 | 29 | #include "exec/exec-all.h" |
9002ec79 | 30 | #include "tcg.h" |
1de7afc9 PB |
31 | #include "qemu/timer.h" |
32 | #include "qemu/envlist.h" | |
d8fd2954 | 33 | #include "elf.h" |
508127e2 | 34 | #include "exec/log.h" |
04a6dfeb | 35 | |
d088d664 AJ |
36 | char *exec_path; |
37 | ||
1b530a6d | 38 | int singlestep; |
8cb76755 SW |
39 | static const char *filename; |
40 | static const char *argv0; | |
41 | static int gdbstub_port; | |
42 | static envlist_t *envlist; | |
51fb256a | 43 | static const char *cpu_model; |
379f6698 PB |
44 | unsigned long mmap_min_addr; |
45 | unsigned long guest_base; | |
46 | int have_guest_base; | |
120a9848 PB |
47 | |
48 | #define EXCP_DUMP(env, fmt, ...) \ | |
49 | do { \ | |
50 | CPUState *cs = ENV_GET_CPU(env); \ | |
51 | fprintf(stderr, fmt , ## __VA_ARGS__); \ | |
52 | cpu_dump_state(cs, stderr, fprintf, 0); \ | |
53 | if (qemu_log_separate()) { \ | |
54 | qemu_log(fmt, ## __VA_ARGS__); \ | |
55 | log_cpu_state(cs, 0); \ | |
56 | } \ | |
57 | } while (0) | |
58 | ||
288e65b9 AG |
59 | #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64) |
60 | /* | |
61 | * When running 32-on-64 we should make sure we can fit all of the possible | |
62 | * guest address space into a contiguous chunk of virtual host memory. | |
63 | * | |
64 | * This way we will never overlap with our own libraries or binaries or stack | |
65 | * or anything else that QEMU maps. | |
66 | */ | |
314992b1 AG |
67 | # ifdef TARGET_MIPS |
68 | /* MIPS only supports 31 bits of virtual address space for user space */ | |
69 | unsigned long reserved_va = 0x77000000; | |
70 | # else | |
288e65b9 | 71 | unsigned long reserved_va = 0xf7000000; |
314992b1 | 72 | # endif |
288e65b9 | 73 | #else |
68a1c816 | 74 | unsigned long reserved_va; |
379f6698 | 75 | #endif |
1b530a6d | 76 | |
d03f9c32 | 77 | static void usage(int exitcode); |
fc9c5412 | 78 | |
7ee2822c | 79 | static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX; |
e586822a | 80 | const char *qemu_uname_release; |
586314f2 | 81 | |
9de5e440 FB |
82 | /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so |
83 | we allocate a bigger stack. Need a better solution, for example | |
84 | by remapping the process stack directly at the right place */ | |
703e0e89 | 85 | unsigned long guest_stack_size = 8 * 1024 * 1024UL; |
31e31b8a FB |
86 | |
87 | void gemu_log(const char *fmt, ...) | |
88 | { | |
89 | va_list ap; | |
90 | ||
91 | va_start(ap, fmt); | |
92 | vfprintf(stderr, fmt, ap); | |
93 | va_end(ap); | |
94 | } | |
95 | ||
8fcd3692 | 96 | #if defined(TARGET_I386) |
05390248 | 97 | int cpu_get_pic_interrupt(CPUX86State *env) |
92ccca6a FB |
98 | { |
99 | return -1; | |
100 | } | |
8fcd3692 | 101 | #endif |
92ccca6a | 102 | |
d5975363 PB |
103 | /***********************************************************/ |
104 | /* Helper routines for implementing atomic operations. */ | |
105 | ||
106 | /* To implement exclusive operations we force all cpus to syncronise. | |
107 | We don't require a full sync, only that no cpus are executing guest code. | |
108 | The alternative is to map target atomic ops onto host equivalents, | |
109 | which requires quite a lot of per host/target work. */ | |
c2764719 | 110 | static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER; |
d5975363 PB |
111 | static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER; |
112 | static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER; | |
113 | static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER; | |
114 | static int pending_cpus; | |
115 | ||
116 | /* Make sure everything is in a consistent state for calling fork(). */ | |
117 | void fork_start(void) | |
118 | { | |
677ef623 | 119 | qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); |
d5975363 | 120 | pthread_mutex_lock(&exclusive_lock); |
d032d1b4 | 121 | mmap_fork_start(); |
d5975363 PB |
122 | } |
123 | ||
124 | void fork_end(int child) | |
125 | { | |
d032d1b4 | 126 | mmap_fork_end(child); |
d5975363 | 127 | if (child) { |
bdc44640 | 128 | CPUState *cpu, *next_cpu; |
d5975363 PB |
129 | /* Child processes created by fork() only have a single thread. |
130 | Discard information about the parent threads. */ | |
bdc44640 AF |
131 | CPU_FOREACH_SAFE(cpu, next_cpu) { |
132 | if (cpu != thread_cpu) { | |
133 | QTAILQ_REMOVE(&cpus, thread_cpu, node); | |
134 | } | |
135 | } | |
d5975363 PB |
136 | pending_cpus = 0; |
137 | pthread_mutex_init(&exclusive_lock, NULL); | |
c2764719 | 138 | pthread_mutex_init(&cpu_list_mutex, NULL); |
d5975363 PB |
139 | pthread_cond_init(&exclusive_cond, NULL); |
140 | pthread_cond_init(&exclusive_resume, NULL); | |
677ef623 | 141 | qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); |
f7ec7f7b | 142 | gdbserver_fork(thread_cpu); |
d5975363 PB |
143 | } else { |
144 | pthread_mutex_unlock(&exclusive_lock); | |
677ef623 | 145 | qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); |
d5975363 | 146 | } |
d5975363 PB |
147 | } |
148 | ||
149 | /* Wait for pending exclusive operations to complete. The exclusive lock | |
150 | must be held. */ | |
151 | static inline void exclusive_idle(void) | |
152 | { | |
153 | while (pending_cpus) { | |
154 | pthread_cond_wait(&exclusive_resume, &exclusive_lock); | |
155 | } | |
156 | } | |
157 | ||
158 | /* Start an exclusive operation. | |
159 | Must only be called from outside cpu_arm_exec. */ | |
160 | static inline void start_exclusive(void) | |
161 | { | |
0315c31c AF |
162 | CPUState *other_cpu; |
163 | ||
d5975363 PB |
164 | pthread_mutex_lock(&exclusive_lock); |
165 | exclusive_idle(); | |
166 | ||
167 | pending_cpus = 1; | |
168 | /* Make all other cpus stop executing. */ | |
bdc44640 | 169 | CPU_FOREACH(other_cpu) { |
0315c31c | 170 | if (other_cpu->running) { |
d5975363 | 171 | pending_cpus++; |
60a3e17a | 172 | cpu_exit(other_cpu); |
d5975363 PB |
173 | } |
174 | } | |
175 | if (pending_cpus > 1) { | |
176 | pthread_cond_wait(&exclusive_cond, &exclusive_lock); | |
177 | } | |
178 | } | |
179 | ||
180 | /* Finish an exclusive operation. */ | |
f7e61b22 | 181 | static inline void __attribute__((unused)) end_exclusive(void) |
d5975363 PB |
182 | { |
183 | pending_cpus = 0; | |
184 | pthread_cond_broadcast(&exclusive_resume); | |
185 | pthread_mutex_unlock(&exclusive_lock); | |
186 | } | |
187 | ||
188 | /* Wait for exclusive ops to finish, and begin cpu execution. */ | |
0315c31c | 189 | static inline void cpu_exec_start(CPUState *cpu) |
d5975363 PB |
190 | { |
191 | pthread_mutex_lock(&exclusive_lock); | |
192 | exclusive_idle(); | |
0315c31c | 193 | cpu->running = true; |
d5975363 PB |
194 | pthread_mutex_unlock(&exclusive_lock); |
195 | } | |
196 | ||
197 | /* Mark cpu as not executing, and release pending exclusive ops. */ | |
0315c31c | 198 | static inline void cpu_exec_end(CPUState *cpu) |
d5975363 PB |
199 | { |
200 | pthread_mutex_lock(&exclusive_lock); | |
0315c31c | 201 | cpu->running = false; |
d5975363 PB |
202 | if (pending_cpus > 1) { |
203 | pending_cpus--; | |
204 | if (pending_cpus == 1) { | |
205 | pthread_cond_signal(&exclusive_cond); | |
206 | } | |
207 | } | |
208 | exclusive_idle(); | |
209 | pthread_mutex_unlock(&exclusive_lock); | |
210 | } | |
c2764719 PB |
211 | |
212 | void cpu_list_lock(void) | |
213 | { | |
214 | pthread_mutex_lock(&cpu_list_mutex); | |
215 | } | |
216 | ||
217 | void cpu_list_unlock(void) | |
218 | { | |
219 | pthread_mutex_unlock(&cpu_list_mutex); | |
220 | } | |
d5975363 PB |
221 | |
222 | ||
a541f297 FB |
223 | #ifdef TARGET_I386 |
224 | /***********************************************************/ | |
225 | /* CPUX86 core interface */ | |
226 | ||
28ab0e2e FB |
227 | uint64_t cpu_get_tsc(CPUX86State *env) |
228 | { | |
4a7428c5 | 229 | return cpu_get_host_ticks(); |
28ab0e2e FB |
230 | } |
231 | ||
5fafdf24 | 232 | static void write_dt(void *ptr, unsigned long addr, unsigned long limit, |
f4beb510 | 233 | int flags) |
6dbad63e | 234 | { |
f4beb510 | 235 | unsigned int e1, e2; |
53a5960a | 236 | uint32_t *p; |
6dbad63e FB |
237 | e1 = (addr << 16) | (limit & 0xffff); |
238 | e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); | |
f4beb510 | 239 | e2 |= flags; |
53a5960a | 240 | p = ptr; |
d538e8f5 | 241 | p[0] = tswap32(e1); |
242 | p[1] = tswap32(e2); | |
f4beb510 FB |
243 | } |
244 | ||
e441570f | 245 | static uint64_t *idt_table; |
eb38c52c | 246 | #ifdef TARGET_X86_64 |
d2fd1af7 FB |
247 | static void set_gate64(void *ptr, unsigned int type, unsigned int dpl, |
248 | uint64_t addr, unsigned int sel) | |
f4beb510 | 249 | { |
4dbc422b | 250 | uint32_t *p, e1, e2; |
f4beb510 FB |
251 | e1 = (addr & 0xffff) | (sel << 16); |
252 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
53a5960a | 253 | p = ptr; |
4dbc422b FB |
254 | p[0] = tswap32(e1); |
255 | p[1] = tswap32(e2); | |
256 | p[2] = tswap32(addr >> 32); | |
257 | p[3] = 0; | |
6dbad63e | 258 | } |
d2fd1af7 FB |
259 | /* only dpl matters as we do only user space emulation */ |
260 | static void set_idt(int n, unsigned int dpl) | |
261 | { | |
262 | set_gate64(idt_table + n * 2, 0, dpl, 0, 0); | |
263 | } | |
264 | #else | |
d2fd1af7 FB |
265 | static void set_gate(void *ptr, unsigned int type, unsigned int dpl, |
266 | uint32_t addr, unsigned int sel) | |
267 | { | |
4dbc422b | 268 | uint32_t *p, e1, e2; |
d2fd1af7 FB |
269 | e1 = (addr & 0xffff) | (sel << 16); |
270 | e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); | |
271 | p = ptr; | |
4dbc422b FB |
272 | p[0] = tswap32(e1); |
273 | p[1] = tswap32(e2); | |
d2fd1af7 FB |
274 | } |
275 | ||
f4beb510 FB |
276 | /* only dpl matters as we do only user space emulation */ |
277 | static void set_idt(int n, unsigned int dpl) | |
278 | { | |
279 | set_gate(idt_table + n, 0, dpl, 0, 0); | |
280 | } | |
d2fd1af7 | 281 | #endif |
31e31b8a | 282 | |
89e957e7 | 283 | void cpu_loop(CPUX86State *env) |
1b6b029e | 284 | { |
db6b81d4 | 285 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
bc8a22cc | 286 | int trapnr; |
992f48a0 | 287 | abi_ulong pc; |
0284b03b | 288 | abi_ulong ret; |
c227f099 | 289 | target_siginfo_t info; |
851e67a1 | 290 | |
1b6b029e | 291 | for(;;) { |
b040bc9c | 292 | cpu_exec_start(cs); |
ea3e9847 | 293 | trapnr = cpu_x86_exec(cs); |
b040bc9c | 294 | cpu_exec_end(cs); |
bc8a22cc | 295 | switch(trapnr) { |
f4beb510 | 296 | case 0x80: |
d2fd1af7 | 297 | /* linux syscall from int $0x80 */ |
0284b03b TB |
298 | ret = do_syscall(env, |
299 | env->regs[R_EAX], | |
300 | env->regs[R_EBX], | |
301 | env->regs[R_ECX], | |
302 | env->regs[R_EDX], | |
303 | env->regs[R_ESI], | |
304 | env->regs[R_EDI], | |
305 | env->regs[R_EBP], | |
306 | 0, 0); | |
307 | if (ret == -TARGET_ERESTARTSYS) { | |
308 | env->eip -= 2; | |
309 | } else if (ret != -TARGET_QEMU_ESIGRETURN) { | |
310 | env->regs[R_EAX] = ret; | |
311 | } | |
f4beb510 | 312 | break; |
d2fd1af7 FB |
313 | #ifndef TARGET_ABI32 |
314 | case EXCP_SYSCALL: | |
5ba18547 | 315 | /* linux syscall from syscall instruction */ |
0284b03b TB |
316 | ret = do_syscall(env, |
317 | env->regs[R_EAX], | |
318 | env->regs[R_EDI], | |
319 | env->regs[R_ESI], | |
320 | env->regs[R_EDX], | |
321 | env->regs[10], | |
322 | env->regs[8], | |
323 | env->regs[9], | |
324 | 0, 0); | |
325 | if (ret == -TARGET_ERESTARTSYS) { | |
326 | env->eip -= 2; | |
327 | } else if (ret != -TARGET_QEMU_ESIGRETURN) { | |
328 | env->regs[R_EAX] = ret; | |
329 | } | |
d2fd1af7 FB |
330 | break; |
331 | #endif | |
f4beb510 FB |
332 | case EXCP0B_NOSEG: |
333 | case EXCP0C_STACK: | |
a86b3c64 | 334 | info.si_signo = TARGET_SIGBUS; |
f4beb510 FB |
335 | info.si_errno = 0; |
336 | info.si_code = TARGET_SI_KERNEL; | |
337 | info._sifields._sigfault._addr = 0; | |
624f7979 | 338 | queue_signal(env, info.si_signo, &info); |
f4beb510 | 339 | break; |
1b6b029e | 340 | case EXCP0D_GPF: |
d2fd1af7 | 341 | /* XXX: potential problem if ABI32 */ |
84409ddb | 342 | #ifndef TARGET_X86_64 |
851e67a1 | 343 | if (env->eflags & VM_MASK) { |
89e957e7 | 344 | handle_vm86_fault(env); |
84409ddb JM |
345 | } else |
346 | #endif | |
347 | { | |
a86b3c64 | 348 | info.si_signo = TARGET_SIGSEGV; |
f4beb510 FB |
349 | info.si_errno = 0; |
350 | info.si_code = TARGET_SI_KERNEL; | |
351 | info._sifields._sigfault._addr = 0; | |
624f7979 | 352 | queue_signal(env, info.si_signo, &info); |
1b6b029e FB |
353 | } |
354 | break; | |
b689bc57 | 355 | case EXCP0E_PAGE: |
a86b3c64 | 356 | info.si_signo = TARGET_SIGSEGV; |
b689bc57 FB |
357 | info.si_errno = 0; |
358 | if (!(env->error_code & 1)) | |
359 | info.si_code = TARGET_SEGV_MAPERR; | |
360 | else | |
361 | info.si_code = TARGET_SEGV_ACCERR; | |
970a87a6 | 362 | info._sifields._sigfault._addr = env->cr[2]; |
624f7979 | 363 | queue_signal(env, info.si_signo, &info); |
b689bc57 | 364 | break; |
9de5e440 | 365 | case EXCP00_DIVZ: |
84409ddb | 366 | #ifndef TARGET_X86_64 |
bc8a22cc | 367 | if (env->eflags & VM_MASK) { |
447db213 | 368 | handle_vm86_trap(env, trapnr); |
84409ddb JM |
369 | } else |
370 | #endif | |
371 | { | |
bc8a22cc | 372 | /* division by zero */ |
a86b3c64 | 373 | info.si_signo = TARGET_SIGFPE; |
bc8a22cc FB |
374 | info.si_errno = 0; |
375 | info.si_code = TARGET_FPE_INTDIV; | |
376 | info._sifields._sigfault._addr = env->eip; | |
624f7979 | 377 | queue_signal(env, info.si_signo, &info); |
bc8a22cc | 378 | } |
9de5e440 | 379 | break; |
01df040b | 380 | case EXCP01_DB: |
447db213 | 381 | case EXCP03_INT3: |
84409ddb | 382 | #ifndef TARGET_X86_64 |
447db213 FB |
383 | if (env->eflags & VM_MASK) { |
384 | handle_vm86_trap(env, trapnr); | |
84409ddb JM |
385 | } else |
386 | #endif | |
387 | { | |
a86b3c64 | 388 | info.si_signo = TARGET_SIGTRAP; |
447db213 | 389 | info.si_errno = 0; |
01df040b | 390 | if (trapnr == EXCP01_DB) { |
447db213 FB |
391 | info.si_code = TARGET_TRAP_BRKPT; |
392 | info._sifields._sigfault._addr = env->eip; | |
393 | } else { | |
394 | info.si_code = TARGET_SI_KERNEL; | |
395 | info._sifields._sigfault._addr = 0; | |
396 | } | |
624f7979 | 397 | queue_signal(env, info.si_signo, &info); |
447db213 FB |
398 | } |
399 | break; | |
9de5e440 FB |
400 | case EXCP04_INTO: |
401 | case EXCP05_BOUND: | |
84409ddb | 402 | #ifndef TARGET_X86_64 |
bc8a22cc | 403 | if (env->eflags & VM_MASK) { |
447db213 | 404 | handle_vm86_trap(env, trapnr); |
84409ddb JM |
405 | } else |
406 | #endif | |
407 | { | |
a86b3c64 | 408 | info.si_signo = TARGET_SIGSEGV; |
bc8a22cc | 409 | info.si_errno = 0; |
b689bc57 | 410 | info.si_code = TARGET_SI_KERNEL; |
bc8a22cc | 411 | info._sifields._sigfault._addr = 0; |
624f7979 | 412 | queue_signal(env, info.si_signo, &info); |
bc8a22cc | 413 | } |
9de5e440 FB |
414 | break; |
415 | case EXCP06_ILLOP: | |
a86b3c64 | 416 | info.si_signo = TARGET_SIGILL; |
9de5e440 FB |
417 | info.si_errno = 0; |
418 | info.si_code = TARGET_ILL_ILLOPN; | |
419 | info._sifields._sigfault._addr = env->eip; | |
624f7979 | 420 | queue_signal(env, info.si_signo, &info); |
9de5e440 FB |
421 | break; |
422 | case EXCP_INTERRUPT: | |
423 | /* just indicate that signals should be handled asap */ | |
424 | break; | |
1fddef4b FB |
425 | case EXCP_DEBUG: |
426 | { | |
427 | int sig; | |
428 | ||
db6b81d4 | 429 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
1fddef4b FB |
430 | if (sig) |
431 | { | |
432 | info.si_signo = sig; | |
433 | info.si_errno = 0; | |
434 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 435 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
436 | } |
437 | } | |
438 | break; | |
1b6b029e | 439 | default: |
970a87a6 | 440 | pc = env->segs[R_CS].base + env->eip; |
120a9848 PB |
441 | EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", |
442 | (long)pc, trapnr); | |
1b6b029e FB |
443 | abort(); |
444 | } | |
66fb9763 | 445 | process_pending_signals(env); |
1b6b029e FB |
446 | } |
447 | } | |
b346ff46 FB |
448 | #endif |
449 | ||
450 | #ifdef TARGET_ARM | |
451 | ||
49017bd8 | 452 | #define get_user_code_u32(x, gaddr, env) \ |
d8fd2954 | 453 | ({ abi_long __r = get_user_u32((x), (gaddr)); \ |
f9fd40eb | 454 | if (!__r && bswap_code(arm_sctlr_b(env))) { \ |
d8fd2954 PB |
455 | (x) = bswap32(x); \ |
456 | } \ | |
457 | __r; \ | |
458 | }) | |
459 | ||
49017bd8 | 460 | #define get_user_code_u16(x, gaddr, env) \ |
d8fd2954 | 461 | ({ abi_long __r = get_user_u16((x), (gaddr)); \ |
f9fd40eb | 462 | if (!__r && bswap_code(arm_sctlr_b(env))) { \ |
d8fd2954 PB |
463 | (x) = bswap16(x); \ |
464 | } \ | |
465 | __r; \ | |
466 | }) | |
467 | ||
c3ae85fc PB |
468 | #define get_user_data_u32(x, gaddr, env) \ |
469 | ({ abi_long __r = get_user_u32((x), (gaddr)); \ | |
470 | if (!__r && arm_cpu_bswap_data(env)) { \ | |
471 | (x) = bswap32(x); \ | |
472 | } \ | |
473 | __r; \ | |
474 | }) | |
475 | ||
476 | #define get_user_data_u16(x, gaddr, env) \ | |
477 | ({ abi_long __r = get_user_u16((x), (gaddr)); \ | |
478 | if (!__r && arm_cpu_bswap_data(env)) { \ | |
479 | (x) = bswap16(x); \ | |
480 | } \ | |
481 | __r; \ | |
482 | }) | |
483 | ||
484 | #define put_user_data_u32(x, gaddr, env) \ | |
485 | ({ typeof(x) __x = (x); \ | |
486 | if (arm_cpu_bswap_data(env)) { \ | |
487 | __x = bswap32(__x); \ | |
488 | } \ | |
489 | put_user_u32(__x, (gaddr)); \ | |
490 | }) | |
491 | ||
492 | #define put_user_data_u16(x, gaddr, env) \ | |
493 | ({ typeof(x) __x = (x); \ | |
494 | if (arm_cpu_bswap_data(env)) { \ | |
495 | __x = bswap16(__x); \ | |
496 | } \ | |
497 | put_user_u16(__x, (gaddr)); \ | |
498 | }) | |
499 | ||
1861c454 PM |
500 | #ifdef TARGET_ABI32 |
501 | /* Commpage handling -- there is no commpage for AArch64 */ | |
502 | ||
97cc7560 DDAG |
503 | /* |
504 | * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt | |
505 | * Input: | |
506 | * r0 = pointer to oldval | |
507 | * r1 = pointer to newval | |
508 | * r2 = pointer to target value | |
509 | * | |
510 | * Output: | |
511 | * r0 = 0 if *ptr was changed, non-0 if no exchange happened | |
512 | * C set if *ptr was changed, clear if no exchange happened | |
513 | * | |
514 | * Note segv's in kernel helpers are a bit tricky, we can set the | |
515 | * data address sensibly but the PC address is just the entry point. | |
516 | */ | |
517 | static void arm_kernel_cmpxchg64_helper(CPUARMState *env) | |
518 | { | |
519 | uint64_t oldval, newval, val; | |
520 | uint32_t addr, cpsr; | |
521 | target_siginfo_t info; | |
522 | ||
523 | /* Based on the 32 bit code in do_kernel_trap */ | |
524 | ||
525 | /* XXX: This only works between threads, not between processes. | |
526 | It's probably possible to implement this with native host | |
527 | operations. However things like ldrex/strex are much harder so | |
528 | there's not much point trying. */ | |
529 | start_exclusive(); | |
530 | cpsr = cpsr_read(env); | |
531 | addr = env->regs[2]; | |
532 | ||
533 | if (get_user_u64(oldval, env->regs[0])) { | |
abf1172f | 534 | env->exception.vaddress = env->regs[0]; |
97cc7560 DDAG |
535 | goto segv; |
536 | }; | |
537 | ||
538 | if (get_user_u64(newval, env->regs[1])) { | |
abf1172f | 539 | env->exception.vaddress = env->regs[1]; |
97cc7560 DDAG |
540 | goto segv; |
541 | }; | |
542 | ||
543 | if (get_user_u64(val, addr)) { | |
abf1172f | 544 | env->exception.vaddress = addr; |
97cc7560 DDAG |
545 | goto segv; |
546 | } | |
547 | ||
548 | if (val == oldval) { | |
549 | val = newval; | |
550 | ||
551 | if (put_user_u64(val, addr)) { | |
abf1172f | 552 | env->exception.vaddress = addr; |
97cc7560 DDAG |
553 | goto segv; |
554 | }; | |
555 | ||
556 | env->regs[0] = 0; | |
557 | cpsr |= CPSR_C; | |
558 | } else { | |
559 | env->regs[0] = -1; | |
560 | cpsr &= ~CPSR_C; | |
561 | } | |
50866ba5 | 562 | cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); |
97cc7560 DDAG |
563 | end_exclusive(); |
564 | return; | |
565 | ||
566 | segv: | |
567 | end_exclusive(); | |
568 | /* We get the PC of the entry address - which is as good as anything, | |
569 | on a real kernel what you get depends on which mode it uses. */ | |
a86b3c64 | 570 | info.si_signo = TARGET_SIGSEGV; |
97cc7560 DDAG |
571 | info.si_errno = 0; |
572 | /* XXX: check env->error_code */ | |
573 | info.si_code = TARGET_SEGV_MAPERR; | |
abf1172f | 574 | info._sifields._sigfault._addr = env->exception.vaddress; |
97cc7560 | 575 | queue_signal(env, info.si_signo, &info); |
97cc7560 DDAG |
576 | } |
577 | ||
fbb4a2e3 PB |
578 | /* Handle a jump to the kernel code page. */ |
579 | static int | |
580 | do_kernel_trap(CPUARMState *env) | |
581 | { | |
582 | uint32_t addr; | |
583 | uint32_t cpsr; | |
584 | uint32_t val; | |
585 | ||
586 | switch (env->regs[15]) { | |
587 | case 0xffff0fa0: /* __kernel_memory_barrier */ | |
588 | /* ??? No-op. Will need to do better for SMP. */ | |
589 | break; | |
590 | case 0xffff0fc0: /* __kernel_cmpxchg */ | |
d5975363 PB |
591 | /* XXX: This only works between threads, not between processes. |
592 | It's probably possible to implement this with native host | |
593 | operations. However things like ldrex/strex are much harder so | |
594 | there's not much point trying. */ | |
595 | start_exclusive(); | |
fbb4a2e3 PB |
596 | cpsr = cpsr_read(env); |
597 | addr = env->regs[2]; | |
598 | /* FIXME: This should SEGV if the access fails. */ | |
599 | if (get_user_u32(val, addr)) | |
600 | val = ~env->regs[0]; | |
601 | if (val == env->regs[0]) { | |
602 | val = env->regs[1]; | |
603 | /* FIXME: Check for segfaults. */ | |
604 | put_user_u32(val, addr); | |
605 | env->regs[0] = 0; | |
606 | cpsr |= CPSR_C; | |
607 | } else { | |
608 | env->regs[0] = -1; | |
609 | cpsr &= ~CPSR_C; | |
610 | } | |
50866ba5 | 611 | cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr); |
d5975363 | 612 | end_exclusive(); |
fbb4a2e3 PB |
613 | break; |
614 | case 0xffff0fe0: /* __kernel_get_tls */ | |
b8d43285 | 615 | env->regs[0] = cpu_get_tls(env); |
fbb4a2e3 | 616 | break; |
97cc7560 DDAG |
617 | case 0xffff0f60: /* __kernel_cmpxchg64 */ |
618 | arm_kernel_cmpxchg64_helper(env); | |
619 | break; | |
620 | ||
fbb4a2e3 PB |
621 | default: |
622 | return 1; | |
623 | } | |
624 | /* Jump back to the caller. */ | |
625 | addr = env->regs[14]; | |
626 | if (addr & 1) { | |
627 | env->thumb = 1; | |
628 | addr &= ~1; | |
629 | } | |
630 | env->regs[15] = addr; | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
fa2ef212 | 635 | /* Store exclusive handling for AArch32 */ |
426f5abc PB |
636 | static int do_strex(CPUARMState *env) |
637 | { | |
03d05e2d | 638 | uint64_t val; |
426f5abc PB |
639 | int size; |
640 | int rc = 1; | |
641 | int segv = 0; | |
642 | uint32_t addr; | |
643 | start_exclusive(); | |
03d05e2d | 644 | if (env->exclusive_addr != env->exclusive_test) { |
426f5abc PB |
645 | goto fail; |
646 | } | |
03d05e2d PM |
647 | /* We know we're always AArch32 so the address is in uint32_t range |
648 | * unless it was the -1 exclusive-monitor-lost value (which won't | |
649 | * match exclusive_test above). | |
650 | */ | |
651 | assert(extract64(env->exclusive_addr, 32, 32) == 0); | |
652 | addr = env->exclusive_addr; | |
426f5abc PB |
653 | size = env->exclusive_info & 0xf; |
654 | switch (size) { | |
655 | case 0: | |
656 | segv = get_user_u8(val, addr); | |
657 | break; | |
658 | case 1: | |
c3ae85fc | 659 | segv = get_user_data_u16(val, addr, env); |
426f5abc PB |
660 | break; |
661 | case 2: | |
662 | case 3: | |
c3ae85fc | 663 | segv = get_user_data_u32(val, addr, env); |
426f5abc | 664 | break; |
f7001a3b AJ |
665 | default: |
666 | abort(); | |
426f5abc PB |
667 | } |
668 | if (segv) { | |
abf1172f | 669 | env->exception.vaddress = addr; |
426f5abc PB |
670 | goto done; |
671 | } | |
426f5abc | 672 | if (size == 3) { |
03d05e2d | 673 | uint32_t valhi; |
c3ae85fc | 674 | segv = get_user_data_u32(valhi, addr + 4, env); |
426f5abc | 675 | if (segv) { |
abf1172f | 676 | env->exception.vaddress = addr + 4; |
426f5abc PB |
677 | goto done; |
678 | } | |
c3ae85fc PB |
679 | if (arm_cpu_bswap_data(env)) { |
680 | val = deposit64((uint64_t)valhi, 32, 32, val); | |
681 | } else { | |
682 | val = deposit64(val, 32, 32, valhi); | |
683 | } | |
426f5abc | 684 | } |
03d05e2d PM |
685 | if (val != env->exclusive_val) { |
686 | goto fail; | |
687 | } | |
688 | ||
426f5abc PB |
689 | val = env->regs[(env->exclusive_info >> 8) & 0xf]; |
690 | switch (size) { | |
691 | case 0: | |
692 | segv = put_user_u8(val, addr); | |
693 | break; | |
694 | case 1: | |
c3ae85fc | 695 | segv = put_user_data_u16(val, addr, env); |
426f5abc PB |
696 | break; |
697 | case 2: | |
698 | case 3: | |
c3ae85fc | 699 | segv = put_user_data_u32(val, addr, env); |
426f5abc PB |
700 | break; |
701 | } | |
702 | if (segv) { | |
abf1172f | 703 | env->exception.vaddress = addr; |
426f5abc PB |
704 | goto done; |
705 | } | |
706 | if (size == 3) { | |
707 | val = env->regs[(env->exclusive_info >> 12) & 0xf]; | |
c3ae85fc | 708 | segv = put_user_data_u32(val, addr + 4, env); |
426f5abc | 709 | if (segv) { |
abf1172f | 710 | env->exception.vaddress = addr + 4; |
426f5abc PB |
711 | goto done; |
712 | } | |
713 | } | |
714 | rc = 0; | |
715 | fail: | |
725b8a69 | 716 | env->regs[15] += 4; |
426f5abc PB |
717 | env->regs[(env->exclusive_info >> 4) & 0xf] = rc; |
718 | done: | |
719 | end_exclusive(); | |
720 | return segv; | |
721 | } | |
722 | ||
b346ff46 FB |
723 | void cpu_loop(CPUARMState *env) |
724 | { | |
0315c31c | 725 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b346ff46 FB |
726 | int trapnr; |
727 | unsigned int n, insn; | |
c227f099 | 728 | target_siginfo_t info; |
b5ff1b31 | 729 | uint32_t addr; |
3b46e624 | 730 | |
b346ff46 | 731 | for(;;) { |
0315c31c | 732 | cpu_exec_start(cs); |
ea3e9847 | 733 | trapnr = cpu_arm_exec(cs); |
0315c31c | 734 | cpu_exec_end(cs); |
b346ff46 FB |
735 | switch(trapnr) { |
736 | case EXCP_UDEF: | |
c6981055 | 737 | { |
0429a971 | 738 | TaskState *ts = cs->opaque; |
c6981055 | 739 | uint32_t opcode; |
6d9a42be | 740 | int rc; |
c6981055 FB |
741 | |
742 | /* we handle the FPU emulation here, as Linux */ | |
743 | /* we get the opcode */ | |
2f619698 | 744 | /* FIXME - what to do if get_user() fails? */ |
49017bd8 | 745 | get_user_code_u32(opcode, env->regs[15], env); |
3b46e624 | 746 | |
6d9a42be AJ |
747 | rc = EmulateAll(opcode, &ts->fpa, env); |
748 | if (rc == 0) { /* illegal instruction */ | |
a86b3c64 | 749 | info.si_signo = TARGET_SIGILL; |
c6981055 FB |
750 | info.si_errno = 0; |
751 | info.si_code = TARGET_ILL_ILLOPN; | |
752 | info._sifields._sigfault._addr = env->regs[15]; | |
624f7979 | 753 | queue_signal(env, info.si_signo, &info); |
6d9a42be AJ |
754 | } else if (rc < 0) { /* FP exception */ |
755 | int arm_fpe=0; | |
756 | ||
757 | /* translate softfloat flags to FPSR flags */ | |
758 | if (-rc & float_flag_invalid) | |
759 | arm_fpe |= BIT_IOC; | |
760 | if (-rc & float_flag_divbyzero) | |
761 | arm_fpe |= BIT_DZC; | |
762 | if (-rc & float_flag_overflow) | |
763 | arm_fpe |= BIT_OFC; | |
764 | if (-rc & float_flag_underflow) | |
765 | arm_fpe |= BIT_UFC; | |
766 | if (-rc & float_flag_inexact) | |
767 | arm_fpe |= BIT_IXC; | |
768 | ||
769 | FPSR fpsr = ts->fpa.fpsr; | |
770 | //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe); | |
771 | ||
772 | if (fpsr & (arm_fpe << 16)) { /* exception enabled? */ | |
a86b3c64 | 773 | info.si_signo = TARGET_SIGFPE; |
6d9a42be AJ |
774 | info.si_errno = 0; |
775 | ||
776 | /* ordered by priority, least first */ | |
777 | if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; | |
778 | if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; | |
779 | if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; | |
780 | if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; | |
781 | if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; | |
782 | ||
783 | info._sifields._sigfault._addr = env->regs[15]; | |
624f7979 | 784 | queue_signal(env, info.si_signo, &info); |
6d9a42be AJ |
785 | } else { |
786 | env->regs[15] += 4; | |
787 | } | |
788 | ||
789 | /* accumulate unenabled exceptions */ | |
790 | if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC)) | |
791 | fpsr |= BIT_IXC; | |
792 | if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC)) | |
793 | fpsr |= BIT_UFC; | |
794 | if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC)) | |
795 | fpsr |= BIT_OFC; | |
796 | if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC)) | |
797 | fpsr |= BIT_DZC; | |
798 | if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC)) | |
799 | fpsr |= BIT_IOC; | |
800 | ts->fpa.fpsr=fpsr; | |
801 | } else { /* everything OK */ | |
c6981055 FB |
802 | /* increment PC */ |
803 | env->regs[15] += 4; | |
804 | } | |
805 | } | |
b346ff46 FB |
806 | break; |
807 | case EXCP_SWI: | |
06c949e6 | 808 | case EXCP_BKPT: |
b346ff46 | 809 | { |
ce4defa0 | 810 | env->eabi = 1; |
b346ff46 | 811 | /* system call */ |
06c949e6 PB |
812 | if (trapnr == EXCP_BKPT) { |
813 | if (env->thumb) { | |
2f619698 | 814 | /* FIXME - what to do if get_user() fails? */ |
49017bd8 | 815 | get_user_code_u16(insn, env->regs[15], env); |
06c949e6 PB |
816 | n = insn & 0xff; |
817 | env->regs[15] += 2; | |
818 | } else { | |
2f619698 | 819 | /* FIXME - what to do if get_user() fails? */ |
49017bd8 | 820 | get_user_code_u32(insn, env->regs[15], env); |
06c949e6 PB |
821 | n = (insn & 0xf) | ((insn >> 4) & 0xff0); |
822 | env->regs[15] += 4; | |
823 | } | |
192c7bd9 | 824 | } else { |
06c949e6 | 825 | if (env->thumb) { |
2f619698 | 826 | /* FIXME - what to do if get_user() fails? */ |
49017bd8 | 827 | get_user_code_u16(insn, env->regs[15] - 2, env); |
06c949e6 PB |
828 | n = insn & 0xff; |
829 | } else { | |
2f619698 | 830 | /* FIXME - what to do if get_user() fails? */ |
49017bd8 | 831 | get_user_code_u32(insn, env->regs[15] - 4, env); |
06c949e6 PB |
832 | n = insn & 0xffffff; |
833 | } | |
192c7bd9 FB |
834 | } |
835 | ||
6f1f31c0 | 836 | if (n == ARM_NR_cacheflush) { |
dcfd14b3 | 837 | /* nop */ |
a4f81979 FB |
838 | } else if (n == ARM_NR_semihosting |
839 | || n == ARM_NR_thumb_semihosting) { | |
840 | env->regs[0] = do_arm_semihosting (env); | |
3a1363ac | 841 | } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { |
b346ff46 | 842 | /* linux syscall */ |
ce4defa0 | 843 | if (env->thumb || n == 0) { |
192c7bd9 FB |
844 | n = env->regs[7]; |
845 | } else { | |
846 | n -= ARM_SYSCALL_BASE; | |
ce4defa0 | 847 | env->eabi = 0; |
192c7bd9 | 848 | } |
fbb4a2e3 PB |
849 | if ( n > ARM_NR_BASE) { |
850 | switch (n) { | |
851 | case ARM_NR_cacheflush: | |
dcfd14b3 | 852 | /* nop */ |
fbb4a2e3 PB |
853 | break; |
854 | case ARM_NR_set_tls: | |
855 | cpu_set_tls(env, env->regs[0]); | |
856 | env->regs[0] = 0; | |
857 | break; | |
d5355087 HL |
858 | case ARM_NR_breakpoint: |
859 | env->regs[15] -= env->thumb ? 2 : 4; | |
860 | goto excp_debug; | |
fbb4a2e3 PB |
861 | default: |
862 | gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", | |
863 | n); | |
864 | env->regs[0] = -TARGET_ENOSYS; | |
865 | break; | |
866 | } | |
867 | } else { | |
868 | env->regs[0] = do_syscall(env, | |
869 | n, | |
870 | env->regs[0], | |
871 | env->regs[1], | |
872 | env->regs[2], | |
873 | env->regs[3], | |
874 | env->regs[4], | |
5945cfcb PM |
875 | env->regs[5], |
876 | 0, 0); | |
fbb4a2e3 | 877 | } |
b346ff46 FB |
878 | } else { |
879 | goto error; | |
880 | } | |
881 | } | |
882 | break; | |
43fff238 FB |
883 | case EXCP_INTERRUPT: |
884 | /* just indicate that signals should be handled asap */ | |
885 | break; | |
abf1172f PM |
886 | case EXCP_STREX: |
887 | if (!do_strex(env)) { | |
888 | break; | |
889 | } | |
890 | /* fall through for segv */ | |
68016c62 FB |
891 | case EXCP_PREFETCH_ABORT: |
892 | case EXCP_DATA_ABORT: | |
abf1172f | 893 | addr = env->exception.vaddress; |
68016c62 | 894 | { |
a86b3c64 | 895 | info.si_signo = TARGET_SIGSEGV; |
68016c62 FB |
896 | info.si_errno = 0; |
897 | /* XXX: check env->error_code */ | |
898 | info.si_code = TARGET_SEGV_MAPERR; | |
b5ff1b31 | 899 | info._sifields._sigfault._addr = addr; |
624f7979 | 900 | queue_signal(env, info.si_signo, &info); |
68016c62 FB |
901 | } |
902 | break; | |
1fddef4b | 903 | case EXCP_DEBUG: |
d5355087 | 904 | excp_debug: |
1fddef4b FB |
905 | { |
906 | int sig; | |
907 | ||
db6b81d4 | 908 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
1fddef4b FB |
909 | if (sig) |
910 | { | |
911 | info.si_signo = sig; | |
912 | info.si_errno = 0; | |
913 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 914 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
915 | } |
916 | } | |
917 | break; | |
fbb4a2e3 PB |
918 | case EXCP_KERNEL_TRAP: |
919 | if (do_kernel_trap(env)) | |
920 | goto error; | |
921 | break; | |
f911e0a3 PM |
922 | case EXCP_YIELD: |
923 | /* nothing to do here for user-mode, just resume guest code */ | |
924 | break; | |
b346ff46 FB |
925 | default: |
926 | error: | |
120a9848 | 927 | EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
b346ff46 FB |
928 | abort(); |
929 | } | |
930 | process_pending_signals(env); | |
931 | } | |
932 | } | |
933 | ||
1861c454 PM |
934 | #else |
935 | ||
fa2ef212 MM |
936 | /* |
937 | * Handle AArch64 store-release exclusive | |
938 | * | |
939 | * rs = gets the status result of store exclusive | |
940 | * rt = is the register that is stored | |
941 | * rt2 = is the second register store (in STP) | |
942 | * | |
943 | */ | |
944 | static int do_strex_a64(CPUARMState *env) | |
945 | { | |
946 | uint64_t val; | |
947 | int size; | |
948 | bool is_pair; | |
949 | int rc = 1; | |
950 | int segv = 0; | |
951 | uint64_t addr; | |
952 | int rs, rt, rt2; | |
953 | ||
954 | start_exclusive(); | |
955 | /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */ | |
956 | size = extract32(env->exclusive_info, 0, 2); | |
957 | is_pair = extract32(env->exclusive_info, 2, 1); | |
958 | rs = extract32(env->exclusive_info, 4, 5); | |
959 | rt = extract32(env->exclusive_info, 9, 5); | |
960 | rt2 = extract32(env->exclusive_info, 14, 5); | |
961 | ||
962 | addr = env->exclusive_addr; | |
963 | ||
964 | if (addr != env->exclusive_test) { | |
965 | goto finish; | |
966 | } | |
967 | ||
968 | switch (size) { | |
969 | case 0: | |
970 | segv = get_user_u8(val, addr); | |
971 | break; | |
972 | case 1: | |
973 | segv = get_user_u16(val, addr); | |
974 | break; | |
975 | case 2: | |
976 | segv = get_user_u32(val, addr); | |
977 | break; | |
978 | case 3: | |
979 | segv = get_user_u64(val, addr); | |
980 | break; | |
981 | default: | |
982 | abort(); | |
983 | } | |
984 | if (segv) { | |
abf1172f | 985 | env->exception.vaddress = addr; |
fa2ef212 MM |
986 | goto error; |
987 | } | |
988 | if (val != env->exclusive_val) { | |
989 | goto finish; | |
990 | } | |
991 | if (is_pair) { | |
992 | if (size == 2) { | |
993 | segv = get_user_u32(val, addr + 4); | |
994 | } else { | |
995 | segv = get_user_u64(val, addr + 8); | |
996 | } | |
997 | if (segv) { | |
abf1172f | 998 | env->exception.vaddress = addr + (size == 2 ? 4 : 8); |
fa2ef212 MM |
999 | goto error; |
1000 | } | |
1001 | if (val != env->exclusive_high) { | |
1002 | goto finish; | |
1003 | } | |
1004 | } | |
2ea5a2ca JG |
1005 | /* handle the zero register */ |
1006 | val = rt == 31 ? 0 : env->xregs[rt]; | |
fa2ef212 MM |
1007 | switch (size) { |
1008 | case 0: | |
1009 | segv = put_user_u8(val, addr); | |
1010 | break; | |
1011 | case 1: | |
1012 | segv = put_user_u16(val, addr); | |
1013 | break; | |
1014 | case 2: | |
1015 | segv = put_user_u32(val, addr); | |
1016 | break; | |
1017 | case 3: | |
1018 | segv = put_user_u64(val, addr); | |
1019 | break; | |
1020 | } | |
1021 | if (segv) { | |
1022 | goto error; | |
1023 | } | |
1024 | if (is_pair) { | |
2ea5a2ca JG |
1025 | /* handle the zero register */ |
1026 | val = rt2 == 31 ? 0 : env->xregs[rt2]; | |
fa2ef212 MM |
1027 | if (size == 2) { |
1028 | segv = put_user_u32(val, addr + 4); | |
1029 | } else { | |
1030 | segv = put_user_u64(val, addr + 8); | |
1031 | } | |
1032 | if (segv) { | |
abf1172f | 1033 | env->exception.vaddress = addr + (size == 2 ? 4 : 8); |
fa2ef212 MM |
1034 | goto error; |
1035 | } | |
1036 | } | |
1037 | rc = 0; | |
1038 | finish: | |
1039 | env->pc += 4; | |
1040 | /* rs == 31 encodes a write to the ZR, thus throwing away | |
1041 | * the status return. This is rather silly but valid. | |
1042 | */ | |
1043 | if (rs < 31) { | |
1044 | env->xregs[rs] = rc; | |
1045 | } | |
1046 | error: | |
1047 | /* instruction faulted, PC does not advance */ | |
1048 | /* either way a strex releases any exclusive lock we have */ | |
1049 | env->exclusive_addr = -1; | |
1050 | end_exclusive(); | |
1051 | return segv; | |
1052 | } | |
1053 | ||
1861c454 PM |
1054 | /* AArch64 main loop */ |
1055 | void cpu_loop(CPUARMState *env) | |
1056 | { | |
1057 | CPUState *cs = CPU(arm_env_get_cpu(env)); | |
1058 | int trapnr, sig; | |
1059 | target_siginfo_t info; | |
1861c454 PM |
1060 | |
1061 | for (;;) { | |
1062 | cpu_exec_start(cs); | |
ea3e9847 | 1063 | trapnr = cpu_arm_exec(cs); |
1861c454 PM |
1064 | cpu_exec_end(cs); |
1065 | ||
1066 | switch (trapnr) { | |
1067 | case EXCP_SWI: | |
1068 | env->xregs[0] = do_syscall(env, | |
1069 | env->xregs[8], | |
1070 | env->xregs[0], | |
1071 | env->xregs[1], | |
1072 | env->xregs[2], | |
1073 | env->xregs[3], | |
1074 | env->xregs[4], | |
1075 | env->xregs[5], | |
1076 | 0, 0); | |
1077 | break; | |
1078 | case EXCP_INTERRUPT: | |
1079 | /* just indicate that signals should be handled asap */ | |
1080 | break; | |
1081 | case EXCP_UDEF: | |
a86b3c64 | 1082 | info.si_signo = TARGET_SIGILL; |
1861c454 PM |
1083 | info.si_errno = 0; |
1084 | info.si_code = TARGET_ILL_ILLOPN; | |
1085 | info._sifields._sigfault._addr = env->pc; | |
1086 | queue_signal(env, info.si_signo, &info); | |
1087 | break; | |
abf1172f PM |
1088 | case EXCP_STREX: |
1089 | if (!do_strex_a64(env)) { | |
1090 | break; | |
1091 | } | |
1092 | /* fall through for segv */ | |
1861c454 | 1093 | case EXCP_PREFETCH_ABORT: |
1861c454 | 1094 | case EXCP_DATA_ABORT: |
a86b3c64 | 1095 | info.si_signo = TARGET_SIGSEGV; |
1861c454 PM |
1096 | info.si_errno = 0; |
1097 | /* XXX: check env->error_code */ | |
1098 | info.si_code = TARGET_SEGV_MAPERR; | |
686581ad | 1099 | info._sifields._sigfault._addr = env->exception.vaddress; |
1861c454 PM |
1100 | queue_signal(env, info.si_signo, &info); |
1101 | break; | |
1102 | case EXCP_DEBUG: | |
1103 | case EXCP_BKPT: | |
1104 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); | |
1105 | if (sig) { | |
1106 | info.si_signo = sig; | |
1107 | info.si_errno = 0; | |
1108 | info.si_code = TARGET_TRAP_BRKPT; | |
1109 | queue_signal(env, info.si_signo, &info); | |
1110 | } | |
1111 | break; | |
8012c84f PM |
1112 | case EXCP_SEMIHOST: |
1113 | env->xregs[0] = do_arm_semihosting(env); | |
1114 | break; | |
f911e0a3 PM |
1115 | case EXCP_YIELD: |
1116 | /* nothing to do here for user-mode, just resume guest code */ | |
1117 | break; | |
1861c454 | 1118 | default: |
120a9848 | 1119 | EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
1861c454 PM |
1120 | abort(); |
1121 | } | |
1122 | process_pending_signals(env); | |
fa2ef212 MM |
1123 | /* Exception return on AArch64 always clears the exclusive monitor, |
1124 | * so any return to running guest code implies this. | |
1125 | * A strex (successful or otherwise) also clears the monitor, so | |
1126 | * we don't need to specialcase EXCP_STREX. | |
1127 | */ | |
1128 | env->exclusive_addr = -1; | |
1861c454 PM |
1129 | } |
1130 | } | |
1131 | #endif /* ndef TARGET_ABI32 */ | |
1132 | ||
b346ff46 | 1133 | #endif |
1b6b029e | 1134 | |
d2fbca94 GX |
1135 | #ifdef TARGET_UNICORE32 |
1136 | ||
05390248 | 1137 | void cpu_loop(CPUUniCore32State *env) |
d2fbca94 | 1138 | { |
0315c31c | 1139 | CPUState *cs = CPU(uc32_env_get_cpu(env)); |
d2fbca94 GX |
1140 | int trapnr; |
1141 | unsigned int n, insn; | |
1142 | target_siginfo_t info; | |
1143 | ||
1144 | for (;;) { | |
0315c31c | 1145 | cpu_exec_start(cs); |
ea3e9847 | 1146 | trapnr = uc32_cpu_exec(cs); |
0315c31c | 1147 | cpu_exec_end(cs); |
d2fbca94 GX |
1148 | switch (trapnr) { |
1149 | case UC32_EXCP_PRIV: | |
1150 | { | |
1151 | /* system call */ | |
1152 | get_user_u32(insn, env->regs[31] - 4); | |
1153 | n = insn & 0xffffff; | |
1154 | ||
1155 | if (n >= UC32_SYSCALL_BASE) { | |
1156 | /* linux syscall */ | |
1157 | n -= UC32_SYSCALL_BASE; | |
1158 | if (n == UC32_SYSCALL_NR_set_tls) { | |
1159 | cpu_set_tls(env, env->regs[0]); | |
1160 | env->regs[0] = 0; | |
1161 | } else { | |
1162 | env->regs[0] = do_syscall(env, | |
1163 | n, | |
1164 | env->regs[0], | |
1165 | env->regs[1], | |
1166 | env->regs[2], | |
1167 | env->regs[3], | |
1168 | env->regs[4], | |
5945cfcb PM |
1169 | env->regs[5], |
1170 | 0, 0); | |
d2fbca94 GX |
1171 | } |
1172 | } else { | |
1173 | goto error; | |
1174 | } | |
1175 | } | |
1176 | break; | |
d48813dd GX |
1177 | case UC32_EXCP_DTRAP: |
1178 | case UC32_EXCP_ITRAP: | |
a86b3c64 | 1179 | info.si_signo = TARGET_SIGSEGV; |
d2fbca94 GX |
1180 | info.si_errno = 0; |
1181 | /* XXX: check env->error_code */ | |
1182 | info.si_code = TARGET_SEGV_MAPERR; | |
1183 | info._sifields._sigfault._addr = env->cp0.c4_faultaddr; | |
1184 | queue_signal(env, info.si_signo, &info); | |
1185 | break; | |
1186 | case EXCP_INTERRUPT: | |
1187 | /* just indicate that signals should be handled asap */ | |
1188 | break; | |
1189 | case EXCP_DEBUG: | |
1190 | { | |
1191 | int sig; | |
1192 | ||
db6b81d4 | 1193 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
d2fbca94 GX |
1194 | if (sig) { |
1195 | info.si_signo = sig; | |
1196 | info.si_errno = 0; | |
1197 | info.si_code = TARGET_TRAP_BRKPT; | |
1198 | queue_signal(env, info.si_signo, &info); | |
1199 | } | |
1200 | } | |
1201 | break; | |
1202 | default: | |
1203 | goto error; | |
1204 | } | |
1205 | process_pending_signals(env); | |
1206 | } | |
1207 | ||
1208 | error: | |
120a9848 | 1209 | EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
d2fbca94 GX |
1210 | abort(); |
1211 | } | |
1212 | #endif | |
1213 | ||
93ac68bc | 1214 | #ifdef TARGET_SPARC |
ed23fbd9 | 1215 | #define SPARC64_STACK_BIAS 2047 |
93ac68bc | 1216 | |
060366c5 FB |
1217 | //#define DEBUG_WIN |
1218 | ||
2623cbaf FB |
1219 | /* WARNING: dealing with register windows _is_ complicated. More info |
1220 | can be found at http://www.sics.se/~psm/sparcstack.html */ | |
060366c5 FB |
1221 | static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) |
1222 | { | |
1a14026e | 1223 | index = (index + cwp * 16) % (16 * env->nwindows); |
060366c5 FB |
1224 | /* wrap handling : if cwp is on the last window, then we use the |
1225 | registers 'after' the end */ | |
1a14026e BS |
1226 | if (index < 8 && env->cwp == env->nwindows - 1) |
1227 | index += 16 * env->nwindows; | |
060366c5 FB |
1228 | return index; |
1229 | } | |
1230 | ||
2623cbaf FB |
1231 | /* save the register window 'cwp1' */ |
1232 | static inline void save_window_offset(CPUSPARCState *env, int cwp1) | |
060366c5 | 1233 | { |
2623cbaf | 1234 | unsigned int i; |
992f48a0 | 1235 | abi_ulong sp_ptr; |
3b46e624 | 1236 | |
53a5960a | 1237 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; |
ed23fbd9 BS |
1238 | #ifdef TARGET_SPARC64 |
1239 | if (sp_ptr & 3) | |
1240 | sp_ptr += SPARC64_STACK_BIAS; | |
1241 | #endif | |
060366c5 | 1242 | #if defined(DEBUG_WIN) |
2daf0284 BS |
1243 | printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n", |
1244 | sp_ptr, cwp1); | |
060366c5 | 1245 | #endif |
2623cbaf | 1246 | for(i = 0; i < 16; i++) { |
2f619698 FB |
1247 | /* FIXME - what to do if put_user() fails? */ |
1248 | put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
992f48a0 | 1249 | sp_ptr += sizeof(abi_ulong); |
2623cbaf | 1250 | } |
060366c5 FB |
1251 | } |
1252 | ||
1253 | static void save_window(CPUSPARCState *env) | |
1254 | { | |
5ef54116 | 1255 | #ifndef TARGET_SPARC64 |
2623cbaf | 1256 | unsigned int new_wim; |
1a14026e BS |
1257 | new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & |
1258 | ((1LL << env->nwindows) - 1); | |
1259 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); | |
2623cbaf | 1260 | env->wim = new_wim; |
5ef54116 | 1261 | #else |
1a14026e | 1262 | save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); |
5ef54116 FB |
1263 | env->cansave++; |
1264 | env->canrestore--; | |
1265 | #endif | |
060366c5 FB |
1266 | } |
1267 | ||
1268 | static void restore_window(CPUSPARCState *env) | |
1269 | { | |
eda52953 BS |
1270 | #ifndef TARGET_SPARC64 |
1271 | unsigned int new_wim; | |
1272 | #endif | |
1273 | unsigned int i, cwp1; | |
992f48a0 | 1274 | abi_ulong sp_ptr; |
3b46e624 | 1275 | |
eda52953 | 1276 | #ifndef TARGET_SPARC64 |
1a14026e BS |
1277 | new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & |
1278 | ((1LL << env->nwindows) - 1); | |
eda52953 | 1279 | #endif |
3b46e624 | 1280 | |
060366c5 | 1281 | /* restore the invalid window */ |
1a14026e | 1282 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); |
53a5960a | 1283 | sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; |
ed23fbd9 BS |
1284 | #ifdef TARGET_SPARC64 |
1285 | if (sp_ptr & 3) | |
1286 | sp_ptr += SPARC64_STACK_BIAS; | |
1287 | #endif | |
060366c5 | 1288 | #if defined(DEBUG_WIN) |
2daf0284 BS |
1289 | printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n", |
1290 | sp_ptr, cwp1); | |
060366c5 | 1291 | #endif |
2623cbaf | 1292 | for(i = 0; i < 16; i++) { |
2f619698 FB |
1293 | /* FIXME - what to do if get_user() fails? */ |
1294 | get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); | |
992f48a0 | 1295 | sp_ptr += sizeof(abi_ulong); |
2623cbaf | 1296 | } |
5ef54116 FB |
1297 | #ifdef TARGET_SPARC64 |
1298 | env->canrestore++; | |
1a14026e BS |
1299 | if (env->cleanwin < env->nwindows - 1) |
1300 | env->cleanwin++; | |
5ef54116 | 1301 | env->cansave--; |
eda52953 BS |
1302 | #else |
1303 | env->wim = new_wim; | |
5ef54116 | 1304 | #endif |
060366c5 FB |
1305 | } |
1306 | ||
1307 | static void flush_windows(CPUSPARCState *env) | |
1308 | { | |
1309 | int offset, cwp1; | |
2623cbaf FB |
1310 | |
1311 | offset = 1; | |
060366c5 FB |
1312 | for(;;) { |
1313 | /* if restore would invoke restore_window(), then we can stop */ | |
1a14026e | 1314 | cwp1 = cpu_cwp_inc(env, env->cwp + offset); |
eda52953 | 1315 | #ifndef TARGET_SPARC64 |
060366c5 FB |
1316 | if (env->wim & (1 << cwp1)) |
1317 | break; | |
eda52953 BS |
1318 | #else |
1319 | if (env->canrestore == 0) | |
1320 | break; | |
1321 | env->cansave++; | |
1322 | env->canrestore--; | |
1323 | #endif | |
2623cbaf | 1324 | save_window_offset(env, cwp1); |
060366c5 FB |
1325 | offset++; |
1326 | } | |
1a14026e | 1327 | cwp1 = cpu_cwp_inc(env, env->cwp + 1); |
eda52953 BS |
1328 | #ifndef TARGET_SPARC64 |
1329 | /* set wim so that restore will reload the registers */ | |
2623cbaf | 1330 | env->wim = 1 << cwp1; |
eda52953 | 1331 | #endif |
2623cbaf FB |
1332 | #if defined(DEBUG_WIN) |
1333 | printf("flush_windows: nb=%d\n", offset - 1); | |
80a9d035 | 1334 | #endif |
2623cbaf | 1335 | } |
060366c5 | 1336 | |
93ac68bc FB |
1337 | void cpu_loop (CPUSPARCState *env) |
1338 | { | |
878096ee | 1339 | CPUState *cs = CPU(sparc_env_get_cpu(env)); |
2cc20260 RH |
1340 | int trapnr; |
1341 | abi_long ret; | |
c227f099 | 1342 | target_siginfo_t info; |
3b46e624 | 1343 | |
060366c5 | 1344 | while (1) { |
b040bc9c | 1345 | cpu_exec_start(cs); |
ea3e9847 | 1346 | trapnr = cpu_sparc_exec(cs); |
b040bc9c | 1347 | cpu_exec_end(cs); |
3b46e624 | 1348 | |
20132b96 RH |
1349 | /* Compute PSR before exposing state. */ |
1350 | if (env->cc_op != CC_OP_FLAGS) { | |
1351 | cpu_get_psr(env); | |
1352 | } | |
1353 | ||
060366c5 | 1354 | switch (trapnr) { |
5ef54116 | 1355 | #ifndef TARGET_SPARC64 |
5fafdf24 | 1356 | case 0x88: |
060366c5 | 1357 | case 0x90: |
5ef54116 | 1358 | #else |
cb33da57 | 1359 | case 0x110: |
5ef54116 FB |
1360 | case 0x16d: |
1361 | #endif | |
060366c5 | 1362 | ret = do_syscall (env, env->gregs[1], |
5fafdf24 TS |
1363 | env->regwptr[0], env->regwptr[1], |
1364 | env->regwptr[2], env->regwptr[3], | |
5945cfcb PM |
1365 | env->regwptr[4], env->regwptr[5], |
1366 | 0, 0); | |
2cc20260 | 1367 | if ((abi_ulong)ret >= (abi_ulong)(-515)) { |
992f48a0 | 1368 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
27908725 FB |
1369 | env->xcc |= PSR_CARRY; |
1370 | #else | |
060366c5 | 1371 | env->psr |= PSR_CARRY; |
27908725 | 1372 | #endif |
060366c5 FB |
1373 | ret = -ret; |
1374 | } else { | |
992f48a0 | 1375 | #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) |
27908725 FB |
1376 | env->xcc &= ~PSR_CARRY; |
1377 | #else | |
060366c5 | 1378 | env->psr &= ~PSR_CARRY; |
27908725 | 1379 | #endif |
060366c5 FB |
1380 | } |
1381 | env->regwptr[0] = ret; | |
1382 | /* next instruction */ | |
1383 | env->pc = env->npc; | |
1384 | env->npc = env->npc + 4; | |
1385 | break; | |
1386 | case 0x83: /* flush windows */ | |
992f48a0 BS |
1387 | #ifdef TARGET_ABI32 |
1388 | case 0x103: | |
1389 | #endif | |
2623cbaf | 1390 | flush_windows(env); |
060366c5 FB |
1391 | /* next instruction */ |
1392 | env->pc = env->npc; | |
1393 | env->npc = env->npc + 4; | |
1394 | break; | |
3475187d | 1395 | #ifndef TARGET_SPARC64 |
060366c5 FB |
1396 | case TT_WIN_OVF: /* window overflow */ |
1397 | save_window(env); | |
1398 | break; | |
1399 | case TT_WIN_UNF: /* window underflow */ | |
1400 | restore_window(env); | |
1401 | break; | |
61ff6f58 FB |
1402 | case TT_TFAULT: |
1403 | case TT_DFAULT: | |
1404 | { | |
59f7182f | 1405 | info.si_signo = TARGET_SIGSEGV; |
61ff6f58 FB |
1406 | info.si_errno = 0; |
1407 | /* XXX: check env->error_code */ | |
1408 | info.si_code = TARGET_SEGV_MAPERR; | |
1409 | info._sifields._sigfault._addr = env->mmuregs[4]; | |
624f7979 | 1410 | queue_signal(env, info.si_signo, &info); |
61ff6f58 FB |
1411 | } |
1412 | break; | |
3475187d | 1413 | #else |
5ef54116 FB |
1414 | case TT_SPILL: /* window overflow */ |
1415 | save_window(env); | |
1416 | break; | |
1417 | case TT_FILL: /* window underflow */ | |
1418 | restore_window(env); | |
1419 | break; | |
7f84a729 BS |
1420 | case TT_TFAULT: |
1421 | case TT_DFAULT: | |
1422 | { | |
59f7182f | 1423 | info.si_signo = TARGET_SIGSEGV; |
7f84a729 BS |
1424 | info.si_errno = 0; |
1425 | /* XXX: check env->error_code */ | |
1426 | info.si_code = TARGET_SEGV_MAPERR; | |
1427 | if (trapnr == TT_DFAULT) | |
1428 | info._sifields._sigfault._addr = env->dmmuregs[4]; | |
1429 | else | |
8194f35a | 1430 | info._sifields._sigfault._addr = cpu_tsptr(env)->tpc; |
624f7979 | 1431 | queue_signal(env, info.si_signo, &info); |
7f84a729 BS |
1432 | } |
1433 | break; | |
27524dc3 | 1434 | #ifndef TARGET_ABI32 |
5bfb56b2 BS |
1435 | case 0x16e: |
1436 | flush_windows(env); | |
1437 | sparc64_get_context(env); | |
1438 | break; | |
1439 | case 0x16f: | |
1440 | flush_windows(env); | |
1441 | sparc64_set_context(env); | |
1442 | break; | |
27524dc3 | 1443 | #endif |
3475187d | 1444 | #endif |
48dc41eb FB |
1445 | case EXCP_INTERRUPT: |
1446 | /* just indicate that signals should be handled asap */ | |
1447 | break; | |
75f22e4e RH |
1448 | case TT_ILL_INSN: |
1449 | { | |
1450 | info.si_signo = TARGET_SIGILL; | |
1451 | info.si_errno = 0; | |
1452 | info.si_code = TARGET_ILL_ILLOPC; | |
1453 | info._sifields._sigfault._addr = env->pc; | |
1454 | queue_signal(env, info.si_signo, &info); | |
1455 | } | |
1456 | break; | |
1fddef4b FB |
1457 | case EXCP_DEBUG: |
1458 | { | |
1459 | int sig; | |
1460 | ||
db6b81d4 | 1461 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
1fddef4b FB |
1462 | if (sig) |
1463 | { | |
1464 | info.si_signo = sig; | |
1465 | info.si_errno = 0; | |
1466 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 1467 | queue_signal(env, info.si_signo, &info); |
1fddef4b FB |
1468 | } |
1469 | } | |
1470 | break; | |
060366c5 FB |
1471 | default: |
1472 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 1473 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 1474 | exit(EXIT_FAILURE); |
060366c5 FB |
1475 | } |
1476 | process_pending_signals (env); | |
1477 | } | |
93ac68bc FB |
1478 | } |
1479 | ||
1480 | #endif | |
1481 | ||
67867308 | 1482 | #ifdef TARGET_PPC |
05390248 | 1483 | static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env) |
9fddaa0c | 1484 | { |
4a7428c5 | 1485 | return cpu_get_host_ticks(); |
9fddaa0c | 1486 | } |
3b46e624 | 1487 | |
05390248 | 1488 | uint64_t cpu_ppc_load_tbl(CPUPPCState *env) |
9fddaa0c | 1489 | { |
e3ea6529 | 1490 | return cpu_ppc_get_tb(env); |
9fddaa0c | 1491 | } |
3b46e624 | 1492 | |
05390248 | 1493 | uint32_t cpu_ppc_load_tbu(CPUPPCState *env) |
9fddaa0c FB |
1494 | { |
1495 | return cpu_ppc_get_tb(env) >> 32; | |
1496 | } | |
3b46e624 | 1497 | |
05390248 | 1498 | uint64_t cpu_ppc_load_atbl(CPUPPCState *env) |
9fddaa0c | 1499 | { |
b711de95 | 1500 | return cpu_ppc_get_tb(env); |
9fddaa0c | 1501 | } |
5fafdf24 | 1502 | |
05390248 | 1503 | uint32_t cpu_ppc_load_atbu(CPUPPCState *env) |
9fddaa0c | 1504 | { |
a062e36c | 1505 | return cpu_ppc_get_tb(env) >> 32; |
9fddaa0c | 1506 | } |
76a66253 | 1507 | |
05390248 | 1508 | uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) |
76a66253 JM |
1509 | __attribute__ (( alias ("cpu_ppc_load_tbu") )); |
1510 | ||
05390248 | 1511 | uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env) |
9fddaa0c | 1512 | { |
76a66253 | 1513 | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
9fddaa0c | 1514 | } |
76a66253 | 1515 | |
a750fc0b | 1516 | /* XXX: to be fixed */ |
73b01960 | 1517 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
a750fc0b JM |
1518 | { |
1519 | return -1; | |
1520 | } | |
1521 | ||
73b01960 | 1522 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
a750fc0b JM |
1523 | { |
1524 | return -1; | |
1525 | } | |
1526 | ||
56f066bb NF |
1527 | static int do_store_exclusive(CPUPPCState *env) |
1528 | { | |
1529 | target_ulong addr; | |
1530 | target_ulong page_addr; | |
e22c357b | 1531 | target_ulong val, val2 __attribute__((unused)) = 0; |
56f066bb NF |
1532 | int flags; |
1533 | int segv = 0; | |
1534 | ||
1535 | addr = env->reserve_ea; | |
1536 | page_addr = addr & TARGET_PAGE_MASK; | |
1537 | start_exclusive(); | |
1538 | mmap_lock(); | |
1539 | flags = page_get_flags(page_addr); | |
1540 | if ((flags & PAGE_READ) == 0) { | |
1541 | segv = 1; | |
1542 | } else { | |
1543 | int reg = env->reserve_info & 0x1f; | |
4b1daa72 | 1544 | int size = env->reserve_info >> 5; |
56f066bb NF |
1545 | int stored = 0; |
1546 | ||
1547 | if (addr == env->reserve_addr) { | |
1548 | switch (size) { | |
1549 | case 1: segv = get_user_u8(val, addr); break; | |
1550 | case 2: segv = get_user_u16(val, addr); break; | |
1551 | case 4: segv = get_user_u32(val, addr); break; | |
1552 | #if defined(TARGET_PPC64) | |
1553 | case 8: segv = get_user_u64(val, addr); break; | |
27b95bfe TM |
1554 | case 16: { |
1555 | segv = get_user_u64(val, addr); | |
1556 | if (!segv) { | |
1557 | segv = get_user_u64(val2, addr + 8); | |
1558 | } | |
1559 | break; | |
1560 | } | |
56f066bb NF |
1561 | #endif |
1562 | default: abort(); | |
1563 | } | |
1564 | if (!segv && val == env->reserve_val) { | |
1565 | val = env->gpr[reg]; | |
1566 | switch (size) { | |
1567 | case 1: segv = put_user_u8(val, addr); break; | |
1568 | case 2: segv = put_user_u16(val, addr); break; | |
1569 | case 4: segv = put_user_u32(val, addr); break; | |
1570 | #if defined(TARGET_PPC64) | |
1571 | case 8: segv = put_user_u64(val, addr); break; | |
27b95bfe TM |
1572 | case 16: { |
1573 | if (val2 == env->reserve_val2) { | |
e22c357b DK |
1574 | if (msr_le) { |
1575 | val2 = val; | |
1576 | val = env->gpr[reg+1]; | |
1577 | } else { | |
1578 | val2 = env->gpr[reg+1]; | |
1579 | } | |
27b95bfe TM |
1580 | segv = put_user_u64(val, addr); |
1581 | if (!segv) { | |
1582 | segv = put_user_u64(val2, addr + 8); | |
1583 | } | |
1584 | } | |
1585 | break; | |
1586 | } | |
56f066bb NF |
1587 | #endif |
1588 | default: abort(); | |
1589 | } | |
1590 | if (!segv) { | |
1591 | stored = 1; | |
1592 | } | |
1593 | } | |
1594 | } | |
1595 | env->crf[0] = (stored << 1) | xer_so; | |
1596 | env->reserve_addr = (target_ulong)-1; | |
1597 | } | |
1598 | if (!segv) { | |
1599 | env->nip += 4; | |
1600 | } | |
1601 | mmap_unlock(); | |
1602 | end_exclusive(); | |
1603 | return segv; | |
1604 | } | |
1605 | ||
67867308 FB |
1606 | void cpu_loop(CPUPPCState *env) |
1607 | { | |
0315c31c | 1608 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
c227f099 | 1609 | target_siginfo_t info; |
61190b14 | 1610 | int trapnr; |
9e0e2f96 | 1611 | target_ulong ret; |
3b46e624 | 1612 | |
67867308 | 1613 | for(;;) { |
0315c31c | 1614 | cpu_exec_start(cs); |
ea3e9847 | 1615 | trapnr = cpu_ppc_exec(cs); |
0315c31c | 1616 | cpu_exec_end(cs); |
67867308 | 1617 | switch(trapnr) { |
e1833e1f JM |
1618 | case POWERPC_EXCP_NONE: |
1619 | /* Just go on */ | |
67867308 | 1620 | break; |
e1833e1f | 1621 | case POWERPC_EXCP_CRITICAL: /* Critical input */ |
a47dddd7 | 1622 | cpu_abort(cs, "Critical interrupt while in user mode. " |
e1833e1f | 1623 | "Aborting\n"); |
61190b14 | 1624 | break; |
e1833e1f | 1625 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
a47dddd7 | 1626 | cpu_abort(cs, "Machine check exception while in user mode. " |
e1833e1f JM |
1627 | "Aborting\n"); |
1628 | break; | |
1629 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
90e189ec | 1630 | EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n", |
e1833e1f JM |
1631 | env->spr[SPR_DAR]); |
1632 | /* XXX: check this. Seems bugged */ | |
2be0071f FB |
1633 | switch (env->error_code & 0xFF000000) { |
1634 | case 0x40000000: | |
61190b14 FB |
1635 | info.si_signo = TARGET_SIGSEGV; |
1636 | info.si_errno = 0; | |
1637 | info.si_code = TARGET_SEGV_MAPERR; | |
1638 | break; | |
2be0071f | 1639 | case 0x04000000: |
61190b14 FB |
1640 | info.si_signo = TARGET_SIGILL; |
1641 | info.si_errno = 0; | |
1642 | info.si_code = TARGET_ILL_ILLADR; | |
1643 | break; | |
2be0071f | 1644 | case 0x08000000: |
61190b14 FB |
1645 | info.si_signo = TARGET_SIGSEGV; |
1646 | info.si_errno = 0; | |
1647 | info.si_code = TARGET_SEGV_ACCERR; | |
1648 | break; | |
61190b14 FB |
1649 | default: |
1650 | /* Let's send a regular segfault... */ | |
e1833e1f JM |
1651 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", |
1652 | env->error_code); | |
61190b14 FB |
1653 | info.si_signo = TARGET_SIGSEGV; |
1654 | info.si_errno = 0; | |
1655 | info.si_code = TARGET_SEGV_MAPERR; | |
1656 | break; | |
1657 | } | |
67867308 | 1658 | info._sifields._sigfault._addr = env->nip; |
624f7979 | 1659 | queue_signal(env, info.si_signo, &info); |
67867308 | 1660 | break; |
e1833e1f | 1661 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
90e189ec BS |
1662 | EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx |
1663 | "\n", env->spr[SPR_SRR0]); | |
e1833e1f | 1664 | /* XXX: check this */ |
2be0071f FB |
1665 | switch (env->error_code & 0xFF000000) { |
1666 | case 0x40000000: | |
61190b14 | 1667 | info.si_signo = TARGET_SIGSEGV; |
67867308 | 1668 | info.si_errno = 0; |
61190b14 FB |
1669 | info.si_code = TARGET_SEGV_MAPERR; |
1670 | break; | |
2be0071f FB |
1671 | case 0x10000000: |
1672 | case 0x08000000: | |
61190b14 FB |
1673 | info.si_signo = TARGET_SIGSEGV; |
1674 | info.si_errno = 0; | |
1675 | info.si_code = TARGET_SEGV_ACCERR; | |
1676 | break; | |
1677 | default: | |
1678 | /* Let's send a regular segfault... */ | |
e1833e1f JM |
1679 | EXCP_DUMP(env, "Invalid segfault errno (%02x)\n", |
1680 | env->error_code); | |
61190b14 FB |
1681 | info.si_signo = TARGET_SIGSEGV; |
1682 | info.si_errno = 0; | |
1683 | info.si_code = TARGET_SEGV_MAPERR; | |
1684 | break; | |
1685 | } | |
1686 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1687 | queue_signal(env, info.si_signo, &info); |
67867308 | 1688 | break; |
e1833e1f | 1689 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
a47dddd7 | 1690 | cpu_abort(cs, "External interrupt while in user mode. " |
e1833e1f JM |
1691 | "Aborting\n"); |
1692 | break; | |
1693 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ | |
1694 | EXCP_DUMP(env, "Unaligned memory access\n"); | |
1695 | /* XXX: check this */ | |
61190b14 | 1696 | info.si_signo = TARGET_SIGBUS; |
67867308 | 1697 | info.si_errno = 0; |
61190b14 | 1698 | info.si_code = TARGET_BUS_ADRALN; |
6bb9a0a9 | 1699 | info._sifields._sigfault._addr = env->nip; |
624f7979 | 1700 | queue_signal(env, info.si_signo, &info); |
67867308 | 1701 | break; |
e1833e1f JM |
1702 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
1703 | /* XXX: check this */ | |
61190b14 | 1704 | switch (env->error_code & ~0xF) { |
e1833e1f JM |
1705 | case POWERPC_EXCP_FP: |
1706 | EXCP_DUMP(env, "Floating point program exception\n"); | |
61190b14 FB |
1707 | info.si_signo = TARGET_SIGFPE; |
1708 | info.si_errno = 0; | |
1709 | switch (env->error_code & 0xF) { | |
e1833e1f | 1710 | case POWERPC_EXCP_FP_OX: |
61190b14 FB |
1711 | info.si_code = TARGET_FPE_FLTOVF; |
1712 | break; | |
e1833e1f | 1713 | case POWERPC_EXCP_FP_UX: |
61190b14 FB |
1714 | info.si_code = TARGET_FPE_FLTUND; |
1715 | break; | |
e1833e1f JM |
1716 | case POWERPC_EXCP_FP_ZX: |
1717 | case POWERPC_EXCP_FP_VXZDZ: | |
61190b14 FB |
1718 | info.si_code = TARGET_FPE_FLTDIV; |
1719 | break; | |
e1833e1f | 1720 | case POWERPC_EXCP_FP_XX: |
61190b14 FB |
1721 | info.si_code = TARGET_FPE_FLTRES; |
1722 | break; | |
e1833e1f | 1723 | case POWERPC_EXCP_FP_VXSOFT: |
61190b14 FB |
1724 | info.si_code = TARGET_FPE_FLTINV; |
1725 | break; | |
7c58044c | 1726 | case POWERPC_EXCP_FP_VXSNAN: |
e1833e1f JM |
1727 | case POWERPC_EXCP_FP_VXISI: |
1728 | case POWERPC_EXCP_FP_VXIDI: | |
1729 | case POWERPC_EXCP_FP_VXIMZ: | |
1730 | case POWERPC_EXCP_FP_VXVC: | |
1731 | case POWERPC_EXCP_FP_VXSQRT: | |
1732 | case POWERPC_EXCP_FP_VXCVI: | |
61190b14 FB |
1733 | info.si_code = TARGET_FPE_FLTSUB; |
1734 | break; | |
1735 | default: | |
e1833e1f JM |
1736 | EXCP_DUMP(env, "Unknown floating point exception (%02x)\n", |
1737 | env->error_code); | |
1738 | break; | |
61190b14 | 1739 | } |
e1833e1f JM |
1740 | break; |
1741 | case POWERPC_EXCP_INVAL: | |
1742 | EXCP_DUMP(env, "Invalid instruction\n"); | |
61190b14 FB |
1743 | info.si_signo = TARGET_SIGILL; |
1744 | info.si_errno = 0; | |
1745 | switch (env->error_code & 0xF) { | |
e1833e1f | 1746 | case POWERPC_EXCP_INVAL_INVAL: |
61190b14 FB |
1747 | info.si_code = TARGET_ILL_ILLOPC; |
1748 | break; | |
e1833e1f | 1749 | case POWERPC_EXCP_INVAL_LSWX: |
a750fc0b | 1750 | info.si_code = TARGET_ILL_ILLOPN; |
61190b14 | 1751 | break; |
e1833e1f | 1752 | case POWERPC_EXCP_INVAL_SPR: |
61190b14 FB |
1753 | info.si_code = TARGET_ILL_PRVREG; |
1754 | break; | |
e1833e1f | 1755 | case POWERPC_EXCP_INVAL_FP: |
61190b14 FB |
1756 | info.si_code = TARGET_ILL_COPROC; |
1757 | break; | |
1758 | default: | |
e1833e1f JM |
1759 | EXCP_DUMP(env, "Unknown invalid operation (%02x)\n", |
1760 | env->error_code & 0xF); | |
61190b14 FB |
1761 | info.si_code = TARGET_ILL_ILLADR; |
1762 | break; | |
1763 | } | |
1764 | break; | |
e1833e1f JM |
1765 | case POWERPC_EXCP_PRIV: |
1766 | EXCP_DUMP(env, "Privilege violation\n"); | |
61190b14 FB |
1767 | info.si_signo = TARGET_SIGILL; |
1768 | info.si_errno = 0; | |
1769 | switch (env->error_code & 0xF) { | |
e1833e1f | 1770 | case POWERPC_EXCP_PRIV_OPC: |
61190b14 FB |
1771 | info.si_code = TARGET_ILL_PRVOPC; |
1772 | break; | |
e1833e1f | 1773 | case POWERPC_EXCP_PRIV_REG: |
61190b14 | 1774 | info.si_code = TARGET_ILL_PRVREG; |
e1833e1f | 1775 | break; |
61190b14 | 1776 | default: |
e1833e1f JM |
1777 | EXCP_DUMP(env, "Unknown privilege violation (%02x)\n", |
1778 | env->error_code & 0xF); | |
61190b14 FB |
1779 | info.si_code = TARGET_ILL_PRVOPC; |
1780 | break; | |
1781 | } | |
1782 | break; | |
e1833e1f | 1783 | case POWERPC_EXCP_TRAP: |
a47dddd7 | 1784 | cpu_abort(cs, "Tried to call a TRAP\n"); |
e1833e1f | 1785 | break; |
61190b14 FB |
1786 | default: |
1787 | /* Should not happen ! */ | |
a47dddd7 | 1788 | cpu_abort(cs, "Unknown program exception (%02x)\n", |
e1833e1f JM |
1789 | env->error_code); |
1790 | break; | |
61190b14 FB |
1791 | } |
1792 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1793 | queue_signal(env, info.si_signo, &info); |
67867308 | 1794 | break; |
e1833e1f JM |
1795 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
1796 | EXCP_DUMP(env, "No floating point allowed\n"); | |
61190b14 | 1797 | info.si_signo = TARGET_SIGILL; |
67867308 | 1798 | info.si_errno = 0; |
61190b14 FB |
1799 | info.si_code = TARGET_ILL_COPROC; |
1800 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1801 | queue_signal(env, info.si_signo, &info); |
67867308 | 1802 | break; |
e1833e1f | 1803 | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
a47dddd7 | 1804 | cpu_abort(cs, "Syscall exception while in user mode. " |
e1833e1f | 1805 | "Aborting\n"); |
61190b14 | 1806 | break; |
e1833e1f JM |
1807 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
1808 | EXCP_DUMP(env, "No APU instruction allowed\n"); | |
1809 | info.si_signo = TARGET_SIGILL; | |
1810 | info.si_errno = 0; | |
1811 | info.si_code = TARGET_ILL_COPROC; | |
1812 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1813 | queue_signal(env, info.si_signo, &info); |
61190b14 | 1814 | break; |
e1833e1f | 1815 | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
a47dddd7 | 1816 | cpu_abort(cs, "Decrementer interrupt while in user mode. " |
e1833e1f | 1817 | "Aborting\n"); |
61190b14 | 1818 | break; |
e1833e1f | 1819 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
a47dddd7 | 1820 | cpu_abort(cs, "Fix interval timer interrupt while in user mode. " |
e1833e1f JM |
1821 | "Aborting\n"); |
1822 | break; | |
1823 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ | |
a47dddd7 | 1824 | cpu_abort(cs, "Watchdog timer interrupt while in user mode. " |
e1833e1f JM |
1825 | "Aborting\n"); |
1826 | break; | |
1827 | case POWERPC_EXCP_DTLB: /* Data TLB error */ | |
a47dddd7 | 1828 | cpu_abort(cs, "Data TLB exception while in user mode. " |
e1833e1f JM |
1829 | "Aborting\n"); |
1830 | break; | |
1831 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
a47dddd7 | 1832 | cpu_abort(cs, "Instruction TLB exception while in user mode. " |
e1833e1f JM |
1833 | "Aborting\n"); |
1834 | break; | |
e1833e1f JM |
1835 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ |
1836 | EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n"); | |
1837 | info.si_signo = TARGET_SIGILL; | |
1838 | info.si_errno = 0; | |
1839 | info.si_code = TARGET_ILL_COPROC; | |
1840 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1841 | queue_signal(env, info.si_signo, &info); |
e1833e1f JM |
1842 | break; |
1843 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ | |
a47dddd7 | 1844 | cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); |
e1833e1f JM |
1845 | break; |
1846 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ | |
a47dddd7 | 1847 | cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); |
e1833e1f JM |
1848 | break; |
1849 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ | |
a47dddd7 | 1850 | cpu_abort(cs, "Performance monitor exception not handled\n"); |
e1833e1f JM |
1851 | break; |
1852 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ | |
a47dddd7 | 1853 | cpu_abort(cs, "Doorbell interrupt while in user mode. " |
e1833e1f JM |
1854 | "Aborting\n"); |
1855 | break; | |
1856 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ | |
a47dddd7 | 1857 | cpu_abort(cs, "Doorbell critical interrupt while in user mode. " |
e1833e1f JM |
1858 | "Aborting\n"); |
1859 | break; | |
1860 | case POWERPC_EXCP_RESET: /* System reset exception */ | |
a47dddd7 | 1861 | cpu_abort(cs, "Reset interrupt while in user mode. " |
e1833e1f JM |
1862 | "Aborting\n"); |
1863 | break; | |
e1833e1f | 1864 | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
a47dddd7 | 1865 | cpu_abort(cs, "Data segment exception while in user mode. " |
e1833e1f JM |
1866 | "Aborting\n"); |
1867 | break; | |
1868 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
a47dddd7 | 1869 | cpu_abort(cs, "Instruction segment exception " |
e1833e1f JM |
1870 | "while in user mode. Aborting\n"); |
1871 | break; | |
e85e7c6e | 1872 | /* PowerPC 64 with hypervisor mode support */ |
e1833e1f | 1873 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
a47dddd7 | 1874 | cpu_abort(cs, "Hypervisor decrementer interrupt " |
e1833e1f JM |
1875 | "while in user mode. Aborting\n"); |
1876 | break; | |
e1833e1f JM |
1877 | case POWERPC_EXCP_TRACE: /* Trace exception */ |
1878 | /* Nothing to do: | |
1879 | * we use this exception to emulate step-by-step execution mode. | |
1880 | */ | |
1881 | break; | |
e85e7c6e | 1882 | /* PowerPC 64 with hypervisor mode support */ |
e1833e1f | 1883 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
a47dddd7 | 1884 | cpu_abort(cs, "Hypervisor data storage exception " |
e1833e1f JM |
1885 | "while in user mode. Aborting\n"); |
1886 | break; | |
1887 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ | |
a47dddd7 | 1888 | cpu_abort(cs, "Hypervisor instruction storage exception " |
e1833e1f JM |
1889 | "while in user mode. Aborting\n"); |
1890 | break; | |
1891 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
a47dddd7 | 1892 | cpu_abort(cs, "Hypervisor data segment exception " |
e1833e1f JM |
1893 | "while in user mode. Aborting\n"); |
1894 | break; | |
1895 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ | |
a47dddd7 | 1896 | cpu_abort(cs, "Hypervisor instruction segment exception " |
e1833e1f JM |
1897 | "while in user mode. Aborting\n"); |
1898 | break; | |
e1833e1f JM |
1899 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
1900 | EXCP_DUMP(env, "No Altivec instructions allowed\n"); | |
1901 | info.si_signo = TARGET_SIGILL; | |
1902 | info.si_errno = 0; | |
1903 | info.si_code = TARGET_ILL_COPROC; | |
1904 | info._sifields._sigfault._addr = env->nip - 4; | |
624f7979 | 1905 | queue_signal(env, info.si_signo, &info); |
e1833e1f JM |
1906 | break; |
1907 | case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ | |
a47dddd7 | 1908 | cpu_abort(cs, "Programmable interval timer interrupt " |
e1833e1f JM |
1909 | "while in user mode. Aborting\n"); |
1910 | break; | |
1911 | case POWERPC_EXCP_IO: /* IO error exception */ | |
a47dddd7 | 1912 | cpu_abort(cs, "IO error exception while in user mode. " |
e1833e1f JM |
1913 | "Aborting\n"); |
1914 | break; | |
1915 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
a47dddd7 | 1916 | cpu_abort(cs, "Run mode exception while in user mode. " |
e1833e1f JM |
1917 | "Aborting\n"); |
1918 | break; | |
1919 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
a47dddd7 | 1920 | cpu_abort(cs, "Emulation trap exception not handled\n"); |
e1833e1f JM |
1921 | break; |
1922 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
a47dddd7 | 1923 | cpu_abort(cs, "Instruction fetch TLB exception " |
e1833e1f JM |
1924 | "while in user-mode. Aborting"); |
1925 | break; | |
1926 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
a47dddd7 | 1927 | cpu_abort(cs, "Data load TLB exception while in user-mode. " |
e1833e1f JM |
1928 | "Aborting"); |
1929 | break; | |
1930 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
a47dddd7 | 1931 | cpu_abort(cs, "Data store TLB exception while in user-mode. " |
e1833e1f JM |
1932 | "Aborting"); |
1933 | break; | |
1934 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
a47dddd7 | 1935 | cpu_abort(cs, "Floating-point assist exception not handled\n"); |
e1833e1f JM |
1936 | break; |
1937 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ | |
a47dddd7 | 1938 | cpu_abort(cs, "Instruction address breakpoint exception " |
e1833e1f JM |
1939 | "not handled\n"); |
1940 | break; | |
1941 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
a47dddd7 | 1942 | cpu_abort(cs, "System management interrupt while in user mode. " |
e1833e1f JM |
1943 | "Aborting\n"); |
1944 | break; | |
1945 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
a47dddd7 | 1946 | cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " |
e1833e1f JM |
1947 | "Aborting\n"); |
1948 | break; | |
1949 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ | |
a47dddd7 | 1950 | cpu_abort(cs, "Performance monitor exception not handled\n"); |
e1833e1f JM |
1951 | break; |
1952 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
a47dddd7 | 1953 | cpu_abort(cs, "Vector assist exception not handled\n"); |
e1833e1f JM |
1954 | break; |
1955 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
a47dddd7 | 1956 | cpu_abort(cs, "Soft patch exception not handled\n"); |
e1833e1f JM |
1957 | break; |
1958 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
a47dddd7 | 1959 | cpu_abort(cs, "Maintenance exception while in user mode. " |
e1833e1f JM |
1960 | "Aborting\n"); |
1961 | break; | |
1962 | case POWERPC_EXCP_STOP: /* stop translation */ | |
1963 | /* We did invalidate the instruction cache. Go on */ | |
1964 | break; | |
1965 | case POWERPC_EXCP_BRANCH: /* branch instruction: */ | |
1966 | /* We just stopped because of a branch. Go on */ | |
1967 | break; | |
1968 | case POWERPC_EXCP_SYSCALL_USER: | |
1969 | /* system call in user-mode emulation */ | |
1970 | /* WARNING: | |
1971 | * PPC ABI uses overflow flag in cr0 to signal an error | |
1972 | * in syscalls. | |
1973 | */ | |
e1833e1f JM |
1974 | env->crf[0] &= ~0x1; |
1975 | ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], | |
1976 | env->gpr[5], env->gpr[6], env->gpr[7], | |
5945cfcb | 1977 | env->gpr[8], 0, 0); |
9e0e2f96 | 1978 | if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { |
bcd4933a NF |
1979 | /* Returning from a successful sigreturn syscall. |
1980 | Avoid corrupting register state. */ | |
1981 | break; | |
1982 | } | |
9e0e2f96 | 1983 | if (ret > (target_ulong)(-515)) { |
e1833e1f JM |
1984 | env->crf[0] |= 0x1; |
1985 | ret = -ret; | |
61190b14 | 1986 | } |
e1833e1f | 1987 | env->gpr[3] = ret; |
e1833e1f | 1988 | break; |
56f066bb NF |
1989 | case POWERPC_EXCP_STCX: |
1990 | if (do_store_exclusive(env)) { | |
1991 | info.si_signo = TARGET_SIGSEGV; | |
1992 | info.si_errno = 0; | |
1993 | info.si_code = TARGET_SEGV_MAPERR; | |
1994 | info._sifields._sigfault._addr = env->nip; | |
1995 | queue_signal(env, info.si_signo, &info); | |
1996 | } | |
1997 | break; | |
71f75756 AJ |
1998 | case EXCP_DEBUG: |
1999 | { | |
2000 | int sig; | |
2001 | ||
db6b81d4 | 2002 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
71f75756 AJ |
2003 | if (sig) { |
2004 | info.si_signo = sig; | |
2005 | info.si_errno = 0; | |
2006 | info.si_code = TARGET_TRAP_BRKPT; | |
2007 | queue_signal(env, info.si_signo, &info); | |
2008 | } | |
2009 | } | |
2010 | break; | |
56ba31ff JM |
2011 | case EXCP_INTERRUPT: |
2012 | /* just indicate that signals should be handled asap */ | |
2013 | break; | |
e1833e1f | 2014 | default: |
a47dddd7 | 2015 | cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr); |
e1833e1f | 2016 | break; |
67867308 FB |
2017 | } |
2018 | process_pending_signals(env); | |
2019 | } | |
2020 | } | |
2021 | #endif | |
2022 | ||
048f6b4d FB |
2023 | #ifdef TARGET_MIPS |
2024 | ||
ff4f7382 RH |
2025 | # ifdef TARGET_ABI_MIPSO32 |
2026 | # define MIPS_SYS(name, args) args, | |
048f6b4d | 2027 | static const uint8_t mips_syscall_args[] = { |
29fb0f25 | 2028 | MIPS_SYS(sys_syscall , 8) /* 4000 */ |
048f6b4d FB |
2029 | MIPS_SYS(sys_exit , 1) |
2030 | MIPS_SYS(sys_fork , 0) | |
2031 | MIPS_SYS(sys_read , 3) | |
2032 | MIPS_SYS(sys_write , 3) | |
2033 | MIPS_SYS(sys_open , 3) /* 4005 */ | |
2034 | MIPS_SYS(sys_close , 1) | |
2035 | MIPS_SYS(sys_waitpid , 3) | |
2036 | MIPS_SYS(sys_creat , 2) | |
2037 | MIPS_SYS(sys_link , 2) | |
2038 | MIPS_SYS(sys_unlink , 1) /* 4010 */ | |
2039 | MIPS_SYS(sys_execve , 0) | |
2040 | MIPS_SYS(sys_chdir , 1) | |
2041 | MIPS_SYS(sys_time , 1) | |
2042 | MIPS_SYS(sys_mknod , 3) | |
2043 | MIPS_SYS(sys_chmod , 2) /* 4015 */ | |
2044 | MIPS_SYS(sys_lchown , 3) | |
2045 | MIPS_SYS(sys_ni_syscall , 0) | |
2046 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */ | |
2047 | MIPS_SYS(sys_lseek , 3) | |
2048 | MIPS_SYS(sys_getpid , 0) /* 4020 */ | |
2049 | MIPS_SYS(sys_mount , 5) | |
868e34d7 | 2050 | MIPS_SYS(sys_umount , 1) |
048f6b4d FB |
2051 | MIPS_SYS(sys_setuid , 1) |
2052 | MIPS_SYS(sys_getuid , 0) | |
2053 | MIPS_SYS(sys_stime , 1) /* 4025 */ | |
2054 | MIPS_SYS(sys_ptrace , 4) | |
2055 | MIPS_SYS(sys_alarm , 1) | |
2056 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */ | |
2057 | MIPS_SYS(sys_pause , 0) | |
2058 | MIPS_SYS(sys_utime , 2) /* 4030 */ | |
2059 | MIPS_SYS(sys_ni_syscall , 0) | |
2060 | MIPS_SYS(sys_ni_syscall , 0) | |
2061 | MIPS_SYS(sys_access , 2) | |
2062 | MIPS_SYS(sys_nice , 1) | |
2063 | MIPS_SYS(sys_ni_syscall , 0) /* 4035 */ | |
2064 | MIPS_SYS(sys_sync , 0) | |
2065 | MIPS_SYS(sys_kill , 2) | |
2066 | MIPS_SYS(sys_rename , 2) | |
2067 | MIPS_SYS(sys_mkdir , 2) | |
2068 | MIPS_SYS(sys_rmdir , 1) /* 4040 */ | |
2069 | MIPS_SYS(sys_dup , 1) | |
2070 | MIPS_SYS(sys_pipe , 0) | |
2071 | MIPS_SYS(sys_times , 1) | |
2072 | MIPS_SYS(sys_ni_syscall , 0) | |
2073 | MIPS_SYS(sys_brk , 1) /* 4045 */ | |
2074 | MIPS_SYS(sys_setgid , 1) | |
2075 | MIPS_SYS(sys_getgid , 0) | |
2076 | MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */ | |
2077 | MIPS_SYS(sys_geteuid , 0) | |
2078 | MIPS_SYS(sys_getegid , 0) /* 4050 */ | |
2079 | MIPS_SYS(sys_acct , 0) | |
868e34d7 | 2080 | MIPS_SYS(sys_umount2 , 2) |
048f6b4d FB |
2081 | MIPS_SYS(sys_ni_syscall , 0) |
2082 | MIPS_SYS(sys_ioctl , 3) | |
2083 | MIPS_SYS(sys_fcntl , 3) /* 4055 */ | |
2084 | MIPS_SYS(sys_ni_syscall , 2) | |
2085 | MIPS_SYS(sys_setpgid , 2) | |
2086 | MIPS_SYS(sys_ni_syscall , 0) | |
2087 | MIPS_SYS(sys_olduname , 1) | |
2088 | MIPS_SYS(sys_umask , 1) /* 4060 */ | |
2089 | MIPS_SYS(sys_chroot , 1) | |
2090 | MIPS_SYS(sys_ustat , 2) | |
2091 | MIPS_SYS(sys_dup2 , 2) | |
2092 | MIPS_SYS(sys_getppid , 0) | |
2093 | MIPS_SYS(sys_getpgrp , 0) /* 4065 */ | |
2094 | MIPS_SYS(sys_setsid , 0) | |
2095 | MIPS_SYS(sys_sigaction , 3) | |
2096 | MIPS_SYS(sys_sgetmask , 0) | |
2097 | MIPS_SYS(sys_ssetmask , 1) | |
2098 | MIPS_SYS(sys_setreuid , 2) /* 4070 */ | |
2099 | MIPS_SYS(sys_setregid , 2) | |
2100 | MIPS_SYS(sys_sigsuspend , 0) | |
2101 | MIPS_SYS(sys_sigpending , 1) | |
2102 | MIPS_SYS(sys_sethostname , 2) | |
2103 | MIPS_SYS(sys_setrlimit , 2) /* 4075 */ | |
2104 | MIPS_SYS(sys_getrlimit , 2) | |
2105 | MIPS_SYS(sys_getrusage , 2) | |
2106 | MIPS_SYS(sys_gettimeofday, 2) | |
2107 | MIPS_SYS(sys_settimeofday, 2) | |
2108 | MIPS_SYS(sys_getgroups , 2) /* 4080 */ | |
2109 | MIPS_SYS(sys_setgroups , 2) | |
2110 | MIPS_SYS(sys_ni_syscall , 0) /* old_select */ | |
2111 | MIPS_SYS(sys_symlink , 2) | |
2112 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */ | |
2113 | MIPS_SYS(sys_readlink , 3) /* 4085 */ | |
2114 | MIPS_SYS(sys_uselib , 1) | |
2115 | MIPS_SYS(sys_swapon , 2) | |
2116 | MIPS_SYS(sys_reboot , 3) | |
2117 | MIPS_SYS(old_readdir , 3) | |
2118 | MIPS_SYS(old_mmap , 6) /* 4090 */ | |
2119 | MIPS_SYS(sys_munmap , 2) | |
2120 | MIPS_SYS(sys_truncate , 2) | |
2121 | MIPS_SYS(sys_ftruncate , 2) | |
2122 | MIPS_SYS(sys_fchmod , 2) | |
2123 | MIPS_SYS(sys_fchown , 3) /* 4095 */ | |
2124 | MIPS_SYS(sys_getpriority , 2) | |
2125 | MIPS_SYS(sys_setpriority , 3) | |
2126 | MIPS_SYS(sys_ni_syscall , 0) | |
2127 | MIPS_SYS(sys_statfs , 2) | |
2128 | MIPS_SYS(sys_fstatfs , 2) /* 4100 */ | |
2129 | MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */ | |
2130 | MIPS_SYS(sys_socketcall , 2) | |
2131 | MIPS_SYS(sys_syslog , 3) | |
2132 | MIPS_SYS(sys_setitimer , 3) | |
2133 | MIPS_SYS(sys_getitimer , 2) /* 4105 */ | |
2134 | MIPS_SYS(sys_newstat , 2) | |
2135 | MIPS_SYS(sys_newlstat , 2) | |
2136 | MIPS_SYS(sys_newfstat , 2) | |
2137 | MIPS_SYS(sys_uname , 1) | |
2138 | MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */ | |
2139 | MIPS_SYS(sys_vhangup , 0) | |
2140 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */ | |
2141 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */ | |
2142 | MIPS_SYS(sys_wait4 , 4) | |
2143 | MIPS_SYS(sys_swapoff , 1) /* 4115 */ | |
2144 | MIPS_SYS(sys_sysinfo , 1) | |
2145 | MIPS_SYS(sys_ipc , 6) | |
2146 | MIPS_SYS(sys_fsync , 1) | |
2147 | MIPS_SYS(sys_sigreturn , 0) | |
18113962 | 2148 | MIPS_SYS(sys_clone , 6) /* 4120 */ |
048f6b4d FB |
2149 | MIPS_SYS(sys_setdomainname, 2) |
2150 | MIPS_SYS(sys_newuname , 1) | |
2151 | MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */ | |
2152 | MIPS_SYS(sys_adjtimex , 1) | |
2153 | MIPS_SYS(sys_mprotect , 3) /* 4125 */ | |
2154 | MIPS_SYS(sys_sigprocmask , 3) | |
2155 | MIPS_SYS(sys_ni_syscall , 0) /* was create_module */ | |
2156 | MIPS_SYS(sys_init_module , 5) | |
2157 | MIPS_SYS(sys_delete_module, 1) | |
2158 | MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */ | |
2159 | MIPS_SYS(sys_quotactl , 0) | |
2160 | MIPS_SYS(sys_getpgid , 1) | |
2161 | MIPS_SYS(sys_fchdir , 1) | |
2162 | MIPS_SYS(sys_bdflush , 2) | |
2163 | MIPS_SYS(sys_sysfs , 3) /* 4135 */ | |
2164 | MIPS_SYS(sys_personality , 1) | |
2165 | MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */ | |
2166 | MIPS_SYS(sys_setfsuid , 1) | |
2167 | MIPS_SYS(sys_setfsgid , 1) | |
2168 | MIPS_SYS(sys_llseek , 5) /* 4140 */ | |
2169 | MIPS_SYS(sys_getdents , 3) | |
2170 | MIPS_SYS(sys_select , 5) | |
2171 | MIPS_SYS(sys_flock , 2) | |
2172 | MIPS_SYS(sys_msync , 3) | |
2173 | MIPS_SYS(sys_readv , 3) /* 4145 */ | |
2174 | MIPS_SYS(sys_writev , 3) | |
2175 | MIPS_SYS(sys_cacheflush , 3) | |
2176 | MIPS_SYS(sys_cachectl , 3) | |
2177 | MIPS_SYS(sys_sysmips , 4) | |
2178 | MIPS_SYS(sys_ni_syscall , 0) /* 4150 */ | |
2179 | MIPS_SYS(sys_getsid , 1) | |
2180 | MIPS_SYS(sys_fdatasync , 0) | |
2181 | MIPS_SYS(sys_sysctl , 1) | |
2182 | MIPS_SYS(sys_mlock , 2) | |
2183 | MIPS_SYS(sys_munlock , 2) /* 4155 */ | |
2184 | MIPS_SYS(sys_mlockall , 1) | |
2185 | MIPS_SYS(sys_munlockall , 0) | |
2186 | MIPS_SYS(sys_sched_setparam, 2) | |
2187 | MIPS_SYS(sys_sched_getparam, 2) | |
2188 | MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */ | |
2189 | MIPS_SYS(sys_sched_getscheduler, 1) | |
2190 | MIPS_SYS(sys_sched_yield , 0) | |
2191 | MIPS_SYS(sys_sched_get_priority_max, 1) | |
2192 | MIPS_SYS(sys_sched_get_priority_min, 1) | |
2193 | MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */ | |
2194 | MIPS_SYS(sys_nanosleep, 2) | |
b0932e06 | 2195 | MIPS_SYS(sys_mremap , 5) |
048f6b4d FB |
2196 | MIPS_SYS(sys_accept , 3) |
2197 | MIPS_SYS(sys_bind , 3) | |
2198 | MIPS_SYS(sys_connect , 3) /* 4170 */ | |
2199 | MIPS_SYS(sys_getpeername , 3) | |
2200 | MIPS_SYS(sys_getsockname , 3) | |
2201 | MIPS_SYS(sys_getsockopt , 5) | |
2202 | MIPS_SYS(sys_listen , 2) | |
2203 | MIPS_SYS(sys_recv , 4) /* 4175 */ | |
2204 | MIPS_SYS(sys_recvfrom , 6) | |
2205 | MIPS_SYS(sys_recvmsg , 3) | |
2206 | MIPS_SYS(sys_send , 4) | |
2207 | MIPS_SYS(sys_sendmsg , 3) | |
2208 | MIPS_SYS(sys_sendto , 6) /* 4180 */ | |
2209 | MIPS_SYS(sys_setsockopt , 5) | |
2210 | MIPS_SYS(sys_shutdown , 2) | |
2211 | MIPS_SYS(sys_socket , 3) | |
2212 | MIPS_SYS(sys_socketpair , 4) | |
2213 | MIPS_SYS(sys_setresuid , 3) /* 4185 */ | |
2214 | MIPS_SYS(sys_getresuid , 3) | |
2215 | MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */ | |
2216 | MIPS_SYS(sys_poll , 3) | |
2217 | MIPS_SYS(sys_nfsservctl , 3) | |
2218 | MIPS_SYS(sys_setresgid , 3) /* 4190 */ | |
2219 | MIPS_SYS(sys_getresgid , 3) | |
2220 | MIPS_SYS(sys_prctl , 5) | |
2221 | MIPS_SYS(sys_rt_sigreturn, 0) | |
2222 | MIPS_SYS(sys_rt_sigaction, 4) | |
2223 | MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */ | |
2224 | MIPS_SYS(sys_rt_sigpending, 2) | |
2225 | MIPS_SYS(sys_rt_sigtimedwait, 4) | |
2226 | MIPS_SYS(sys_rt_sigqueueinfo, 3) | |
2227 | MIPS_SYS(sys_rt_sigsuspend, 0) | |
2228 | MIPS_SYS(sys_pread64 , 6) /* 4200 */ | |
2229 | MIPS_SYS(sys_pwrite64 , 6) | |
2230 | MIPS_SYS(sys_chown , 3) | |
2231 | MIPS_SYS(sys_getcwd , 2) | |
2232 | MIPS_SYS(sys_capget , 2) | |
2233 | MIPS_SYS(sys_capset , 2) /* 4205 */ | |
053ebb27 | 2234 | MIPS_SYS(sys_sigaltstack , 2) |
048f6b4d FB |
2235 | MIPS_SYS(sys_sendfile , 4) |
2236 | MIPS_SYS(sys_ni_syscall , 0) | |
2237 | MIPS_SYS(sys_ni_syscall , 0) | |
2238 | MIPS_SYS(sys_mmap2 , 6) /* 4210 */ | |
2239 | MIPS_SYS(sys_truncate64 , 4) | |
2240 | MIPS_SYS(sys_ftruncate64 , 4) | |
2241 | MIPS_SYS(sys_stat64 , 2) | |
2242 | MIPS_SYS(sys_lstat64 , 2) | |
2243 | MIPS_SYS(sys_fstat64 , 2) /* 4215 */ | |
2244 | MIPS_SYS(sys_pivot_root , 2) | |
2245 | MIPS_SYS(sys_mincore , 3) | |
2246 | MIPS_SYS(sys_madvise , 3) | |
2247 | MIPS_SYS(sys_getdents64 , 3) | |
2248 | MIPS_SYS(sys_fcntl64 , 3) /* 4220 */ | |
2249 | MIPS_SYS(sys_ni_syscall , 0) | |
2250 | MIPS_SYS(sys_gettid , 0) | |
2251 | MIPS_SYS(sys_readahead , 5) | |
2252 | MIPS_SYS(sys_setxattr , 5) | |
2253 | MIPS_SYS(sys_lsetxattr , 5) /* 4225 */ | |
2254 | MIPS_SYS(sys_fsetxattr , 5) | |
2255 | MIPS_SYS(sys_getxattr , 4) | |
2256 | MIPS_SYS(sys_lgetxattr , 4) | |
2257 | MIPS_SYS(sys_fgetxattr , 4) | |
2258 | MIPS_SYS(sys_listxattr , 3) /* 4230 */ | |
2259 | MIPS_SYS(sys_llistxattr , 3) | |
2260 | MIPS_SYS(sys_flistxattr , 3) | |
2261 | MIPS_SYS(sys_removexattr , 2) | |
2262 | MIPS_SYS(sys_lremovexattr, 2) | |
2263 | MIPS_SYS(sys_fremovexattr, 2) /* 4235 */ | |
2264 | MIPS_SYS(sys_tkill , 2) | |
2265 | MIPS_SYS(sys_sendfile64 , 5) | |
43be1343 | 2266 | MIPS_SYS(sys_futex , 6) |
048f6b4d FB |
2267 | MIPS_SYS(sys_sched_setaffinity, 3) |
2268 | MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */ | |
2269 | MIPS_SYS(sys_io_setup , 2) | |
2270 | MIPS_SYS(sys_io_destroy , 1) | |
2271 | MIPS_SYS(sys_io_getevents, 5) | |
2272 | MIPS_SYS(sys_io_submit , 3) | |
2273 | MIPS_SYS(sys_io_cancel , 3) /* 4245 */ | |
2274 | MIPS_SYS(sys_exit_group , 1) | |
2275 | MIPS_SYS(sys_lookup_dcookie, 3) | |
2276 | MIPS_SYS(sys_epoll_create, 1) | |
2277 | MIPS_SYS(sys_epoll_ctl , 4) | |
2278 | MIPS_SYS(sys_epoll_wait , 3) /* 4250 */ | |
2279 | MIPS_SYS(sys_remap_file_pages, 5) | |
2280 | MIPS_SYS(sys_set_tid_address, 1) | |
2281 | MIPS_SYS(sys_restart_syscall, 0) | |
2282 | MIPS_SYS(sys_fadvise64_64, 7) | |
2283 | MIPS_SYS(sys_statfs64 , 3) /* 4255 */ | |
2284 | MIPS_SYS(sys_fstatfs64 , 2) | |
2285 | MIPS_SYS(sys_timer_create, 3) | |
2286 | MIPS_SYS(sys_timer_settime, 4) | |
2287 | MIPS_SYS(sys_timer_gettime, 2) | |
2288 | MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */ | |
2289 | MIPS_SYS(sys_timer_delete, 1) | |
2290 | MIPS_SYS(sys_clock_settime, 2) | |
2291 | MIPS_SYS(sys_clock_gettime, 2) | |
2292 | MIPS_SYS(sys_clock_getres, 2) | |
2293 | MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */ | |
2294 | MIPS_SYS(sys_tgkill , 3) | |
2295 | MIPS_SYS(sys_utimes , 2) | |
2296 | MIPS_SYS(sys_mbind , 4) | |
2297 | MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */ | |
2298 | MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */ | |
2299 | MIPS_SYS(sys_mq_open , 4) | |
2300 | MIPS_SYS(sys_mq_unlink , 1) | |
2301 | MIPS_SYS(sys_mq_timedsend, 5) | |
2302 | MIPS_SYS(sys_mq_timedreceive, 5) | |
2303 | MIPS_SYS(sys_mq_notify , 2) /* 4275 */ | |
2304 | MIPS_SYS(sys_mq_getsetattr, 3) | |
2305 | MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */ | |
2306 | MIPS_SYS(sys_waitid , 4) | |
2307 | MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */ | |
2308 | MIPS_SYS(sys_add_key , 5) | |
388bb21a | 2309 | MIPS_SYS(sys_request_key, 4) |
048f6b4d | 2310 | MIPS_SYS(sys_keyctl , 5) |
6f5b89a0 | 2311 | MIPS_SYS(sys_set_thread_area, 1) |
388bb21a TS |
2312 | MIPS_SYS(sys_inotify_init, 0) |
2313 | MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */ | |
2314 | MIPS_SYS(sys_inotify_rm_watch, 2) | |
2315 | MIPS_SYS(sys_migrate_pages, 4) | |
2316 | MIPS_SYS(sys_openat, 4) | |
2317 | MIPS_SYS(sys_mkdirat, 3) | |
2318 | MIPS_SYS(sys_mknodat, 4) /* 4290 */ | |
2319 | MIPS_SYS(sys_fchownat, 5) | |
2320 | MIPS_SYS(sys_futimesat, 3) | |
2321 | MIPS_SYS(sys_fstatat64, 4) | |
2322 | MIPS_SYS(sys_unlinkat, 3) | |
2323 | MIPS_SYS(sys_renameat, 4) /* 4295 */ | |
2324 | MIPS_SYS(sys_linkat, 5) | |
2325 | MIPS_SYS(sys_symlinkat, 3) | |
2326 | MIPS_SYS(sys_readlinkat, 4) | |
2327 | MIPS_SYS(sys_fchmodat, 3) | |
2328 | MIPS_SYS(sys_faccessat, 3) /* 4300 */ | |
2329 | MIPS_SYS(sys_pselect6, 6) | |
2330 | MIPS_SYS(sys_ppoll, 5) | |
2331 | MIPS_SYS(sys_unshare, 1) | |
b0932e06 | 2332 | MIPS_SYS(sys_splice, 6) |
388bb21a TS |
2333 | MIPS_SYS(sys_sync_file_range, 7) /* 4305 */ |
2334 | MIPS_SYS(sys_tee, 4) | |
2335 | MIPS_SYS(sys_vmsplice, 4) | |
2336 | MIPS_SYS(sys_move_pages, 6) | |
2337 | MIPS_SYS(sys_set_robust_list, 2) | |
2338 | MIPS_SYS(sys_get_robust_list, 3) /* 4310 */ | |
2339 | MIPS_SYS(sys_kexec_load, 4) | |
2340 | MIPS_SYS(sys_getcpu, 3) | |
2341 | MIPS_SYS(sys_epoll_pwait, 6) | |
2342 | MIPS_SYS(sys_ioprio_set, 3) | |
2343 | MIPS_SYS(sys_ioprio_get, 2) | |
d979e8eb PM |
2344 | MIPS_SYS(sys_utimensat, 4) |
2345 | MIPS_SYS(sys_signalfd, 3) | |
2346 | MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */ | |
2347 | MIPS_SYS(sys_eventfd, 1) | |
2348 | MIPS_SYS(sys_fallocate, 6) /* 4320 */ | |
2349 | MIPS_SYS(sys_timerfd_create, 2) | |
2350 | MIPS_SYS(sys_timerfd_gettime, 2) | |
2351 | MIPS_SYS(sys_timerfd_settime, 4) | |
2352 | MIPS_SYS(sys_signalfd4, 4) | |
2353 | MIPS_SYS(sys_eventfd2, 2) /* 4325 */ | |
2354 | MIPS_SYS(sys_epoll_create1, 1) | |
2355 | MIPS_SYS(sys_dup3, 3) | |
2356 | MIPS_SYS(sys_pipe2, 2) | |
2357 | MIPS_SYS(sys_inotify_init1, 1) | |
2358 | MIPS_SYS(sys_preadv, 6) /* 4330 */ | |
2359 | MIPS_SYS(sys_pwritev, 6) | |
2360 | MIPS_SYS(sys_rt_tgsigqueueinfo, 4) | |
2361 | MIPS_SYS(sys_perf_event_open, 5) | |
2362 | MIPS_SYS(sys_accept4, 4) | |
2363 | MIPS_SYS(sys_recvmmsg, 5) /* 4335 */ | |
2364 | MIPS_SYS(sys_fanotify_init, 2) | |
2365 | MIPS_SYS(sys_fanotify_mark, 6) | |
2366 | MIPS_SYS(sys_prlimit64, 4) | |
2367 | MIPS_SYS(sys_name_to_handle_at, 5) | |
2368 | MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */ | |
2369 | MIPS_SYS(sys_clock_adjtime, 2) | |
2370 | MIPS_SYS(sys_syncfs, 1) | |
048f6b4d | 2371 | }; |
ff4f7382 RH |
2372 | # undef MIPS_SYS |
2373 | # endif /* O32 */ | |
048f6b4d | 2374 | |
590bc601 PB |
2375 | static int do_store_exclusive(CPUMIPSState *env) |
2376 | { | |
2377 | target_ulong addr; | |
2378 | target_ulong page_addr; | |
2379 | target_ulong val; | |
2380 | int flags; | |
2381 | int segv = 0; | |
2382 | int reg; | |
2383 | int d; | |
2384 | ||
5499b6ff | 2385 | addr = env->lladdr; |
590bc601 PB |
2386 | page_addr = addr & TARGET_PAGE_MASK; |
2387 | start_exclusive(); | |
2388 | mmap_lock(); | |
2389 | flags = page_get_flags(page_addr); | |
2390 | if ((flags & PAGE_READ) == 0) { | |
2391 | segv = 1; | |
2392 | } else { | |
2393 | reg = env->llreg & 0x1f; | |
2394 | d = (env->llreg & 0x20) != 0; | |
2395 | if (d) { | |
2396 | segv = get_user_s64(val, addr); | |
2397 | } else { | |
2398 | segv = get_user_s32(val, addr); | |
2399 | } | |
2400 | if (!segv) { | |
2401 | if (val != env->llval) { | |
2402 | env->active_tc.gpr[reg] = 0; | |
2403 | } else { | |
2404 | if (d) { | |
2405 | segv = put_user_u64(env->llnewval, addr); | |
2406 | } else { | |
2407 | segv = put_user_u32(env->llnewval, addr); | |
2408 | } | |
2409 | if (!segv) { | |
2410 | env->active_tc.gpr[reg] = 1; | |
2411 | } | |
2412 | } | |
2413 | } | |
2414 | } | |
5499b6ff | 2415 | env->lladdr = -1; |
590bc601 PB |
2416 | if (!segv) { |
2417 | env->active_tc.PC += 4; | |
2418 | } | |
2419 | mmap_unlock(); | |
2420 | end_exclusive(); | |
2421 | return segv; | |
2422 | } | |
2423 | ||
54b2f42c MI |
2424 | /* Break codes */ |
2425 | enum { | |
2426 | BRK_OVERFLOW = 6, | |
2427 | BRK_DIVZERO = 7 | |
2428 | }; | |
2429 | ||
2430 | static int do_break(CPUMIPSState *env, target_siginfo_t *info, | |
2431 | unsigned int code) | |
2432 | { | |
2433 | int ret = -1; | |
2434 | ||
2435 | switch (code) { | |
2436 | case BRK_OVERFLOW: | |
2437 | case BRK_DIVZERO: | |
2438 | info->si_signo = TARGET_SIGFPE; | |
2439 | info->si_errno = 0; | |
2440 | info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV; | |
2441 | queue_signal(env, info->si_signo, &*info); | |
2442 | ret = 0; | |
2443 | break; | |
2444 | default: | |
b51910ba PJ |
2445 | info->si_signo = TARGET_SIGTRAP; |
2446 | info->si_errno = 0; | |
2447 | queue_signal(env, info->si_signo, &*info); | |
2448 | ret = 0; | |
54b2f42c MI |
2449 | break; |
2450 | } | |
2451 | ||
2452 | return ret; | |
2453 | } | |
2454 | ||
048f6b4d FB |
2455 | void cpu_loop(CPUMIPSState *env) |
2456 | { | |
0315c31c | 2457 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
c227f099 | 2458 | target_siginfo_t info; |
ff4f7382 RH |
2459 | int trapnr; |
2460 | abi_long ret; | |
2461 | # ifdef TARGET_ABI_MIPSO32 | |
048f6b4d | 2462 | unsigned int syscall_num; |
ff4f7382 | 2463 | # endif |
048f6b4d FB |
2464 | |
2465 | for(;;) { | |
0315c31c | 2466 | cpu_exec_start(cs); |
ea3e9847 | 2467 | trapnr = cpu_mips_exec(cs); |
0315c31c | 2468 | cpu_exec_end(cs); |
048f6b4d FB |
2469 | switch(trapnr) { |
2470 | case EXCP_SYSCALL: | |
b5dc7732 | 2471 | env->active_tc.PC += 4; |
ff4f7382 RH |
2472 | # ifdef TARGET_ABI_MIPSO32 |
2473 | syscall_num = env->active_tc.gpr[2] - 4000; | |
388bb21a | 2474 | if (syscall_num >= sizeof(mips_syscall_args)) { |
7c2f6157 | 2475 | ret = -TARGET_ENOSYS; |
388bb21a TS |
2476 | } else { |
2477 | int nb_args; | |
992f48a0 BS |
2478 | abi_ulong sp_reg; |
2479 | abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0; | |
388bb21a TS |
2480 | |
2481 | nb_args = mips_syscall_args[syscall_num]; | |
b5dc7732 | 2482 | sp_reg = env->active_tc.gpr[29]; |
388bb21a TS |
2483 | switch (nb_args) { |
2484 | /* these arguments are taken from the stack */ | |
94c19610 ACH |
2485 | case 8: |
2486 | if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { | |
2487 | goto done_syscall; | |
2488 | } | |
2489 | case 7: | |
2490 | if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { | |
2491 | goto done_syscall; | |
2492 | } | |
2493 | case 6: | |
2494 | if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { | |
2495 | goto done_syscall; | |
2496 | } | |
2497 | case 5: | |
2498 | if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) { | |
2499 | goto done_syscall; | |
2500 | } | |
388bb21a TS |
2501 | default: |
2502 | break; | |
048f6b4d | 2503 | } |
b5dc7732 TS |
2504 | ret = do_syscall(env, env->active_tc.gpr[2], |
2505 | env->active_tc.gpr[4], | |
2506 | env->active_tc.gpr[5], | |
2507 | env->active_tc.gpr[6], | |
2508 | env->active_tc.gpr[7], | |
5945cfcb | 2509 | arg5, arg6, arg7, arg8); |
388bb21a | 2510 | } |
94c19610 | 2511 | done_syscall: |
ff4f7382 RH |
2512 | # else |
2513 | ret = do_syscall(env, env->active_tc.gpr[2], | |
2514 | env->active_tc.gpr[4], env->active_tc.gpr[5], | |
2515 | env->active_tc.gpr[6], env->active_tc.gpr[7], | |
2516 | env->active_tc.gpr[8], env->active_tc.gpr[9], | |
2517 | env->active_tc.gpr[10], env->active_tc.gpr[11]); | |
2518 | # endif /* O32 */ | |
0b1bcb00 PB |
2519 | if (ret == -TARGET_QEMU_ESIGRETURN) { |
2520 | /* Returning from a successful sigreturn syscall. | |
2521 | Avoid clobbering register state. */ | |
2522 | break; | |
2523 | } | |
ff4f7382 | 2524 | if ((abi_ulong)ret >= (abi_ulong)-1133) { |
b5dc7732 | 2525 | env->active_tc.gpr[7] = 1; /* error flag */ |
388bb21a TS |
2526 | ret = -ret; |
2527 | } else { | |
b5dc7732 | 2528 | env->active_tc.gpr[7] = 0; /* error flag */ |
048f6b4d | 2529 | } |
b5dc7732 | 2530 | env->active_tc.gpr[2] = ret; |
048f6b4d | 2531 | break; |
ca7c2b1b TS |
2532 | case EXCP_TLBL: |
2533 | case EXCP_TLBS: | |
e6e5bd2d WT |
2534 | case EXCP_AdEL: |
2535 | case EXCP_AdES: | |
e4474235 PB |
2536 | info.si_signo = TARGET_SIGSEGV; |
2537 | info.si_errno = 0; | |
2538 | /* XXX: check env->error_code */ | |
2539 | info.si_code = TARGET_SEGV_MAPERR; | |
2540 | info._sifields._sigfault._addr = env->CP0_BadVAddr; | |
2541 | queue_signal(env, info.si_signo, &info); | |
2542 | break; | |
6900e84b | 2543 | case EXCP_CpU: |
048f6b4d | 2544 | case EXCP_RI: |
bc1ad2de FB |
2545 | info.si_signo = TARGET_SIGILL; |
2546 | info.si_errno = 0; | |
2547 | info.si_code = 0; | |
624f7979 | 2548 | queue_signal(env, info.si_signo, &info); |
048f6b4d | 2549 | break; |
106ec879 FB |
2550 | case EXCP_INTERRUPT: |
2551 | /* just indicate that signals should be handled asap */ | |
2552 | break; | |
d08b2a28 PB |
2553 | case EXCP_DEBUG: |
2554 | { | |
2555 | int sig; | |
2556 | ||
db6b81d4 | 2557 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
d08b2a28 PB |
2558 | if (sig) |
2559 | { | |
2560 | info.si_signo = sig; | |
2561 | info.si_errno = 0; | |
2562 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2563 | queue_signal(env, info.si_signo, &info); |
d08b2a28 PB |
2564 | } |
2565 | } | |
2566 | break; | |
590bc601 PB |
2567 | case EXCP_SC: |
2568 | if (do_store_exclusive(env)) { | |
2569 | info.si_signo = TARGET_SIGSEGV; | |
2570 | info.si_errno = 0; | |
2571 | info.si_code = TARGET_SEGV_MAPERR; | |
2572 | info._sifields._sigfault._addr = env->active_tc.PC; | |
2573 | queue_signal(env, info.si_signo, &info); | |
2574 | } | |
2575 | break; | |
853c3240 JL |
2576 | case EXCP_DSPDIS: |
2577 | info.si_signo = TARGET_SIGILL; | |
2578 | info.si_errno = 0; | |
2579 | info.si_code = TARGET_ILL_ILLOPC; | |
2580 | queue_signal(env, info.si_signo, &info); | |
2581 | break; | |
54b2f42c MI |
2582 | /* The code below was inspired by the MIPS Linux kernel trap |
2583 | * handling code in arch/mips/kernel/traps.c. | |
2584 | */ | |
2585 | case EXCP_BREAK: | |
2586 | { | |
2587 | abi_ulong trap_instr; | |
2588 | unsigned int code; | |
2589 | ||
a0333817 KCY |
2590 | if (env->hflags & MIPS_HFLAG_M16) { |
2591 | if (env->insn_flags & ASE_MICROMIPS) { | |
2592 | /* microMIPS mode */ | |
1308c464 KCY |
2593 | ret = get_user_u16(trap_instr, env->active_tc.PC); |
2594 | if (ret != 0) { | |
2595 | goto error; | |
2596 | } | |
a0333817 | 2597 | |
1308c464 KCY |
2598 | if ((trap_instr >> 10) == 0x11) { |
2599 | /* 16-bit instruction */ | |
2600 | code = trap_instr & 0xf; | |
2601 | } else { | |
2602 | /* 32-bit instruction */ | |
2603 | abi_ulong instr_lo; | |
2604 | ||
2605 | ret = get_user_u16(instr_lo, | |
2606 | env->active_tc.PC + 2); | |
2607 | if (ret != 0) { | |
2608 | goto error; | |
2609 | } | |
2610 | trap_instr = (trap_instr << 16) | instr_lo; | |
2611 | code = ((trap_instr >> 6) & ((1 << 20) - 1)); | |
2612 | /* Unfortunately, microMIPS also suffers from | |
2613 | the old assembler bug... */ | |
2614 | if (code >= (1 << 10)) { | |
2615 | code >>= 10; | |
2616 | } | |
2617 | } | |
a0333817 KCY |
2618 | } else { |
2619 | /* MIPS16e mode */ | |
2620 | ret = get_user_u16(trap_instr, env->active_tc.PC); | |
2621 | if (ret != 0) { | |
2622 | goto error; | |
2623 | } | |
2624 | code = (trap_instr >> 6) & 0x3f; | |
a0333817 KCY |
2625 | } |
2626 | } else { | |
f01a361b | 2627 | ret = get_user_u32(trap_instr, env->active_tc.PC); |
1308c464 KCY |
2628 | if (ret != 0) { |
2629 | goto error; | |
2630 | } | |
54b2f42c | 2631 | |
1308c464 KCY |
2632 | /* As described in the original Linux kernel code, the |
2633 | * below checks on 'code' are to work around an old | |
2634 | * assembly bug. | |
2635 | */ | |
2636 | code = ((trap_instr >> 6) & ((1 << 20) - 1)); | |
2637 | if (code >= (1 << 10)) { | |
2638 | code >>= 10; | |
2639 | } | |
54b2f42c MI |
2640 | } |
2641 | ||
2642 | if (do_break(env, &info, code) != 0) { | |
2643 | goto error; | |
2644 | } | |
2645 | } | |
2646 | break; | |
2647 | case EXCP_TRAP: | |
2648 | { | |
2649 | abi_ulong trap_instr; | |
2650 | unsigned int code = 0; | |
2651 | ||
a0333817 KCY |
2652 | if (env->hflags & MIPS_HFLAG_M16) { |
2653 | /* microMIPS mode */ | |
2654 | abi_ulong instr[2]; | |
2655 | ||
2656 | ret = get_user_u16(instr[0], env->active_tc.PC) || | |
2657 | get_user_u16(instr[1], env->active_tc.PC + 2); | |
2658 | ||
2659 | trap_instr = (instr[0] << 16) | instr[1]; | |
2660 | } else { | |
f01a361b | 2661 | ret = get_user_u32(trap_instr, env->active_tc.PC); |
a0333817 KCY |
2662 | } |
2663 | ||
54b2f42c MI |
2664 | if (ret != 0) { |
2665 | goto error; | |
2666 | } | |
2667 | ||
2668 | /* The immediate versions don't provide a code. */ | |
2669 | if (!(trap_instr & 0xFC000000)) { | |
a0333817 KCY |
2670 | if (env->hflags & MIPS_HFLAG_M16) { |
2671 | /* microMIPS mode */ | |
2672 | code = ((trap_instr >> 12) & ((1 << 4) - 1)); | |
2673 | } else { | |
2674 | code = ((trap_instr >> 6) & ((1 << 10) - 1)); | |
2675 | } | |
54b2f42c MI |
2676 | } |
2677 | ||
2678 | if (do_break(env, &info, code) != 0) { | |
2679 | goto error; | |
2680 | } | |
2681 | } | |
2682 | break; | |
048f6b4d | 2683 | default: |
54b2f42c | 2684 | error: |
120a9848 | 2685 | EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
048f6b4d FB |
2686 | abort(); |
2687 | } | |
2688 | process_pending_signals(env); | |
2689 | } | |
2690 | } | |
2691 | #endif | |
2692 | ||
d962783e JL |
2693 | #ifdef TARGET_OPENRISC |
2694 | ||
2695 | void cpu_loop(CPUOpenRISCState *env) | |
2696 | { | |
878096ee | 2697 | CPUState *cs = CPU(openrisc_env_get_cpu(env)); |
d962783e JL |
2698 | int trapnr, gdbsig; |
2699 | ||
2700 | for (;;) { | |
b040bc9c | 2701 | cpu_exec_start(cs); |
ea3e9847 | 2702 | trapnr = cpu_openrisc_exec(cs); |
b040bc9c | 2703 | cpu_exec_end(cs); |
d962783e JL |
2704 | gdbsig = 0; |
2705 | ||
2706 | switch (trapnr) { | |
2707 | case EXCP_RESET: | |
120a9848 | 2708 | qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc); |
4d1275c2 | 2709 | exit(EXIT_FAILURE); |
d962783e JL |
2710 | break; |
2711 | case EXCP_BUSERR: | |
120a9848 | 2712 | qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc); |
a86b3c64 | 2713 | gdbsig = TARGET_SIGBUS; |
d962783e JL |
2714 | break; |
2715 | case EXCP_DPF: | |
2716 | case EXCP_IPF: | |
878096ee | 2717 | cpu_dump_state(cs, stderr, fprintf, 0); |
d962783e JL |
2718 | gdbsig = TARGET_SIGSEGV; |
2719 | break; | |
2720 | case EXCP_TICK: | |
120a9848 | 2721 | qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc); |
d962783e JL |
2722 | break; |
2723 | case EXCP_ALIGN: | |
120a9848 | 2724 | qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc); |
a86b3c64 | 2725 | gdbsig = TARGET_SIGBUS; |
d962783e JL |
2726 | break; |
2727 | case EXCP_ILLEGAL: | |
120a9848 | 2728 | qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc); |
a86b3c64 | 2729 | gdbsig = TARGET_SIGILL; |
d962783e JL |
2730 | break; |
2731 | case EXCP_INT: | |
120a9848 | 2732 | qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc); |
d962783e JL |
2733 | break; |
2734 | case EXCP_DTLBMISS: | |
2735 | case EXCP_ITLBMISS: | |
120a9848 | 2736 | qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n"); |
d962783e JL |
2737 | break; |
2738 | case EXCP_RANGE: | |
120a9848 | 2739 | qemu_log_mask(CPU_LOG_INT, "\nRange\n"); |
a86b3c64 | 2740 | gdbsig = TARGET_SIGSEGV; |
d962783e JL |
2741 | break; |
2742 | case EXCP_SYSCALL: | |
2743 | env->pc += 4; /* 0xc00; */ | |
2744 | env->gpr[11] = do_syscall(env, | |
2745 | env->gpr[11], /* return value */ | |
2746 | env->gpr[3], /* r3 - r7 are params */ | |
2747 | env->gpr[4], | |
2748 | env->gpr[5], | |
2749 | env->gpr[6], | |
2750 | env->gpr[7], | |
2751 | env->gpr[8], 0, 0); | |
2752 | break; | |
2753 | case EXCP_FPE: | |
120a9848 | 2754 | qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n"); |
d962783e JL |
2755 | break; |
2756 | case EXCP_TRAP: | |
120a9848 | 2757 | qemu_log_mask(CPU_LOG_INT, "\nTrap\n"); |
a86b3c64 | 2758 | gdbsig = TARGET_SIGTRAP; |
d962783e JL |
2759 | break; |
2760 | case EXCP_NR: | |
120a9848 | 2761 | qemu_log_mask(CPU_LOG_INT, "\nNR\n"); |
d962783e JL |
2762 | break; |
2763 | default: | |
120a9848 | 2764 | EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n", |
d962783e | 2765 | trapnr); |
d962783e JL |
2766 | gdbsig = TARGET_SIGILL; |
2767 | break; | |
2768 | } | |
2769 | if (gdbsig) { | |
db6b81d4 | 2770 | gdb_handlesig(cs, gdbsig); |
d962783e | 2771 | if (gdbsig != TARGET_SIGTRAP) { |
4d1275c2 | 2772 | exit(EXIT_FAILURE); |
d962783e JL |
2773 | } |
2774 | } | |
2775 | ||
2776 | process_pending_signals(env); | |
2777 | } | |
2778 | } | |
2779 | ||
2780 | #endif /* TARGET_OPENRISC */ | |
2781 | ||
fdf9b3e8 | 2782 | #ifdef TARGET_SH4 |
05390248 | 2783 | void cpu_loop(CPUSH4State *env) |
fdf9b3e8 | 2784 | { |
878096ee | 2785 | CPUState *cs = CPU(sh_env_get_cpu(env)); |
fdf9b3e8 | 2786 | int trapnr, ret; |
c227f099 | 2787 | target_siginfo_t info; |
3b46e624 | 2788 | |
fdf9b3e8 | 2789 | while (1) { |
b040bc9c | 2790 | cpu_exec_start(cs); |
ea3e9847 | 2791 | trapnr = cpu_sh4_exec(cs); |
b040bc9c | 2792 | cpu_exec_end(cs); |
3b46e624 | 2793 | |
fdf9b3e8 FB |
2794 | switch (trapnr) { |
2795 | case 0x160: | |
0b6d3ae0 | 2796 | env->pc += 2; |
5fafdf24 TS |
2797 | ret = do_syscall(env, |
2798 | env->gregs[3], | |
2799 | env->gregs[4], | |
2800 | env->gregs[5], | |
2801 | env->gregs[6], | |
2802 | env->gregs[7], | |
2803 | env->gregs[0], | |
5945cfcb PM |
2804 | env->gregs[1], |
2805 | 0, 0); | |
9c2a9ea1 | 2806 | env->gregs[0] = ret; |
fdf9b3e8 | 2807 | break; |
c3b5bc8a TS |
2808 | case EXCP_INTERRUPT: |
2809 | /* just indicate that signals should be handled asap */ | |
2810 | break; | |
355fb23d PB |
2811 | case EXCP_DEBUG: |
2812 | { | |
2813 | int sig; | |
2814 | ||
db6b81d4 | 2815 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
355fb23d PB |
2816 | if (sig) |
2817 | { | |
2818 | info.si_signo = sig; | |
2819 | info.si_errno = 0; | |
2820 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2821 | queue_signal(env, info.si_signo, &info); |
355fb23d PB |
2822 | } |
2823 | } | |
2824 | break; | |
c3b5bc8a TS |
2825 | case 0xa0: |
2826 | case 0xc0: | |
a86b3c64 | 2827 | info.si_signo = TARGET_SIGSEGV; |
c3b5bc8a TS |
2828 | info.si_errno = 0; |
2829 | info.si_code = TARGET_SEGV_MAPERR; | |
2830 | info._sifields._sigfault._addr = env->tea; | |
624f7979 | 2831 | queue_signal(env, info.si_signo, &info); |
c3b5bc8a TS |
2832 | break; |
2833 | ||
fdf9b3e8 FB |
2834 | default: |
2835 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 2836 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 2837 | exit(EXIT_FAILURE); |
fdf9b3e8 FB |
2838 | } |
2839 | process_pending_signals (env); | |
2840 | } | |
2841 | } | |
2842 | #endif | |
2843 | ||
48733d19 | 2844 | #ifdef TARGET_CRIS |
05390248 | 2845 | void cpu_loop(CPUCRISState *env) |
48733d19 | 2846 | { |
878096ee | 2847 | CPUState *cs = CPU(cris_env_get_cpu(env)); |
48733d19 | 2848 | int trapnr, ret; |
c227f099 | 2849 | target_siginfo_t info; |
48733d19 TS |
2850 | |
2851 | while (1) { | |
b040bc9c | 2852 | cpu_exec_start(cs); |
ea3e9847 | 2853 | trapnr = cpu_cris_exec(cs); |
b040bc9c | 2854 | cpu_exec_end(cs); |
48733d19 TS |
2855 | switch (trapnr) { |
2856 | case 0xaa: | |
2857 | { | |
a86b3c64 | 2858 | info.si_signo = TARGET_SIGSEGV; |
48733d19 TS |
2859 | info.si_errno = 0; |
2860 | /* XXX: check env->error_code */ | |
2861 | info.si_code = TARGET_SEGV_MAPERR; | |
e00c1e71 | 2862 | info._sifields._sigfault._addr = env->pregs[PR_EDA]; |
624f7979 | 2863 | queue_signal(env, info.si_signo, &info); |
48733d19 TS |
2864 | } |
2865 | break; | |
b6d3abda EI |
2866 | case EXCP_INTERRUPT: |
2867 | /* just indicate that signals should be handled asap */ | |
2868 | break; | |
48733d19 TS |
2869 | case EXCP_BREAK: |
2870 | ret = do_syscall(env, | |
2871 | env->regs[9], | |
2872 | env->regs[10], | |
2873 | env->regs[11], | |
2874 | env->regs[12], | |
2875 | env->regs[13], | |
2876 | env->pregs[7], | |
5945cfcb PM |
2877 | env->pregs[11], |
2878 | 0, 0); | |
48733d19 | 2879 | env->regs[10] = ret; |
48733d19 TS |
2880 | break; |
2881 | case EXCP_DEBUG: | |
2882 | { | |
2883 | int sig; | |
2884 | ||
db6b81d4 | 2885 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
48733d19 TS |
2886 | if (sig) |
2887 | { | |
2888 | info.si_signo = sig; | |
2889 | info.si_errno = 0; | |
2890 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 2891 | queue_signal(env, info.si_signo, &info); |
48733d19 TS |
2892 | } |
2893 | } | |
2894 | break; | |
2895 | default: | |
2896 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 2897 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 2898 | exit(EXIT_FAILURE); |
48733d19 TS |
2899 | } |
2900 | process_pending_signals (env); | |
2901 | } | |
2902 | } | |
2903 | #endif | |
2904 | ||
b779e29e | 2905 | #ifdef TARGET_MICROBLAZE |
05390248 | 2906 | void cpu_loop(CPUMBState *env) |
b779e29e | 2907 | { |
878096ee | 2908 | CPUState *cs = CPU(mb_env_get_cpu(env)); |
b779e29e | 2909 | int trapnr, ret; |
c227f099 | 2910 | target_siginfo_t info; |
b779e29e EI |
2911 | |
2912 | while (1) { | |
b040bc9c | 2913 | cpu_exec_start(cs); |
ea3e9847 | 2914 | trapnr = cpu_mb_exec(cs); |
b040bc9c | 2915 | cpu_exec_end(cs); |
b779e29e EI |
2916 | switch (trapnr) { |
2917 | case 0xaa: | |
2918 | { | |
a86b3c64 | 2919 | info.si_signo = TARGET_SIGSEGV; |
b779e29e EI |
2920 | info.si_errno = 0; |
2921 | /* XXX: check env->error_code */ | |
2922 | info.si_code = TARGET_SEGV_MAPERR; | |
2923 | info._sifields._sigfault._addr = 0; | |
2924 | queue_signal(env, info.si_signo, &info); | |
2925 | } | |
2926 | break; | |
2927 | case EXCP_INTERRUPT: | |
2928 | /* just indicate that signals should be handled asap */ | |
2929 | break; | |
2930 | case EXCP_BREAK: | |
2931 | /* Return address is 4 bytes after the call. */ | |
2932 | env->regs[14] += 4; | |
d7dce494 | 2933 | env->sregs[SR_PC] = env->regs[14]; |
b779e29e EI |
2934 | ret = do_syscall(env, |
2935 | env->regs[12], | |
2936 | env->regs[5], | |
2937 | env->regs[6], | |
2938 | env->regs[7], | |
2939 | env->regs[8], | |
2940 | env->regs[9], | |
5945cfcb PM |
2941 | env->regs[10], |
2942 | 0, 0); | |
b779e29e | 2943 | env->regs[3] = ret; |
b779e29e | 2944 | break; |
b76da7e3 EI |
2945 | case EXCP_HW_EXCP: |
2946 | env->regs[17] = env->sregs[SR_PC] + 4; | |
2947 | if (env->iflags & D_FLAG) { | |
2948 | env->sregs[SR_ESR] |= 1 << 12; | |
2949 | env->sregs[SR_PC] -= 4; | |
b4916d7b | 2950 | /* FIXME: if branch was immed, replay the imm as well. */ |
b76da7e3 EI |
2951 | } |
2952 | ||
2953 | env->iflags &= ~(IMM_FLAG | D_FLAG); | |
2954 | ||
2955 | switch (env->sregs[SR_ESR] & 31) { | |
22a78d64 | 2956 | case ESR_EC_DIVZERO: |
a86b3c64 | 2957 | info.si_signo = TARGET_SIGFPE; |
22a78d64 EI |
2958 | info.si_errno = 0; |
2959 | info.si_code = TARGET_FPE_FLTDIV; | |
2960 | info._sifields._sigfault._addr = 0; | |
2961 | queue_signal(env, info.si_signo, &info); | |
2962 | break; | |
b76da7e3 | 2963 | case ESR_EC_FPU: |
a86b3c64 | 2964 | info.si_signo = TARGET_SIGFPE; |
b76da7e3 EI |
2965 | info.si_errno = 0; |
2966 | if (env->sregs[SR_FSR] & FSR_IO) { | |
2967 | info.si_code = TARGET_FPE_FLTINV; | |
2968 | } | |
2969 | if (env->sregs[SR_FSR] & FSR_DZ) { | |
2970 | info.si_code = TARGET_FPE_FLTDIV; | |
2971 | } | |
2972 | info._sifields._sigfault._addr = 0; | |
2973 | queue_signal(env, info.si_signo, &info); | |
2974 | break; | |
2975 | default: | |
2976 | printf ("Unhandled hw-exception: 0x%x\n", | |
2e42d52d | 2977 | env->sregs[SR_ESR] & ESR_EC_MASK); |
878096ee | 2978 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 2979 | exit(EXIT_FAILURE); |
b76da7e3 EI |
2980 | break; |
2981 | } | |
2982 | break; | |
b779e29e EI |
2983 | case EXCP_DEBUG: |
2984 | { | |
2985 | int sig; | |
2986 | ||
db6b81d4 | 2987 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
b779e29e EI |
2988 | if (sig) |
2989 | { | |
2990 | info.si_signo = sig; | |
2991 | info.si_errno = 0; | |
2992 | info.si_code = TARGET_TRAP_BRKPT; | |
2993 | queue_signal(env, info.si_signo, &info); | |
2994 | } | |
2995 | } | |
2996 | break; | |
2997 | default: | |
2998 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 2999 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 3000 | exit(EXIT_FAILURE); |
b779e29e EI |
3001 | } |
3002 | process_pending_signals (env); | |
3003 | } | |
3004 | } | |
3005 | #endif | |
3006 | ||
e6e5906b PB |
3007 | #ifdef TARGET_M68K |
3008 | ||
3009 | void cpu_loop(CPUM68KState *env) | |
3010 | { | |
878096ee | 3011 | CPUState *cs = CPU(m68k_env_get_cpu(env)); |
e6e5906b PB |
3012 | int trapnr; |
3013 | unsigned int n; | |
c227f099 | 3014 | target_siginfo_t info; |
0429a971 | 3015 | TaskState *ts = cs->opaque; |
3b46e624 | 3016 | |
e6e5906b | 3017 | for(;;) { |
b040bc9c | 3018 | cpu_exec_start(cs); |
ea3e9847 | 3019 | trapnr = cpu_m68k_exec(cs); |
b040bc9c | 3020 | cpu_exec_end(cs); |
e6e5906b PB |
3021 | switch(trapnr) { |
3022 | case EXCP_ILLEGAL: | |
3023 | { | |
3024 | if (ts->sim_syscalls) { | |
3025 | uint16_t nr; | |
d8d5119c | 3026 | get_user_u16(nr, env->pc + 2); |
e6e5906b PB |
3027 | env->pc += 4; |
3028 | do_m68k_simcall(env, nr); | |
3029 | } else { | |
3030 | goto do_sigill; | |
3031 | } | |
3032 | } | |
3033 | break; | |
a87295e8 | 3034 | case EXCP_HALT_INSN: |
e6e5906b | 3035 | /* Semihosing syscall. */ |
a87295e8 | 3036 | env->pc += 4; |
e6e5906b PB |
3037 | do_m68k_semihosting(env, env->dregs[0]); |
3038 | break; | |
3039 | case EXCP_LINEA: | |
3040 | case EXCP_LINEF: | |
3041 | case EXCP_UNSUPPORTED: | |
3042 | do_sigill: | |
a86b3c64 | 3043 | info.si_signo = TARGET_SIGILL; |
e6e5906b PB |
3044 | info.si_errno = 0; |
3045 | info.si_code = TARGET_ILL_ILLOPN; | |
3046 | info._sifields._sigfault._addr = env->pc; | |
624f7979 | 3047 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
3048 | break; |
3049 | case EXCP_TRAP0: | |
3050 | { | |
3051 | ts->sim_syscalls = 0; | |
3052 | n = env->dregs[0]; | |
3053 | env->pc += 2; | |
5fafdf24 TS |
3054 | env->dregs[0] = do_syscall(env, |
3055 | n, | |
e6e5906b PB |
3056 | env->dregs[1], |
3057 | env->dregs[2], | |
3058 | env->dregs[3], | |
3059 | env->dregs[4], | |
3060 | env->dregs[5], | |
5945cfcb PM |
3061 | env->aregs[0], |
3062 | 0, 0); | |
e6e5906b PB |
3063 | } |
3064 | break; | |
3065 | case EXCP_INTERRUPT: | |
3066 | /* just indicate that signals should be handled asap */ | |
3067 | break; | |
3068 | case EXCP_ACCESS: | |
3069 | { | |
a86b3c64 | 3070 | info.si_signo = TARGET_SIGSEGV; |
e6e5906b PB |
3071 | info.si_errno = 0; |
3072 | /* XXX: check env->error_code */ | |
3073 | info.si_code = TARGET_SEGV_MAPERR; | |
3074 | info._sifields._sigfault._addr = env->mmu.ar; | |
624f7979 | 3075 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
3076 | } |
3077 | break; | |
3078 | case EXCP_DEBUG: | |
3079 | { | |
3080 | int sig; | |
3081 | ||
db6b81d4 | 3082 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
e6e5906b PB |
3083 | if (sig) |
3084 | { | |
3085 | info.si_signo = sig; | |
3086 | info.si_errno = 0; | |
3087 | info.si_code = TARGET_TRAP_BRKPT; | |
624f7979 | 3088 | queue_signal(env, info.si_signo, &info); |
e6e5906b PB |
3089 | } |
3090 | } | |
3091 | break; | |
3092 | default: | |
120a9848 | 3093 | EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr); |
e6e5906b PB |
3094 | abort(); |
3095 | } | |
3096 | process_pending_signals(env); | |
3097 | } | |
3098 | } | |
3099 | #endif /* TARGET_M68K */ | |
3100 | ||
7a3148a9 | 3101 | #ifdef TARGET_ALPHA |
6910b8f6 RH |
3102 | static void do_store_exclusive(CPUAlphaState *env, int reg, int quad) |
3103 | { | |
3104 | target_ulong addr, val, tmp; | |
3105 | target_siginfo_t info; | |
3106 | int ret = 0; | |
3107 | ||
3108 | addr = env->lock_addr; | |
3109 | tmp = env->lock_st_addr; | |
3110 | env->lock_addr = -1; | |
3111 | env->lock_st_addr = 0; | |
3112 | ||
3113 | start_exclusive(); | |
3114 | mmap_lock(); | |
3115 | ||
3116 | if (addr == tmp) { | |
3117 | if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { | |
3118 | goto do_sigsegv; | |
3119 | } | |
3120 | ||
3121 | if (val == env->lock_value) { | |
3122 | tmp = env->ir[reg]; | |
3123 | if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) { | |
3124 | goto do_sigsegv; | |
3125 | } | |
3126 | ret = 1; | |
3127 | } | |
3128 | } | |
3129 | env->ir[reg] = ret; | |
3130 | env->pc += 4; | |
3131 | ||
3132 | mmap_unlock(); | |
3133 | end_exclusive(); | |
3134 | return; | |
3135 | ||
3136 | do_sigsegv: | |
3137 | mmap_unlock(); | |
3138 | end_exclusive(); | |
3139 | ||
3140 | info.si_signo = TARGET_SIGSEGV; | |
3141 | info.si_errno = 0; | |
3142 | info.si_code = TARGET_SEGV_MAPERR; | |
3143 | info._sifields._sigfault._addr = addr; | |
3144 | queue_signal(env, TARGET_SIGSEGV, &info); | |
3145 | } | |
3146 | ||
05390248 | 3147 | void cpu_loop(CPUAlphaState *env) |
7a3148a9 | 3148 | { |
878096ee | 3149 | CPUState *cs = CPU(alpha_env_get_cpu(env)); |
e96efcfc | 3150 | int trapnr; |
c227f099 | 3151 | target_siginfo_t info; |
6049f4f8 | 3152 | abi_long sysret; |
3b46e624 | 3153 | |
7a3148a9 | 3154 | while (1) { |
b040bc9c | 3155 | cpu_exec_start(cs); |
ea3e9847 | 3156 | trapnr = cpu_alpha_exec(cs); |
b040bc9c | 3157 | cpu_exec_end(cs); |
3b46e624 | 3158 | |
ac316ca4 RH |
3159 | /* All of the traps imply a transition through PALcode, which |
3160 | implies an REI instruction has been executed. Which means | |
3161 | that the intr_flag should be cleared. */ | |
3162 | env->intr_flag = 0; | |
3163 | ||
7a3148a9 JM |
3164 | switch (trapnr) { |
3165 | case EXCP_RESET: | |
3166 | fprintf(stderr, "Reset requested. Exit\n"); | |
4d1275c2 | 3167 | exit(EXIT_FAILURE); |
7a3148a9 JM |
3168 | break; |
3169 | case EXCP_MCHK: | |
3170 | fprintf(stderr, "Machine check exception. Exit\n"); | |
4d1275c2 | 3171 | exit(EXIT_FAILURE); |
7a3148a9 | 3172 | break; |
07b6c13b RH |
3173 | case EXCP_SMP_INTERRUPT: |
3174 | case EXCP_CLK_INTERRUPT: | |
3175 | case EXCP_DEV_INTERRUPT: | |
5fafdf24 | 3176 | fprintf(stderr, "External interrupt. Exit\n"); |
4d1275c2 | 3177 | exit(EXIT_FAILURE); |
7a3148a9 | 3178 | break; |
07b6c13b | 3179 | case EXCP_MMFAULT: |
6910b8f6 | 3180 | env->lock_addr = -1; |
6049f4f8 RH |
3181 | info.si_signo = TARGET_SIGSEGV; |
3182 | info.si_errno = 0; | |
129d8aa5 | 3183 | info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID |
0be1d07c | 3184 | ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR); |
129d8aa5 | 3185 | info._sifields._sigfault._addr = env->trap_arg0; |
6049f4f8 | 3186 | queue_signal(env, info.si_signo, &info); |
7a3148a9 | 3187 | break; |
7a3148a9 | 3188 | case EXCP_UNALIGN: |
6910b8f6 | 3189 | env->lock_addr = -1; |
6049f4f8 RH |
3190 | info.si_signo = TARGET_SIGBUS; |
3191 | info.si_errno = 0; | |
3192 | info.si_code = TARGET_BUS_ADRALN; | |
129d8aa5 | 3193 | info._sifields._sigfault._addr = env->trap_arg0; |
6049f4f8 | 3194 | queue_signal(env, info.si_signo, &info); |
7a3148a9 JM |
3195 | break; |
3196 | case EXCP_OPCDEC: | |
6049f4f8 | 3197 | do_sigill: |
6910b8f6 | 3198 | env->lock_addr = -1; |
6049f4f8 RH |
3199 | info.si_signo = TARGET_SIGILL; |
3200 | info.si_errno = 0; | |
3201 | info.si_code = TARGET_ILL_ILLOPC; | |
3202 | info._sifields._sigfault._addr = env->pc; | |
3203 | queue_signal(env, info.si_signo, &info); | |
7a3148a9 | 3204 | break; |
07b6c13b RH |
3205 | case EXCP_ARITH: |
3206 | env->lock_addr = -1; | |
3207 | info.si_signo = TARGET_SIGFPE; | |
3208 | info.si_errno = 0; | |
3209 | info.si_code = TARGET_FPE_FLTINV; | |
3210 | info._sifields._sigfault._addr = env->pc; | |
3211 | queue_signal(env, info.si_signo, &info); | |
3212 | break; | |
7a3148a9 | 3213 | case EXCP_FEN: |
6049f4f8 | 3214 | /* No-op. Linux simply re-enables the FPU. */ |
7a3148a9 | 3215 | break; |
07b6c13b | 3216 | case EXCP_CALL_PAL: |
6910b8f6 | 3217 | env->lock_addr = -1; |
07b6c13b | 3218 | switch (env->error_code) { |
6049f4f8 RH |
3219 | case 0x80: |
3220 | /* BPT */ | |
3221 | info.si_signo = TARGET_SIGTRAP; | |
3222 | info.si_errno = 0; | |
3223 | info.si_code = TARGET_TRAP_BRKPT; | |
3224 | info._sifields._sigfault._addr = env->pc; | |
3225 | queue_signal(env, info.si_signo, &info); | |
3226 | break; | |
3227 | case 0x81: | |
3228 | /* BUGCHK */ | |
3229 | info.si_signo = TARGET_SIGTRAP; | |
3230 | info.si_errno = 0; | |
3231 | info.si_code = 0; | |
3232 | info._sifields._sigfault._addr = env->pc; | |
3233 | queue_signal(env, info.si_signo, &info); | |
3234 | break; | |
3235 | case 0x83: | |
3236 | /* CALLSYS */ | |
3237 | trapnr = env->ir[IR_V0]; | |
3238 | sysret = do_syscall(env, trapnr, | |
3239 | env->ir[IR_A0], env->ir[IR_A1], | |
3240 | env->ir[IR_A2], env->ir[IR_A3], | |
5945cfcb PM |
3241 | env->ir[IR_A4], env->ir[IR_A5], |
3242 | 0, 0); | |
a5b3b13b RH |
3243 | if (trapnr == TARGET_NR_sigreturn |
3244 | || trapnr == TARGET_NR_rt_sigreturn) { | |
3245 | break; | |
3246 | } | |
3247 | /* Syscall writes 0 to V0 to bypass error check, similar | |
0e141977 RH |
3248 | to how this is handled internal to Linux kernel. |
3249 | (Ab)use trapnr temporarily as boolean indicating error. */ | |
3250 | trapnr = (env->ir[IR_V0] != 0 && sysret < 0); | |
3251 | env->ir[IR_V0] = (trapnr ? -sysret : sysret); | |
3252 | env->ir[IR_A3] = trapnr; | |
6049f4f8 RH |
3253 | break; |
3254 | case 0x86: | |
3255 | /* IMB */ | |
3256 | /* ??? We can probably elide the code using page_unprotect | |
3257 | that is checking for self-modifying code. Instead we | |
3258 | could simply call tb_flush here. Until we work out the | |
3259 | changes required to turn off the extra write protection, | |
3260 | this can be a no-op. */ | |
3261 | break; | |
3262 | case 0x9E: | |
3263 | /* RDUNIQUE */ | |
3264 | /* Handled in the translator for usermode. */ | |
3265 | abort(); | |
3266 | case 0x9F: | |
3267 | /* WRUNIQUE */ | |
3268 | /* Handled in the translator for usermode. */ | |
3269 | abort(); | |
3270 | case 0xAA: | |
3271 | /* GENTRAP */ | |
3272 | info.si_signo = TARGET_SIGFPE; | |
3273 | switch (env->ir[IR_A0]) { | |
3274 | case TARGET_GEN_INTOVF: | |
3275 | info.si_code = TARGET_FPE_INTOVF; | |
3276 | break; | |
3277 | case TARGET_GEN_INTDIV: | |
3278 | info.si_code = TARGET_FPE_INTDIV; | |
3279 | break; | |
3280 | case TARGET_GEN_FLTOVF: | |
3281 | info.si_code = TARGET_FPE_FLTOVF; | |
3282 | break; | |
3283 | case TARGET_GEN_FLTUND: | |
3284 | info.si_code = TARGET_FPE_FLTUND; | |
3285 | break; | |
3286 | case TARGET_GEN_FLTINV: | |
3287 | info.si_code = TARGET_FPE_FLTINV; | |
3288 | break; | |
3289 | case TARGET_GEN_FLTINE: | |
3290 | info.si_code = TARGET_FPE_FLTRES; | |
3291 | break; | |
3292 | case TARGET_GEN_ROPRAND: | |
3293 | info.si_code = 0; | |
3294 | break; | |
3295 | default: | |
3296 | info.si_signo = TARGET_SIGTRAP; | |
3297 | info.si_code = 0; | |
3298 | break; | |
3299 | } | |
3300 | info.si_errno = 0; | |
3301 | info._sifields._sigfault._addr = env->pc; | |
3302 | queue_signal(env, info.si_signo, &info); | |
3303 | break; | |
3304 | default: | |
3305 | goto do_sigill; | |
3306 | } | |
7a3148a9 | 3307 | break; |
7a3148a9 | 3308 | case EXCP_DEBUG: |
db6b81d4 | 3309 | info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP); |
6049f4f8 | 3310 | if (info.si_signo) { |
6910b8f6 | 3311 | env->lock_addr = -1; |
6049f4f8 RH |
3312 | info.si_errno = 0; |
3313 | info.si_code = TARGET_TRAP_BRKPT; | |
3314 | queue_signal(env, info.si_signo, &info); | |
7a3148a9 JM |
3315 | } |
3316 | break; | |
6910b8f6 RH |
3317 | case EXCP_STL_C: |
3318 | case EXCP_STQ_C: | |
3319 | do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C); | |
3320 | break; | |
d0f20495 RH |
3321 | case EXCP_INTERRUPT: |
3322 | /* Just indicate that signals should be handled asap. */ | |
3323 | break; | |
7a3148a9 JM |
3324 | default: |
3325 | printf ("Unhandled trap: 0x%x\n", trapnr); | |
878096ee | 3326 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 3327 | exit(EXIT_FAILURE); |
7a3148a9 JM |
3328 | } |
3329 | process_pending_signals (env); | |
3330 | } | |
3331 | } | |
3332 | #endif /* TARGET_ALPHA */ | |
3333 | ||
a4c075f1 UH |
3334 | #ifdef TARGET_S390X |
3335 | void cpu_loop(CPUS390XState *env) | |
3336 | { | |
878096ee | 3337 | CPUState *cs = CPU(s390_env_get_cpu(env)); |
d5a103cd | 3338 | int trapnr, n, sig; |
a4c075f1 | 3339 | target_siginfo_t info; |
d5a103cd | 3340 | target_ulong addr; |
a4c075f1 UH |
3341 | |
3342 | while (1) { | |
b040bc9c | 3343 | cpu_exec_start(cs); |
ea3e9847 | 3344 | trapnr = cpu_s390x_exec(cs); |
b040bc9c | 3345 | cpu_exec_end(cs); |
a4c075f1 UH |
3346 | switch (trapnr) { |
3347 | case EXCP_INTERRUPT: | |
d5a103cd | 3348 | /* Just indicate that signals should be handled asap. */ |
a4c075f1 | 3349 | break; |
a4c075f1 | 3350 | |
d5a103cd RH |
3351 | case EXCP_SVC: |
3352 | n = env->int_svc_code; | |
3353 | if (!n) { | |
3354 | /* syscalls > 255 */ | |
3355 | n = env->regs[1]; | |
a4c075f1 | 3356 | } |
d5a103cd RH |
3357 | env->psw.addr += env->int_svc_ilen; |
3358 | env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3], | |
3359 | env->regs[4], env->regs[5], | |
3360 | env->regs[6], env->regs[7], 0, 0); | |
a4c075f1 | 3361 | break; |
d5a103cd RH |
3362 | |
3363 | case EXCP_DEBUG: | |
db6b81d4 | 3364 | sig = gdb_handlesig(cs, TARGET_SIGTRAP); |
d5a103cd RH |
3365 | if (sig) { |
3366 | n = TARGET_TRAP_BRKPT; | |
3367 | goto do_signal_pc; | |
a4c075f1 UH |
3368 | } |
3369 | break; | |
d5a103cd RH |
3370 | case EXCP_PGM: |
3371 | n = env->int_pgm_code; | |
3372 | switch (n) { | |
3373 | case PGM_OPERATION: | |
3374 | case PGM_PRIVILEGED: | |
a86b3c64 | 3375 | sig = TARGET_SIGILL; |
d5a103cd RH |
3376 | n = TARGET_ILL_ILLOPC; |
3377 | goto do_signal_pc; | |
3378 | case PGM_PROTECTION: | |
3379 | case PGM_ADDRESSING: | |
a86b3c64 | 3380 | sig = TARGET_SIGSEGV; |
a4c075f1 | 3381 | /* XXX: check env->error_code */ |
d5a103cd RH |
3382 | n = TARGET_SEGV_MAPERR; |
3383 | addr = env->__excp_addr; | |
3384 | goto do_signal; | |
3385 | case PGM_EXECUTE: | |
3386 | case PGM_SPECIFICATION: | |
3387 | case PGM_SPECIAL_OP: | |
3388 | case PGM_OPERAND: | |
3389 | do_sigill_opn: | |
a86b3c64 | 3390 | sig = TARGET_SIGILL; |
d5a103cd RH |
3391 | n = TARGET_ILL_ILLOPN; |
3392 | goto do_signal_pc; | |
3393 | ||
3394 | case PGM_FIXPT_OVERFLOW: | |
a86b3c64 | 3395 | sig = TARGET_SIGFPE; |
d5a103cd RH |
3396 | n = TARGET_FPE_INTOVF; |
3397 | goto do_signal_pc; | |
3398 | case PGM_FIXPT_DIVIDE: | |
a86b3c64 | 3399 | sig = TARGET_SIGFPE; |
d5a103cd RH |
3400 | n = TARGET_FPE_INTDIV; |
3401 | goto do_signal_pc; | |
3402 | ||
3403 | case PGM_DATA: | |
3404 | n = (env->fpc >> 8) & 0xff; | |
3405 | if (n == 0xff) { | |
3406 | /* compare-and-trap */ | |
3407 | goto do_sigill_opn; | |
3408 | } else { | |
3409 | /* An IEEE exception, simulated or otherwise. */ | |
3410 | if (n & 0x80) { | |
3411 | n = TARGET_FPE_FLTINV; | |
3412 | } else if (n & 0x40) { | |
3413 | n = TARGET_FPE_FLTDIV; | |
3414 | } else if (n & 0x20) { | |
3415 | n = TARGET_FPE_FLTOVF; | |
3416 | } else if (n & 0x10) { | |
3417 | n = TARGET_FPE_FLTUND; | |
3418 | } else if (n & 0x08) { | |
3419 | n = TARGET_FPE_FLTRES; | |
3420 | } else { | |
3421 | /* ??? Quantum exception; BFP, DFP error. */ | |
3422 | goto do_sigill_opn; | |
3423 | } | |
a86b3c64 | 3424 | sig = TARGET_SIGFPE; |
d5a103cd RH |
3425 | goto do_signal_pc; |
3426 | } | |
3427 | ||
3428 | default: | |
3429 | fprintf(stderr, "Unhandled program exception: %#x\n", n); | |
878096ee | 3430 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 3431 | exit(EXIT_FAILURE); |
a4c075f1 UH |
3432 | } |
3433 | break; | |
d5a103cd RH |
3434 | |
3435 | do_signal_pc: | |
3436 | addr = env->psw.addr; | |
3437 | do_signal: | |
3438 | info.si_signo = sig; | |
3439 | info.si_errno = 0; | |
3440 | info.si_code = n; | |
3441 | info._sifields._sigfault._addr = addr; | |
3442 | queue_signal(env, info.si_signo, &info); | |
a4c075f1 | 3443 | break; |
d5a103cd | 3444 | |
a4c075f1 | 3445 | default: |
d5a103cd | 3446 | fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr); |
878096ee | 3447 | cpu_dump_state(cs, stderr, fprintf, 0); |
4d1275c2 | 3448 | exit(EXIT_FAILURE); |
a4c075f1 UH |
3449 | } |
3450 | process_pending_signals (env); | |
3451 | } | |
3452 | } | |
3453 | ||
3454 | #endif /* TARGET_S390X */ | |
3455 | ||
b16189b2 CG |
3456 | #ifdef TARGET_TILEGX |
3457 | ||
b16189b2 CG |
3458 | static void gen_sigill_reg(CPUTLGState *env) |
3459 | { | |
3460 | target_siginfo_t info; | |
3461 | ||
3462 | info.si_signo = TARGET_SIGILL; | |
3463 | info.si_errno = 0; | |
3464 | info.si_code = TARGET_ILL_PRVREG; | |
3465 | info._sifields._sigfault._addr = env->pc; | |
3466 | queue_signal(env, info.si_signo, &info); | |
3467 | } | |
3468 | ||
a0577d2a | 3469 | static void do_signal(CPUTLGState *env, int signo, int sigcode) |
dd8070d8 CG |
3470 | { |
3471 | target_siginfo_t info; | |
3472 | ||
a0577d2a | 3473 | info.si_signo = signo; |
dd8070d8 | 3474 | info.si_errno = 0; |
dd8070d8 | 3475 | info._sifields._sigfault._addr = env->pc; |
a0577d2a RH |
3476 | |
3477 | if (signo == TARGET_SIGSEGV) { | |
3478 | /* The passed in sigcode is a dummy; check for a page mapping | |
3479 | and pass either MAPERR or ACCERR. */ | |
3480 | target_ulong addr = env->excaddr; | |
3481 | info._sifields._sigfault._addr = addr; | |
3482 | if (page_check_range(addr, 1, PAGE_VALID) < 0) { | |
3483 | sigcode = TARGET_SEGV_MAPERR; | |
3484 | } else { | |
3485 | sigcode = TARGET_SEGV_ACCERR; | |
3486 | } | |
3487 | } | |
3488 | info.si_code = sigcode; | |
3489 | ||
dd8070d8 CG |
3490 | queue_signal(env, info.si_signo, &info); |
3491 | } | |
3492 | ||
a0577d2a RH |
3493 | static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr) |
3494 | { | |
3495 | env->excaddr = addr; | |
3496 | do_signal(env, TARGET_SIGSEGV, 0); | |
3497 | } | |
3498 | ||
0583b233 RH |
3499 | static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val) |
3500 | { | |
3501 | if (unlikely(reg >= TILEGX_R_COUNT)) { | |
3502 | switch (reg) { | |
3503 | case TILEGX_R_SN: | |
3504 | case TILEGX_R_ZERO: | |
3505 | return; | |
3506 | case TILEGX_R_IDN0: | |
3507 | case TILEGX_R_IDN1: | |
3508 | case TILEGX_R_UDN0: | |
3509 | case TILEGX_R_UDN1: | |
3510 | case TILEGX_R_UDN2: | |
3511 | case TILEGX_R_UDN3: | |
3512 | gen_sigill_reg(env); | |
3513 | return; | |
3514 | default: | |
3515 | g_assert_not_reached(); | |
3516 | } | |
3517 | } | |
3518 | env->regs[reg] = val; | |
3519 | } | |
3520 | ||
3521 | /* | |
3522 | * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in | |
3523 | * memory at the address held in the first source register. If the values are | |
3524 | * not equal, then no memory operation is performed. If the values are equal, | |
3525 | * the 8-byte quantity from the second source register is written into memory | |
3526 | * at the address held in the first source register. In either case, the result | |
3527 | * of the instruction is the value read from memory. The compare and write to | |
3528 | * memory are atomic and thus can be used for synchronization purposes. This | |
3529 | * instruction only operates for addresses aligned to a 8-byte boundary. | |
3530 | * Unaligned memory access causes an Unaligned Data Reference interrupt. | |
3531 | * | |
3532 | * Functional Description (64-bit) | |
3533 | * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); | |
3534 | * rf[Dest] = memVal; | |
3535 | * if (memVal == SPR[CmpValueSPR]) | |
3536 | * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); | |
3537 | * | |
3538 | * Functional Description (32-bit) | |
3539 | * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA])); | |
3540 | * rf[Dest] = memVal; | |
3541 | * if (memVal == signExtend32 (SPR[CmpValueSPR])) | |
3542 | * memoryWriteWord (rf[SrcA], rf[SrcB]); | |
3543 | * | |
3544 | * | |
3545 | * This function also processes exch and exch4 which need not process SPR. | |
3546 | */ | |
3547 | static void do_exch(CPUTLGState *env, bool quad, bool cmp) | |
3548 | { | |
3549 | target_ulong addr; | |
3550 | target_long val, sprval; | |
3551 | ||
3552 | start_exclusive(); | |
3553 | ||
3554 | addr = env->atomic_srca; | |
3555 | if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { | |
3556 | goto sigsegv_maperr; | |
3557 | } | |
3558 | ||
3559 | if (cmp) { | |
3560 | if (quad) { | |
3561 | sprval = env->spregs[TILEGX_SPR_CMPEXCH]; | |
3562 | } else { | |
3563 | sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32); | |
3564 | } | |
3565 | } | |
3566 | ||
3567 | if (!cmp || val == sprval) { | |
3568 | target_long valb = env->atomic_srcb; | |
3569 | if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { | |
3570 | goto sigsegv_maperr; | |
3571 | } | |
3572 | } | |
3573 | ||
3574 | set_regval(env, env->atomic_dstr, val); | |
3575 | end_exclusive(); | |
3576 | return; | |
3577 | ||
3578 | sigsegv_maperr: | |
3579 | end_exclusive(); | |
3580 | gen_sigsegv_maperr(env, addr); | |
3581 | } | |
3582 | ||
3583 | static void do_fetch(CPUTLGState *env, int trapnr, bool quad) | |
3584 | { | |
3585 | int8_t write = 1; | |
3586 | target_ulong addr; | |
3587 | target_long val, valb; | |
3588 | ||
3589 | start_exclusive(); | |
3590 | ||
3591 | addr = env->atomic_srca; | |
3592 | valb = env->atomic_srcb; | |
3593 | if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) { | |
3594 | goto sigsegv_maperr; | |
3595 | } | |
3596 | ||
3597 | switch (trapnr) { | |
3598 | case TILEGX_EXCP_OPCODE_FETCHADD: | |
3599 | case TILEGX_EXCP_OPCODE_FETCHADD4: | |
3600 | valb += val; | |
3601 | break; | |
3602 | case TILEGX_EXCP_OPCODE_FETCHADDGEZ: | |
3603 | valb += val; | |
3604 | if (valb < 0) { | |
3605 | write = 0; | |
3606 | } | |
3607 | break; | |
3608 | case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: | |
3609 | valb += val; | |
3610 | if ((int32_t)valb < 0) { | |
3611 | write = 0; | |
3612 | } | |
3613 | break; | |
3614 | case TILEGX_EXCP_OPCODE_FETCHAND: | |
3615 | case TILEGX_EXCP_OPCODE_FETCHAND4: | |
3616 | valb &= val; | |
3617 | break; | |
3618 | case TILEGX_EXCP_OPCODE_FETCHOR: | |
3619 | case TILEGX_EXCP_OPCODE_FETCHOR4: | |
3620 | valb |= val; | |
3621 | break; | |
3622 | default: | |
3623 | g_assert_not_reached(); | |
3624 | } | |
3625 | ||
3626 | if (write) { | |
3627 | if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) { | |
3628 | goto sigsegv_maperr; | |
3629 | } | |
3630 | } | |
3631 | ||
3632 | set_regval(env, env->atomic_dstr, val); | |
3633 | end_exclusive(); | |
3634 | return; | |
3635 | ||
3636 | sigsegv_maperr: | |
3637 | end_exclusive(); | |
3638 | gen_sigsegv_maperr(env, addr); | |
3639 | } | |
3640 | ||
b16189b2 CG |
3641 | void cpu_loop(CPUTLGState *env) |
3642 | { | |
3643 | CPUState *cs = CPU(tilegx_env_get_cpu(env)); | |
3644 | int trapnr; | |
3645 | ||
3646 | while (1) { | |
3647 | cpu_exec_start(cs); | |
3648 | trapnr = cpu_tilegx_exec(cs); | |
3649 | cpu_exec_end(cs); | |
3650 | switch (trapnr) { | |
3651 | case TILEGX_EXCP_SYSCALL: | |
3652 | env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR], | |
3653 | env->regs[0], env->regs[1], | |
3654 | env->regs[2], env->regs[3], | |
3655 | env->regs[4], env->regs[5], | |
3656 | env->regs[6], env->regs[7]); | |
3657 | env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE]) | |
3658 | ? - env->regs[TILEGX_R_RE] | |
3659 | : 0; | |
3660 | break; | |
0583b233 RH |
3661 | case TILEGX_EXCP_OPCODE_EXCH: |
3662 | do_exch(env, true, false); | |
3663 | break; | |
3664 | case TILEGX_EXCP_OPCODE_EXCH4: | |
3665 | do_exch(env, false, false); | |
3666 | break; | |
3667 | case TILEGX_EXCP_OPCODE_CMPEXCH: | |
3668 | do_exch(env, true, true); | |
3669 | break; | |
3670 | case TILEGX_EXCP_OPCODE_CMPEXCH4: | |
3671 | do_exch(env, false, true); | |
3672 | break; | |
3673 | case TILEGX_EXCP_OPCODE_FETCHADD: | |
3674 | case TILEGX_EXCP_OPCODE_FETCHADDGEZ: | |
3675 | case TILEGX_EXCP_OPCODE_FETCHAND: | |
3676 | case TILEGX_EXCP_OPCODE_FETCHOR: | |
3677 | do_fetch(env, trapnr, true); | |
3678 | break; | |
3679 | case TILEGX_EXCP_OPCODE_FETCHADD4: | |
3680 | case TILEGX_EXCP_OPCODE_FETCHADDGEZ4: | |
3681 | case TILEGX_EXCP_OPCODE_FETCHAND4: | |
3682 | case TILEGX_EXCP_OPCODE_FETCHOR4: | |
3683 | do_fetch(env, trapnr, false); | |
3684 | break; | |
dd8070d8 | 3685 | case TILEGX_EXCP_SIGNAL: |
a0577d2a | 3686 | do_signal(env, env->signo, env->sigcode); |
dd8070d8 | 3687 | break; |
b16189b2 CG |
3688 | case TILEGX_EXCP_REG_IDN_ACCESS: |
3689 | case TILEGX_EXCP_REG_UDN_ACCESS: | |
3690 | gen_sigill_reg(env); | |
3691 | break; | |
3692 | default: | |
3693 | fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr); | |
3694 | g_assert_not_reached(); | |
3695 | } | |
3696 | process_pending_signals(env); | |
3697 | } | |
3698 | } | |
3699 | ||
3700 | #endif | |
3701 | ||
a2247f8e | 3702 | THREAD CPUState *thread_cpu; |
59faf6d6 | 3703 | |
edf8e2af MW |
3704 | void task_settid(TaskState *ts) |
3705 | { | |
3706 | if (ts->ts_tid == 0) { | |
edf8e2af | 3707 | ts->ts_tid = (pid_t)syscall(SYS_gettid); |
edf8e2af MW |
3708 | } |
3709 | } | |
3710 | ||
3711 | void stop_all_tasks(void) | |
3712 | { | |
3713 | /* | |
3714 | * We trust that when using NPTL, start_exclusive() | |
3715 | * handles thread stopping correctly. | |
3716 | */ | |
3717 | start_exclusive(); | |
3718 | } | |
3719 | ||
c3a92833 | 3720 | /* Assumes contents are already zeroed. */ |
624f7979 PB |
3721 | void init_task_state(TaskState *ts) |
3722 | { | |
3723 | int i; | |
3724 | ||
624f7979 PB |
3725 | ts->used = 1; |
3726 | ts->first_free = ts->sigqueue_table; | |
3727 | for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) { | |
3728 | ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1]; | |
3729 | } | |
3730 | ts->sigqueue_table[i].next = NULL; | |
3731 | } | |
fc9c5412 | 3732 | |
30ba0ee5 AF |
3733 | CPUArchState *cpu_copy(CPUArchState *env) |
3734 | { | |
ff4700b0 | 3735 | CPUState *cpu = ENV_GET_CPU(env); |
2994fd96 | 3736 | CPUState *new_cpu = cpu_init(cpu_model); |
61c7480f | 3737 | CPUArchState *new_env = new_cpu->env_ptr; |
30ba0ee5 AF |
3738 | CPUBreakpoint *bp; |
3739 | CPUWatchpoint *wp; | |
30ba0ee5 AF |
3740 | |
3741 | /* Reset non arch specific state */ | |
75a34036 | 3742 | cpu_reset(new_cpu); |
30ba0ee5 AF |
3743 | |
3744 | memcpy(new_env, env, sizeof(CPUArchState)); | |
3745 | ||
3746 | /* Clone all break/watchpoints. | |
3747 | Note: Once we support ptrace with hw-debug register access, make sure | |
3748 | BP_CPU break/watchpoints are handled correctly on clone. */ | |
1d085f6c TB |
3749 | QTAILQ_INIT(&new_cpu->breakpoints); |
3750 | QTAILQ_INIT(&new_cpu->watchpoints); | |
f0c3c505 | 3751 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { |
b3310ab3 | 3752 | cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); |
30ba0ee5 | 3753 | } |
ff4700b0 | 3754 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { |
05068c0d | 3755 | cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL); |
30ba0ee5 | 3756 | } |
30ba0ee5 AF |
3757 | |
3758 | return new_env; | |
3759 | } | |
3760 | ||
fc9c5412 JS |
3761 | static void handle_arg_help(const char *arg) |
3762 | { | |
4d1275c2 | 3763 | usage(EXIT_SUCCESS); |
fc9c5412 JS |
3764 | } |
3765 | ||
3766 | static void handle_arg_log(const char *arg) | |
3767 | { | |
3768 | int mask; | |
fc9c5412 | 3769 | |
4fde1eba | 3770 | mask = qemu_str_to_log_mask(arg); |
fc9c5412 | 3771 | if (!mask) { |
59a6fa6e | 3772 | qemu_print_log_usage(stdout); |
4d1275c2 | 3773 | exit(EXIT_FAILURE); |
fc9c5412 | 3774 | } |
f2937a33 | 3775 | qemu_log_needs_buffers(); |
24537a01 | 3776 | qemu_set_log(mask); |
fc9c5412 JS |
3777 | } |
3778 | ||
50171d42 CWR |
3779 | static void handle_arg_log_filename(const char *arg) |
3780 | { | |
9a7e5424 | 3781 | qemu_set_log_filename(arg); |
50171d42 CWR |
3782 | } |
3783 | ||
fc9c5412 JS |
3784 | static void handle_arg_set_env(const char *arg) |
3785 | { | |
3786 | char *r, *p, *token; | |
3787 | r = p = strdup(arg); | |
3788 | while ((token = strsep(&p, ",")) != NULL) { | |
3789 | if (envlist_setenv(envlist, token) != 0) { | |
4d1275c2 | 3790 | usage(EXIT_FAILURE); |
fc9c5412 JS |
3791 | } |
3792 | } | |
3793 | free(r); | |
3794 | } | |
3795 | ||
3796 | static void handle_arg_unset_env(const char *arg) | |
3797 | { | |
3798 | char *r, *p, *token; | |
3799 | r = p = strdup(arg); | |
3800 | while ((token = strsep(&p, ",")) != NULL) { | |
3801 | if (envlist_unsetenv(envlist, token) != 0) { | |
4d1275c2 | 3802 | usage(EXIT_FAILURE); |
fc9c5412 JS |
3803 | } |
3804 | } | |
3805 | free(r); | |
3806 | } | |
3807 | ||
3808 | static void handle_arg_argv0(const char *arg) | |
3809 | { | |
3810 | argv0 = strdup(arg); | |
3811 | } | |
3812 | ||
3813 | static void handle_arg_stack_size(const char *arg) | |
3814 | { | |
3815 | char *p; | |
3816 | guest_stack_size = strtoul(arg, &p, 0); | |
3817 | if (guest_stack_size == 0) { | |
4d1275c2 | 3818 | usage(EXIT_FAILURE); |
fc9c5412 JS |
3819 | } |
3820 | ||
3821 | if (*p == 'M') { | |
3822 | guest_stack_size *= 1024 * 1024; | |
3823 | } else if (*p == 'k' || *p == 'K') { | |
3824 | guest_stack_size *= 1024; | |
3825 | } | |
3826 | } | |
3827 | ||
3828 | static void handle_arg_ld_prefix(const char *arg) | |
3829 | { | |
3830 | interp_prefix = strdup(arg); | |
3831 | } | |
3832 | ||
3833 | static void handle_arg_pagesize(const char *arg) | |
3834 | { | |
3835 | qemu_host_page_size = atoi(arg); | |
3836 | if (qemu_host_page_size == 0 || | |
3837 | (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) { | |
3838 | fprintf(stderr, "page size must be a power of two\n"); | |
4d1275c2 | 3839 | exit(EXIT_FAILURE); |
fc9c5412 JS |
3840 | } |
3841 | } | |
3842 | ||
c5e4a5a9 MR |
3843 | static void handle_arg_randseed(const char *arg) |
3844 | { | |
3845 | unsigned long long seed; | |
3846 | ||
3847 | if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) { | |
3848 | fprintf(stderr, "Invalid seed number: %s\n", arg); | |
4d1275c2 | 3849 | exit(EXIT_FAILURE); |
c5e4a5a9 MR |
3850 | } |
3851 | srand(seed); | |
3852 | } | |
3853 | ||
fc9c5412 JS |
3854 | static void handle_arg_gdb(const char *arg) |
3855 | { | |
3856 | gdbstub_port = atoi(arg); | |
3857 | } | |
3858 | ||
3859 | static void handle_arg_uname(const char *arg) | |
3860 | { | |
3861 | qemu_uname_release = strdup(arg); | |
3862 | } | |
3863 | ||
3864 | static void handle_arg_cpu(const char *arg) | |
3865 | { | |
3866 | cpu_model = strdup(arg); | |
c8057f95 | 3867 | if (cpu_model == NULL || is_help_option(cpu_model)) { |
fc9c5412 | 3868 | /* XXX: implement xxx_cpu_list for targets that still miss it */ |
e916cbf8 PM |
3869 | #if defined(cpu_list) |
3870 | cpu_list(stdout, &fprintf); | |
fc9c5412 | 3871 | #endif |
4d1275c2 | 3872 | exit(EXIT_FAILURE); |
fc9c5412 JS |
3873 | } |
3874 | } | |
3875 | ||
fc9c5412 JS |
3876 | static void handle_arg_guest_base(const char *arg) |
3877 | { | |
3878 | guest_base = strtol(arg, NULL, 0); | |
3879 | have_guest_base = 1; | |
3880 | } | |
3881 | ||
3882 | static void handle_arg_reserved_va(const char *arg) | |
3883 | { | |
3884 | char *p; | |
3885 | int shift = 0; | |
3886 | reserved_va = strtoul(arg, &p, 0); | |
3887 | switch (*p) { | |
3888 | case 'k': | |
3889 | case 'K': | |
3890 | shift = 10; | |
3891 | break; | |
3892 | case 'M': | |
3893 | shift = 20; | |
3894 | break; | |
3895 | case 'G': | |
3896 | shift = 30; | |
3897 | break; | |
3898 | } | |
3899 | if (shift) { | |
3900 | unsigned long unshifted = reserved_va; | |
3901 | p++; | |
3902 | reserved_va <<= shift; | |
3903 | if (((reserved_va >> shift) != unshifted) | |
3904 | #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS | |
3905 | || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) | |
3906 | #endif | |
3907 | ) { | |
3908 | fprintf(stderr, "Reserved virtual address too big\n"); | |
4d1275c2 | 3909 | exit(EXIT_FAILURE); |
fc9c5412 JS |
3910 | } |
3911 | } | |
3912 | if (*p) { | |
3913 | fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p); | |
4d1275c2 | 3914 | exit(EXIT_FAILURE); |
fc9c5412 JS |
3915 | } |
3916 | } | |
fc9c5412 JS |
3917 | |
3918 | static void handle_arg_singlestep(const char *arg) | |
3919 | { | |
3920 | singlestep = 1; | |
3921 | } | |
3922 | ||
3923 | static void handle_arg_strace(const char *arg) | |
3924 | { | |
3925 | do_strace = 1; | |
3926 | } | |
3927 | ||
3928 | static void handle_arg_version(const char *arg) | |
3929 | { | |
2e59915d | 3930 | printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION |
fc9c5412 | 3931 | ", Copyright (c) 2003-2008 Fabrice Bellard\n"); |
4d1275c2 | 3932 | exit(EXIT_SUCCESS); |
fc9c5412 JS |
3933 | } |
3934 | ||
3935 | struct qemu_argument { | |
3936 | const char *argv; | |
3937 | const char *env; | |
3938 | bool has_arg; | |
3939 | void (*handle_opt)(const char *arg); | |
3940 | const char *example; | |
3941 | const char *help; | |
3942 | }; | |
3943 | ||
42644cee | 3944 | static const struct qemu_argument arg_table[] = { |
fc9c5412 JS |
3945 | {"h", "", false, handle_arg_help, |
3946 | "", "print this help"}, | |
daaf8c8e MI |
3947 | {"help", "", false, handle_arg_help, |
3948 | "", ""}, | |
fc9c5412 JS |
3949 | {"g", "QEMU_GDB", true, handle_arg_gdb, |
3950 | "port", "wait gdb connection to 'port'"}, | |
3951 | {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix, | |
3952 | "path", "set the elf interpreter prefix to 'path'"}, | |
3953 | {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size, | |
3954 | "size", "set the stack size to 'size' bytes"}, | |
3955 | {"cpu", "QEMU_CPU", true, handle_arg_cpu, | |
c8057f95 | 3956 | "model", "select CPU (-cpu help for list)"}, |
fc9c5412 JS |
3957 | {"E", "QEMU_SET_ENV", true, handle_arg_set_env, |
3958 | "var=value", "sets targets environment variable (see below)"}, | |
3959 | {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env, | |
3960 | "var", "unsets targets environment variable (see below)"}, | |
3961 | {"0", "QEMU_ARGV0", true, handle_arg_argv0, | |
3962 | "argv0", "forces target process argv[0] to be 'argv0'"}, | |
3963 | {"r", "QEMU_UNAME", true, handle_arg_uname, | |
3964 | "uname", "set qemu uname release string to 'uname'"}, | |
fc9c5412 JS |
3965 | {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base, |
3966 | "address", "set guest_base address to 'address'"}, | |
3967 | {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va, | |
3968 | "size", "reserve 'size' bytes for guest virtual address space"}, | |
fc9c5412 | 3969 | {"d", "QEMU_LOG", true, handle_arg_log, |
989b697d PM |
3970 | "item[,...]", "enable logging of specified items " |
3971 | "(use '-d help' for a list of items)"}, | |
50171d42 | 3972 | {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, |
989b697d | 3973 | "logfile", "write logs to 'logfile' (default stderr)"}, |
fc9c5412 JS |
3974 | {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, |
3975 | "pagesize", "set the host page size to 'pagesize'"}, | |
3976 | {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep, | |
3977 | "", "run in singlestep mode"}, | |
3978 | {"strace", "QEMU_STRACE", false, handle_arg_strace, | |
3979 | "", "log system calls"}, | |
c5e4a5a9 MR |
3980 | {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed, |
3981 | "", "Seed for pseudo-random number generator"}, | |
fc9c5412 | 3982 | {"version", "QEMU_VERSION", false, handle_arg_version, |
1386d4c0 | 3983 | "", "display version information and exit"}, |
fc9c5412 JS |
3984 | {NULL, NULL, false, NULL, NULL, NULL} |
3985 | }; | |
3986 | ||
d03f9c32 | 3987 | static void usage(int exitcode) |
fc9c5412 | 3988 | { |
42644cee | 3989 | const struct qemu_argument *arginfo; |
fc9c5412 JS |
3990 | int maxarglen; |
3991 | int maxenvlen; | |
3992 | ||
2e59915d PB |
3993 | printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n" |
3994 | "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n" | |
fc9c5412 JS |
3995 | "\n" |
3996 | "Options and associated environment variables:\n" | |
3997 | "\n"); | |
3998 | ||
63ec54d7 PM |
3999 | /* Calculate column widths. We must always have at least enough space |
4000 | * for the column header. | |
4001 | */ | |
4002 | maxarglen = strlen("Argument"); | |
4003 | maxenvlen = strlen("Env-variable"); | |
fc9c5412 JS |
4004 | |
4005 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
63ec54d7 PM |
4006 | int arglen = strlen(arginfo->argv); |
4007 | if (arginfo->has_arg) { | |
4008 | arglen += strlen(arginfo->example) + 1; | |
4009 | } | |
fc9c5412 JS |
4010 | if (strlen(arginfo->env) > maxenvlen) { |
4011 | maxenvlen = strlen(arginfo->env); | |
4012 | } | |
63ec54d7 PM |
4013 | if (arglen > maxarglen) { |
4014 | maxarglen = arglen; | |
fc9c5412 JS |
4015 | } |
4016 | } | |
4017 | ||
63ec54d7 PM |
4018 | printf("%-*s %-*s Description\n", maxarglen+1, "Argument", |
4019 | maxenvlen, "Env-variable"); | |
fc9c5412 JS |
4020 | |
4021 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
4022 | if (arginfo->has_arg) { | |
4023 | printf("-%s %-*s %-*s %s\n", arginfo->argv, | |
63ec54d7 PM |
4024 | (int)(maxarglen - strlen(arginfo->argv) - 1), |
4025 | arginfo->example, maxenvlen, arginfo->env, arginfo->help); | |
fc9c5412 | 4026 | } else { |
63ec54d7 | 4027 | printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv, |
fc9c5412 JS |
4028 | maxenvlen, arginfo->env, |
4029 | arginfo->help); | |
4030 | } | |
4031 | } | |
4032 | ||
4033 | printf("\n" | |
4034 | "Defaults:\n" | |
4035 | "QEMU_LD_PREFIX = %s\n" | |
989b697d | 4036 | "QEMU_STACK_SIZE = %ld byte\n", |
fc9c5412 | 4037 | interp_prefix, |
989b697d | 4038 | guest_stack_size); |
fc9c5412 JS |
4039 | |
4040 | printf("\n" | |
4041 | "You can use -E and -U options or the QEMU_SET_ENV and\n" | |
4042 | "QEMU_UNSET_ENV environment variables to set and unset\n" | |
4043 | "environment variables for the target process.\n" | |
4044 | "It is possible to provide several variables by separating them\n" | |
4045 | "by commas in getsubopt(3) style. Additionally it is possible to\n" | |
4046 | "provide the -E and -U options multiple times.\n" | |
4047 | "The following lines are equivalent:\n" | |
4048 | " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" | |
4049 | " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" | |
4050 | " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" | |
4051 | "Note that if you provide several changes to a single variable\n" | |
4052 | "the last change will stay in effect.\n"); | |
4053 | ||
d03f9c32 | 4054 | exit(exitcode); |
fc9c5412 JS |
4055 | } |
4056 | ||
4057 | static int parse_args(int argc, char **argv) | |
4058 | { | |
4059 | const char *r; | |
4060 | int optind; | |
42644cee | 4061 | const struct qemu_argument *arginfo; |
fc9c5412 JS |
4062 | |
4063 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
4064 | if (arginfo->env == NULL) { | |
4065 | continue; | |
4066 | } | |
4067 | ||
4068 | r = getenv(arginfo->env); | |
4069 | if (r != NULL) { | |
4070 | arginfo->handle_opt(r); | |
4071 | } | |
4072 | } | |
4073 | ||
4074 | optind = 1; | |
4075 | for (;;) { | |
4076 | if (optind >= argc) { | |
4077 | break; | |
4078 | } | |
4079 | r = argv[optind]; | |
4080 | if (r[0] != '-') { | |
4081 | break; | |
4082 | } | |
4083 | optind++; | |
4084 | r++; | |
4085 | if (!strcmp(r, "-")) { | |
4086 | break; | |
4087 | } | |
ba02577c MI |
4088 | /* Treat --foo the same as -foo. */ |
4089 | if (r[0] == '-') { | |
4090 | r++; | |
4091 | } | |
fc9c5412 JS |
4092 | |
4093 | for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { | |
4094 | if (!strcmp(r, arginfo->argv)) { | |
fc9c5412 | 4095 | if (arginfo->has_arg) { |
1386d4c0 | 4096 | if (optind >= argc) { |
138940bf MI |
4097 | (void) fprintf(stderr, |
4098 | "qemu: missing argument for option '%s'\n", r); | |
4d1275c2 | 4099 | exit(EXIT_FAILURE); |
1386d4c0 PM |
4100 | } |
4101 | arginfo->handle_opt(argv[optind]); | |
fc9c5412 | 4102 | optind++; |
1386d4c0 PM |
4103 | } else { |
4104 | arginfo->handle_opt(NULL); | |
fc9c5412 | 4105 | } |
fc9c5412 JS |
4106 | break; |
4107 | } | |
4108 | } | |
4109 | ||
4110 | /* no option matched the current argv */ | |
4111 | if (arginfo->handle_opt == NULL) { | |
138940bf | 4112 | (void) fprintf(stderr, "qemu: unknown option '%s'\n", r); |
4d1275c2 | 4113 | exit(EXIT_FAILURE); |
fc9c5412 JS |
4114 | } |
4115 | } | |
4116 | ||
4117 | if (optind >= argc) { | |
138940bf | 4118 | (void) fprintf(stderr, "qemu: no user program specified\n"); |
4d1275c2 | 4119 | exit(EXIT_FAILURE); |
fc9c5412 JS |
4120 | } |
4121 | ||
4122 | filename = argv[optind]; | |
4123 | exec_path = argv[optind]; | |
4124 | ||
4125 | return optind; | |
4126 | } | |
4127 | ||
902b3d5c | 4128 | int main(int argc, char **argv, char **envp) |
31e31b8a | 4129 | { |
01ffc75b | 4130 | struct target_pt_regs regs1, *regs = ®s1; |
31e31b8a | 4131 | struct image_info info1, *info = &info1; |
edf8e2af | 4132 | struct linux_binprm bprm; |
48e15fc2 | 4133 | TaskState *ts; |
9349b4f9 | 4134 | CPUArchState *env; |
db6b81d4 | 4135 | CPUState *cpu; |
586314f2 | 4136 | int optind; |
04a6dfeb | 4137 | char **target_environ, **wrk; |
7d8cec95 AJ |
4138 | char **target_argv; |
4139 | int target_argc; | |
7d8cec95 | 4140 | int i; |
fd4d81dd | 4141 | int ret; |
03cfd8fa | 4142 | int execfd; |
b12b6a18 | 4143 | |
ce008c1f AF |
4144 | module_call_init(MODULE_INIT_QOM); |
4145 | ||
04a6dfeb AJ |
4146 | if ((envlist = envlist_create()) == NULL) { |
4147 | (void) fprintf(stderr, "Unable to allocate envlist\n"); | |
4d1275c2 | 4148 | exit(EXIT_FAILURE); |
04a6dfeb AJ |
4149 | } |
4150 | ||
4151 | /* add current environment into the list */ | |
4152 | for (wrk = environ; *wrk != NULL; wrk++) { | |
4153 | (void) envlist_setenv(envlist, *wrk); | |
4154 | } | |
4155 | ||
703e0e89 RH |
4156 | /* Read the stack limit from the kernel. If it's "unlimited", |
4157 | then we can do little else besides use the default. */ | |
4158 | { | |
4159 | struct rlimit lim; | |
4160 | if (getrlimit(RLIMIT_STACK, &lim) == 0 | |
81bbe906 TY |
4161 | && lim.rlim_cur != RLIM_INFINITY |
4162 | && lim.rlim_cur == (target_long)lim.rlim_cur) { | |
703e0e89 RH |
4163 | guest_stack_size = lim.rlim_cur; |
4164 | } | |
4165 | } | |
4166 | ||
b1f9be31 | 4167 | cpu_model = NULL; |
b5ec5ce0 | 4168 | |
c5e4a5a9 MR |
4169 | srand(time(NULL)); |
4170 | ||
fc9c5412 | 4171 | optind = parse_args(argc, argv); |
586314f2 | 4172 | |
31e31b8a | 4173 | /* Zero out regs */ |
01ffc75b | 4174 | memset(regs, 0, sizeof(struct target_pt_regs)); |
31e31b8a FB |
4175 | |
4176 | /* Zero out image_info */ | |
4177 | memset(info, 0, sizeof(struct image_info)); | |
4178 | ||
edf8e2af MW |
4179 | memset(&bprm, 0, sizeof (bprm)); |
4180 | ||
74cd30b8 FB |
4181 | /* Scan interp_prefix dir for replacement files. */ |
4182 | init_paths(interp_prefix); | |
4183 | ||
4a24a758 PM |
4184 | init_qemu_uname_release(); |
4185 | ||
46027c07 | 4186 | if (cpu_model == NULL) { |
aaed909a | 4187 | #if defined(TARGET_I386) |
46027c07 FB |
4188 | #ifdef TARGET_X86_64 |
4189 | cpu_model = "qemu64"; | |
4190 | #else | |
4191 | cpu_model = "qemu32"; | |
4192 | #endif | |
aaed909a | 4193 | #elif defined(TARGET_ARM) |
088ab16c | 4194 | cpu_model = "any"; |
d2fbca94 GX |
4195 | #elif defined(TARGET_UNICORE32) |
4196 | cpu_model = "any"; | |
aaed909a FB |
4197 | #elif defined(TARGET_M68K) |
4198 | cpu_model = "any"; | |
4199 | #elif defined(TARGET_SPARC) | |
4200 | #ifdef TARGET_SPARC64 | |
4201 | cpu_model = "TI UltraSparc II"; | |
4202 | #else | |
4203 | cpu_model = "Fujitsu MB86904"; | |
46027c07 | 4204 | #endif |
aaed909a FB |
4205 | #elif defined(TARGET_MIPS) |
4206 | #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64) | |
74797f40 | 4207 | cpu_model = "5KEf"; |
aaed909a FB |
4208 | #else |
4209 | cpu_model = "24Kf"; | |
4210 | #endif | |
d962783e JL |
4211 | #elif defined TARGET_OPENRISC |
4212 | cpu_model = "or1200"; | |
aaed909a | 4213 | #elif defined(TARGET_PPC) |
a74029f6 | 4214 | # ifdef TARGET_PPC64 |
de3f1b98 | 4215 | cpu_model = "POWER8"; |
a74029f6 | 4216 | # else |
aaed909a | 4217 | cpu_model = "750"; |
a74029f6 | 4218 | # endif |
91c45a38 RH |
4219 | #elif defined TARGET_SH4 |
4220 | cpu_model = TYPE_SH7785_CPU; | |
aaed909a FB |
4221 | #else |
4222 | cpu_model = "any"; | |
4223 | #endif | |
4224 | } | |
d5ab9713 | 4225 | tcg_exec_init(0); |
83fb7adf FB |
4226 | /* NOTE: we need to init the CPU at this stage to get |
4227 | qemu_host_page_size */ | |
2994fd96 EH |
4228 | cpu = cpu_init(cpu_model); |
4229 | if (!cpu) { | |
aaed909a | 4230 | fprintf(stderr, "Unable to find CPU definition\n"); |
4d1275c2 | 4231 | exit(EXIT_FAILURE); |
aaed909a | 4232 | } |
2994fd96 | 4233 | env = cpu->env_ptr; |
0ac46af3 | 4234 | cpu_reset(cpu); |
b55a37c9 | 4235 | |
db6b81d4 | 4236 | thread_cpu = cpu; |
3b46e624 | 4237 | |
b6741956 FB |
4238 | if (getenv("QEMU_STRACE")) { |
4239 | do_strace = 1; | |
b92c47c1 TS |
4240 | } |
4241 | ||
c5e4a5a9 MR |
4242 | if (getenv("QEMU_RAND_SEED")) { |
4243 | handle_arg_randseed(getenv("QEMU_RAND_SEED")); | |
4244 | } | |
4245 | ||
04a6dfeb AJ |
4246 | target_environ = envlist_to_environ(envlist, NULL); |
4247 | envlist_free(envlist); | |
b12b6a18 | 4248 | |
379f6698 PB |
4249 | /* |
4250 | * Now that page sizes are configured in cpu_init() we can do | |
4251 | * proper page alignment for guest_base. | |
4252 | */ | |
4253 | guest_base = HOST_PAGE_ALIGN(guest_base); | |
68a1c816 | 4254 | |
806d1021 MI |
4255 | if (reserved_va || have_guest_base) { |
4256 | guest_base = init_guest_space(guest_base, reserved_va, 0, | |
4257 | have_guest_base); | |
4258 | if (guest_base == (unsigned long)-1) { | |
097b8cb8 PM |
4259 | fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address " |
4260 | "space for use as guest address space (check your virtual " | |
4261 | "memory ulimit setting or reserve less using -R option)\n", | |
4262 | reserved_va); | |
4d1275c2 | 4263 | exit(EXIT_FAILURE); |
68a1c816 | 4264 | } |
97cc7560 | 4265 | |
806d1021 MI |
4266 | if (reserved_va) { |
4267 | mmap_next_start = reserved_va; | |
97cc7560 DDAG |
4268 | } |
4269 | } | |
379f6698 PB |
4270 | |
4271 | /* | |
4272 | * Read in mmap_min_addr kernel parameter. This value is used | |
4273 | * When loading the ELF image to determine whether guest_base | |
14f24e14 | 4274 | * is needed. It is also used in mmap_find_vma. |
379f6698 | 4275 | */ |
14f24e14 | 4276 | { |
379f6698 PB |
4277 | FILE *fp; |
4278 | ||
4279 | if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) { | |
4280 | unsigned long tmp; | |
4281 | if (fscanf(fp, "%lu", &tmp) == 1) { | |
4282 | mmap_min_addr = tmp; | |
13829020 | 4283 | qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr); |
379f6698 PB |
4284 | } |
4285 | fclose(fp); | |
4286 | } | |
4287 | } | |
379f6698 | 4288 | |
7d8cec95 AJ |
4289 | /* |
4290 | * Prepare copy of argv vector for target. | |
4291 | */ | |
4292 | target_argc = argc - optind; | |
4293 | target_argv = calloc(target_argc + 1, sizeof (char *)); | |
4294 | if (target_argv == NULL) { | |
4295 | (void) fprintf(stderr, "Unable to allocate memory for target_argv\n"); | |
4d1275c2 | 4296 | exit(EXIT_FAILURE); |
7d8cec95 AJ |
4297 | } |
4298 | ||
4299 | /* | |
4300 | * If argv0 is specified (using '-0' switch) we replace | |
4301 | * argv[0] pointer with the given one. | |
4302 | */ | |
4303 | i = 0; | |
4304 | if (argv0 != NULL) { | |
4305 | target_argv[i++] = strdup(argv0); | |
4306 | } | |
4307 | for (; i < target_argc; i++) { | |
4308 | target_argv[i] = strdup(argv[optind + i]); | |
4309 | } | |
4310 | target_argv[target_argc] = NULL; | |
4311 | ||
c78d65e8 | 4312 | ts = g_new0(TaskState, 1); |
edf8e2af MW |
4313 | init_task_state(ts); |
4314 | /* build Task State */ | |
4315 | ts->info = info; | |
4316 | ts->bprm = &bprm; | |
0429a971 | 4317 | cpu->opaque = ts; |
edf8e2af MW |
4318 | task_settid(ts); |
4319 | ||
0b959cf5 RH |
4320 | execfd = qemu_getauxval(AT_EXECFD); |
4321 | if (execfd == 0) { | |
03cfd8fa | 4322 | execfd = open(filename, O_RDONLY); |
0b959cf5 RH |
4323 | if (execfd < 0) { |
4324 | printf("Error while loading %s: %s\n", filename, strerror(errno)); | |
4d1275c2 | 4325 | _exit(EXIT_FAILURE); |
0b959cf5 | 4326 | } |
03cfd8fa LV |
4327 | } |
4328 | ||
4329 | ret = loader_exec(execfd, filename, target_argv, target_environ, regs, | |
fd4d81dd AP |
4330 | info, &bprm); |
4331 | if (ret != 0) { | |
885c1d10 | 4332 | printf("Error while loading %s: %s\n", filename, strerror(-ret)); |
4d1275c2 | 4333 | _exit(EXIT_FAILURE); |
b12b6a18 TS |
4334 | } |
4335 | ||
4336 | for (wrk = target_environ; *wrk; wrk++) { | |
4337 | free(*wrk); | |
31e31b8a | 4338 | } |
3b46e624 | 4339 | |
b12b6a18 TS |
4340 | free(target_environ); |
4341 | ||
13829020 | 4342 | if (qemu_loglevel_mask(CPU_LOG_PAGE)) { |
379f6698 | 4343 | qemu_log("guest_base 0x%lx\n", guest_base); |
2e77eac6 BS |
4344 | log_page_dump(); |
4345 | ||
4346 | qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk); | |
4347 | qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code); | |
4348 | qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", | |
4349 | info->start_code); | |
4350 | qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", | |
4351 | info->start_data); | |
4352 | qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data); | |
4353 | qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", | |
4354 | info->start_stack); | |
4355 | qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk); | |
4356 | qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry); | |
4357 | } | |
31e31b8a | 4358 | |
53a5960a | 4359 | target_set_brk(info->brk); |
31e31b8a | 4360 | syscall_init(); |
66fb9763 | 4361 | signal_init(); |
31e31b8a | 4362 | |
9002ec79 RH |
4363 | /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay |
4364 | generating the prologue until now so that the prologue can take | |
4365 | the real value of GUEST_BASE into account. */ | |
4366 | tcg_prologue_init(&tcg_ctx); | |
9002ec79 | 4367 | |
b346ff46 | 4368 | #if defined(TARGET_I386) |
3802ce26 | 4369 | env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; |
b98dbc90 | 4370 | env->hflags |= HF_PE_MASK | HF_CPL_MASK; |
0514ef2f | 4371 | if (env->features[FEAT_1_EDX] & CPUID_SSE) { |
1bde465e FB |
4372 | env->cr[4] |= CR4_OSFXSR_MASK; |
4373 | env->hflags |= HF_OSFXSR_MASK; | |
4374 | } | |
d2fd1af7 | 4375 | #ifndef TARGET_ABI32 |
4dbc422b | 4376 | /* enable 64 bit mode if possible */ |
0514ef2f | 4377 | if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { |
4dbc422b | 4378 | fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n"); |
4d1275c2 | 4379 | exit(EXIT_FAILURE); |
4dbc422b | 4380 | } |
d2fd1af7 | 4381 | env->cr[4] |= CR4_PAE_MASK; |
4dbc422b | 4382 | env->efer |= MSR_EFER_LMA | MSR_EFER_LME; |
d2fd1af7 FB |
4383 | env->hflags |= HF_LMA_MASK; |
4384 | #endif | |
1bde465e | 4385 | |
415e561f FB |
4386 | /* flags setup : we activate the IRQs by default as in user mode */ |
4387 | env->eflags |= IF_MASK; | |
3b46e624 | 4388 | |
6dbad63e | 4389 | /* linux register setup */ |
d2fd1af7 | 4390 | #ifndef TARGET_ABI32 |
84409ddb JM |
4391 | env->regs[R_EAX] = regs->rax; |
4392 | env->regs[R_EBX] = regs->rbx; | |
4393 | env->regs[R_ECX] = regs->rcx; | |
4394 | env->regs[R_EDX] = regs->rdx; | |
4395 | env->regs[R_ESI] = regs->rsi; | |
4396 | env->regs[R_EDI] = regs->rdi; | |
4397 | env->regs[R_EBP] = regs->rbp; | |
4398 | env->regs[R_ESP] = regs->rsp; | |
4399 | env->eip = regs->rip; | |
4400 | #else | |
0ecfa993 FB |
4401 | env->regs[R_EAX] = regs->eax; |
4402 | env->regs[R_EBX] = regs->ebx; | |
4403 | env->regs[R_ECX] = regs->ecx; | |
4404 | env->regs[R_EDX] = regs->edx; | |
4405 | env->regs[R_ESI] = regs->esi; | |
4406 | env->regs[R_EDI] = regs->edi; | |
4407 | env->regs[R_EBP] = regs->ebp; | |
4408 | env->regs[R_ESP] = regs->esp; | |
dab2ed99 | 4409 | env->eip = regs->eip; |
84409ddb | 4410 | #endif |
31e31b8a | 4411 | |
f4beb510 | 4412 | /* linux interrupt setup */ |
e441570f AZ |
4413 | #ifndef TARGET_ABI32 |
4414 | env->idt.limit = 511; | |
4415 | #else | |
4416 | env->idt.limit = 255; | |
4417 | #endif | |
4418 | env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), | |
4419 | PROT_READ|PROT_WRITE, | |
4420 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
4421 | idt_table = g2h(env->idt.base); | |
f4beb510 FB |
4422 | set_idt(0, 0); |
4423 | set_idt(1, 0); | |
4424 | set_idt(2, 0); | |
4425 | set_idt(3, 3); | |
4426 | set_idt(4, 3); | |
ec95da6c | 4427 | set_idt(5, 0); |
f4beb510 FB |
4428 | set_idt(6, 0); |
4429 | set_idt(7, 0); | |
4430 | set_idt(8, 0); | |
4431 | set_idt(9, 0); | |
4432 | set_idt(10, 0); | |
4433 | set_idt(11, 0); | |
4434 | set_idt(12, 0); | |
4435 | set_idt(13, 0); | |
4436 | set_idt(14, 0); | |
4437 | set_idt(15, 0); | |
4438 | set_idt(16, 0); | |
4439 | set_idt(17, 0); | |
4440 | set_idt(18, 0); | |
4441 | set_idt(19, 0); | |
4442 | set_idt(0x80, 3); | |
4443 | ||
6dbad63e | 4444 | /* linux segment setup */ |
8d18e893 FB |
4445 | { |
4446 | uint64_t *gdt_table; | |
e441570f AZ |
4447 | env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES, |
4448 | PROT_READ|PROT_WRITE, | |
4449 | MAP_ANONYMOUS|MAP_PRIVATE, -1, 0); | |
8d18e893 | 4450 | env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1; |
e441570f | 4451 | gdt_table = g2h(env->gdt.base); |
d2fd1af7 | 4452 | #ifdef TARGET_ABI32 |
8d18e893 FB |
4453 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, |
4454 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
4455 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
d2fd1af7 FB |
4456 | #else |
4457 | /* 64 bit code segment */ | |
4458 | write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff, | |
4459 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
4460 | DESC_L_MASK | | |
4461 | (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT)); | |
4462 | #endif | |
8d18e893 FB |
4463 | write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff, |
4464 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | | |
4465 | (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT)); | |
4466 | } | |
6dbad63e | 4467 | cpu_x86_load_seg(env, R_CS, __USER_CS); |
d2fd1af7 FB |
4468 | cpu_x86_load_seg(env, R_SS, __USER_DS); |
4469 | #ifdef TARGET_ABI32 | |
6dbad63e FB |
4470 | cpu_x86_load_seg(env, R_DS, __USER_DS); |
4471 | cpu_x86_load_seg(env, R_ES, __USER_DS); | |
6dbad63e FB |
4472 | cpu_x86_load_seg(env, R_FS, __USER_DS); |
4473 | cpu_x86_load_seg(env, R_GS, __USER_DS); | |
d6eb40f6 TS |
4474 | /* This hack makes Wine work... */ |
4475 | env->segs[R_FS].selector = 0; | |
d2fd1af7 FB |
4476 | #else |
4477 | cpu_x86_load_seg(env, R_DS, 0); | |
4478 | cpu_x86_load_seg(env, R_ES, 0); | |
4479 | cpu_x86_load_seg(env, R_FS, 0); | |
4480 | cpu_x86_load_seg(env, R_GS, 0); | |
4481 | #endif | |
99033cae AG |
4482 | #elif defined(TARGET_AARCH64) |
4483 | { | |
4484 | int i; | |
4485 | ||
4486 | if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { | |
4487 | fprintf(stderr, | |
4488 | "The selected ARM CPU does not support 64 bit mode\n"); | |
4d1275c2 | 4489 | exit(EXIT_FAILURE); |
99033cae AG |
4490 | } |
4491 | ||
4492 | for (i = 0; i < 31; i++) { | |
4493 | env->xregs[i] = regs->regs[i]; | |
4494 | } | |
4495 | env->pc = regs->pc; | |
4496 | env->xregs[31] = regs->sp; | |
4497 | } | |
b346ff46 FB |
4498 | #elif defined(TARGET_ARM) |
4499 | { | |
4500 | int i; | |
ae087923 PM |
4501 | cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, |
4502 | CPSRWriteByInstr); | |
b346ff46 FB |
4503 | for(i = 0; i < 16; i++) { |
4504 | env->regs[i] = regs->uregs[i]; | |
4505 | } | |
f9fd40eb | 4506 | #ifdef TARGET_WORDS_BIGENDIAN |
d8fd2954 PB |
4507 | /* Enable BE8. */ |
4508 | if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4 | |
4509 | && (info->elf_flags & EF_ARM_BE8)) { | |
9c5a7460 PC |
4510 | env->uncached_cpsr |= CPSR_E; |
4511 | env->cp15.sctlr_el[1] |= SCTLR_E0E; | |
f9fd40eb PB |
4512 | } else { |
4513 | env->cp15.sctlr_el[1] |= SCTLR_B; | |
d8fd2954 | 4514 | } |
f9fd40eb | 4515 | #endif |
b346ff46 | 4516 | } |
d2fbca94 GX |
4517 | #elif defined(TARGET_UNICORE32) |
4518 | { | |
4519 | int i; | |
4520 | cpu_asr_write(env, regs->uregs[32], 0xffffffff); | |
4521 | for (i = 0; i < 32; i++) { | |
4522 | env->regs[i] = regs->uregs[i]; | |
4523 | } | |
4524 | } | |
93ac68bc | 4525 | #elif defined(TARGET_SPARC) |
060366c5 FB |
4526 | { |
4527 | int i; | |
4528 | env->pc = regs->pc; | |
4529 | env->npc = regs->npc; | |
4530 | env->y = regs->y; | |
4531 | for(i = 0; i < 8; i++) | |
4532 | env->gregs[i] = regs->u_regs[i]; | |
4533 | for(i = 0; i < 8; i++) | |
4534 | env->regwptr[i] = regs->u_regs[i + 8]; | |
4535 | } | |
67867308 FB |
4536 | #elif defined(TARGET_PPC) |
4537 | { | |
4538 | int i; | |
3fc6c082 | 4539 | |
0411a972 JM |
4540 | #if defined(TARGET_PPC64) |
4541 | #if defined(TARGET_ABI32) | |
4542 | env->msr &= ~((target_ulong)1 << MSR_SF); | |
e85e7c6e | 4543 | #else |
0411a972 JM |
4544 | env->msr |= (target_ulong)1 << MSR_SF; |
4545 | #endif | |
84409ddb | 4546 | #endif |
67867308 FB |
4547 | env->nip = regs->nip; |
4548 | for(i = 0; i < 32; i++) { | |
4549 | env->gpr[i] = regs->gpr[i]; | |
4550 | } | |
4551 | } | |
e6e5906b PB |
4552 | #elif defined(TARGET_M68K) |
4553 | { | |
e6e5906b PB |
4554 | env->pc = regs->pc; |
4555 | env->dregs[0] = regs->d0; | |
4556 | env->dregs[1] = regs->d1; | |
4557 | env->dregs[2] = regs->d2; | |
4558 | env->dregs[3] = regs->d3; | |
4559 | env->dregs[4] = regs->d4; | |
4560 | env->dregs[5] = regs->d5; | |
4561 | env->dregs[6] = regs->d6; | |
4562 | env->dregs[7] = regs->d7; | |
4563 | env->aregs[0] = regs->a0; | |
4564 | env->aregs[1] = regs->a1; | |
4565 | env->aregs[2] = regs->a2; | |
4566 | env->aregs[3] = regs->a3; | |
4567 | env->aregs[4] = regs->a4; | |
4568 | env->aregs[5] = regs->a5; | |
4569 | env->aregs[6] = regs->a6; | |
4570 | env->aregs[7] = regs->usp; | |
4571 | env->sr = regs->sr; | |
4572 | ts->sim_syscalls = 1; | |
4573 | } | |
b779e29e EI |
4574 | #elif defined(TARGET_MICROBLAZE) |
4575 | { | |
4576 | env->regs[0] = regs->r0; | |
4577 | env->regs[1] = regs->r1; | |
4578 | env->regs[2] = regs->r2; | |
4579 | env->regs[3] = regs->r3; | |
4580 | env->regs[4] = regs->r4; | |
4581 | env->regs[5] = regs->r5; | |
4582 | env->regs[6] = regs->r6; | |
4583 | env->regs[7] = regs->r7; | |
4584 | env->regs[8] = regs->r8; | |
4585 | env->regs[9] = regs->r9; | |
4586 | env->regs[10] = regs->r10; | |
4587 | env->regs[11] = regs->r11; | |
4588 | env->regs[12] = regs->r12; | |
4589 | env->regs[13] = regs->r13; | |
4590 | env->regs[14] = regs->r14; | |
4591 | env->regs[15] = regs->r15; | |
4592 | env->regs[16] = regs->r16; | |
4593 | env->regs[17] = regs->r17; | |
4594 | env->regs[18] = regs->r18; | |
4595 | env->regs[19] = regs->r19; | |
4596 | env->regs[20] = regs->r20; | |
4597 | env->regs[21] = regs->r21; | |
4598 | env->regs[22] = regs->r22; | |
4599 | env->regs[23] = regs->r23; | |
4600 | env->regs[24] = regs->r24; | |
4601 | env->regs[25] = regs->r25; | |
4602 | env->regs[26] = regs->r26; | |
4603 | env->regs[27] = regs->r27; | |
4604 | env->regs[28] = regs->r28; | |
4605 | env->regs[29] = regs->r29; | |
4606 | env->regs[30] = regs->r30; | |
4607 | env->regs[31] = regs->r31; | |
4608 | env->sregs[SR_PC] = regs->pc; | |
4609 | } | |
048f6b4d FB |
4610 | #elif defined(TARGET_MIPS) |
4611 | { | |
4612 | int i; | |
4613 | ||
4614 | for(i = 0; i < 32; i++) { | |
b5dc7732 | 4615 | env->active_tc.gpr[i] = regs->regs[i]; |
048f6b4d | 4616 | } |
0fddbbf2 NF |
4617 | env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1; |
4618 | if (regs->cp0_epc & 1) { | |
4619 | env->hflags |= MIPS_HFLAG_M16; | |
4620 | } | |
048f6b4d | 4621 | } |
d962783e JL |
4622 | #elif defined(TARGET_OPENRISC) |
4623 | { | |
4624 | int i; | |
4625 | ||
4626 | for (i = 0; i < 32; i++) { | |
4627 | env->gpr[i] = regs->gpr[i]; | |
4628 | } | |
4629 | ||
4630 | env->sr = regs->sr; | |
4631 | env->pc = regs->pc; | |
4632 | } | |
fdf9b3e8 FB |
4633 | #elif defined(TARGET_SH4) |
4634 | { | |
4635 | int i; | |
4636 | ||
4637 | for(i = 0; i < 16; i++) { | |
4638 | env->gregs[i] = regs->regs[i]; | |
4639 | } | |
4640 | env->pc = regs->pc; | |
4641 | } | |
7a3148a9 JM |
4642 | #elif defined(TARGET_ALPHA) |
4643 | { | |
4644 | int i; | |
4645 | ||
4646 | for(i = 0; i < 28; i++) { | |
992f48a0 | 4647 | env->ir[i] = ((abi_ulong *)regs)[i]; |
7a3148a9 | 4648 | } |
dad081ee | 4649 | env->ir[IR_SP] = regs->usp; |
7a3148a9 | 4650 | env->pc = regs->pc; |
7a3148a9 | 4651 | } |
48733d19 TS |
4652 | #elif defined(TARGET_CRIS) |
4653 | { | |
4654 | env->regs[0] = regs->r0; | |
4655 | env->regs[1] = regs->r1; | |
4656 | env->regs[2] = regs->r2; | |
4657 | env->regs[3] = regs->r3; | |
4658 | env->regs[4] = regs->r4; | |
4659 | env->regs[5] = regs->r5; | |
4660 | env->regs[6] = regs->r6; | |
4661 | env->regs[7] = regs->r7; | |
4662 | env->regs[8] = regs->r8; | |
4663 | env->regs[9] = regs->r9; | |
4664 | env->regs[10] = regs->r10; | |
4665 | env->regs[11] = regs->r11; | |
4666 | env->regs[12] = regs->r12; | |
4667 | env->regs[13] = regs->r13; | |
4668 | env->regs[14] = info->start_stack; | |
4669 | env->regs[15] = regs->acr; | |
4670 | env->pc = regs->erp; | |
4671 | } | |
a4c075f1 UH |
4672 | #elif defined(TARGET_S390X) |
4673 | { | |
4674 | int i; | |
4675 | for (i = 0; i < 16; i++) { | |
4676 | env->regs[i] = regs->gprs[i]; | |
4677 | } | |
4678 | env->psw.mask = regs->psw.mask; | |
4679 | env->psw.addr = regs->psw.addr; | |
4680 | } | |
b16189b2 CG |
4681 | #elif defined(TARGET_TILEGX) |
4682 | { | |
4683 | int i; | |
4684 | for (i = 0; i < TILEGX_R_COUNT; i++) { | |
4685 | env->regs[i] = regs->regs[i]; | |
4686 | } | |
4687 | for (i = 0; i < TILEGX_SPR_COUNT; i++) { | |
4688 | env->spregs[i] = 0; | |
4689 | } | |
4690 | env->pc = regs->pc; | |
4691 | } | |
b346ff46 FB |
4692 | #else |
4693 | #error unsupported target CPU | |
4694 | #endif | |
31e31b8a | 4695 | |
d2fbca94 | 4696 | #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) |
a87295e8 PB |
4697 | ts->stack_base = info->start_stack; |
4698 | ts->heap_base = info->brk; | |
4699 | /* This will be filled in on the first SYS_HEAPINFO call. */ | |
4700 | ts->heap_limit = 0; | |
4701 | #endif | |
4702 | ||
74c33bed | 4703 | if (gdbstub_port) { |
ff7a981a PM |
4704 | if (gdbserver_start(gdbstub_port) < 0) { |
4705 | fprintf(stderr, "qemu: could not open gdbserver on port %d\n", | |
4706 | gdbstub_port); | |
4d1275c2 | 4707 | exit(EXIT_FAILURE); |
ff7a981a | 4708 | } |
db6b81d4 | 4709 | gdb_handlesig(cpu, 0); |
1fddef4b | 4710 | } |
1b6b029e FB |
4711 | cpu_loop(env); |
4712 | /* never exits */ | |
31e31b8a FB |
4713 | return 0; |
4714 | } |