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[qemu.git] / hw / misc / ivshmem.c
CommitLineData
6cbf4c8c
CM
1/*
2 * Inter-VM Shared Memory PCI device.
3 *
4 * Author:
5 * Cam Macdonell <[email protected]>
6 *
7 * Based On: cirrus_vga.c
8 * Copyright (c) 2004 Fabrice Bellard
9 * Copyright (c) 2004 Makoto Suzuki (suzu)
10 *
11 * and rtl8139.c
12 * Copyright (c) 2006 Igor Kovalenko
13 *
14 * This code is licensed under the GNU GPL v2.
6b620ca3
PB
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
6cbf4c8c 18 */
0d1c9782 19#include "qemu/osdep.h"
da34e65c 20#include "qapi/error.h"
f348b6d1 21#include "qemu/cutils.h"
83c9f4ca 22#include "hw/hw.h"
0d09e41a 23#include "hw/i386/pc.h"
83c9f4ca 24#include "hw/pci/pci.h"
660c97ee 25#include "hw/pci/msi.h"
83c9f4ca 26#include "hw/pci/msix.h"
9c17d615 27#include "sysemu/kvm.h"
caf71f86 28#include "migration/migration.h"
d49b6836 29#include "qemu/error-report.h"
1de7afc9 30#include "qemu/event_notifier.h"
5503e285 31#include "qom/object_interfaces.h"
dccfcd0e 32#include "sysemu/char.h"
d9453c93 33#include "sysemu/hostmem.h"
5400c02b 34#include "sysemu/qtest.h"
d9453c93 35#include "qapi/visitor.h"
6cbf4c8c 36
5105b1d8
DM
37#include "hw/misc/ivshmem.h"
38
b8ef62a9
PB
39#define PCI_VENDOR_ID_IVSHMEM PCI_VENDOR_ID_REDHAT_QUMRANET
40#define PCI_DEVICE_ID_IVSHMEM 0x1110
41
cd9953f7 42#define IVSHMEM_MAX_PEERS UINT16_MAX
6cbf4c8c
CM
43#define IVSHMEM_IOEVENTFD 0
44#define IVSHMEM_MSI 1
45
6cbf4c8c
CM
46#define IVSHMEM_REG_BAR_SIZE 0x100
47
a4fa93bf
MA
48#define IVSHMEM_DEBUG 0
49#define IVSHMEM_DPRINTF(fmt, ...) \
50 do { \
51 if (IVSHMEM_DEBUG) { \
52 printf("IVSHMEM: " fmt, ## __VA_ARGS__); \
53 } \
54 } while (0)
6cbf4c8c 55
5400c02b
MA
56#define TYPE_IVSHMEM_COMMON "ivshmem-common"
57#define IVSHMEM_COMMON(obj) \
58 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_COMMON)
59
60#define TYPE_IVSHMEM_PLAIN "ivshmem-plain"
61#define IVSHMEM_PLAIN(obj) \
62 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_PLAIN)
63
64#define TYPE_IVSHMEM_DOORBELL "ivshmem-doorbell"
65#define IVSHMEM_DOORBELL(obj) \
66 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM_DOORBELL)
67
eb3fedf3
PC
68#define TYPE_IVSHMEM "ivshmem"
69#define IVSHMEM(obj) \
70 OBJECT_CHECK(IVShmemState, (obj), TYPE_IVSHMEM)
71
6cbf4c8c
CM
72typedef struct Peer {
73 int nb_eventfds;
563027cc 74 EventNotifier *eventfds;
6cbf4c8c
CM
75} Peer;
76
0f57350e 77typedef struct MSIVector {
6cbf4c8c 78 PCIDevice *pdev;
660c97ee 79 int virq;
0f57350e 80} MSIVector;
6cbf4c8c
CM
81
82typedef struct IVShmemState {
b7578eaa
AF
83 /*< private >*/
84 PCIDevice parent_obj;
85 /*< public >*/
86
ddc85284
MA
87 uint32_t features;
88
89 /* exactly one of these two may be set */
90 HostMemoryBackend *hostmem; /* with interrupts */
becdfa00 91 CharBackend server_chr; /* without interrupts */
ddc85284
MA
92
93 /* registers */
6cbf4c8c
CM
94 uint32_t intrmask;
95 uint32_t intrstatus;
ddc85284 96 int vm_id;
6cbf4c8c 97
ddc85284
MA
98 /* BARs */
99 MemoryRegion ivshmem_mmio; /* BAR 0 (registers) */
c2d8019c
MA
100 MemoryRegion *ivshmem_bar2; /* BAR 2 (shared memory) */
101 MemoryRegion server_bar2; /* used with server_chr */
6cbf4c8c 102
ddc85284 103 /* interrupt support */
6cbf4c8c 104 Peer *peers;
cd9953f7 105 int nb_peers; /* space in @peers[] */
6cbf4c8c 106 uint32_t vectors;
0f57350e 107 MSIVector *msi_vectors;
ee276391
MA
108 uint64_t msg_buf; /* buffer for receiving server messages */
109 int msg_buffered_bytes; /* #bytes in @msg_buf */
6cbf4c8c 110
ddc85284 111 /* migration stuff */
2a845da7 112 OnOffAuto master;
38e0735e
AL
113 Error *migration_blocker;
114
5400c02b
MA
115 /* legacy cruft */
116 char *role;
117 char *shmobj;
118 char *sizearg;
119 size_t legacy_size;
120 uint32_t not_legacy_32bit;
6cbf4c8c
CM
121} IVShmemState;
122
123/* registers for the Inter-VM shared memory device */
124enum ivshmem_registers {
125 INTRMASK = 0,
126 INTRSTATUS = 4,
127 IVPOSITION = 8,
128 DOORBELL = 12,
129};
130
131static inline uint32_t ivshmem_has_feature(IVShmemState *ivs,
132 unsigned int feature) {
133 return (ivs->features & (1 << feature));
134}
135
2a845da7
MA
136static inline bool ivshmem_is_master(IVShmemState *s)
137{
138 assert(s->master != ON_OFF_AUTO_AUTO);
139 return s->master == ON_OFF_AUTO_ON;
140}
141
d8a5da07 142static void ivshmem_update_irq(IVShmemState *s)
6cbf4c8c 143{
b7578eaa 144 PCIDevice *d = PCI_DEVICE(s);
434ad76d 145 uint32_t isr = s->intrstatus & s->intrmask;
6cbf4c8c 146
5400c02b
MA
147 /*
148 * Do nothing unless the device actually uses INTx. Here's how
149 * the device variants signal interrupts, what they put in PCI
150 * config space:
151 * Device variant Interrupt Interrupt Pin MSI-X cap.
152 * ivshmem-plain none 0 no
153 * ivshmem-doorbell MSI-X 1 yes(1)
154 * ivshmem,msi=off INTx 1 no
155 * ivshmem,msi=on MSI-X 1(2) yes(1)
156 * (1) if guest enabled MSI-X
157 * (2) the device lies
158 * Leads to the condition for doing nothing:
159 */
160 if (ivshmem_has_feature(s, IVSHMEM_MSI)
161 || !d->config[PCI_INTERRUPT_PIN]) {
2d1d422d
MA
162 return;
163 }
164
6cbf4c8c
CM
165 /* don't print ISR resets */
166 if (isr) {
167 IVSHMEM_DPRINTF("Set IRQ to %d (%04x %04x)\n",
dbc464d4 168 isr ? 1 : 0, s->intrstatus, s->intrmask);
6cbf4c8c
CM
169 }
170
434ad76d 171 pci_set_irq(d, isr != 0);
6cbf4c8c
CM
172}
173
174static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
175{
176 IVSHMEM_DPRINTF("IntrMask write(w) val = 0x%04x\n", val);
177
178 s->intrmask = val;
d8a5da07 179 ivshmem_update_irq(s);
6cbf4c8c
CM
180}
181
182static uint32_t ivshmem_IntrMask_read(IVShmemState *s)
183{
184 uint32_t ret = s->intrmask;
185
186 IVSHMEM_DPRINTF("intrmask read(w) val = 0x%04x\n", ret);
6cbf4c8c
CM
187 return ret;
188}
189
190static void ivshmem_IntrStatus_write(IVShmemState *s, uint32_t val)
191{
192 IVSHMEM_DPRINTF("IntrStatus write(w) val = 0x%04x\n", val);
193
194 s->intrstatus = val;
d8a5da07 195 ivshmem_update_irq(s);
6cbf4c8c
CM
196}
197
198static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
199{
200 uint32_t ret = s->intrstatus;
201
202 /* reading ISR clears all interrupts */
203 s->intrstatus = 0;
d8a5da07 204 ivshmem_update_irq(s);
6cbf4c8c
CM
205 return ret;
206}
207
a8170e5e 208static void ivshmem_io_write(void *opaque, hwaddr addr,
cb06608e 209 uint64_t val, unsigned size)
6cbf4c8c
CM
210{
211 IVShmemState *s = opaque;
212
6cbf4c8c
CM
213 uint16_t dest = val >> 16;
214 uint16_t vector = val & 0xff;
215
216 addr &= 0xfc;
217
218 IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr);
219 switch (addr)
220 {
221 case INTRMASK:
222 ivshmem_IntrMask_write(s, val);
223 break;
224
225 case INTRSTATUS:
226 ivshmem_IntrStatus_write(s, val);
227 break;
228
229 case DOORBELL:
230 /* check that dest VM ID is reasonable */
95c8425c 231 if (dest >= s->nb_peers) {
6cbf4c8c
CM
232 IVSHMEM_DPRINTF("Invalid destination VM ID (%d)\n", dest);
233 break;
234 }
235
236 /* check doorbell range */
1b27d7a1 237 if (vector < s->peers[dest].nb_eventfds) {
563027cc
PB
238 IVSHMEM_DPRINTF("Notifying VM %d on vector %d\n", dest, vector);
239 event_notifier_set(&s->peers[dest].eventfds[vector]);
f59bb378
MAL
240 } else {
241 IVSHMEM_DPRINTF("Invalid destination vector %d on VM %d\n",
242 vector, dest);
6cbf4c8c
CM
243 }
244 break;
245 default:
f59bb378 246 IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr);
6cbf4c8c
CM
247 }
248}
249
a8170e5e 250static uint64_t ivshmem_io_read(void *opaque, hwaddr addr,
cb06608e 251 unsigned size)
6cbf4c8c
CM
252{
253
254 IVShmemState *s = opaque;
255 uint32_t ret;
256
257 switch (addr)
258 {
259 case INTRMASK:
260 ret = ivshmem_IntrMask_read(s);
261 break;
262
263 case INTRSTATUS:
264 ret = ivshmem_IntrStatus_read(s);
265 break;
266
267 case IVPOSITION:
1309cf44 268 ret = s->vm_id;
6cbf4c8c
CM
269 break;
270
271 default:
272 IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr);
273 ret = 0;
274 }
275
276 return ret;
277}
278
cb06608e
AK
279static const MemoryRegionOps ivshmem_mmio_ops = {
280 .read = ivshmem_io_read,
281 .write = ivshmem_io_write,
282 .endianness = DEVICE_NATIVE_ENDIAN,
283 .impl = {
284 .min_access_size = 4,
285 .max_access_size = 4,
286 },
6cbf4c8c
CM
287};
288
9940c323
MAL
289static void ivshmem_vector_notify(void *opaque)
290{
0f57350e 291 MSIVector *entry = opaque;
6cbf4c8c 292 PCIDevice *pdev = entry->pdev;
5400c02b 293 IVShmemState *s = IVSHMEM_COMMON(pdev);
0f57350e 294 int vector = entry - s->msi_vectors;
9940c323
MAL
295 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
296
297 if (!event_notifier_test_and_clear(n)) {
298 return;
299 }
6cbf4c8c 300
d160f3f7 301 IVSHMEM_DPRINTF("interrupt on vector %p %d\n", pdev, vector);
9940c323 302 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8
MA
303 if (msix_enabled(pdev)) {
304 msix_notify(pdev, vector);
305 }
9940c323
MAL
306 } else {
307 ivshmem_IntrStatus_write(s, 1);
308 }
6cbf4c8c
CM
309}
310
660c97ee
MAL
311static int ivshmem_vector_unmask(PCIDevice *dev, unsigned vector,
312 MSIMessage msg)
313{
5400c02b 314 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
315 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
316 MSIVector *v = &s->msi_vectors[vector];
317 int ret;
318
319 IVSHMEM_DPRINTF("vector unmask %p %d\n", dev, vector);
320
321 ret = kvm_irqchip_update_msi_route(kvm_state, v->virq, msg, dev);
322 if (ret < 0) {
323 return ret;
324 }
3f1fea0f 325 kvm_irqchip_commit_routes(kvm_state);
660c97ee
MAL
326
327 return kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL, v->virq);
328}
329
330static void ivshmem_vector_mask(PCIDevice *dev, unsigned vector)
331{
5400c02b 332 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
333 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
334 int ret;
335
336 IVSHMEM_DPRINTF("vector mask %p %d\n", dev, vector);
337
338 ret = kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, n,
339 s->msi_vectors[vector].virq);
340 if (ret != 0) {
341 error_report("remove_irqfd_notifier_gsi failed");
342 }
343}
344
345static void ivshmem_vector_poll(PCIDevice *dev,
346 unsigned int vector_start,
347 unsigned int vector_end)
348{
5400c02b 349 IVShmemState *s = IVSHMEM_COMMON(dev);
660c97ee
MAL
350 unsigned int vector;
351
352 IVSHMEM_DPRINTF("vector poll %p %d-%d\n", dev, vector_start, vector_end);
353
354 vector_end = MIN(vector_end, s->vectors);
355
356 for (vector = vector_start; vector < vector_end; vector++) {
357 EventNotifier *notifier = &s->peers[s->vm_id].eventfds[vector];
358
359 if (!msix_is_masked(dev, vector)) {
360 continue;
361 }
362
363 if (event_notifier_test_and_clear(notifier)) {
364 msix_set_pending(dev, vector);
365 }
366 }
367}
368
9940c323
MAL
369static void watch_vector_notifier(IVShmemState *s, EventNotifier *n,
370 int vector)
6cbf4c8c 371{
563027cc 372 int eventfd = event_notifier_get_fd(n);
6cbf4c8c 373
3c27969b 374 assert(!s->msi_vectors[vector].pdev);
9940c323 375 s->msi_vectors[vector].pdev = PCI_DEVICE(s);
6cbf4c8c 376
9940c323
MAL
377 qemu_set_fd_handler(eventfd, ivshmem_vector_notify,
378 NULL, &s->msi_vectors[vector]);
6cbf4c8c
CM
379}
380
563027cc
PB
381static void ivshmem_add_eventfd(IVShmemState *s, int posn, int i)
382{
383 memory_region_add_eventfd(&s->ivshmem_mmio,
384 DOORBELL,
385 4,
386 true,
387 (posn << 16) | i,
753d5e14 388 &s->peers[posn].eventfds[i]);
563027cc
PB
389}
390
391static void ivshmem_del_eventfd(IVShmemState *s, int posn, int i)
392{
393 memory_region_del_eventfd(&s->ivshmem_mmio,
394 DOORBELL,
395 4,
396 true,
397 (posn << 16) | i,
753d5e14 398 &s->peers[posn].eventfds[i]);
563027cc
PB
399}
400
f456179f 401static void close_peer_eventfds(IVShmemState *s, int posn)
6cbf4c8c 402{
f456179f 403 int i, n;
6cbf4c8c 404
9db51b4d 405 assert(posn >= 0 && posn < s->nb_peers);
f456179f 406 n = s->peers[posn].nb_eventfds;
6cbf4c8c 407
9db51b4d
MA
408 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
409 memory_region_transaction_begin();
410 for (i = 0; i < n; i++) {
411 ivshmem_del_eventfd(s, posn, i);
412 }
413 memory_region_transaction_commit();
b6a1f3a5 414 }
9db51b4d 415
f456179f 416 for (i = 0; i < n; i++) {
563027cc 417 event_notifier_cleanup(&s->peers[posn].eventfds[i]);
6cbf4c8c
CM
418 }
419
7267c094 420 g_free(s->peers[posn].eventfds);
6cbf4c8c
CM
421 s->peers[posn].nb_eventfds = 0;
422}
423
cd9953f7 424static void resize_peers(IVShmemState *s, int nb_peers)
34bc07c5 425{
cd9953f7
MA
426 int old_nb_peers = s->nb_peers;
427 int i;
6cbf4c8c 428
cd9953f7
MA
429 assert(nb_peers > old_nb_peers);
430 IVSHMEM_DPRINTF("bumping storage to %d peers\n", nb_peers);
6cbf4c8c 431
cd9953f7
MA
432 s->peers = g_realloc(s->peers, nb_peers * sizeof(Peer));
433 s->nb_peers = nb_peers;
1300b273 434
cd9953f7
MA
435 for (i = old_nb_peers; i < nb_peers; i++) {
436 s->peers[i].eventfds = g_new0(EventNotifier, s->vectors);
437 s->peers[i].nb_eventfds = 0;
6cbf4c8c
CM
438 }
439}
440
1309cf44
MA
441static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector,
442 Error **errp)
660c97ee
MAL
443{
444 PCIDevice *pdev = PCI_DEVICE(s);
660c97ee
MAL
445 int ret;
446
447 IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector);
3c27969b 448 assert(!s->msi_vectors[vector].pdev);
660c97ee 449
d1f6af6a 450 ret = kvm_irqchip_add_msi_route(kvm_state, vector, pdev);
660c97ee 451 if (ret < 0) {
1309cf44
MA
452 error_setg(errp, "kvm_irqchip_add_msi_route failed");
453 return;
660c97ee
MAL
454 }
455
456 s->msi_vectors[vector].virq = ret;
457 s->msi_vectors[vector].pdev = pdev;
660c97ee
MAL
458}
459
1309cf44 460static void setup_interrupt(IVShmemState *s, int vector, Error **errp)
660c97ee
MAL
461{
462 EventNotifier *n = &s->peers[s->vm_id].eventfds[vector];
463 bool with_irqfd = kvm_msi_via_irqfd_enabled() &&
464 ivshmem_has_feature(s, IVSHMEM_MSI);
465 PCIDevice *pdev = PCI_DEVICE(s);
1309cf44 466 Error *err = NULL;
660c97ee
MAL
467
468 IVSHMEM_DPRINTF("setting up interrupt for vector: %d\n", vector);
469
470 if (!with_irqfd) {
97553976 471 IVSHMEM_DPRINTF("with eventfd\n");
9940c323 472 watch_vector_notifier(s, n, vector);
660c97ee 473 } else if (msix_enabled(pdev)) {
97553976 474 IVSHMEM_DPRINTF("with irqfd\n");
1309cf44
MA
475 ivshmem_add_kvm_msi_virq(s, vector, &err);
476 if (err) {
477 error_propagate(errp, err);
660c97ee
MAL
478 return;
479 }
480
481 if (!msix_is_masked(pdev, vector)) {
482 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, n, NULL,
483 s->msi_vectors[vector].virq);
1309cf44 484 /* TODO handle error */
660c97ee
MAL
485 }
486 } else {
487 /* it will be delayed until msix is enabled, in write_config */
97553976 488 IVSHMEM_DPRINTF("with irqfd, delayed until msix enabled\n");
660c97ee
MAL
489 }
490}
491
1309cf44 492static void process_msg_shmem(IVShmemState *s, int fd, Error **errp)
6cbf4c8c 493{
8baeb22b 494 struct stat buf;
5400c02b 495 size_t size;
ca0b7566 496 void *ptr;
6cbf4c8c 497
c2d8019c 498 if (s->ivshmem_bar2) {
1309cf44 499 error_setg(errp, "server sent unexpected shared memory message");
ca0b7566 500 close(fd);
0f14fd71 501 return;
a2e9011b
SH
502 }
503
8baeb22b
MA
504 if (fstat(fd, &buf) < 0) {
505 error_setg_errno(errp, errno,
506 "can't determine size of shared memory sent by server");
507 close(fd);
508 return;
509 }
510
5400c02b
MA
511 size = buf.st_size;
512
513 /* Legacy cruft */
514 if (s->legacy_size != SIZE_MAX) {
515 if (size < s->legacy_size) {
516 error_setg(errp, "server sent only %zd bytes of shared memory",
517 (size_t)buf.st_size);
518 close(fd);
519 return;
520 }
521 size = s->legacy_size;
cd9953f7
MA
522 }
523
ca0b7566 524 /* mmap the region and map into the BAR2 */
5400c02b 525 ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
ca0b7566 526 if (ptr == MAP_FAILED) {
1309cf44 527 error_setg_errno(errp, errno, "Failed to mmap shared memory");
ca0b7566
MA
528 close(fd);
529 return;
6cbf4c8c 530 }
c2d8019c 531 memory_region_init_ram_ptr(&s->server_bar2, OBJECT(s),
5400c02b 532 "ivshmem.bar2", size, ptr);
4ff87573 533 memory_region_set_fd(&s->server_bar2, fd);
c2d8019c 534 s->ivshmem_bar2 = &s->server_bar2;
ca0b7566
MA
535}
536
1309cf44
MA
537static void process_msg_disconnect(IVShmemState *s, uint16_t posn,
538 Error **errp)
ca0b7566
MA
539{
540 IVSHMEM_DPRINTF("posn %d has gone away\n", posn);
9db51b4d 541 if (posn >= s->nb_peers || posn == s->vm_id) {
1309cf44 542 error_setg(errp, "invalid peer %d", posn);
9db51b4d
MA
543 return;
544 }
ca0b7566
MA
545 close_peer_eventfds(s, posn);
546}
6cbf4c8c 547
1309cf44
MA
548static void process_msg_connect(IVShmemState *s, uint16_t posn, int fd,
549 Error **errp)
ca0b7566
MA
550{
551 Peer *peer = &s->peers[posn];
552 int vector;
9a2f0e64 553
ca0b7566
MA
554 /*
555 * The N-th connect message for this peer comes with the file
556 * descriptor for vector N-1. Count messages to find the vector.
557 */
558 if (peer->nb_eventfds >= s->vectors) {
1309cf44
MA
559 error_setg(errp, "Too many eventfd received, device has %d vectors",
560 s->vectors);
ca0b7566 561 close(fd);
6f8a16d5 562 return;
6cbf4c8c 563 }
ca0b7566 564 vector = peer->nb_eventfds++;
6cbf4c8c 565
ca0b7566
MA
566 IVSHMEM_DPRINTF("eventfds[%d][%d] = %d\n", posn, vector, fd);
567 event_notifier_init_fd(&peer->eventfds[vector], fd);
568 fcntl_setfl(fd, O_NONBLOCK); /* msix/irqfd poll non block */
945001a1 569
ca0b7566 570 if (posn == s->vm_id) {
1309cf44
MA
571 setup_interrupt(s, vector, errp);
572 /* TODO do we need to handle the error? */
ca0b7566 573 }
6cbf4c8c 574
ca0b7566
MA
575 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD)) {
576 ivshmem_add_eventfd(s, posn, vector);
577 }
578}
6cbf4c8c 579
1309cf44 580static void process_msg(IVShmemState *s, int64_t msg, int fd, Error **errp)
ca0b7566
MA
581{
582 IVSHMEM_DPRINTF("posn is %" PRId64 ", fd is %d\n", msg, fd);
6cbf4c8c 583
ca0b7566 584 if (msg < -1 || msg > IVSHMEM_MAX_PEERS) {
1309cf44 585 error_setg(errp, "server sent invalid message %" PRId64, msg);
ca0b7566 586 close(fd);
6cbf4c8c
CM
587 return;
588 }
589
ca0b7566 590 if (msg == -1) {
1309cf44 591 process_msg_shmem(s, fd, errp);
1ee57de4
MAL
592 return;
593 }
594
ca0b7566
MA
595 if (msg >= s->nb_peers) {
596 resize_peers(s, msg + 1);
597 }
6cbf4c8c 598
ca0b7566 599 if (fd >= 0) {
1309cf44 600 process_msg_connect(s, msg, fd, errp);
ca0b7566 601 } else {
1309cf44 602 process_msg_disconnect(s, msg, errp);
6cbf4c8c 603 }
ca0b7566 604}
6cbf4c8c 605
ee276391
MA
606static int ivshmem_can_receive(void *opaque)
607{
608 IVShmemState *s = opaque;
609
610 assert(s->msg_buffered_bytes < sizeof(s->msg_buf));
611 return sizeof(s->msg_buf) - s->msg_buffered_bytes;
612}
613
ca0b7566
MA
614static void ivshmem_read(void *opaque, const uint8_t *buf, int size)
615{
616 IVShmemState *s = opaque;
1309cf44 617 Error *err = NULL;
ca0b7566
MA
618 int fd;
619 int64_t msg;
620
ee276391
MA
621 assert(size >= 0 && s->msg_buffered_bytes + size <= sizeof(s->msg_buf));
622 memcpy((unsigned char *)&s->msg_buf + s->msg_buffered_bytes, buf, size);
623 s->msg_buffered_bytes += size;
624 if (s->msg_buffered_bytes < sizeof(s->msg_buf)) {
ca0b7566 625 return;
6cbf4c8c 626 }
ee276391
MA
627 msg = le64_to_cpu(s->msg_buf);
628 s->msg_buffered_bytes = 0;
ca0b7566 629
5345fdb4 630 fd = qemu_chr_fe_get_msgfd(&s->server_chr);
ca0b7566 631
1309cf44
MA
632 process_msg(s, msg, fd, &err);
633 if (err) {
634 error_report_err(err);
635 }
6cbf4c8c
CM
636}
637
1309cf44 638static int64_t ivshmem_recv_msg(IVShmemState *s, int *pfd, Error **errp)
5105b1d8 639{
3a55fc0f
MA
640 int64_t msg;
641 int n, ret;
642
643 n = 0;
644 do {
5345fdb4
MAL
645 ret = qemu_chr_fe_read_all(&s->server_chr, (uint8_t *)&msg + n,
646 sizeof(msg) - n);
3a55fc0f 647 if (ret < 0 && ret != -EINTR) {
1309cf44 648 error_setg_errno(errp, -ret, "read from server failed");
3a55fc0f
MA
649 return INT64_MIN;
650 }
651 n += ret;
652 } while (n < sizeof(msg));
5105b1d8 653
5345fdb4 654 *pfd = qemu_chr_fe_get_msgfd(&s->server_chr);
3a55fc0f
MA
655 return msg;
656}
5105b1d8 657
1309cf44 658static void ivshmem_recv_setup(IVShmemState *s, Error **errp)
3a55fc0f 659{
1309cf44 660 Error *err = NULL;
3a55fc0f
MA
661 int64_t msg;
662 int fd;
663
1309cf44
MA
664 msg = ivshmem_recv_msg(s, &fd, &err);
665 if (err) {
666 error_propagate(errp, err);
667 return;
668 }
669 if (msg != IVSHMEM_PROTOCOL_VERSION) {
670 error_setg(errp, "server sent version %" PRId64 ", expecting %d",
671 msg, IVSHMEM_PROTOCOL_VERSION);
672 return;
673 }
674 if (fd != -1) {
675 error_setg(errp, "server sent invalid version message");
5105b1d8
DM
676 return;
677 }
678
a3feb086
MA
679 /*
680 * ivshmem-server sends the remaining initial messages in a fixed
681 * order, but the device has always accepted them in any order.
682 * Stay as compatible as practical, just in case people use
683 * servers that behave differently.
684 */
685
686 /*
687 * ivshmem_device_spec.txt has always required the ID message
688 * right here, and ivshmem-server has always complied. However,
689 * older versions of the device accepted it out of order, but
690 * broke when an interrupt setup message arrived before it.
691 */
692 msg = ivshmem_recv_msg(s, &fd, &err);
693 if (err) {
694 error_propagate(errp, err);
695 return;
696 }
697 if (fd != -1 || msg < 0 || msg > IVSHMEM_MAX_PEERS) {
698 error_setg(errp, "server sent invalid ID message");
699 return;
700 }
701 s->vm_id = msg;
702
3a55fc0f
MA
703 /*
704 * Receive more messages until we got shared memory.
705 */
706 do {
1309cf44
MA
707 msg = ivshmem_recv_msg(s, &fd, &err);
708 if (err) {
709 error_propagate(errp, err);
710 return;
711 }
712 process_msg(s, msg, fd, &err);
713 if (err) {
714 error_propagate(errp, err);
715 return;
716 }
3a55fc0f 717 } while (msg != -1);
1309cf44
MA
718
719 /*
720 * This function must either map the shared memory or fail. The
721 * loop above ensures that: it terminates normally only after it
722 * successfully processed the server's shared memory message.
723 * Assert that actually mapped the shared memory:
724 */
c2d8019c 725 assert(s->ivshmem_bar2);
5105b1d8
DM
726}
727
4490c711
MT
728/* Select the MSI-X vectors used by device.
729 * ivshmem maps events to vectors statically, so
730 * we just enable all vectors on init and after reset. */
082751e8 731static void ivshmem_msix_vector_use(IVShmemState *s)
4490c711 732{
b7578eaa 733 PCIDevice *d = PCI_DEVICE(s);
4490c711
MT
734 int i;
735
4490c711 736 for (i = 0; i < s->vectors; i++) {
b7578eaa 737 msix_vector_use(d, i);
4490c711
MT
738 }
739}
740
6cbf4c8c
CM
741static void ivshmem_reset(DeviceState *d)
742{
5400c02b 743 IVShmemState *s = IVSHMEM_COMMON(d);
6cbf4c8c
CM
744
745 s->intrstatus = 0;
972ad215 746 s->intrmask = 0;
082751e8
MA
747 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
748 ivshmem_msix_vector_use(s);
749 }
6cbf4c8c
CM
750}
751
fd47bfe5 752static int ivshmem_setup_interrupts(IVShmemState *s)
4490c711 753{
fd47bfe5
MAL
754 /* allocate QEMU callback data for receiving interrupts */
755 s->msi_vectors = g_malloc0(s->vectors * sizeof(MSIVector));
6cbf4c8c 756
fd47bfe5
MAL
757 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
758 if (msix_init_exclusive_bar(PCI_DEVICE(s), s->vectors, 1)) {
759 return -1;
760 }
1116b539 761
fd47bfe5 762 IVSHMEM_DPRINTF("msix initialized (%d vectors)\n", s->vectors);
082751e8 763 ivshmem_msix_vector_use(s);
fd47bfe5 764 }
4490c711 765
d58d7e84 766 return 0;
6cbf4c8c
CM
767}
768
660c97ee
MAL
769static void ivshmem_enable_irqfd(IVShmemState *s)
770{
771 PCIDevice *pdev = PCI_DEVICE(s);
772 int i;
773
774 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
1309cf44
MA
775 Error *err = NULL;
776
777 ivshmem_add_kvm_msi_virq(s, i, &err);
778 if (err) {
779 error_report_err(err);
780 /* TODO do we need to handle the error? */
781 }
660c97ee
MAL
782 }
783
784 if (msix_set_vector_notifiers(pdev,
785 ivshmem_vector_unmask,
786 ivshmem_vector_mask,
787 ivshmem_vector_poll)) {
788 error_report("ivshmem: msix_set_vector_notifiers failed");
789 }
790}
791
792static void ivshmem_remove_kvm_msi_virq(IVShmemState *s, int vector)
793{
794 IVSHMEM_DPRINTF("ivshmem_remove_kvm_msi_virq vector:%d\n", vector);
795
796 if (s->msi_vectors[vector].pdev == NULL) {
797 return;
798 }
799
800 /* it was cleaned when masked in the frontend. */
801 kvm_irqchip_release_virq(kvm_state, s->msi_vectors[vector].virq);
802
803 s->msi_vectors[vector].pdev = NULL;
804}
805
806static void ivshmem_disable_irqfd(IVShmemState *s)
807{
808 PCIDevice *pdev = PCI_DEVICE(s);
809 int i;
810
811 for (i = 0; i < s->peers[s->vm_id].nb_eventfds; i++) {
812 ivshmem_remove_kvm_msi_virq(s, i);
813 }
814
815 msix_unset_vector_notifiers(pdev);
816}
817
818static void ivshmem_write_config(PCIDevice *pdev, uint32_t address,
d58d7e84 819 uint32_t val, int len)
4490c711 820{
5400c02b 821 IVShmemState *s = IVSHMEM_COMMON(pdev);
660c97ee
MAL
822 int is_enabled, was_enabled = msix_enabled(pdev);
823
824 pci_default_write_config(pdev, address, val, len);
825 is_enabled = msix_enabled(pdev);
826
1309cf44 827 if (kvm_msi_via_irqfd_enabled()) {
660c97ee
MAL
828 if (!was_enabled && is_enabled) {
829 ivshmem_enable_irqfd(s);
830 } else if (was_enabled && !is_enabled) {
831 ivshmem_disable_irqfd(s);
832 }
833 }
4490c711
MT
834}
835
5400c02b 836static void ivshmem_common_realize(PCIDevice *dev, Error **errp)
6cbf4c8c 837{
5400c02b 838 IVShmemState *s = IVSHMEM_COMMON(dev);
d855e275 839 Error *err = NULL;
6cbf4c8c 840 uint8_t *pci_conf;
9113e3f3
MAL
841 uint8_t attr = PCI_BASE_ADDRESS_SPACE_MEMORY |
842 PCI_BASE_ADDRESS_MEM_PREFETCH;
6cbf4c8c 843
6cbf4c8c
CM
844 /* IRQFD requires MSI */
845 if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) &&
846 !ivshmem_has_feature(s, IVSHMEM_MSI)) {
d58d7e84
MAL
847 error_setg(errp, "ioeventfd/irqfd requires MSI");
848 return;
6cbf4c8c
CM
849 }
850
b7578eaa 851 pci_conf = dev->config;
6cbf4c8c 852 pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
6cbf4c8c 853
3c161542 854 memory_region_init_io(&s->ivshmem_mmio, OBJECT(s), &ivshmem_mmio_ops, s,
cb06608e
AK
855 "ivshmem-mmio", IVSHMEM_REG_BAR_SIZE);
856
6cbf4c8c 857 /* region for registers*/
b7578eaa 858 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
e824b2cc 859 &s->ivshmem_mmio);
cb06608e 860
5400c02b 861 if (!s->not_legacy_32bit) {
9113e3f3 862 attr |= PCI_BASE_ADDRESS_MEM_TYPE_64;
c08ba66f 863 }
6cbf4c8c 864
d9453c93 865 if (s->hostmem != NULL) {
d9453c93
MAL
866 IVSHMEM_DPRINTF("using hostmem\n");
867
c2d8019c
MA
868 s->ivshmem_bar2 = host_memory_backend_get_memory(s->hostmem,
869 &error_abort);
5503e285 870 } else {
5345fdb4
MAL
871 CharDriverState *chr = qemu_chr_fe_get_driver(&s->server_chr);
872 assert(chr);
6dc64780 873
6cbf4c8c 874 IVSHMEM_DPRINTF("using shared memory server (socket = %s)\n",
5345fdb4 875 chr->filename);
6cbf4c8c 876
f456179f 877 /* we allocate enough space for 16 peers and grow as needed */
1300b273 878 resize_peers(s, 16);
6cbf4c8c 879
3a55fc0f
MA
880 /*
881 * Receive setup messages from server synchronously.
882 * Older versions did it asynchronously, but that creates a
883 * number of entertaining race conditions.
3a55fc0f 884 */
1309cf44
MA
885 ivshmem_recv_setup(s, &err);
886 if (err) {
887 error_propagate(errp, err);
888 return;
3a55fc0f
MA
889 }
890
62a830b6
MA
891 if (s->master == ON_OFF_AUTO_ON && s->vm_id != 0) {
892 error_setg(errp,
893 "master must connect to the server before any peers");
894 return;
895 }
896
5345fdb4 897 qemu_chr_fe_set_handlers(&s->server_chr, ivshmem_can_receive,
39ab61c6 898 ivshmem_read, NULL, s, NULL, true);
1309cf44 899
3a55fc0f
MA
900 if (ivshmem_setup_interrupts(s) < 0) {
901 error_setg(errp, "failed to initialize interrupts");
902 return;
903 }
d855e275
MA
904 }
905
c2d8019c
MA
906 vmstate_register_ram(s->ivshmem_bar2, DEVICE(s));
907 pci_register_bar(PCI_DEVICE(s), 2, attr, s->ivshmem_bar2);
908
2a845da7
MA
909 if (s->master == ON_OFF_AUTO_AUTO) {
910 s->master = s->vm_id == 0 ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
911 }
912
913 if (!ivshmem_is_master(s)) {
d855e275
MA
914 error_setg(&s->migration_blocker,
915 "Migration is disabled when using feature 'peer mode' in device 'ivshmem'");
916 migrate_add_blocker(s->migration_blocker);
6cbf4c8c 917 }
6cbf4c8c
CM
918}
919
5400c02b
MA
920static void ivshmem_exit(PCIDevice *dev)
921{
922 IVShmemState *s = IVSHMEM_COMMON(dev);
f64a078d
MAL
923 int i;
924
38e0735e
AL
925 if (s->migration_blocker) {
926 migrate_del_blocker(s->migration_blocker);
927 error_free(s->migration_blocker);
928 }
929
c2d8019c 930 if (memory_region_is_mapped(s->ivshmem_bar2)) {
d9453c93 931 if (!s->hostmem) {
c2d8019c 932 void *addr = memory_region_get_ram_ptr(s->ivshmem_bar2);
56a571d9 933 int fd;
d9453c93 934
5400c02b 935 if (munmap(addr, memory_region_size(s->ivshmem_bar2) == -1)) {
d9453c93
MAL
936 error_report("Failed to munmap shared memory %s",
937 strerror(errno));
938 }
56a571d9 939
4ff87573 940 fd = memory_region_get_fd(s->ivshmem_bar2);
c2d8019c 941 close(fd);
d9453c93 942 }
f64a078d 943
c2d8019c 944 vmstate_unregister_ram(s->ivshmem_bar2, DEVICE(dev));
f64a078d
MAL
945 }
946
f64a078d
MAL
947 if (s->peers) {
948 for (i = 0; i < s->nb_peers; i++) {
f456179f 949 close_peer_eventfds(s, i);
f64a078d
MAL
950 }
951 g_free(s->peers);
952 }
953
954 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
955 msix_uninit_exclusive_bar(dev);
956 }
957
0f57350e 958 g_free(s->msi_vectors);
6cbf4c8c
CM
959}
960
1f8552df
MAL
961static int ivshmem_pre_load(void *opaque)
962{
963 IVShmemState *s = opaque;
964
2a845da7 965 if (!ivshmem_is_master(s)) {
1f8552df
MAL
966 error_report("'peer' devices are not migratable");
967 return -EINVAL;
968 }
969
970 return 0;
971}
972
973static int ivshmem_post_load(void *opaque, int version_id)
974{
975 IVShmemState *s = opaque;
976
977 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
082751e8 978 ivshmem_msix_vector_use(s);
1f8552df 979 }
1f8552df
MAL
980 return 0;
981}
982
5400c02b 983static void ivshmem_common_class_init(ObjectClass *klass, void *data)
40021f08 984{
39bffca2 985 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL
986 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
987
5400c02b
MA
988 k->realize = ivshmem_common_realize;
989 k->exit = ivshmem_exit;
d58d7e84 990 k->config_write = ivshmem_write_config;
b8ef62a9
PB
991 k->vendor_id = PCI_VENDOR_ID_IVSHMEM;
992 k->device_id = PCI_DEVICE_ID_IVSHMEM;
40021f08 993 k->class_id = PCI_CLASS_MEMORY_RAM;
5400c02b 994 k->revision = 1;
39bffca2 995 dc->reset = ivshmem_reset;
125ee0ed 996 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
d383537d 997 dc->desc = "Inter-VM shared memory";
40021f08
AL
998}
999
ddc85284
MA
1000static const TypeInfo ivshmem_common_info = {
1001 .name = TYPE_IVSHMEM_COMMON,
1002 .parent = TYPE_PCI_DEVICE,
1003 .instance_size = sizeof(IVShmemState),
1004 .abstract = true,
1005 .class_init = ivshmem_common_class_init,
1006};
5400c02b 1007
d9453c93
MAL
1008static void ivshmem_check_memdev_is_busy(Object *obj, const char *name,
1009 Object *val, Error **errp)
1010{
2aece63c 1011 if (host_memory_backend_is_mapped(MEMORY_BACKEND(val))) {
d9453c93
MAL
1012 char *path = object_get_canonical_path_component(val);
1013 error_setg(errp, "can't use already busy memdev: %s", path);
1014 g_free(path);
1015 } else {
1016 qdev_prop_allow_set_link_before_realize(obj, name, val, errp);
1017 }
1018}
1019
5400c02b
MA
1020static const VMStateDescription ivshmem_plain_vmsd = {
1021 .name = TYPE_IVSHMEM_PLAIN,
1022 .version_id = 0,
1023 .minimum_version_id = 0,
1024 .pre_load = ivshmem_pre_load,
1025 .post_load = ivshmem_post_load,
1026 .fields = (VMStateField[]) {
1027 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1028 VMSTATE_UINT32(intrstatus, IVShmemState),
1029 VMSTATE_UINT32(intrmask, IVShmemState),
1030 VMSTATE_END_OF_LIST()
1031 },
1032};
1033
1034static Property ivshmem_plain_properties[] = {
1035 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1036 DEFINE_PROP_END_OF_LIST(),
1037};
1038
1039static void ivshmem_plain_init(Object *obj)
1040{
1041 IVShmemState *s = IVSHMEM_PLAIN(obj);
1042
1043 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
1044 (Object **)&s->hostmem,
1045 ivshmem_check_memdev_is_busy,
1046 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1047 &error_abort);
1048}
1049
6dc64780
MAL
1050static void ivshmem_plain_realize(PCIDevice *dev, Error **errp)
1051{
1052 IVShmemState *s = IVSHMEM_COMMON(dev);
1053
1054 if (!s->hostmem) {
1055 error_setg(errp, "You must specify a 'memdev'");
1056 return;
1057 }
1058
1059 ivshmem_common_realize(dev, errp);
2aece63c
XG
1060 host_memory_backend_set_mapped(s->hostmem, true);
1061}
1062
1063static void ivshmem_plain_exit(PCIDevice *pci_dev)
1064{
1065 IVShmemState *s = IVSHMEM_COMMON(pci_dev);
1066
1067 host_memory_backend_set_mapped(s->hostmem, false);
6dc64780
MAL
1068}
1069
5400c02b
MA
1070static void ivshmem_plain_class_init(ObjectClass *klass, void *data)
1071{
1072 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1073 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1074
6dc64780 1075 k->realize = ivshmem_plain_realize;
2aece63c 1076 k->exit = ivshmem_plain_exit;
5400c02b
MA
1077 dc->props = ivshmem_plain_properties;
1078 dc->vmsd = &ivshmem_plain_vmsd;
1079}
1080
1081static const TypeInfo ivshmem_plain_info = {
1082 .name = TYPE_IVSHMEM_PLAIN,
1083 .parent = TYPE_IVSHMEM_COMMON,
1084 .instance_size = sizeof(IVShmemState),
1085 .instance_init = ivshmem_plain_init,
1086 .class_init = ivshmem_plain_class_init,
1087};
1088
1089static const VMStateDescription ivshmem_doorbell_vmsd = {
1090 .name = TYPE_IVSHMEM_DOORBELL,
1091 .version_id = 0,
1092 .minimum_version_id = 0,
1093 .pre_load = ivshmem_pre_load,
1094 .post_load = ivshmem_post_load,
1095 .fields = (VMStateField[]) {
1096 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1097 VMSTATE_MSIX(parent_obj, IVShmemState),
1098 VMSTATE_UINT32(intrstatus, IVShmemState),
1099 VMSTATE_UINT32(intrmask, IVShmemState),
1100 VMSTATE_END_OF_LIST()
1101 },
1102};
1103
1104static Property ivshmem_doorbell_properties[] = {
1105 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1106 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1107 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1108 true),
1109 DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF),
1110 DEFINE_PROP_END_OF_LIST(),
1111};
1112
1113static void ivshmem_doorbell_init(Object *obj)
1114{
1115 IVShmemState *s = IVSHMEM_DOORBELL(obj);
1116
1117 s->features |= (1 << IVSHMEM_MSI);
1118 s->legacy_size = SIZE_MAX; /* whatever the server sends */
1119}
1120
6dc64780
MAL
1121static void ivshmem_doorbell_realize(PCIDevice *dev, Error **errp)
1122{
1123 IVShmemState *s = IVSHMEM_COMMON(dev);
1124
5345fdb4 1125 if (!qemu_chr_fe_get_driver(&s->server_chr)) {
6dc64780
MAL
1126 error_setg(errp, "You must specify a 'chardev'");
1127 return;
1128 }
1129
1130 ivshmem_common_realize(dev, errp);
1131}
1132
5400c02b
MA
1133static void ivshmem_doorbell_class_init(ObjectClass *klass, void *data)
1134{
1135 DeviceClass *dc = DEVICE_CLASS(klass);
6dc64780 1136 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
5400c02b 1137
6dc64780 1138 k->realize = ivshmem_doorbell_realize;
5400c02b
MA
1139 dc->props = ivshmem_doorbell_properties;
1140 dc->vmsd = &ivshmem_doorbell_vmsd;
1141}
1142
1143static const TypeInfo ivshmem_doorbell_info = {
1144 .name = TYPE_IVSHMEM_DOORBELL,
1145 .parent = TYPE_IVSHMEM_COMMON,
1146 .instance_size = sizeof(IVShmemState),
1147 .instance_init = ivshmem_doorbell_init,
1148 .class_init = ivshmem_doorbell_class_init,
1149};
1150
ddc85284
MA
1151static int ivshmem_load_old(QEMUFile *f, void *opaque, int version_id)
1152{
1153 IVShmemState *s = opaque;
1154 PCIDevice *pdev = PCI_DEVICE(s);
1155 int ret;
1156
1157 IVSHMEM_DPRINTF("ivshmem_load_old\n");
1158
1159 if (version_id != 0) {
1160 return -EINVAL;
1161 }
1162
1163 ret = ivshmem_pre_load(s);
1164 if (ret) {
1165 return ret;
1166 }
1167
1168 ret = pci_device_load(pdev, f);
1169 if (ret) {
1170 return ret;
1171 }
1172
1173 if (ivshmem_has_feature(s, IVSHMEM_MSI)) {
1174 msix_load(pdev, f);
1175 ivshmem_msix_vector_use(s);
1176 } else {
1177 s->intrstatus = qemu_get_be32(f);
1178 s->intrmask = qemu_get_be32(f);
1179 }
1180
1181 return 0;
1182}
1183
1184static bool test_msix(void *opaque, int version_id)
1185{
1186 IVShmemState *s = opaque;
1187
1188 return ivshmem_has_feature(s, IVSHMEM_MSI);
1189}
1190
1191static bool test_no_msix(void *opaque, int version_id)
1192{
1193 return !test_msix(opaque, version_id);
1194}
1195
1196static const VMStateDescription ivshmem_vmsd = {
1197 .name = "ivshmem",
1198 .version_id = 1,
1199 .minimum_version_id = 1,
1200 .pre_load = ivshmem_pre_load,
1201 .post_load = ivshmem_post_load,
1202 .fields = (VMStateField[]) {
1203 VMSTATE_PCI_DEVICE(parent_obj, IVShmemState),
1204
1205 VMSTATE_MSIX_TEST(parent_obj, IVShmemState, test_msix),
1206 VMSTATE_UINT32_TEST(intrstatus, IVShmemState, test_no_msix),
1207 VMSTATE_UINT32_TEST(intrmask, IVShmemState, test_no_msix),
1208
1209 VMSTATE_END_OF_LIST()
1210 },
1211 .load_state_old = ivshmem_load_old,
1212 .minimum_version_id_old = 0
1213};
1214
1215static Property ivshmem_properties[] = {
1216 DEFINE_PROP_CHR("chardev", IVShmemState, server_chr),
1217 DEFINE_PROP_STRING("size", IVShmemState, sizearg),
1218 DEFINE_PROP_UINT32("vectors", IVShmemState, vectors, 1),
1219 DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD,
1220 false),
1221 DEFINE_PROP_BIT("msi", IVShmemState, features, IVSHMEM_MSI, true),
1222 DEFINE_PROP_STRING("shm", IVShmemState, shmobj),
1223 DEFINE_PROP_STRING("role", IVShmemState, role),
1224 DEFINE_PROP_UINT32("use64", IVShmemState, not_legacy_32bit, 1),
1225 DEFINE_PROP_END_OF_LIST(),
1226};
1227
1228static void desugar_shm(IVShmemState *s)
1229{
1230 Object *obj;
1231 char *path;
1232
1233 obj = object_new("memory-backend-file");
1234 path = g_strdup_printf("/dev/shm/%s", s->shmobj);
1235 object_property_set_str(obj, path, "mem-path", &error_abort);
1236 g_free(path);
1237 object_property_set_int(obj, s->legacy_size, "size", &error_abort);
1238 object_property_set_bool(obj, true, "share", &error_abort);
1239 object_property_add_child(OBJECT(s), "internal-shm-backend", obj,
1240 &error_abort);
1241 user_creatable_complete(obj, &error_abort);
1242 s->hostmem = MEMORY_BACKEND(obj);
1243}
1244
1245static void ivshmem_realize(PCIDevice *dev, Error **errp)
1246{
1247 IVShmemState *s = IVSHMEM_COMMON(dev);
1248
1249 if (!qtest_enabled()) {
1250 error_report("ivshmem is deprecated, please use ivshmem-plain"
1251 " or ivshmem-doorbell instead");
1252 }
1253
5345fdb4 1254 if (!!qemu_chr_fe_get_driver(&s->server_chr) + !!s->shmobj != 1) {
13fd2cb6 1255 error_setg(errp, "You must specify either 'shm' or 'chardev'");
ddc85284
MA
1256 return;
1257 }
1258
13fd2cb6 1259 if (s->sizearg == NULL) {
ddc85284
MA
1260 s->legacy_size = 4 << 20; /* 4 MB default */
1261 } else {
1262 char *end;
1263 int64_t size = qemu_strtosz(s->sizearg, &end);
1264 if (size < 0 || (size_t)size != size || *end != '\0'
1265 || !is_power_of_2(size)) {
1266 error_setg(errp, "Invalid size %s", s->sizearg);
1267 return;
1268 }
1269 s->legacy_size = size;
1270 }
1271
1272 /* check that role is reasonable */
1273 if (s->role) {
1274 if (strncmp(s->role, "peer", 5) == 0) {
1275 s->master = ON_OFF_AUTO_OFF;
1276 } else if (strncmp(s->role, "master", 7) == 0) {
1277 s->master = ON_OFF_AUTO_ON;
1278 } else {
1279 error_setg(errp, "'role' must be 'peer' or 'master'");
1280 return;
1281 }
1282 } else {
1283 s->master = ON_OFF_AUTO_AUTO;
1284 }
1285
1286 if (s->shmobj) {
1287 desugar_shm(s);
1288 }
1289
1290 /*
1291 * Note: we don't use INTx with IVSHMEM_MSI at all, so this is a
1292 * bald-faced lie then. But it's a backwards compatible lie.
1293 */
1294 pci_config_set_interrupt_pin(dev->config, 1);
1295
1296 ivshmem_common_realize(dev, errp);
1297}
1298
ddc85284
MA
1299static void ivshmem_class_init(ObjectClass *klass, void *data)
1300{
1301 DeviceClass *dc = DEVICE_CLASS(klass);
1302 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1303
1304 k->realize = ivshmem_realize;
1305 k->revision = 0;
1306 dc->desc = "Inter-VM shared memory (legacy)";
1307 dc->props = ivshmem_properties;
1308 dc->vmsd = &ivshmem_vmsd;
1309}
1310
1311static const TypeInfo ivshmem_info = {
1312 .name = TYPE_IVSHMEM,
1313 .parent = TYPE_IVSHMEM_COMMON,
1314 .instance_size = sizeof(IVShmemState),
ddc85284
MA
1315 .class_init = ivshmem_class_init,
1316};
1317
83f7d43a 1318static void ivshmem_register_types(void)
6cbf4c8c 1319{
5400c02b
MA
1320 type_register_static(&ivshmem_common_info);
1321 type_register_static(&ivshmem_plain_info);
1322 type_register_static(&ivshmem_doorbell_info);
39bffca2 1323 type_register_static(&ivshmem_info);
6cbf4c8c
CM
1324}
1325
83f7d43a 1326type_init(ivshmem_register_types)
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