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target-mips: Implement FCR31's R/W bitmask and related functionalities
[qemu.git] / linux-user / main.c
CommitLineData
31e31b8a 1/*
93ac68bc 2 * qemu user main
5fafdf24 3 *
68d0f70e 4 * Copyright (c) 2003-2008 Fabrice Bellard
31e31b8a
FB		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
8167ee88 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31e31b8a 18 */
d39594e9 19#include "qemu/osdep.h"
67a1de0d 20#include "qemu-version.h"
edf8e2af 21#include <sys/syscall.h>
703e0e89 22#include <sys/resource.h>
31e31b8a 23
daa76aa4 24#include "qapi/error.h"
3ef693a0 25#include "qemu.h"
f348b6d1
VB		 26#include "qemu/path.h"
27#include "qemu/cutils.h"
28#include "qemu/help_option.h"
2b41f10e 29#include "cpu.h"
63c91552 30#include "exec/exec-all.h"
9002ec79 31#include "tcg.h"
1de7afc9
PB		 32#include "qemu/timer.h"
33#include "qemu/envlist.h"
d8fd2954 34#include "elf.h"
508127e2 35#include "exec/log.h"
04a6dfeb 36
d088d664
AJ		 37char *exec_path;
38
1b530a6d 39int singlestep;
8cb76755
SW		 40static const char *filename;
41static const char *argv0;
42static int gdbstub_port;
43static envlist_t *envlist;
51fb256a 44static const char *cpu_model;
379f6698
PB		 45unsigned long mmap_min_addr;
46unsigned long guest_base;
47int have_guest_base;
120a9848
PB		 48
49#define EXCP_DUMP(env, fmt, ...) \
50do { \
51 CPUState *cs = ENV_GET_CPU(env); \
52 fprintf(stderr, fmt , ## __VA_ARGS__); \
53 cpu_dump_state(cs, stderr, fprintf, 0); \
54 if (qemu_log_separate()) { \
55 qemu_log(fmt, ## __VA_ARGS__); \
56 log_cpu_state(cs, 0); \
57 } \
58} while (0)
59
288e65b9
AG		 60#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
61/*
62 * When running 32-on-64 we should make sure we can fit all of the possible
63 * guest address space into a contiguous chunk of virtual host memory.
64 *
65 * This way we will never overlap with our own libraries or binaries or stack
66 * or anything else that QEMU maps.
67 */
314992b1
AG		 68# ifdef TARGET_MIPS
69/* MIPS only supports 31 bits of virtual address space for user space */
70unsigned long reserved_va = 0x77000000;
71# else
288e65b9 72unsigned long reserved_va = 0xf7000000;
314992b1 73# endif
288e65b9 74#else
68a1c816 75unsigned long reserved_va;
379f6698 76#endif
1b530a6d 77
d03f9c32 78static void usage(int exitcode);
fc9c5412 79
7ee2822c 80static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
e586822a 81const char *qemu_uname_release;
586314f2 82
9de5e440
FB		 83/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
84 we allocate a bigger stack. Need a better solution, for example
85 by remapping the process stack directly at the right place */
703e0e89 86unsigned long guest_stack_size = 8 * 1024 * 1024UL;
31e31b8a
FB		 87
88void gemu_log(const char *fmt, ...)
89{
90 va_list ap;
91
92 va_start(ap, fmt);
93 vfprintf(stderr, fmt, ap);
94 va_end(ap);
95}
96
8fcd3692 97#if defined(TARGET_I386)
05390248 98int cpu_get_pic_interrupt(CPUX86State *env)
92ccca6a
FB		 99{
100 return -1;
101}
8fcd3692 102#endif
92ccca6a 103
d5975363
PB		 104/***********************************************************/
105/* Helper routines for implementing atomic operations. */
106
107/* To implement exclusive operations we force all cpus to syncronise.
108 We don't require a full sync, only that no cpus are executing guest code.
109 The alternative is to map target atomic ops onto host equivalents,
110 which requires quite a lot of per host/target work. */
c2764719 111static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
d5975363
PB		 112static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
113static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
114static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
115static int pending_cpus;
116
117/* Make sure everything is in a consistent state for calling fork(). */
118void fork_start(void)
119{
677ef623 120 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 121 pthread_mutex_lock(&exclusive_lock);
d032d1b4 122 mmap_fork_start();
d5975363
PB		 123}
124
125void fork_end(int child)
126{
d032d1b4 127 mmap_fork_end(child);
d5975363 128 if (child) {
bdc44640 129 CPUState *cpu, *next_cpu;
d5975363
PB		 130 /* Child processes created by fork() only have a single thread.
131 Discard information about the parent threads. */
bdc44640
AF		 132 CPU_FOREACH_SAFE(cpu, next_cpu) {
133 if (cpu != thread_cpu) {
014628a7 134 QTAILQ_REMOVE(&cpus, cpu, node);
bdc44640
AF		 135 }
136 }
d5975363
PB		 137 pending_cpus = 0;
138 pthread_mutex_init(&exclusive_lock, NULL);
c2764719 139 pthread_mutex_init(&cpu_list_mutex, NULL);
d5975363
PB		 140 pthread_cond_init(&exclusive_cond, NULL);
141 pthread_cond_init(&exclusive_resume, NULL);
677ef623 142 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
f7ec7f7b 143 gdbserver_fork(thread_cpu);
d5975363
PB		 144 } else {
145 pthread_mutex_unlock(&exclusive_lock);
677ef623 146 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
d5975363 147 }
d5975363
PB		 148}
149
150/* Wait for pending exclusive operations to complete. The exclusive lock
151 must be held. */
152static inline void exclusive_idle(void)
153{
154 while (pending_cpus) {
155 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
156 }
157}
158
159/* Start an exclusive operation.
160 Must only be called from outside cpu_arm_exec. */
161static inline void start_exclusive(void)
162{
0315c31c
AF		 163 CPUState *other_cpu;
164
d5975363
PB		 165 pthread_mutex_lock(&exclusive_lock);
166 exclusive_idle();
167
168 pending_cpus = 1;
169 /* Make all other cpus stop executing. */
bdc44640 170 CPU_FOREACH(other_cpu) {
0315c31c 171 if (other_cpu->running) {
d5975363 172 pending_cpus++;
60a3e17a 173 cpu_exit(other_cpu);
d5975363
PB		 174 }
175 }
176 if (pending_cpus > 1) {
177 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
178 }
179}
180
181/* Finish an exclusive operation. */
f7e61b22 182static inline void __attribute__((unused)) end_exclusive(void)
d5975363
PB		 183{
184 pending_cpus = 0;
185 pthread_cond_broadcast(&exclusive_resume);
186 pthread_mutex_unlock(&exclusive_lock);
187}
188
189/* Wait for exclusive ops to finish, and begin cpu execution. */
0315c31c 190static inline void cpu_exec_start(CPUState *cpu)
d5975363
PB		 191{
192 pthread_mutex_lock(&exclusive_lock);
193 exclusive_idle();
0315c31c 194 cpu->running = true;
d5975363
PB		 195 pthread_mutex_unlock(&exclusive_lock);
196}
197
198/* Mark cpu as not executing, and release pending exclusive ops. */
0315c31c 199static inline void cpu_exec_end(CPUState *cpu)
d5975363
PB		 200{
201 pthread_mutex_lock(&exclusive_lock);
0315c31c 202 cpu->running = false;
d5975363
PB		 203 if (pending_cpus > 1) {
204 pending_cpus--;
205 if (pending_cpus == 1) {
206 pthread_cond_signal(&exclusive_cond);
207 }
208 }
209 exclusive_idle();
210 pthread_mutex_unlock(&exclusive_lock);
211}
c2764719
PB		 212
213void cpu_list_lock(void)
214{
215 pthread_mutex_lock(&cpu_list_mutex);
216}
217
218void cpu_list_unlock(void)
219{
220 pthread_mutex_unlock(&cpu_list_mutex);
221}
d5975363
PB		 222
223
a541f297
FB		 224#ifdef TARGET_I386
225/***********************************************************/
226/* CPUX86 core interface */
227
28ab0e2e
FB		 228uint64_t cpu_get_tsc(CPUX86State *env)
229{
4a7428c5 230 return cpu_get_host_ticks();
28ab0e2e
FB		 231}
232
5fafdf24 233static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
f4beb510 234 int flags)
6dbad63e 235{
f4beb510 236 unsigned int e1, e2;
53a5960a 237 uint32_t *p;
6dbad63e
FB		 238 e1 = (addr << 16) | (limit & 0xffff);
239 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
f4beb510 240 e2 |= flags;
53a5960a 241 p = ptr;
d538e8f5 242 p[0] = tswap32(e1);
243 p[1] = tswap32(e2);
f4beb510
FB		 244}
245
e441570f 246static uint64_t *idt_table;
eb38c52c 247#ifdef TARGET_X86_64
d2fd1af7
FB		 248static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
249 uint64_t addr, unsigned int sel)
f4beb510 250{
4dbc422b 251 uint32_t *p, e1, e2;
f4beb510
FB		 252 e1 = (addr & 0xffff) | (sel << 16);
253 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
53a5960a 254 p = ptr;
4dbc422b
FB		 255 p[0] = tswap32(e1);
256 p[1] = tswap32(e2);
257 p[2] = tswap32(addr >> 32);
258 p[3] = 0;
6dbad63e 259}
d2fd1af7
FB		 260/* only dpl matters as we do only user space emulation */
261static void set_idt(int n, unsigned int dpl)
262{
263 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
264}
265#else
d2fd1af7
FB		 266static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
267 uint32_t addr, unsigned int sel)
268{
4dbc422b 269 uint32_t *p, e1, e2;
d2fd1af7
FB		 270 e1 = (addr & 0xffff) | (sel << 16);
271 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
272 p = ptr;
4dbc422b
FB		 273 p[0] = tswap32(e1);
274 p[1] = tswap32(e2);
d2fd1af7
FB		 275}
276
f4beb510
FB		 277/* only dpl matters as we do only user space emulation */
278static void set_idt(int n, unsigned int dpl)
279{
280 set_gate(idt_table + n, 0, dpl, 0, 0);
281}
d2fd1af7 282#endif
31e31b8a 283
89e957e7 284void cpu_loop(CPUX86State *env)
1b6b029e 285{
db6b81d4 286 CPUState *cs = CPU(x86_env_get_cpu(env));
bc8a22cc 287 int trapnr;
992f48a0 288 abi_ulong pc;
0284b03b 289 abi_ulong ret;
c227f099 290 target_siginfo_t info;
851e67a1 291
1b6b029e 292 for(;;) {
b040bc9c 293 cpu_exec_start(cs);
ea3e9847 294 trapnr = cpu_x86_exec(cs);
b040bc9c 295 cpu_exec_end(cs);
bc8a22cc 296 switch(trapnr) {
f4beb510 297 case 0x80:
d2fd1af7 298 /* linux syscall from int $0x80 */
0284b03b
TB		 299 ret = do_syscall(env,
300 env->regs[R_EAX],
301 env->regs[R_EBX],
302 env->regs[R_ECX],
303 env->regs[R_EDX],
304 env->regs[R_ESI],
305 env->regs[R_EDI],
306 env->regs[R_EBP],
307 0, 0);
308 if (ret == -TARGET_ERESTARTSYS) {
309 env->eip -= 2;
310 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
311 env->regs[R_EAX] = ret;
312 }
f4beb510 313 break;
d2fd1af7
FB		 314#ifndef TARGET_ABI32
315 case EXCP_SYSCALL:
5ba18547 316 /* linux syscall from syscall instruction */
0284b03b
TB		 317 ret = do_syscall(env,
318 env->regs[R_EAX],
319 env->regs[R_EDI],
320 env->regs[R_ESI],
321 env->regs[R_EDX],
322 env->regs[10],
323 env->regs[8],
324 env->regs[9],
325 0, 0);
326 if (ret == -TARGET_ERESTARTSYS) {
327 env->eip -= 2;
328 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
329 env->regs[R_EAX] = ret;
330 }
d2fd1af7
FB		 331 break;
332#endif
f4beb510
FB		 333 case EXCP0B_NOSEG:
334 case EXCP0C_STACK:
a86b3c64 335 info.si_signo = TARGET_SIGBUS;
f4beb510
FB		 336 info.si_errno = 0;
337 info.si_code = TARGET_SI_KERNEL;
338 info._sifields._sigfault._addr = 0;
624f7979 339 queue_signal(env, info.si_signo, &info);
f4beb510 340 break;
1b6b029e 341 case EXCP0D_GPF:
d2fd1af7 342 /* XXX: potential problem if ABI32 */
84409ddb 343#ifndef TARGET_X86_64
851e67a1 344 if (env->eflags & VM_MASK) {
89e957e7 345 handle_vm86_fault(env);
84409ddb
JM		 346 } else
347#endif
348 {
a86b3c64 349 info.si_signo = TARGET_SIGSEGV;
f4beb510
FB		 350 info.si_errno = 0;
351 info.si_code = TARGET_SI_KERNEL;
352 info._sifields._sigfault._addr = 0;
624f7979 353 queue_signal(env, info.si_signo, &info);
1b6b029e
FB		 354 }
355 break;
b689bc57 356 case EXCP0E_PAGE:
a86b3c64 357 info.si_signo = TARGET_SIGSEGV;
b689bc57
FB		 358 info.si_errno = 0;
359 if (!(env->error_code & 1))
360 info.si_code = TARGET_SEGV_MAPERR;
361 else
362 info.si_code = TARGET_SEGV_ACCERR;
970a87a6 363 info._sifields._sigfault._addr = env->cr[2];
624f7979 364 queue_signal(env, info.si_signo, &info);
b689bc57 365 break;
9de5e440 366 case EXCP00_DIVZ:
84409ddb 367#ifndef TARGET_X86_64
bc8a22cc 368 if (env->eflags & VM_MASK) {
447db213 369 handle_vm86_trap(env, trapnr);
84409ddb
JM		 370 } else
371#endif
372 {
bc8a22cc 373 /* division by zero */
a86b3c64 374 info.si_signo = TARGET_SIGFPE;
bc8a22cc
FB		 375 info.si_errno = 0;
376 info.si_code = TARGET_FPE_INTDIV;
377 info._sifields._sigfault._addr = env->eip;
624f7979 378 queue_signal(env, info.si_signo, &info);
bc8a22cc 379 }
9de5e440 380 break;
01df040b 381 case EXCP01_DB:
447db213 382 case EXCP03_INT3:
84409ddb 383#ifndef TARGET_X86_64
447db213
FB		 384 if (env->eflags & VM_MASK) {
385 handle_vm86_trap(env, trapnr);
84409ddb
JM		 386 } else
387#endif
388 {
a86b3c64 389 info.si_signo = TARGET_SIGTRAP;
447db213 390 info.si_errno = 0;
01df040b 391 if (trapnr == EXCP01_DB) {
447db213
FB		 392 info.si_code = TARGET_TRAP_BRKPT;
393 info._sifields._sigfault._addr = env->eip;
394 } else {
395 info.si_code = TARGET_SI_KERNEL;
396 info._sifields._sigfault._addr = 0;
397 }
624f7979 398 queue_signal(env, info.si_signo, &info);
447db213
FB		 399 }
400 break;
9de5e440
FB		 401 case EXCP04_INTO:
402 case EXCP05_BOUND:
84409ddb 403#ifndef TARGET_X86_64
bc8a22cc 404 if (env->eflags & VM_MASK) {
447db213 405 handle_vm86_trap(env, trapnr);
84409ddb
JM		 406 } else
407#endif
408 {
a86b3c64 409 info.si_signo = TARGET_SIGSEGV;
bc8a22cc 410 info.si_errno = 0;
b689bc57 411 info.si_code = TARGET_SI_KERNEL;
bc8a22cc 412 info._sifields._sigfault._addr = 0;
624f7979 413 queue_signal(env, info.si_signo, &info);
bc8a22cc 414 }
9de5e440
FB		 415 break;
416 case EXCP06_ILLOP:
a86b3c64 417 info.si_signo = TARGET_SIGILL;
9de5e440
FB		 418 info.si_errno = 0;
419 info.si_code = TARGET_ILL_ILLOPN;
420 info._sifields._sigfault._addr = env->eip;
624f7979 421 queue_signal(env, info.si_signo, &info);
9de5e440
FB		 422 break;
423 case EXCP_INTERRUPT:
424 /* just indicate that signals should be handled asap */
425 break;
1fddef4b
FB		 426 case EXCP_DEBUG:
427 {
428 int sig;
429
db6b81d4 430 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 431 if (sig)
432 {
433 info.si_signo = sig;
434 info.si_errno = 0;
435 info.si_code = TARGET_TRAP_BRKPT;
624f7979 436 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 437 }
438 }
439 break;
1b6b029e 440 default:
970a87a6 441 pc = env->segs[R_CS].base + env->eip;
120a9848
PB		 442 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
443 (long)pc, trapnr);
1b6b029e
FB		 444 abort();
445 }
66fb9763 446 process_pending_signals(env);
1b6b029e
FB		 447 }
448}
b346ff46
FB		 449#endif
450
451#ifdef TARGET_ARM
452
49017bd8 453#define get_user_code_u32(x, gaddr, env) \
d8fd2954 454 ({ abi_long __r = get_user_u32((x), (gaddr)); \
f9fd40eb 455 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 456 (x) = bswap32(x); \
457 } \
458 __r; \
459 })
460
49017bd8 461#define get_user_code_u16(x, gaddr, env) \
d8fd2954 462 ({ abi_long __r = get_user_u16((x), (gaddr)); \
f9fd40eb 463 if (!__r && bswap_code(arm_sctlr_b(env))) { \
d8fd2954
PB		 464 (x) = bswap16(x); \
465 } \
466 __r; \
467 })
468
c3ae85fc
PB		 469#define get_user_data_u32(x, gaddr, env) \
470 ({ abi_long __r = get_user_u32((x), (gaddr)); \
471 if (!__r && arm_cpu_bswap_data(env)) { \
472 (x) = bswap32(x); \
473 } \
474 __r; \
475 })
476
477#define get_user_data_u16(x, gaddr, env) \
478 ({ abi_long __r = get_user_u16((x), (gaddr)); \
479 if (!__r && arm_cpu_bswap_data(env)) { \
480 (x) = bswap16(x); \
481 } \
482 __r; \
483 })
484
485#define put_user_data_u32(x, gaddr, env) \
486 ({ typeof(x) __x = (x); \
487 if (arm_cpu_bswap_data(env)) { \
488 __x = bswap32(__x); \
489 } \
490 put_user_u32(__x, (gaddr)); \
491 })
492
493#define put_user_data_u16(x, gaddr, env) \
494 ({ typeof(x) __x = (x); \
495 if (arm_cpu_bswap_data(env)) { \
496 __x = bswap16(__x); \
497 } \
498 put_user_u16(__x, (gaddr)); \
499 })
500
1861c454
PM		 501#ifdef TARGET_ABI32
502/* Commpage handling -- there is no commpage for AArch64 */
503
97cc7560
DDAG		 504/*
505 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
506 * Input:
507 * r0 = pointer to oldval
508 * r1 = pointer to newval
509 * r2 = pointer to target value
510 *
511 * Output:
512 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
513 * C set if *ptr was changed, clear if no exchange happened
514 *
515 * Note segv's in kernel helpers are a bit tricky, we can set the
516 * data address sensibly but the PC address is just the entry point.
517 */
518static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
519{
520 uint64_t oldval, newval, val;
521 uint32_t addr, cpsr;
522 target_siginfo_t info;
523
524 /* Based on the 32 bit code in do_kernel_trap */
525
526 /* XXX: This only works between threads, not between processes.
527 It's probably possible to implement this with native host
528 operations. However things like ldrex/strex are much harder so
529 there's not much point trying. */
530 start_exclusive();
531 cpsr = cpsr_read(env);
532 addr = env->regs[2];
533
534 if (get_user_u64(oldval, env->regs[0])) {
abf1172f 535 env->exception.vaddress = env->regs[0];
97cc7560
DDAG		 536 goto segv;
537 };
538
539 if (get_user_u64(newval, env->regs[1])) {
abf1172f 540 env->exception.vaddress = env->regs[1];
97cc7560
DDAG		 541 goto segv;
542 };
543
544 if (get_user_u64(val, addr)) {
abf1172f 545 env->exception.vaddress = addr;
97cc7560
DDAG		 546 goto segv;
547 }
548
549 if (val == oldval) {
550 val = newval;
551
552 if (put_user_u64(val, addr)) {
abf1172f 553 env->exception.vaddress = addr;
97cc7560
DDAG		 554 goto segv;
555 };
556
557 env->regs[0] = 0;
558 cpsr |= CPSR_C;
559 } else {
560 env->regs[0] = -1;
561 cpsr &= ~CPSR_C;
562 }
50866ba5 563 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
97cc7560
DDAG		 564 end_exclusive();
565 return;
566
567segv:
568 end_exclusive();
569 /* We get the PC of the entry address - which is as good as anything,
570 on a real kernel what you get depends on which mode it uses. */
a86b3c64 571 info.si_signo = TARGET_SIGSEGV;
97cc7560
DDAG		 572 info.si_errno = 0;
573 /* XXX: check env->error_code */
574 info.si_code = TARGET_SEGV_MAPERR;
abf1172f 575 info._sifields._sigfault._addr = env->exception.vaddress;
97cc7560 576 queue_signal(env, info.si_signo, &info);
97cc7560
DDAG		 577}
578
fbb4a2e3
PB		 579/* Handle a jump to the kernel code page. */
580static int
581do_kernel_trap(CPUARMState *env)
582{
583 uint32_t addr;
584 uint32_t cpsr;
585 uint32_t val;
586
587 switch (env->regs[15]) {
588 case 0xffff0fa0: /* __kernel_memory_barrier */
589 /* ??? No-op. Will need to do better for SMP. */
590 break;
591 case 0xffff0fc0: /* __kernel_cmpxchg */
d5975363
PB		 592 /* XXX: This only works between threads, not between processes.
593 It's probably possible to implement this with native host
594 operations. However things like ldrex/strex are much harder so
595 there's not much point trying. */
596 start_exclusive();
fbb4a2e3
PB		 597 cpsr = cpsr_read(env);
598 addr = env->regs[2];
599 /* FIXME: This should SEGV if the access fails. */
600 if (get_user_u32(val, addr))
601 val = ~env->regs[0];
602 if (val == env->regs[0]) {
603 val = env->regs[1];
604 /* FIXME: Check for segfaults. */
605 put_user_u32(val, addr);
606 env->regs[0] = 0;
607 cpsr |= CPSR_C;
608 } else {
609 env->regs[0] = -1;
610 cpsr &= ~CPSR_C;
611 }
50866ba5 612 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
d5975363 613 end_exclusive();
fbb4a2e3
PB		 614 break;
615 case 0xffff0fe0: /* __kernel_get_tls */
b8d43285 616 env->regs[0] = cpu_get_tls(env);
fbb4a2e3 617 break;
97cc7560
DDAG		 618 case 0xffff0f60: /* __kernel_cmpxchg64 */
619 arm_kernel_cmpxchg64_helper(env);
620 break;
621
fbb4a2e3
PB		 622 default:
623 return 1;
624 }
625 /* Jump back to the caller. */
626 addr = env->regs[14];
627 if (addr & 1) {
628 env->thumb = 1;
629 addr &= ~1;
630 }
631 env->regs[15] = addr;
632
633 return 0;
634}
635
fa2ef212 636/* Store exclusive handling for AArch32 */
426f5abc
PB		 637static int do_strex(CPUARMState *env)
638{
03d05e2d 639 uint64_t val;
426f5abc
PB		 640 int size;
641 int rc = 1;
642 int segv = 0;
643 uint32_t addr;
644 start_exclusive();
03d05e2d 645 if (env->exclusive_addr != env->exclusive_test) {
426f5abc
PB		 646 goto fail;
647 }
03d05e2d
PM		 648 /* We know we're always AArch32 so the address is in uint32_t range
649 * unless it was the -1 exclusive-monitor-lost value (which won't
650 * match exclusive_test above).
651 */
652 assert(extract64(env->exclusive_addr, 32, 32) == 0);
653 addr = env->exclusive_addr;
426f5abc
PB		 654 size = env->exclusive_info & 0xf;
655 switch (size) {
656 case 0:
657 segv = get_user_u8(val, addr);
658 break;
659 case 1:
c3ae85fc 660 segv = get_user_data_u16(val, addr, env);
426f5abc
PB		 661 break;
662 case 2:
663 case 3:
c3ae85fc 664 segv = get_user_data_u32(val, addr, env);
426f5abc 665 break;
f7001a3b
AJ		 666 default:
667 abort();
426f5abc
PB		 668 }
669 if (segv) {
abf1172f 670 env->exception.vaddress = addr;
426f5abc
PB		 671 goto done;
672 }
426f5abc 673 if (size == 3) {
03d05e2d 674 uint32_t valhi;
c3ae85fc 675 segv = get_user_data_u32(valhi, addr + 4, env);
426f5abc 676 if (segv) {
abf1172f 677 env->exception.vaddress = addr + 4;
426f5abc
PB		 678 goto done;
679 }
c3ae85fc
PB		 680 if (arm_cpu_bswap_data(env)) {
681 val = deposit64((uint64_t)valhi, 32, 32, val);
682 } else {
683 val = deposit64(val, 32, 32, valhi);
684 }
426f5abc 685 }
03d05e2d
PM		 686 if (val != env->exclusive_val) {
687 goto fail;
688 }
689
426f5abc
PB		 690 val = env->regs[(env->exclusive_info >> 8) & 0xf];
691 switch (size) {
692 case 0:
693 segv = put_user_u8(val, addr);
694 break;
695 case 1:
c3ae85fc 696 segv = put_user_data_u16(val, addr, env);
426f5abc
PB		 697 break;
698 case 2:
699 case 3:
c3ae85fc 700 segv = put_user_data_u32(val, addr, env);
426f5abc
PB		 701 break;
702 }
703 if (segv) {
abf1172f 704 env->exception.vaddress = addr;
426f5abc
PB		 705 goto done;
706 }
707 if (size == 3) {
708 val = env->regs[(env->exclusive_info >> 12) & 0xf];
c3ae85fc 709 segv = put_user_data_u32(val, addr + 4, env);
426f5abc 710 if (segv) {
abf1172f 711 env->exception.vaddress = addr + 4;
426f5abc
PB		 712 goto done;
713 }
714 }
715 rc = 0;
716fail:
725b8a69 717 env->regs[15] += 4;
426f5abc
PB		 718 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
719done:
720 end_exclusive();
721 return segv;
722}
723
b346ff46
FB		 724void cpu_loop(CPUARMState *env)
725{
0315c31c 726 CPUState *cs = CPU(arm_env_get_cpu(env));
b346ff46
FB		 727 int trapnr;
728 unsigned int n, insn;
c227f099 729 target_siginfo_t info;
b5ff1b31 730 uint32_t addr;
f0267ef7 731 abi_ulong ret;
3b46e624 732
b346ff46 733 for(;;) {
0315c31c 734 cpu_exec_start(cs);
ea3e9847 735 trapnr = cpu_arm_exec(cs);
0315c31c 736 cpu_exec_end(cs);
b346ff46
FB		 737 switch(trapnr) {
738 case EXCP_UDEF:
c6981055 739 {
0429a971 740 TaskState *ts = cs->opaque;
c6981055 741 uint32_t opcode;
6d9a42be 742 int rc;
c6981055
FB		 743
744 /* we handle the FPU emulation here, as Linux */
745 /* we get the opcode */
2f619698 746 /* FIXME - what to do if get_user() fails? */
49017bd8 747 get_user_code_u32(opcode, env->regs[15], env);
3b46e624 748
6d9a42be
AJ		 749 rc = EmulateAll(opcode, &ts->fpa, env);
750 if (rc == 0) { /* illegal instruction */
a86b3c64 751 info.si_signo = TARGET_SIGILL;
c6981055
FB		 752 info.si_errno = 0;
753 info.si_code = TARGET_ILL_ILLOPN;
754 info._sifields._sigfault._addr = env->regs[15];
624f7979 755 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 756 } else if (rc < 0) { /* FP exception */
757 int arm_fpe=0;
758
759 /* translate softfloat flags to FPSR flags */
760 if (-rc & float_flag_invalid)
761 arm_fpe |= BIT_IOC;
762 if (-rc & float_flag_divbyzero)
763 arm_fpe |= BIT_DZC;
764 if (-rc & float_flag_overflow)
765 arm_fpe |= BIT_OFC;
766 if (-rc & float_flag_underflow)
767 arm_fpe |= BIT_UFC;
768 if (-rc & float_flag_inexact)
769 arm_fpe |= BIT_IXC;
770
771 FPSR fpsr = ts->fpa.fpsr;
772 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
773
774 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
a86b3c64 775 info.si_signo = TARGET_SIGFPE;
6d9a42be
AJ		 776 info.si_errno = 0;
777
778 /* ordered by priority, least first */
779 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
780 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
781 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
782 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
783 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
784
785 info._sifields._sigfault._addr = env->regs[15];
624f7979 786 queue_signal(env, info.si_signo, &info);
6d9a42be
AJ		 787 } else {
788 env->regs[15] += 4;
789 }
790
791 /* accumulate unenabled exceptions */
792 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
793 fpsr |= BIT_IXC;
794 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
795 fpsr |= BIT_UFC;
796 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
797 fpsr |= BIT_OFC;
798 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
799 fpsr |= BIT_DZC;
800 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
801 fpsr |= BIT_IOC;
802 ts->fpa.fpsr=fpsr;
803 } else { /* everything OK */
c6981055
FB		 804 /* increment PC */
805 env->regs[15] += 4;
806 }
807 }
b346ff46
FB		 808 break;
809 case EXCP_SWI:
06c949e6 810 case EXCP_BKPT:
b346ff46 811 {
ce4defa0 812 env->eabi = 1;
b346ff46 813 /* system call */
06c949e6
PB		 814 if (trapnr == EXCP_BKPT) {
815 if (env->thumb) {
2f619698 816 /* FIXME - what to do if get_user() fails? */
49017bd8 817 get_user_code_u16(insn, env->regs[15], env);
06c949e6
PB		 818 n = insn & 0xff;
819 env->regs[15] += 2;
820 } else {
2f619698 821 /* FIXME - what to do if get_user() fails? */
49017bd8 822 get_user_code_u32(insn, env->regs[15], env);
06c949e6
PB		 823 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
824 env->regs[15] += 4;
825 }
192c7bd9 826 } else {
06c949e6 827 if (env->thumb) {
2f619698 828 /* FIXME - what to do if get_user() fails? */
49017bd8 829 get_user_code_u16(insn, env->regs[15] - 2, env);
06c949e6
PB		 830 n = insn & 0xff;
831 } else {
2f619698 832 /* FIXME - what to do if get_user() fails? */
49017bd8 833 get_user_code_u32(insn, env->regs[15] - 4, env);
06c949e6
PB		 834 n = insn & 0xffffff;
835 }
192c7bd9
FB		 836 }
837
6f1f31c0 838 if (n == ARM_NR_cacheflush) {
dcfd14b3 839 /* nop */
a4f81979
FB		 840 } else if (n == ARM_NR_semihosting
841 || n == ARM_NR_thumb_semihosting) {
842 env->regs[0] = do_arm_semihosting (env);
3a1363ac 843 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
b346ff46 844 /* linux syscall */
ce4defa0 845 if (env->thumb || n == 0) {
192c7bd9
FB		 846 n = env->regs[7];
847 } else {
848 n -= ARM_SYSCALL_BASE;
ce4defa0 849 env->eabi = 0;
192c7bd9 850 }
fbb4a2e3
PB		 851 if ( n > ARM_NR_BASE) {
852 switch (n) {
853 case ARM_NR_cacheflush:
dcfd14b3 854 /* nop */
fbb4a2e3
PB		 855 break;
856 case ARM_NR_set_tls:
857 cpu_set_tls(env, env->regs[0]);
858 env->regs[0] = 0;
859 break;
d5355087
HL		 860 case ARM_NR_breakpoint:
861 env->regs[15] -= env->thumb ? 2 : 4;
862 goto excp_debug;
fbb4a2e3
PB		 863 default:
864 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
865 n);
866 env->regs[0] = -TARGET_ENOSYS;
867 break;
868 }
869 } else {
f0267ef7
TB		 870 ret = do_syscall(env,
871 n,
872 env->regs[0],
873 env->regs[1],
874 env->regs[2],
875 env->regs[3],
876 env->regs[4],
877 env->regs[5],
878 0, 0);
879 if (ret == -TARGET_ERESTARTSYS) {
880 env->regs[15] -= env->thumb ? 2 : 4;
881 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
882 env->regs[0] = ret;
883 }
fbb4a2e3 884 }
b346ff46
FB		 885 } else {
886 goto error;
887 }
888 }
889 break;
43fff238
FB		 890 case EXCP_INTERRUPT:
891 /* just indicate that signals should be handled asap */
892 break;
abf1172f
PM		 893 case EXCP_STREX:
894 if (!do_strex(env)) {
895 break;
896 }
897 /* fall through for segv */
68016c62
FB		 898 case EXCP_PREFETCH_ABORT:
899 case EXCP_DATA_ABORT:
abf1172f 900 addr = env->exception.vaddress;
68016c62 901 {
a86b3c64 902 info.si_signo = TARGET_SIGSEGV;
68016c62
FB		 903 info.si_errno = 0;
904 /* XXX: check env->error_code */
905 info.si_code = TARGET_SEGV_MAPERR;
b5ff1b31 906 info._sifields._sigfault._addr = addr;
624f7979 907 queue_signal(env, info.si_signo, &info);
68016c62
FB		 908 }
909 break;
1fddef4b 910 case EXCP_DEBUG:
d5355087 911 excp_debug:
1fddef4b
FB		 912 {
913 int sig;
914
db6b81d4 915 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 916 if (sig)
917 {
918 info.si_signo = sig;
919 info.si_errno = 0;
920 info.si_code = TARGET_TRAP_BRKPT;
624f7979 921 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 922 }
923 }
924 break;
fbb4a2e3
PB		 925 case EXCP_KERNEL_TRAP:
926 if (do_kernel_trap(env))
927 goto error;
928 break;
f911e0a3
PM		 929 case EXCP_YIELD:
930 /* nothing to do here for user-mode, just resume guest code */
931 break;
b346ff46
FB		 932 default:
933 error:
120a9848 934 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
b346ff46
FB		 935 abort();
936 }
937 process_pending_signals(env);
938 }
939}
940
1861c454
PM		 941#else
942
fa2ef212
MM		 943/*
944 * Handle AArch64 store-release exclusive
945 *
946 * rs = gets the status result of store exclusive
947 * rt = is the register that is stored
948 * rt2 = is the second register store (in STP)
949 *
950 */
951static int do_strex_a64(CPUARMState *env)
952{
953 uint64_t val;
954 int size;
955 bool is_pair;
956 int rc = 1;
957 int segv = 0;
958 uint64_t addr;
959 int rs, rt, rt2;
960
961 start_exclusive();
962 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
963 size = extract32(env->exclusive_info, 0, 2);
964 is_pair = extract32(env->exclusive_info, 2, 1);
965 rs = extract32(env->exclusive_info, 4, 5);
966 rt = extract32(env->exclusive_info, 9, 5);
967 rt2 = extract32(env->exclusive_info, 14, 5);
968
969 addr = env->exclusive_addr;
970
971 if (addr != env->exclusive_test) {
972 goto finish;
973 }
974
975 switch (size) {
976 case 0:
977 segv = get_user_u8(val, addr);
978 break;
979 case 1:
980 segv = get_user_u16(val, addr);
981 break;
982 case 2:
983 segv = get_user_u32(val, addr);
984 break;
985 case 3:
986 segv = get_user_u64(val, addr);
987 break;
988 default:
989 abort();
990 }
991 if (segv) {
abf1172f 992 env->exception.vaddress = addr;
fa2ef212
MM		 993 goto error;
994 }
995 if (val != env->exclusive_val) {
996 goto finish;
997 }
998 if (is_pair) {
999 if (size == 2) {
1000 segv = get_user_u32(val, addr + 4);
1001 } else {
1002 segv = get_user_u64(val, addr + 8);
1003 }
1004 if (segv) {
abf1172f 1005 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1006 goto error;
1007 }
1008 if (val != env->exclusive_high) {
1009 goto finish;
1010 }
1011 }
2ea5a2ca
JG		 1012 /* handle the zero register */
1013 val = rt == 31 ? 0 : env->xregs[rt];
fa2ef212
MM		 1014 switch (size) {
1015 case 0:
1016 segv = put_user_u8(val, addr);
1017 break;
1018 case 1:
1019 segv = put_user_u16(val, addr);
1020 break;
1021 case 2:
1022 segv = put_user_u32(val, addr);
1023 break;
1024 case 3:
1025 segv = put_user_u64(val, addr);
1026 break;
1027 }
1028 if (segv) {
1029 goto error;
1030 }
1031 if (is_pair) {
2ea5a2ca
JG		 1032 /* handle the zero register */
1033 val = rt2 == 31 ? 0 : env->xregs[rt2];
fa2ef212
MM		 1034 if (size == 2) {
1035 segv = put_user_u32(val, addr + 4);
1036 } else {
1037 segv = put_user_u64(val, addr + 8);
1038 }
1039 if (segv) {
abf1172f 1040 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
fa2ef212
MM		 1041 goto error;
1042 }
1043 }
1044 rc = 0;
1045finish:
1046 env->pc += 4;
1047 /* rs == 31 encodes a write to the ZR, thus throwing away
1048 * the status return. This is rather silly but valid.
1049 */
1050 if (rs < 31) {
1051 env->xregs[rs] = rc;
1052 }
1053error:
1054 /* instruction faulted, PC does not advance */
1055 /* either way a strex releases any exclusive lock we have */
1056 env->exclusive_addr = -1;
1057 end_exclusive();
1058 return segv;
1059}
1060
1861c454
PM		 1061/* AArch64 main loop */
1062void cpu_loop(CPUARMState *env)
1063{
1064 CPUState *cs = CPU(arm_env_get_cpu(env));
1065 int trapnr, sig;
f0267ef7 1066 abi_long ret;
1861c454 1067 target_siginfo_t info;
1861c454
PM		 1068
1069 for (;;) {
1070 cpu_exec_start(cs);
ea3e9847 1071 trapnr = cpu_arm_exec(cs);
1861c454
PM		 1072 cpu_exec_end(cs);
1073
1074 switch (trapnr) {
1075 case EXCP_SWI:
f0267ef7
TB		 1076 ret = do_syscall(env,
1077 env->xregs[8],
1078 env->xregs[0],
1079 env->xregs[1],
1080 env->xregs[2],
1081 env->xregs[3],
1082 env->xregs[4],
1083 env->xregs[5],
1084 0, 0);
1085 if (ret == -TARGET_ERESTARTSYS) {
1086 env->pc -= 4;
1087 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1088 env->xregs[0] = ret;
1089 }
1861c454
PM		 1090 break;
1091 case EXCP_INTERRUPT:
1092 /* just indicate that signals should be handled asap */
1093 break;
1094 case EXCP_UDEF:
a86b3c64 1095 info.si_signo = TARGET_SIGILL;
1861c454
PM		 1096 info.si_errno = 0;
1097 info.si_code = TARGET_ILL_ILLOPN;
1098 info._sifields._sigfault._addr = env->pc;
1099 queue_signal(env, info.si_signo, &info);
1100 break;
abf1172f
PM		 1101 case EXCP_STREX:
1102 if (!do_strex_a64(env)) {
1103 break;
1104 }
1105 /* fall through for segv */
1861c454 1106 case EXCP_PREFETCH_ABORT:
1861c454 1107 case EXCP_DATA_ABORT:
a86b3c64 1108 info.si_signo = TARGET_SIGSEGV;
1861c454
PM		 1109 info.si_errno = 0;
1110 /* XXX: check env->error_code */
1111 info.si_code = TARGET_SEGV_MAPERR;
686581ad 1112 info._sifields._sigfault._addr = env->exception.vaddress;
1861c454
PM		 1113 queue_signal(env, info.si_signo, &info);
1114 break;
1115 case EXCP_DEBUG:
1116 case EXCP_BKPT:
1117 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1118 if (sig) {
1119 info.si_signo = sig;
1120 info.si_errno = 0;
1121 info.si_code = TARGET_TRAP_BRKPT;
1122 queue_signal(env, info.si_signo, &info);
1123 }
1124 break;
8012c84f
PM		 1125 case EXCP_SEMIHOST:
1126 env->xregs[0] = do_arm_semihosting(env);
1127 break;
f911e0a3
PM		 1128 case EXCP_YIELD:
1129 /* nothing to do here for user-mode, just resume guest code */
1130 break;
1861c454 1131 default:
120a9848 1132 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1861c454
PM		 1133 abort();
1134 }
1135 process_pending_signals(env);
fa2ef212
MM		 1136 /* Exception return on AArch64 always clears the exclusive monitor,
1137 * so any return to running guest code implies this.
1138 * A strex (successful or otherwise) also clears the monitor, so
1139 * we don't need to specialcase EXCP_STREX.
1140 */
1141 env->exclusive_addr = -1;
1861c454
PM		 1142 }
1143}
1144#endif /* ndef TARGET_ABI32 */
1145
b346ff46 1146#endif
1b6b029e 1147
d2fbca94
GX		 1148#ifdef TARGET_UNICORE32
1149
05390248 1150void cpu_loop(CPUUniCore32State *env)
d2fbca94 1151{
0315c31c 1152 CPUState *cs = CPU(uc32_env_get_cpu(env));
d2fbca94
GX		 1153 int trapnr;
1154 unsigned int n, insn;
1155 target_siginfo_t info;
1156
1157 for (;;) {
0315c31c 1158 cpu_exec_start(cs);
ea3e9847 1159 trapnr = uc32_cpu_exec(cs);
0315c31c 1160 cpu_exec_end(cs);
d2fbca94
GX		 1161 switch (trapnr) {
1162 case UC32_EXCP_PRIV:
1163 {
1164 /* system call */
1165 get_user_u32(insn, env->regs[31] - 4);
1166 n = insn & 0xffffff;
1167
1168 if (n >= UC32_SYSCALL_BASE) {
1169 /* linux syscall */
1170 n -= UC32_SYSCALL_BASE;
1171 if (n == UC32_SYSCALL_NR_set_tls) {
1172 cpu_set_tls(env, env->regs[0]);
1173 env->regs[0] = 0;
1174 } else {
256cb6af 1175 abi_long ret = do_syscall(env,
d2fbca94
GX		 1176 n,
1177 env->regs[0],
1178 env->regs[1],
1179 env->regs[2],
1180 env->regs[3],
1181 env->regs[4],
5945cfcb
PM		 1182 env->regs[5],
1183 0, 0);
256cb6af
TB		 1184 if (ret == -TARGET_ERESTARTSYS) {
1185 env->regs[31] -= 4;
1186 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1187 env->regs[0] = ret;
1188 }
d2fbca94
GX		 1189 }
1190 } else {
1191 goto error;
1192 }
1193 }
1194 break;
d48813dd
GX		 1195 case UC32_EXCP_DTRAP:
1196 case UC32_EXCP_ITRAP:
a86b3c64 1197 info.si_signo = TARGET_SIGSEGV;
d2fbca94
GX		 1198 info.si_errno = 0;
1199 /* XXX: check env->error_code */
1200 info.si_code = TARGET_SEGV_MAPERR;
1201 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1202 queue_signal(env, info.si_signo, &info);
1203 break;
1204 case EXCP_INTERRUPT:
1205 /* just indicate that signals should be handled asap */
1206 break;
1207 case EXCP_DEBUG:
1208 {
1209 int sig;
1210
db6b81d4 1211 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d2fbca94
GX		 1212 if (sig) {
1213 info.si_signo = sig;
1214 info.si_errno = 0;
1215 info.si_code = TARGET_TRAP_BRKPT;
1216 queue_signal(env, info.si_signo, &info);
1217 }
1218 }
1219 break;
1220 default:
1221 goto error;
1222 }
1223 process_pending_signals(env);
1224 }
1225
1226error:
120a9848 1227 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
d2fbca94
GX		 1228 abort();
1229}
1230#endif
1231
93ac68bc 1232#ifdef TARGET_SPARC
ed23fbd9 1233#define SPARC64_STACK_BIAS 2047
93ac68bc 1234
060366c5
FB		 1235//#define DEBUG_WIN
1236
2623cbaf
FB		 1237/* WARNING: dealing with register windows _is_ complicated. More info
1238 can be found at http://www.sics.se/~psm/sparcstack.html */
060366c5
FB		 1239static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1240{
1a14026e 1241 index = (index + cwp * 16) % (16 * env->nwindows);
060366c5
FB		 1242 /* wrap handling : if cwp is on the last window, then we use the
1243 registers 'after' the end */
1a14026e
BS		 1244 if (index < 8 && env->cwp == env->nwindows - 1)
1245 index += 16 * env->nwindows;
060366c5
FB		 1246 return index;
1247}
1248
2623cbaf
FB		 1249/* save the register window 'cwp1' */
1250static inline void save_window_offset(CPUSPARCState *env, int cwp1)
060366c5 1251{
2623cbaf 1252 unsigned int i;
992f48a0 1253 abi_ulong sp_ptr;
3b46e624 1254
53a5960a 1255 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1256#ifdef TARGET_SPARC64
1257 if (sp_ptr & 3)
1258 sp_ptr += SPARC64_STACK_BIAS;
1259#endif
060366c5 1260#if defined(DEBUG_WIN)
2daf0284
BS		 1261 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1262 sp_ptr, cwp1);
060366c5 1263#endif
2623cbaf 1264 for(i = 0; i < 16; i++) {
2f619698
FB		 1265 /* FIXME - what to do if put_user() fails? */
1266 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1267 sp_ptr += sizeof(abi_ulong);
2623cbaf 1268 }
060366c5
FB		 1269}
1270
1271static void save_window(CPUSPARCState *env)
1272{
5ef54116 1273#ifndef TARGET_SPARC64
2623cbaf 1274 unsigned int new_wim;
1a14026e
BS		 1275 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1276 ((1LL << env->nwindows) - 1);
1277 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
2623cbaf 1278 env->wim = new_wim;
5ef54116 1279#else
1a14026e 1280 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
5ef54116
FB		 1281 env->cansave++;
1282 env->canrestore--;
1283#endif
060366c5
FB		 1284}
1285
1286static void restore_window(CPUSPARCState *env)
1287{
eda52953
BS		 1288#ifndef TARGET_SPARC64
1289 unsigned int new_wim;
1290#endif
1291 unsigned int i, cwp1;
992f48a0 1292 abi_ulong sp_ptr;
3b46e624 1293
eda52953 1294#ifndef TARGET_SPARC64
1a14026e
BS		 1295 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1296 ((1LL << env->nwindows) - 1);
eda52953 1297#endif
3b46e624 1298
060366c5 1299 /* restore the invalid window */
1a14026e 1300 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
53a5960a 1301 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
ed23fbd9
BS		 1302#ifdef TARGET_SPARC64
1303 if (sp_ptr & 3)
1304 sp_ptr += SPARC64_STACK_BIAS;
1305#endif
060366c5 1306#if defined(DEBUG_WIN)
2daf0284
BS		 1307 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1308 sp_ptr, cwp1);
060366c5 1309#endif
2623cbaf 1310 for(i = 0; i < 16; i++) {
2f619698
FB		 1311 /* FIXME - what to do if get_user() fails? */
1312 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
992f48a0 1313 sp_ptr += sizeof(abi_ulong);
2623cbaf 1314 }
5ef54116
FB		 1315#ifdef TARGET_SPARC64
1316 env->canrestore++;
1a14026e
BS		 1317 if (env->cleanwin < env->nwindows - 1)
1318 env->cleanwin++;
5ef54116 1319 env->cansave--;
eda52953
BS		 1320#else
1321 env->wim = new_wim;
5ef54116 1322#endif
060366c5
FB		 1323}
1324
1325static void flush_windows(CPUSPARCState *env)
1326{
1327 int offset, cwp1;
2623cbaf
FB		 1328
1329 offset = 1;
060366c5
FB		 1330 for(;;) {
1331 /* if restore would invoke restore_window(), then we can stop */
1a14026e 1332 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
eda52953 1333#ifndef TARGET_SPARC64
060366c5
FB		 1334 if (env->wim & (1 << cwp1))
1335 break;
eda52953
BS		 1336#else
1337 if (env->canrestore == 0)
1338 break;
1339 env->cansave++;
1340 env->canrestore--;
1341#endif
2623cbaf 1342 save_window_offset(env, cwp1);
060366c5
FB		 1343 offset++;
1344 }
1a14026e 1345 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
eda52953
BS		 1346#ifndef TARGET_SPARC64
1347 /* set wim so that restore will reload the registers */
2623cbaf 1348 env->wim = 1 << cwp1;
eda52953 1349#endif
2623cbaf
FB		 1350#if defined(DEBUG_WIN)
1351 printf("flush_windows: nb=%d\n", offset - 1);
80a9d035 1352#endif
2623cbaf 1353}
060366c5 1354
93ac68bc
FB		 1355void cpu_loop (CPUSPARCState *env)
1356{
878096ee 1357 CPUState *cs = CPU(sparc_env_get_cpu(env));
2cc20260
RH		 1358 int trapnr;
1359 abi_long ret;
c227f099 1360 target_siginfo_t info;
3b46e624 1361
060366c5 1362 while (1) {
b040bc9c 1363 cpu_exec_start(cs);
ea3e9847 1364 trapnr = cpu_sparc_exec(cs);
b040bc9c 1365 cpu_exec_end(cs);
3b46e624 1366
20132b96
RH		 1367 /* Compute PSR before exposing state. */
1368 if (env->cc_op != CC_OP_FLAGS) {
1369 cpu_get_psr(env);
1370 }
1371
060366c5 1372 switch (trapnr) {
5ef54116 1373#ifndef TARGET_SPARC64
5fafdf24 1374 case 0x88:
060366c5 1375 case 0x90:
5ef54116 1376#else
cb33da57 1377 case 0x110:
5ef54116
FB		 1378 case 0x16d:
1379#endif
060366c5 1380 ret = do_syscall (env, env->gregs[1],
5fafdf24
TS		 1381 env->regwptr[0], env->regwptr[1],
1382 env->regwptr[2], env->regwptr[3],
5945cfcb
PM		 1383 env->regwptr[4], env->regwptr[5],
1384 0, 0);
c0bea68f
TB		 1385 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1386 break;
1387 }
2cc20260 1388 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
992f48a0 1389#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1390 env->xcc |= PSR_CARRY;
1391#else
060366c5 1392 env->psr |= PSR_CARRY;
27908725 1393#endif
060366c5
FB		 1394 ret = -ret;
1395 } else {
992f48a0 1396#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
27908725
FB		 1397 env->xcc &= ~PSR_CARRY;
1398#else
060366c5 1399 env->psr &= ~PSR_CARRY;
27908725 1400#endif
060366c5
FB		 1401 }
1402 env->regwptr[0] = ret;
1403 /* next instruction */
1404 env->pc = env->npc;
1405 env->npc = env->npc + 4;
1406 break;
1407 case 0x83: /* flush windows */
992f48a0
BS		 1408#ifdef TARGET_ABI32
1409 case 0x103:
1410#endif
2623cbaf 1411 flush_windows(env);
060366c5
FB		 1412 /* next instruction */
1413 env->pc = env->npc;
1414 env->npc = env->npc + 4;
1415 break;
3475187d 1416#ifndef TARGET_SPARC64
060366c5
FB		 1417 case TT_WIN_OVF: /* window overflow */
1418 save_window(env);
1419 break;
1420 case TT_WIN_UNF: /* window underflow */
1421 restore_window(env);
1422 break;
61ff6f58
FB		 1423 case TT_TFAULT:
1424 case TT_DFAULT:
1425 {
59f7182f 1426 info.si_signo = TARGET_SIGSEGV;
61ff6f58
FB		 1427 info.si_errno = 0;
1428 /* XXX: check env->error_code */
1429 info.si_code = TARGET_SEGV_MAPERR;
1430 info._sifields._sigfault._addr = env->mmuregs[4];
624f7979 1431 queue_signal(env, info.si_signo, &info);
61ff6f58
FB		 1432 }
1433 break;
3475187d 1434#else
5ef54116
FB		 1435 case TT_SPILL: /* window overflow */
1436 save_window(env);
1437 break;
1438 case TT_FILL: /* window underflow */
1439 restore_window(env);
1440 break;
7f84a729
BS		 1441 case TT_TFAULT:
1442 case TT_DFAULT:
1443 {
59f7182f 1444 info.si_signo = TARGET_SIGSEGV;
7f84a729
BS		 1445 info.si_errno = 0;
1446 /* XXX: check env->error_code */
1447 info.si_code = TARGET_SEGV_MAPERR;
1448 if (trapnr == TT_DFAULT)
1449 info._sifields._sigfault._addr = env->dmmuregs[4];
1450 else
8194f35a 1451 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
624f7979 1452 queue_signal(env, info.si_signo, &info);
7f84a729
BS		 1453 }
1454 break;
27524dc3 1455#ifndef TARGET_ABI32
5bfb56b2
BS		 1456 case 0x16e:
1457 flush_windows(env);
1458 sparc64_get_context(env);
1459 break;
1460 case 0x16f:
1461 flush_windows(env);
1462 sparc64_set_context(env);
1463 break;
27524dc3 1464#endif
3475187d 1465#endif
48dc41eb
FB		 1466 case EXCP_INTERRUPT:
1467 /* just indicate that signals should be handled asap */
1468 break;
75f22e4e
RH		 1469 case TT_ILL_INSN:
1470 {
1471 info.si_signo = TARGET_SIGILL;
1472 info.si_errno = 0;
1473 info.si_code = TARGET_ILL_ILLOPC;
1474 info._sifields._sigfault._addr = env->pc;
1475 queue_signal(env, info.si_signo, &info);
1476 }
1477 break;
1fddef4b
FB		 1478 case EXCP_DEBUG:
1479 {
1480 int sig;
1481
db6b81d4 1482 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1fddef4b
FB		 1483 if (sig)
1484 {
1485 info.si_signo = sig;
1486 info.si_errno = 0;
1487 info.si_code = TARGET_TRAP_BRKPT;
624f7979 1488 queue_signal(env, info.si_signo, &info);
1fddef4b
FB		 1489 }
1490 }
1491 break;
060366c5
FB		 1492 default:
1493 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 1494 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 1495 exit(EXIT_FAILURE);
060366c5
FB		 1496 }
1497 process_pending_signals (env);
1498 }
93ac68bc
FB		 1499}
1500
1501#endif
1502
67867308 1503#ifdef TARGET_PPC
05390248 1504static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
9fddaa0c 1505{
4a7428c5 1506 return cpu_get_host_ticks();
9fddaa0c 1507}
3b46e624 1508
05390248 1509uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
9fddaa0c 1510{
e3ea6529 1511 return cpu_ppc_get_tb(env);
9fddaa0c 1512}
3b46e624 1513
05390248 1514uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
9fddaa0c
FB		 1515{
1516 return cpu_ppc_get_tb(env) >> 32;
1517}
3b46e624 1518
05390248 1519uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
9fddaa0c 1520{
b711de95 1521 return cpu_ppc_get_tb(env);
9fddaa0c 1522}
5fafdf24 1523
05390248 1524uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
9fddaa0c 1525{
a062e36c 1526 return cpu_ppc_get_tb(env) >> 32;
9fddaa0c 1527}
76a66253 1528
05390248 1529uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
76a66253
JM		 1530__attribute__ (( alias ("cpu_ppc_load_tbu") ));
1531
05390248 1532uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
9fddaa0c 1533{
76a66253 1534 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
9fddaa0c 1535}
76a66253 1536
a750fc0b 1537/* XXX: to be fixed */
73b01960 1538int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
a750fc0b
JM		 1539{
1540 return -1;
1541}
1542
73b01960 1543int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
a750fc0b
JM		 1544{
1545 return -1;
1546}
1547
56f066bb
NF		 1548static int do_store_exclusive(CPUPPCState *env)
1549{
1550 target_ulong addr;
1551 target_ulong page_addr;
e22c357b 1552 target_ulong val, val2 __attribute__((unused)) = 0;
56f066bb
NF		 1553 int flags;
1554 int segv = 0;
1555
1556 addr = env->reserve_ea;
1557 page_addr = addr & TARGET_PAGE_MASK;
1558 start_exclusive();
1559 mmap_lock();
1560 flags = page_get_flags(page_addr);
1561 if ((flags & PAGE_READ) == 0) {
1562 segv = 1;
1563 } else {
1564 int reg = env->reserve_info & 0x1f;
4b1daa72 1565 int size = env->reserve_info >> 5;
56f066bb
NF		 1566 int stored = 0;
1567
1568 if (addr == env->reserve_addr) {
1569 switch (size) {
1570 case 1: segv = get_user_u8(val, addr); break;
1571 case 2: segv = get_user_u16(val, addr); break;
1572 case 4: segv = get_user_u32(val, addr); break;
1573#if defined(TARGET_PPC64)
1574 case 8: segv = get_user_u64(val, addr); break;
27b95bfe
TM		 1575 case 16: {
1576 segv = get_user_u64(val, addr);
1577 if (!segv) {
1578 segv = get_user_u64(val2, addr + 8);
1579 }
1580 break;
1581 }
56f066bb
NF		 1582#endif
1583 default: abort();
1584 }
1585 if (!segv && val == env->reserve_val) {
1586 val = env->gpr[reg];
1587 switch (size) {
1588 case 1: segv = put_user_u8(val, addr); break;
1589 case 2: segv = put_user_u16(val, addr); break;
1590 case 4: segv = put_user_u32(val, addr); break;
1591#if defined(TARGET_PPC64)
1592 case 8: segv = put_user_u64(val, addr); break;
27b95bfe
TM		 1593 case 16: {
1594 if (val2 == env->reserve_val2) {
e22c357b
DK		 1595 if (msr_le) {
1596 val2 = val;
1597 val = env->gpr[reg+1];
1598 } else {
1599 val2 = env->gpr[reg+1];
1600 }
27b95bfe
TM		 1601 segv = put_user_u64(val, addr);
1602 if (!segv) {
1603 segv = put_user_u64(val2, addr + 8);
1604 }
1605 }
1606 break;
1607 }
56f066bb
NF		 1608#endif
1609 default: abort();
1610 }
1611 if (!segv) {
1612 stored = 1;
1613 }
1614 }
1615 }
1616 env->crf[0] = (stored << 1) | xer_so;
1617 env->reserve_addr = (target_ulong)-1;
1618 }
1619 if (!segv) {
1620 env->nip += 4;
1621 }
1622 mmap_unlock();
1623 end_exclusive();
1624 return segv;
1625}
1626
67867308
FB		 1627void cpu_loop(CPUPPCState *env)
1628{
0315c31c 1629 CPUState *cs = CPU(ppc_env_get_cpu(env));
c227f099 1630 target_siginfo_t info;
61190b14 1631 int trapnr;
9e0e2f96 1632 target_ulong ret;
3b46e624 1633
67867308 1634 for(;;) {
0315c31c 1635 cpu_exec_start(cs);
ea3e9847 1636 trapnr = cpu_ppc_exec(cs);
0315c31c 1637 cpu_exec_end(cs);
67867308 1638 switch(trapnr) {
e1833e1f
JM		 1639 case POWERPC_EXCP_NONE:
1640 /* Just go on */
67867308 1641 break;
e1833e1f 1642 case POWERPC_EXCP_CRITICAL: /* Critical input */
a47dddd7 1643 cpu_abort(cs, "Critical interrupt while in user mode. "
e1833e1f 1644 "Aborting\n");
61190b14 1645 break;
e1833e1f 1646 case POWERPC_EXCP_MCHECK: /* Machine check exception */
a47dddd7 1647 cpu_abort(cs, "Machine check exception while in user mode. "
e1833e1f
JM		 1648 "Aborting\n");
1649 break;
1650 case POWERPC_EXCP_DSI: /* Data storage exception */
90e189ec 1651 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
e1833e1f
JM		 1652 env->spr[SPR_DAR]);
1653 /* XXX: check this. Seems bugged */
2be0071f
FB		 1654 switch (env->error_code & 0xFF000000) {
1655 case 0x40000000:
61190b14
FB		 1656 info.si_signo = TARGET_SIGSEGV;
1657 info.si_errno = 0;
1658 info.si_code = TARGET_SEGV_MAPERR;
1659 break;
2be0071f 1660 case 0x04000000:
61190b14
FB		 1661 info.si_signo = TARGET_SIGILL;
1662 info.si_errno = 0;
1663 info.si_code = TARGET_ILL_ILLADR;
1664 break;
2be0071f 1665 case 0x08000000:
61190b14
FB		 1666 info.si_signo = TARGET_SIGSEGV;
1667 info.si_errno = 0;
1668 info.si_code = TARGET_SEGV_ACCERR;
1669 break;
61190b14
FB		 1670 default:
1671 /* Let's send a regular segfault... */
e1833e1f
JM		 1672 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1673 env->error_code);
61190b14
FB		 1674 info.si_signo = TARGET_SIGSEGV;
1675 info.si_errno = 0;
1676 info.si_code = TARGET_SEGV_MAPERR;
1677 break;
1678 }
67867308 1679 info._sifields._sigfault._addr = env->nip;
624f7979 1680 queue_signal(env, info.si_signo, &info);
67867308 1681 break;
e1833e1f 1682 case POWERPC_EXCP_ISI: /* Instruction storage exception */
90e189ec
BS		 1683 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1684 "\n", env->spr[SPR_SRR0]);
e1833e1f 1685 /* XXX: check this */
2be0071f
FB		 1686 switch (env->error_code & 0xFF000000) {
1687 case 0x40000000:
61190b14 1688 info.si_signo = TARGET_SIGSEGV;
67867308 1689 info.si_errno = 0;
61190b14
FB		 1690 info.si_code = TARGET_SEGV_MAPERR;
1691 break;
2be0071f
FB		 1692 case 0x10000000:
1693 case 0x08000000:
61190b14
FB		 1694 info.si_signo = TARGET_SIGSEGV;
1695 info.si_errno = 0;
1696 info.si_code = TARGET_SEGV_ACCERR;
1697 break;
1698 default:
1699 /* Let's send a regular segfault... */
e1833e1f
JM		 1700 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1701 env->error_code);
61190b14
FB		 1702 info.si_signo = TARGET_SIGSEGV;
1703 info.si_errno = 0;
1704 info.si_code = TARGET_SEGV_MAPERR;
1705 break;
1706 }
1707 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1708 queue_signal(env, info.si_signo, &info);
67867308 1709 break;
e1833e1f 1710 case POWERPC_EXCP_EXTERNAL: /* External input */
a47dddd7 1711 cpu_abort(cs, "External interrupt while in user mode. "
e1833e1f
JM		 1712 "Aborting\n");
1713 break;
1714 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1715 EXCP_DUMP(env, "Unaligned memory access\n");
1716 /* XXX: check this */
61190b14 1717 info.si_signo = TARGET_SIGBUS;
67867308 1718 info.si_errno = 0;
61190b14 1719 info.si_code = TARGET_BUS_ADRALN;
6bb9a0a9 1720 info._sifields._sigfault._addr = env->nip;
624f7979 1721 queue_signal(env, info.si_signo, &info);
67867308 1722 break;
e1833e1f 1723 case POWERPC_EXCP_PROGRAM: /* Program exception */
9b2fadda 1724 case POWERPC_EXCP_HV_EMU: /* HV emulation */
e1833e1f 1725 /* XXX: check this */
61190b14 1726 switch (env->error_code & ~0xF) {
e1833e1f
JM		 1727 case POWERPC_EXCP_FP:
1728 EXCP_DUMP(env, "Floating point program exception\n");
61190b14
FB		 1729 info.si_signo = TARGET_SIGFPE;
1730 info.si_errno = 0;
1731 switch (env->error_code & 0xF) {
e1833e1f 1732 case POWERPC_EXCP_FP_OX:
61190b14
FB		 1733 info.si_code = TARGET_FPE_FLTOVF;
1734 break;
e1833e1f 1735 case POWERPC_EXCP_FP_UX:
61190b14
FB		 1736 info.si_code = TARGET_FPE_FLTUND;
1737 break;
e1833e1f
JM		 1738 case POWERPC_EXCP_FP_ZX:
1739 case POWERPC_EXCP_FP_VXZDZ:
61190b14
FB		 1740 info.si_code = TARGET_FPE_FLTDIV;
1741 break;
e1833e1f 1742 case POWERPC_EXCP_FP_XX:
61190b14
FB		 1743 info.si_code = TARGET_FPE_FLTRES;
1744 break;
e1833e1f 1745 case POWERPC_EXCP_FP_VXSOFT:
61190b14
FB		 1746 info.si_code = TARGET_FPE_FLTINV;
1747 break;
7c58044c 1748 case POWERPC_EXCP_FP_VXSNAN:
e1833e1f
JM		 1749 case POWERPC_EXCP_FP_VXISI:
1750 case POWERPC_EXCP_FP_VXIDI:
1751 case POWERPC_EXCP_FP_VXIMZ:
1752 case POWERPC_EXCP_FP_VXVC:
1753 case POWERPC_EXCP_FP_VXSQRT:
1754 case POWERPC_EXCP_FP_VXCVI:
61190b14
FB		 1755 info.si_code = TARGET_FPE_FLTSUB;
1756 break;
1757 default:
e1833e1f
JM		 1758 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1759 env->error_code);
1760 break;
61190b14 1761 }
e1833e1f
JM		 1762 break;
1763 case POWERPC_EXCP_INVAL:
1764 EXCP_DUMP(env, "Invalid instruction\n");
61190b14
FB		 1765 info.si_signo = TARGET_SIGILL;
1766 info.si_errno = 0;
1767 switch (env->error_code & 0xF) {
e1833e1f 1768 case POWERPC_EXCP_INVAL_INVAL:
61190b14
FB		 1769 info.si_code = TARGET_ILL_ILLOPC;
1770 break;
e1833e1f 1771 case POWERPC_EXCP_INVAL_LSWX:
a750fc0b 1772 info.si_code = TARGET_ILL_ILLOPN;
61190b14 1773 break;
e1833e1f 1774 case POWERPC_EXCP_INVAL_SPR:
61190b14
FB		 1775 info.si_code = TARGET_ILL_PRVREG;
1776 break;
e1833e1f 1777 case POWERPC_EXCP_INVAL_FP:
61190b14
FB		 1778 info.si_code = TARGET_ILL_COPROC;
1779 break;
1780 default:
e1833e1f
JM		 1781 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1782 env->error_code & 0xF);
61190b14
FB		 1783 info.si_code = TARGET_ILL_ILLADR;
1784 break;
1785 }
1786 break;
e1833e1f
JM		 1787 case POWERPC_EXCP_PRIV:
1788 EXCP_DUMP(env, "Privilege violation\n");
61190b14
FB		 1789 info.si_signo = TARGET_SIGILL;
1790 info.si_errno = 0;
1791 switch (env->error_code & 0xF) {
e1833e1f 1792 case POWERPC_EXCP_PRIV_OPC:
61190b14
FB		 1793 info.si_code = TARGET_ILL_PRVOPC;
1794 break;
e1833e1f 1795 case POWERPC_EXCP_PRIV_REG:
61190b14 1796 info.si_code = TARGET_ILL_PRVREG;
e1833e1f 1797 break;
61190b14 1798 default:
e1833e1f
JM		 1799 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1800 env->error_code & 0xF);
61190b14
FB		 1801 info.si_code = TARGET_ILL_PRVOPC;
1802 break;
1803 }
1804 break;
e1833e1f 1805 case POWERPC_EXCP_TRAP:
a47dddd7 1806 cpu_abort(cs, "Tried to call a TRAP\n");
e1833e1f 1807 break;
61190b14
FB		 1808 default:
1809 /* Should not happen ! */
a47dddd7 1810 cpu_abort(cs, "Unknown program exception (%02x)\n",
e1833e1f
JM		 1811 env->error_code);
1812 break;
61190b14
FB		 1813 }
1814 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1815 queue_signal(env, info.si_signo, &info);
67867308 1816 break;
e1833e1f
JM		 1817 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1818 EXCP_DUMP(env, "No floating point allowed\n");
61190b14 1819 info.si_signo = TARGET_SIGILL;
67867308 1820 info.si_errno = 0;
61190b14
FB		 1821 info.si_code = TARGET_ILL_COPROC;
1822 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1823 queue_signal(env, info.si_signo, &info);
67867308 1824 break;
e1833e1f 1825 case POWERPC_EXCP_SYSCALL: /* System call exception */
a47dddd7 1826 cpu_abort(cs, "Syscall exception while in user mode. "
e1833e1f 1827 "Aborting\n");
61190b14 1828 break;
e1833e1f
JM		 1829 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1830 EXCP_DUMP(env, "No APU instruction allowed\n");
1831 info.si_signo = TARGET_SIGILL;
1832 info.si_errno = 0;
1833 info.si_code = TARGET_ILL_COPROC;
1834 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1835 queue_signal(env, info.si_signo, &info);
61190b14 1836 break;
e1833e1f 1837 case POWERPC_EXCP_DECR: /* Decrementer exception */
a47dddd7 1838 cpu_abort(cs, "Decrementer interrupt while in user mode. "
e1833e1f 1839 "Aborting\n");
61190b14 1840 break;
e1833e1f 1841 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
a47dddd7 1842 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
e1833e1f
JM		 1843 "Aborting\n");
1844 break;
1845 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
a47dddd7 1846 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
e1833e1f
JM		 1847 "Aborting\n");
1848 break;
1849 case POWERPC_EXCP_DTLB: /* Data TLB error */
a47dddd7 1850 cpu_abort(cs, "Data TLB exception while in user mode. "
e1833e1f
JM		 1851 "Aborting\n");
1852 break;
1853 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
a47dddd7 1854 cpu_abort(cs, "Instruction TLB exception while in user mode. "
e1833e1f
JM		 1855 "Aborting\n");
1856 break;
e1833e1f
JM		 1857 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1858 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1859 info.si_signo = TARGET_SIGILL;
1860 info.si_errno = 0;
1861 info.si_code = TARGET_ILL_COPROC;
1862 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1863 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1864 break;
1865 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
a47dddd7 1866 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
e1833e1f
JM		 1867 break;
1868 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
a47dddd7 1869 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
e1833e1f
JM		 1870 break;
1871 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
a47dddd7 1872 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1873 break;
1874 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
a47dddd7 1875 cpu_abort(cs, "Doorbell interrupt while in user mode. "
e1833e1f
JM		 1876 "Aborting\n");
1877 break;
1878 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
a47dddd7 1879 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
e1833e1f
JM		 1880 "Aborting\n");
1881 break;
1882 case POWERPC_EXCP_RESET: /* System reset exception */
a47dddd7 1883 cpu_abort(cs, "Reset interrupt while in user mode. "
e1833e1f
JM		 1884 "Aborting\n");
1885 break;
e1833e1f 1886 case POWERPC_EXCP_DSEG: /* Data segment exception */
a47dddd7 1887 cpu_abort(cs, "Data segment exception while in user mode. "
e1833e1f
JM		 1888 "Aborting\n");
1889 break;
1890 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
a47dddd7 1891 cpu_abort(cs, "Instruction segment exception "
e1833e1f
JM		 1892 "while in user mode. Aborting\n");
1893 break;
e85e7c6e 1894 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1895 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
a47dddd7 1896 cpu_abort(cs, "Hypervisor decrementer interrupt "
e1833e1f
JM		 1897 "while in user mode. Aborting\n");
1898 break;
e1833e1f
JM		 1899 case POWERPC_EXCP_TRACE: /* Trace exception */
1900 /* Nothing to do:
1901 * we use this exception to emulate step-by-step execution mode.
1902 */
1903 break;
e85e7c6e 1904 /* PowerPC 64 with hypervisor mode support */
e1833e1f 1905 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
a47dddd7 1906 cpu_abort(cs, "Hypervisor data storage exception "
e1833e1f
JM		 1907 "while in user mode. Aborting\n");
1908 break;
1909 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
a47dddd7 1910 cpu_abort(cs, "Hypervisor instruction storage exception "
e1833e1f
JM		 1911 "while in user mode. Aborting\n");
1912 break;
1913 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
a47dddd7 1914 cpu_abort(cs, "Hypervisor data segment exception "
e1833e1f
JM		 1915 "while in user mode. Aborting\n");
1916 break;
1917 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
a47dddd7 1918 cpu_abort(cs, "Hypervisor instruction segment exception "
e1833e1f
JM		 1919 "while in user mode. Aborting\n");
1920 break;
e1833e1f
JM		 1921 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1922 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1923 info.si_signo = TARGET_SIGILL;
1924 info.si_errno = 0;
1925 info.si_code = TARGET_ILL_COPROC;
1926 info._sifields._sigfault._addr = env->nip - 4;
624f7979 1927 queue_signal(env, info.si_signo, &info);
e1833e1f
JM		 1928 break;
1929 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
a47dddd7 1930 cpu_abort(cs, "Programmable interval timer interrupt "
e1833e1f
JM		 1931 "while in user mode. Aborting\n");
1932 break;
1933 case POWERPC_EXCP_IO: /* IO error exception */
a47dddd7 1934 cpu_abort(cs, "IO error exception while in user mode. "
e1833e1f
JM		 1935 "Aborting\n");
1936 break;
1937 case POWERPC_EXCP_RUNM: /* Run mode exception */
a47dddd7 1938 cpu_abort(cs, "Run mode exception while in user mode. "
e1833e1f
JM		 1939 "Aborting\n");
1940 break;
1941 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
a47dddd7 1942 cpu_abort(cs, "Emulation trap exception not handled\n");
e1833e1f
JM		 1943 break;
1944 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
a47dddd7 1945 cpu_abort(cs, "Instruction fetch TLB exception "
e1833e1f
JM		 1946 "while in user-mode. Aborting");
1947 break;
1948 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
a47dddd7 1949 cpu_abort(cs, "Data load TLB exception while in user-mode. "
e1833e1f
JM		 1950 "Aborting");
1951 break;
1952 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
a47dddd7 1953 cpu_abort(cs, "Data store TLB exception while in user-mode. "
e1833e1f
JM		 1954 "Aborting");
1955 break;
1956 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
a47dddd7 1957 cpu_abort(cs, "Floating-point assist exception not handled\n");
e1833e1f
JM		 1958 break;
1959 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
a47dddd7 1960 cpu_abort(cs, "Instruction address breakpoint exception "
e1833e1f
JM		 1961 "not handled\n");
1962 break;
1963 case POWERPC_EXCP_SMI: /* System management interrupt */
a47dddd7 1964 cpu_abort(cs, "System management interrupt while in user mode. "
e1833e1f
JM		 1965 "Aborting\n");
1966 break;
1967 case POWERPC_EXCP_THERM: /* Thermal interrupt */
a47dddd7 1968 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
e1833e1f
JM		 1969 "Aborting\n");
1970 break;
1971 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
a47dddd7 1972 cpu_abort(cs, "Performance monitor exception not handled\n");
e1833e1f
JM		 1973 break;
1974 case POWERPC_EXCP_VPUA: /* Vector assist exception */
a47dddd7 1975 cpu_abort(cs, "Vector assist exception not handled\n");
e1833e1f
JM		 1976 break;
1977 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
a47dddd7 1978 cpu_abort(cs, "Soft patch exception not handled\n");
e1833e1f
JM		 1979 break;
1980 case POWERPC_EXCP_MAINT: /* Maintenance exception */
a47dddd7 1981 cpu_abort(cs, "Maintenance exception while in user mode. "
e1833e1f
JM		 1982 "Aborting\n");
1983 break;
1984 case POWERPC_EXCP_STOP: /* stop translation */
1985 /* We did invalidate the instruction cache. Go on */
1986 break;
1987 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1988 /* We just stopped because of a branch. Go on */
1989 break;
1990 case POWERPC_EXCP_SYSCALL_USER:
1991 /* system call in user-mode emulation */
1992 /* WARNING:
1993 * PPC ABI uses overflow flag in cr0 to signal an error
1994 * in syscalls.
1995 */
e1833e1f
JM		 1996 env->crf[0] &= ~0x1;
1997 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1998 env->gpr[5], env->gpr[6], env->gpr[7],
5945cfcb 1999 env->gpr[8], 0, 0);
6db9d00e
TB		 2000 if (ret == -TARGET_ERESTARTSYS) {
2001 env->nip -= 4;
2002 break;
2003 }
9e0e2f96 2004 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
bcd4933a
NF		 2005 /* Returning from a successful sigreturn syscall.
2006 Avoid corrupting register state. */
2007 break;
2008 }
9e0e2f96 2009 if (ret > (target_ulong)(-515)) {
e1833e1f
JM		 2010 env->crf[0] |= 0x1;
2011 ret = -ret;
61190b14 2012 }
e1833e1f 2013 env->gpr[3] = ret;
e1833e1f 2014 break;
56f066bb
NF		 2015 case POWERPC_EXCP_STCX:
2016 if (do_store_exclusive(env)) {
2017 info.si_signo = TARGET_SIGSEGV;
2018 info.si_errno = 0;
2019 info.si_code = TARGET_SEGV_MAPERR;
2020 info._sifields._sigfault._addr = env->nip;
2021 queue_signal(env, info.si_signo, &info);
2022 }
2023 break;
71f75756
AJ		 2024 case EXCP_DEBUG:
2025 {
2026 int sig;
2027
db6b81d4 2028 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
71f75756
AJ		 2029 if (sig) {
2030 info.si_signo = sig;
2031 info.si_errno = 0;
2032 info.si_code = TARGET_TRAP_BRKPT;
2033 queue_signal(env, info.si_signo, &info);
2034 }
2035 }
2036 break;
56ba31ff
JM		 2037 case EXCP_INTERRUPT:
2038 /* just indicate that signals should be handled asap */
2039 break;
e1833e1f 2040 default:
a47dddd7 2041 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
e1833e1f 2042 break;
67867308
FB		 2043 }
2044 process_pending_signals(env);
2045 }
2046}
2047#endif
2048
048f6b4d
FB		 2049#ifdef TARGET_MIPS
2050
ff4f7382
RH		 2051# ifdef TARGET_ABI_MIPSO32
2052# define MIPS_SYS(name, args) args,
048f6b4d 2053static const uint8_t mips_syscall_args[] = {
29fb0f25 2054 MIPS_SYS(sys_syscall , 8) /* 4000 */
048f6b4d
FB		 2055 MIPS_SYS(sys_exit , 1)
2056 MIPS_SYS(sys_fork , 0)
2057 MIPS_SYS(sys_read , 3)
2058 MIPS_SYS(sys_write , 3)
2059 MIPS_SYS(sys_open , 3) /* 4005 */
2060 MIPS_SYS(sys_close , 1)
2061 MIPS_SYS(sys_waitpid , 3)
2062 MIPS_SYS(sys_creat , 2)
2063 MIPS_SYS(sys_link , 2)
2064 MIPS_SYS(sys_unlink , 1) /* 4010 */
2065 MIPS_SYS(sys_execve , 0)
2066 MIPS_SYS(sys_chdir , 1)
2067 MIPS_SYS(sys_time , 1)
2068 MIPS_SYS(sys_mknod , 3)
2069 MIPS_SYS(sys_chmod , 2) /* 4015 */
2070 MIPS_SYS(sys_lchown , 3)
2071 MIPS_SYS(sys_ni_syscall , 0)
2072 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2073 MIPS_SYS(sys_lseek , 3)
2074 MIPS_SYS(sys_getpid , 0) /* 4020 */
2075 MIPS_SYS(sys_mount , 5)
868e34d7 2076 MIPS_SYS(sys_umount , 1)
048f6b4d
FB		 2077 MIPS_SYS(sys_setuid , 1)
2078 MIPS_SYS(sys_getuid , 0)
2079 MIPS_SYS(sys_stime , 1) /* 4025 */
2080 MIPS_SYS(sys_ptrace , 4)
2081 MIPS_SYS(sys_alarm , 1)
2082 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2083 MIPS_SYS(sys_pause , 0)
2084 MIPS_SYS(sys_utime , 2) /* 4030 */
2085 MIPS_SYS(sys_ni_syscall , 0)
2086 MIPS_SYS(sys_ni_syscall , 0)
2087 MIPS_SYS(sys_access , 2)
2088 MIPS_SYS(sys_nice , 1)
2089 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2090 MIPS_SYS(sys_sync , 0)
2091 MIPS_SYS(sys_kill , 2)
2092 MIPS_SYS(sys_rename , 2)
2093 MIPS_SYS(sys_mkdir , 2)
2094 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2095 MIPS_SYS(sys_dup , 1)
2096 MIPS_SYS(sys_pipe , 0)
2097 MIPS_SYS(sys_times , 1)
2098 MIPS_SYS(sys_ni_syscall , 0)
2099 MIPS_SYS(sys_brk , 1) /* 4045 */
2100 MIPS_SYS(sys_setgid , 1)
2101 MIPS_SYS(sys_getgid , 0)
2102 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2103 MIPS_SYS(sys_geteuid , 0)
2104 MIPS_SYS(sys_getegid , 0) /* 4050 */
2105 MIPS_SYS(sys_acct , 0)
868e34d7 2106 MIPS_SYS(sys_umount2 , 2)
048f6b4d
FB		 2107 MIPS_SYS(sys_ni_syscall , 0)
2108 MIPS_SYS(sys_ioctl , 3)
2109 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2110 MIPS_SYS(sys_ni_syscall , 2)
2111 MIPS_SYS(sys_setpgid , 2)
2112 MIPS_SYS(sys_ni_syscall , 0)
2113 MIPS_SYS(sys_olduname , 1)
2114 MIPS_SYS(sys_umask , 1) /* 4060 */
2115 MIPS_SYS(sys_chroot , 1)
2116 MIPS_SYS(sys_ustat , 2)
2117 MIPS_SYS(sys_dup2 , 2)
2118 MIPS_SYS(sys_getppid , 0)
2119 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2120 MIPS_SYS(sys_setsid , 0)
2121 MIPS_SYS(sys_sigaction , 3)
2122 MIPS_SYS(sys_sgetmask , 0)
2123 MIPS_SYS(sys_ssetmask , 1)
2124 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2125 MIPS_SYS(sys_setregid , 2)
2126 MIPS_SYS(sys_sigsuspend , 0)
2127 MIPS_SYS(sys_sigpending , 1)
2128 MIPS_SYS(sys_sethostname , 2)
2129 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2130 MIPS_SYS(sys_getrlimit , 2)
2131 MIPS_SYS(sys_getrusage , 2)
2132 MIPS_SYS(sys_gettimeofday, 2)
2133 MIPS_SYS(sys_settimeofday, 2)
2134 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2135 MIPS_SYS(sys_setgroups , 2)
2136 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2137 MIPS_SYS(sys_symlink , 2)
2138 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2139 MIPS_SYS(sys_readlink , 3) /* 4085 */
2140 MIPS_SYS(sys_uselib , 1)
2141 MIPS_SYS(sys_swapon , 2)
2142 MIPS_SYS(sys_reboot , 3)
2143 MIPS_SYS(old_readdir , 3)
2144 MIPS_SYS(old_mmap , 6) /* 4090 */
2145 MIPS_SYS(sys_munmap , 2)
2146 MIPS_SYS(sys_truncate , 2)
2147 MIPS_SYS(sys_ftruncate , 2)
2148 MIPS_SYS(sys_fchmod , 2)
2149 MIPS_SYS(sys_fchown , 3) /* 4095 */
2150 MIPS_SYS(sys_getpriority , 2)
2151 MIPS_SYS(sys_setpriority , 3)
2152 MIPS_SYS(sys_ni_syscall , 0)
2153 MIPS_SYS(sys_statfs , 2)
2154 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2155 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2156 MIPS_SYS(sys_socketcall , 2)
2157 MIPS_SYS(sys_syslog , 3)
2158 MIPS_SYS(sys_setitimer , 3)
2159 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2160 MIPS_SYS(sys_newstat , 2)
2161 MIPS_SYS(sys_newlstat , 2)
2162 MIPS_SYS(sys_newfstat , 2)
2163 MIPS_SYS(sys_uname , 1)
2164 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2165 MIPS_SYS(sys_vhangup , 0)
2166 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2167 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2168 MIPS_SYS(sys_wait4 , 4)
2169 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2170 MIPS_SYS(sys_sysinfo , 1)
2171 MIPS_SYS(sys_ipc , 6)
2172 MIPS_SYS(sys_fsync , 1)
2173 MIPS_SYS(sys_sigreturn , 0)
18113962 2174 MIPS_SYS(sys_clone , 6) /* 4120 */
048f6b4d
FB		 2175 MIPS_SYS(sys_setdomainname, 2)
2176 MIPS_SYS(sys_newuname , 1)
2177 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2178 MIPS_SYS(sys_adjtimex , 1)
2179 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2180 MIPS_SYS(sys_sigprocmask , 3)
2181 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2182 MIPS_SYS(sys_init_module , 5)
2183 MIPS_SYS(sys_delete_module, 1)
2184 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2185 MIPS_SYS(sys_quotactl , 0)
2186 MIPS_SYS(sys_getpgid , 1)
2187 MIPS_SYS(sys_fchdir , 1)
2188 MIPS_SYS(sys_bdflush , 2)
2189 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2190 MIPS_SYS(sys_personality , 1)
2191 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2192 MIPS_SYS(sys_setfsuid , 1)
2193 MIPS_SYS(sys_setfsgid , 1)
2194 MIPS_SYS(sys_llseek , 5) /* 4140 */
2195 MIPS_SYS(sys_getdents , 3)
2196 MIPS_SYS(sys_select , 5)
2197 MIPS_SYS(sys_flock , 2)
2198 MIPS_SYS(sys_msync , 3)
2199 MIPS_SYS(sys_readv , 3) /* 4145 */
2200 MIPS_SYS(sys_writev , 3)
2201 MIPS_SYS(sys_cacheflush , 3)
2202 MIPS_SYS(sys_cachectl , 3)
2203 MIPS_SYS(sys_sysmips , 4)
2204 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2205 MIPS_SYS(sys_getsid , 1)
2206 MIPS_SYS(sys_fdatasync , 0)
2207 MIPS_SYS(sys_sysctl , 1)
2208 MIPS_SYS(sys_mlock , 2)
2209 MIPS_SYS(sys_munlock , 2) /* 4155 */
2210 MIPS_SYS(sys_mlockall , 1)
2211 MIPS_SYS(sys_munlockall , 0)
2212 MIPS_SYS(sys_sched_setparam, 2)
2213 MIPS_SYS(sys_sched_getparam, 2)
2214 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2215 MIPS_SYS(sys_sched_getscheduler, 1)
2216 MIPS_SYS(sys_sched_yield , 0)
2217 MIPS_SYS(sys_sched_get_priority_max, 1)
2218 MIPS_SYS(sys_sched_get_priority_min, 1)
2219 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2220 MIPS_SYS(sys_nanosleep, 2)
b0932e06 2221 MIPS_SYS(sys_mremap , 5)
048f6b4d
FB		 2222 MIPS_SYS(sys_accept , 3)
2223 MIPS_SYS(sys_bind , 3)
2224 MIPS_SYS(sys_connect , 3) /* 4170 */
2225 MIPS_SYS(sys_getpeername , 3)
2226 MIPS_SYS(sys_getsockname , 3)
2227 MIPS_SYS(sys_getsockopt , 5)
2228 MIPS_SYS(sys_listen , 2)
2229 MIPS_SYS(sys_recv , 4) /* 4175 */
2230 MIPS_SYS(sys_recvfrom , 6)
2231 MIPS_SYS(sys_recvmsg , 3)
2232 MIPS_SYS(sys_send , 4)
2233 MIPS_SYS(sys_sendmsg , 3)
2234 MIPS_SYS(sys_sendto , 6) /* 4180 */
2235 MIPS_SYS(sys_setsockopt , 5)
2236 MIPS_SYS(sys_shutdown , 2)
2237 MIPS_SYS(sys_socket , 3)
2238 MIPS_SYS(sys_socketpair , 4)
2239 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2240 MIPS_SYS(sys_getresuid , 3)
2241 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2242 MIPS_SYS(sys_poll , 3)
2243 MIPS_SYS(sys_nfsservctl , 3)
2244 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2245 MIPS_SYS(sys_getresgid , 3)
2246 MIPS_SYS(sys_prctl , 5)
2247 MIPS_SYS(sys_rt_sigreturn, 0)
2248 MIPS_SYS(sys_rt_sigaction, 4)
2249 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2250 MIPS_SYS(sys_rt_sigpending, 2)
2251 MIPS_SYS(sys_rt_sigtimedwait, 4)
2252 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2253 MIPS_SYS(sys_rt_sigsuspend, 0)
2254 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2255 MIPS_SYS(sys_pwrite64 , 6)
2256 MIPS_SYS(sys_chown , 3)
2257 MIPS_SYS(sys_getcwd , 2)
2258 MIPS_SYS(sys_capget , 2)
2259 MIPS_SYS(sys_capset , 2) /* 4205 */
053ebb27 2260 MIPS_SYS(sys_sigaltstack , 2)
048f6b4d
FB		 2261 MIPS_SYS(sys_sendfile , 4)
2262 MIPS_SYS(sys_ni_syscall , 0)
2263 MIPS_SYS(sys_ni_syscall , 0)
2264 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2265 MIPS_SYS(sys_truncate64 , 4)
2266 MIPS_SYS(sys_ftruncate64 , 4)
2267 MIPS_SYS(sys_stat64 , 2)
2268 MIPS_SYS(sys_lstat64 , 2)
2269 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2270 MIPS_SYS(sys_pivot_root , 2)
2271 MIPS_SYS(sys_mincore , 3)
2272 MIPS_SYS(sys_madvise , 3)
2273 MIPS_SYS(sys_getdents64 , 3)
2274 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2275 MIPS_SYS(sys_ni_syscall , 0)
2276 MIPS_SYS(sys_gettid , 0)
2277 MIPS_SYS(sys_readahead , 5)
2278 MIPS_SYS(sys_setxattr , 5)
2279 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2280 MIPS_SYS(sys_fsetxattr , 5)
2281 MIPS_SYS(sys_getxattr , 4)
2282 MIPS_SYS(sys_lgetxattr , 4)
2283 MIPS_SYS(sys_fgetxattr , 4)
2284 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2285 MIPS_SYS(sys_llistxattr , 3)
2286 MIPS_SYS(sys_flistxattr , 3)
2287 MIPS_SYS(sys_removexattr , 2)
2288 MIPS_SYS(sys_lremovexattr, 2)
2289 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2290 MIPS_SYS(sys_tkill , 2)
2291 MIPS_SYS(sys_sendfile64 , 5)
43be1343 2292 MIPS_SYS(sys_futex , 6)
048f6b4d
FB		 2293 MIPS_SYS(sys_sched_setaffinity, 3)
2294 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2295 MIPS_SYS(sys_io_setup , 2)
2296 MIPS_SYS(sys_io_destroy , 1)
2297 MIPS_SYS(sys_io_getevents, 5)
2298 MIPS_SYS(sys_io_submit , 3)
2299 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2300 MIPS_SYS(sys_exit_group , 1)
2301 MIPS_SYS(sys_lookup_dcookie, 3)
2302 MIPS_SYS(sys_epoll_create, 1)
2303 MIPS_SYS(sys_epoll_ctl , 4)
2304 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2305 MIPS_SYS(sys_remap_file_pages, 5)
2306 MIPS_SYS(sys_set_tid_address, 1)
2307 MIPS_SYS(sys_restart_syscall, 0)
2308 MIPS_SYS(sys_fadvise64_64, 7)
2309 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2310 MIPS_SYS(sys_fstatfs64 , 2)
2311 MIPS_SYS(sys_timer_create, 3)
2312 MIPS_SYS(sys_timer_settime, 4)
2313 MIPS_SYS(sys_timer_gettime, 2)
2314 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2315 MIPS_SYS(sys_timer_delete, 1)
2316 MIPS_SYS(sys_clock_settime, 2)
2317 MIPS_SYS(sys_clock_gettime, 2)
2318 MIPS_SYS(sys_clock_getres, 2)
2319 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2320 MIPS_SYS(sys_tgkill , 3)
2321 MIPS_SYS(sys_utimes , 2)
2322 MIPS_SYS(sys_mbind , 4)
2323 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2324 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2325 MIPS_SYS(sys_mq_open , 4)
2326 MIPS_SYS(sys_mq_unlink , 1)
2327 MIPS_SYS(sys_mq_timedsend, 5)
2328 MIPS_SYS(sys_mq_timedreceive, 5)
2329 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2330 MIPS_SYS(sys_mq_getsetattr, 3)
2331 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2332 MIPS_SYS(sys_waitid , 4)
2333 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2334 MIPS_SYS(sys_add_key , 5)
388bb21a 2335 MIPS_SYS(sys_request_key, 4)
048f6b4d 2336 MIPS_SYS(sys_keyctl , 5)
6f5b89a0 2337 MIPS_SYS(sys_set_thread_area, 1)
388bb21a
TS		 2338 MIPS_SYS(sys_inotify_init, 0)
2339 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2340 MIPS_SYS(sys_inotify_rm_watch, 2)
2341 MIPS_SYS(sys_migrate_pages, 4)
2342 MIPS_SYS(sys_openat, 4)
2343 MIPS_SYS(sys_mkdirat, 3)
2344 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2345 MIPS_SYS(sys_fchownat, 5)
2346 MIPS_SYS(sys_futimesat, 3)
2347 MIPS_SYS(sys_fstatat64, 4)
2348 MIPS_SYS(sys_unlinkat, 3)
2349 MIPS_SYS(sys_renameat, 4) /* 4295 */
2350 MIPS_SYS(sys_linkat, 5)
2351 MIPS_SYS(sys_symlinkat, 3)
2352 MIPS_SYS(sys_readlinkat, 4)
2353 MIPS_SYS(sys_fchmodat, 3)
2354 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2355 MIPS_SYS(sys_pselect6, 6)
2356 MIPS_SYS(sys_ppoll, 5)
2357 MIPS_SYS(sys_unshare, 1)
b0932e06 2358 MIPS_SYS(sys_splice, 6)
388bb21a
TS		 2359 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2360 MIPS_SYS(sys_tee, 4)
2361 MIPS_SYS(sys_vmsplice, 4)
2362 MIPS_SYS(sys_move_pages, 6)
2363 MIPS_SYS(sys_set_robust_list, 2)
2364 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2365 MIPS_SYS(sys_kexec_load, 4)
2366 MIPS_SYS(sys_getcpu, 3)
2367 MIPS_SYS(sys_epoll_pwait, 6)
2368 MIPS_SYS(sys_ioprio_set, 3)
2369 MIPS_SYS(sys_ioprio_get, 2)
d979e8eb
PM		 2370 MIPS_SYS(sys_utimensat, 4)
2371 MIPS_SYS(sys_signalfd, 3)
2372 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2373 MIPS_SYS(sys_eventfd, 1)
2374 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2375 MIPS_SYS(sys_timerfd_create, 2)
2376 MIPS_SYS(sys_timerfd_gettime, 2)
2377 MIPS_SYS(sys_timerfd_settime, 4)
2378 MIPS_SYS(sys_signalfd4, 4)
2379 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2380 MIPS_SYS(sys_epoll_create1, 1)
2381 MIPS_SYS(sys_dup3, 3)
2382 MIPS_SYS(sys_pipe2, 2)
2383 MIPS_SYS(sys_inotify_init1, 1)
2384 MIPS_SYS(sys_preadv, 6) /* 4330 */
2385 MIPS_SYS(sys_pwritev, 6)
2386 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2387 MIPS_SYS(sys_perf_event_open, 5)
2388 MIPS_SYS(sys_accept4, 4)
2389 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2390 MIPS_SYS(sys_fanotify_init, 2)
2391 MIPS_SYS(sys_fanotify_mark, 6)
2392 MIPS_SYS(sys_prlimit64, 4)
2393 MIPS_SYS(sys_name_to_handle_at, 5)
2394 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2395 MIPS_SYS(sys_clock_adjtime, 2)
2396 MIPS_SYS(sys_syncfs, 1)
048f6b4d 2397};
ff4f7382
RH		 2398# undef MIPS_SYS
2399# endif /* O32 */
048f6b4d 2400
590bc601
PB		 2401static int do_store_exclusive(CPUMIPSState *env)
2402{
2403 target_ulong addr;
2404 target_ulong page_addr;
2405 target_ulong val;
2406 int flags;
2407 int segv = 0;
2408 int reg;
2409 int d;
2410
5499b6ff 2411 addr = env->lladdr;
590bc601
PB		 2412 page_addr = addr & TARGET_PAGE_MASK;
2413 start_exclusive();
2414 mmap_lock();
2415 flags = page_get_flags(page_addr);
2416 if ((flags & PAGE_READ) == 0) {
2417 segv = 1;
2418 } else {
2419 reg = env->llreg & 0x1f;
2420 d = (env->llreg & 0x20) != 0;
2421 if (d) {
2422 segv = get_user_s64(val, addr);
2423 } else {
2424 segv = get_user_s32(val, addr);
2425 }
2426 if (!segv) {
2427 if (val != env->llval) {
2428 env->active_tc.gpr[reg] = 0;
2429 } else {
2430 if (d) {
2431 segv = put_user_u64(env->llnewval, addr);
2432 } else {
2433 segv = put_user_u32(env->llnewval, addr);
2434 }
2435 if (!segv) {
2436 env->active_tc.gpr[reg] = 1;
2437 }
2438 }
2439 }
2440 }
5499b6ff 2441 env->lladdr = -1;
590bc601
PB		 2442 if (!segv) {
2443 env->active_tc.PC += 4;
2444 }
2445 mmap_unlock();
2446 end_exclusive();
2447 return segv;
2448}
2449
54b2f42c
MI		 2450/* Break codes */
2451enum {
2452 BRK_OVERFLOW = 6,
2453 BRK_DIVZERO = 7
2454};
2455
2456static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2457 unsigned int code)
2458{
2459 int ret = -1;
2460
2461 switch (code) {
2462 case BRK_OVERFLOW:
2463 case BRK_DIVZERO:
2464 info->si_signo = TARGET_SIGFPE;
2465 info->si_errno = 0;
2466 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2467 queue_signal(env, info->si_signo, &*info);
2468 ret = 0;
2469 break;
2470 default:
b51910ba
PJ		 2471 info->si_signo = TARGET_SIGTRAP;
2472 info->si_errno = 0;
2473 queue_signal(env, info->si_signo, &*info);
2474 ret = 0;
54b2f42c
MI		 2475 break;
2476 }
2477
2478 return ret;
2479}
2480
048f6b4d
FB		 2481void cpu_loop(CPUMIPSState *env)
2482{
0315c31c 2483 CPUState *cs = CPU(mips_env_get_cpu(env));
c227f099 2484 target_siginfo_t info;
ff4f7382
RH		 2485 int trapnr;
2486 abi_long ret;
2487# ifdef TARGET_ABI_MIPSO32
048f6b4d 2488 unsigned int syscall_num;
ff4f7382 2489# endif
048f6b4d
FB		 2490
2491 for(;;) {
0315c31c 2492 cpu_exec_start(cs);
ea3e9847 2493 trapnr = cpu_mips_exec(cs);
0315c31c 2494 cpu_exec_end(cs);
048f6b4d
FB		 2495 switch(trapnr) {
2496 case EXCP_SYSCALL:
b5dc7732 2497 env->active_tc.PC += 4;
ff4f7382
RH		 2498# ifdef TARGET_ABI_MIPSO32
2499 syscall_num = env->active_tc.gpr[2] - 4000;
388bb21a 2500 if (syscall_num >= sizeof(mips_syscall_args)) {
7c2f6157 2501 ret = -TARGET_ENOSYS;
388bb21a
TS		 2502 } else {
2503 int nb_args;
992f48a0
BS		 2504 abi_ulong sp_reg;
2505 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
388bb21a
TS		 2506
2507 nb_args = mips_syscall_args[syscall_num];
b5dc7732 2508 sp_reg = env->active_tc.gpr[29];
388bb21a
TS		 2509 switch (nb_args) {
2510 /* these arguments are taken from the stack */
94c19610
ACH		 2511 case 8:
2512 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2513 goto done_syscall;
2514 }
2515 case 7:
2516 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2517 goto done_syscall;
2518 }
2519 case 6:
2520 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2521 goto done_syscall;
2522 }
2523 case 5:
2524 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2525 goto done_syscall;
2526 }
388bb21a
TS		 2527 default:
2528 break;
048f6b4d 2529 }
b5dc7732
TS		 2530 ret = do_syscall(env, env->active_tc.gpr[2],
2531 env->active_tc.gpr[4],
2532 env->active_tc.gpr[5],
2533 env->active_tc.gpr[6],
2534 env->active_tc.gpr[7],
5945cfcb 2535 arg5, arg6, arg7, arg8);
388bb21a 2536 }
94c19610 2537done_syscall:
ff4f7382
RH		 2538# else
2539 ret = do_syscall(env, env->active_tc.gpr[2],
2540 env->active_tc.gpr[4], env->active_tc.gpr[5],
2541 env->active_tc.gpr[6], env->active_tc.gpr[7],
2542 env->active_tc.gpr[8], env->active_tc.gpr[9],
2543 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2544# endif /* O32 */
2eb3ae27
TB		 2545 if (ret == -TARGET_ERESTARTSYS) {
2546 env->active_tc.PC -= 4;
2547 break;
2548 }
0b1bcb00
PB		 2549 if (ret == -TARGET_QEMU_ESIGRETURN) {
2550 /* Returning from a successful sigreturn syscall.
2551 Avoid clobbering register state. */
2552 break;
2553 }
ff4f7382 2554 if ((abi_ulong)ret >= (abi_ulong)-1133) {
b5dc7732 2555 env->active_tc.gpr[7] = 1; /* error flag */
388bb21a
TS		 2556 ret = -ret;
2557 } else {
b5dc7732 2558 env->active_tc.gpr[7] = 0; /* error flag */
048f6b4d 2559 }
b5dc7732 2560 env->active_tc.gpr[2] = ret;
048f6b4d 2561 break;
ca7c2b1b
TS		 2562 case EXCP_TLBL:
2563 case EXCP_TLBS:
e6e5bd2d
WT		 2564 case EXCP_AdEL:
2565 case EXCP_AdES:
e4474235
PB		 2566 info.si_signo = TARGET_SIGSEGV;
2567 info.si_errno = 0;
2568 /* XXX: check env->error_code */
2569 info.si_code = TARGET_SEGV_MAPERR;
2570 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2571 queue_signal(env, info.si_signo, &info);
2572 break;
6900e84b 2573 case EXCP_CpU:
048f6b4d 2574 case EXCP_RI:
bc1ad2de
FB		 2575 info.si_signo = TARGET_SIGILL;
2576 info.si_errno = 0;
2577 info.si_code = 0;
624f7979 2578 queue_signal(env, info.si_signo, &info);
048f6b4d 2579 break;
106ec879
FB		 2580 case EXCP_INTERRUPT:
2581 /* just indicate that signals should be handled asap */
2582 break;
d08b2a28
PB		 2583 case EXCP_DEBUG:
2584 {
2585 int sig;
2586
db6b81d4 2587 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d08b2a28
PB		 2588 if (sig)
2589 {
2590 info.si_signo = sig;
2591 info.si_errno = 0;
2592 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2593 queue_signal(env, info.si_signo, &info);
d08b2a28
PB		 2594 }
2595 }
2596 break;
590bc601
PB		 2597 case EXCP_SC:
2598 if (do_store_exclusive(env)) {
2599 info.si_signo = TARGET_SIGSEGV;
2600 info.si_errno = 0;
2601 info.si_code = TARGET_SEGV_MAPERR;
2602 info._sifields._sigfault._addr = env->active_tc.PC;
2603 queue_signal(env, info.si_signo, &info);
2604 }
2605 break;
853c3240
JL		 2606 case EXCP_DSPDIS:
2607 info.si_signo = TARGET_SIGILL;
2608 info.si_errno = 0;
2609 info.si_code = TARGET_ILL_ILLOPC;
2610 queue_signal(env, info.si_signo, &info);
2611 break;
54b2f42c
MI		 2612 /* The code below was inspired by the MIPS Linux kernel trap
2613 * handling code in arch/mips/kernel/traps.c.
2614 */
2615 case EXCP_BREAK:
2616 {
2617 abi_ulong trap_instr;
2618 unsigned int code;
2619
a0333817
KCY		 2620 if (env->hflags & MIPS_HFLAG_M16) {
2621 if (env->insn_flags & ASE_MICROMIPS) {
2622 /* microMIPS mode */
1308c464
KCY		 2623 ret = get_user_u16(trap_instr, env->active_tc.PC);
2624 if (ret != 0) {
2625 goto error;
2626 }
a0333817 2627
1308c464
KCY		 2628 if ((trap_instr >> 10) == 0x11) {
2629 /* 16-bit instruction */
2630 code = trap_instr & 0xf;
2631 } else {
2632 /* 32-bit instruction */
2633 abi_ulong instr_lo;
2634
2635 ret = get_user_u16(instr_lo,
2636 env->active_tc.PC + 2);
2637 if (ret != 0) {
2638 goto error;
2639 }
2640 trap_instr = (trap_instr << 16) | instr_lo;
2641 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2642 /* Unfortunately, microMIPS also suffers from
2643 the old assembler bug... */
2644 if (code >= (1 << 10)) {
2645 code >>= 10;
2646 }
2647 }
a0333817
KCY		 2648 } else {
2649 /* MIPS16e mode */
2650 ret = get_user_u16(trap_instr, env->active_tc.PC);
2651 if (ret != 0) {
2652 goto error;
2653 }
2654 code = (trap_instr >> 6) & 0x3f;
a0333817
KCY		 2655 }
2656 } else {
f01a361b 2657 ret = get_user_u32(trap_instr, env->active_tc.PC);
1308c464
KCY		 2658 if (ret != 0) {
2659 goto error;
2660 }
54b2f42c 2661
1308c464
KCY		 2662 /* As described in the original Linux kernel code, the
2663 * below checks on 'code' are to work around an old
2664 * assembly bug.
2665 */
2666 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2667 if (code >= (1 << 10)) {
2668 code >>= 10;
2669 }
54b2f42c
MI		 2670 }
2671
2672 if (do_break(env, &info, code) != 0) {
2673 goto error;
2674 }
2675 }
2676 break;
2677 case EXCP_TRAP:
2678 {
2679 abi_ulong trap_instr;
2680 unsigned int code = 0;
2681
a0333817
KCY		 2682 if (env->hflags & MIPS_HFLAG_M16) {
2683 /* microMIPS mode */
2684 abi_ulong instr[2];
2685
2686 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2687 get_user_u16(instr[1], env->active_tc.PC + 2);
2688
2689 trap_instr = (instr[0] << 16) | instr[1];
2690 } else {
f01a361b 2691 ret = get_user_u32(trap_instr, env->active_tc.PC);
a0333817
KCY		 2692 }
2693
54b2f42c
MI		 2694 if (ret != 0) {
2695 goto error;
2696 }
2697
2698 /* The immediate versions don't provide a code. */
2699 if (!(trap_instr & 0xFC000000)) {
a0333817
KCY		 2700 if (env->hflags & MIPS_HFLAG_M16) {
2701 /* microMIPS mode */
2702 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2703 } else {
2704 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2705 }
54b2f42c
MI		 2706 }
2707
2708 if (do_break(env, &info, code) != 0) {
2709 goto error;
2710 }
2711 }
2712 break;
048f6b4d 2713 default:
54b2f42c 2714error:
120a9848 2715 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
048f6b4d
FB		 2716 abort();
2717 }
2718 process_pending_signals(env);
2719 }
2720}
2721#endif
2722
d962783e
JL		 2723#ifdef TARGET_OPENRISC
2724
2725void cpu_loop(CPUOpenRISCState *env)
2726{
878096ee 2727 CPUState *cs = CPU(openrisc_env_get_cpu(env));
d962783e 2728 int trapnr, gdbsig;
7fe7231a 2729 abi_long ret;
d962783e
JL		 2730
2731 for (;;) {
b040bc9c 2732 cpu_exec_start(cs);
ea3e9847 2733 trapnr = cpu_openrisc_exec(cs);
b040bc9c 2734 cpu_exec_end(cs);
d962783e
JL		 2735 gdbsig = 0;
2736
2737 switch (trapnr) {
2738 case EXCP_RESET:
120a9848 2739 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
4d1275c2 2740 exit(EXIT_FAILURE);
d962783e
JL		 2741 break;
2742 case EXCP_BUSERR:
120a9848 2743 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
a86b3c64 2744 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2745 break;
2746 case EXCP_DPF:
2747 case EXCP_IPF:
878096ee 2748 cpu_dump_state(cs, stderr, fprintf, 0);
d962783e
JL		 2749 gdbsig = TARGET_SIGSEGV;
2750 break;
2751 case EXCP_TICK:
120a9848 2752 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
d962783e
JL		 2753 break;
2754 case EXCP_ALIGN:
120a9848 2755 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
a86b3c64 2756 gdbsig = TARGET_SIGBUS;
d962783e
JL		 2757 break;
2758 case EXCP_ILLEGAL:
120a9848 2759 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
a86b3c64 2760 gdbsig = TARGET_SIGILL;
d962783e
JL		 2761 break;
2762 case EXCP_INT:
120a9848 2763 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
d962783e
JL		 2764 break;
2765 case EXCP_DTLBMISS:
2766 case EXCP_ITLBMISS:
120a9848 2767 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
d962783e
JL		 2768 break;
2769 case EXCP_RANGE:
120a9848 2770 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
a86b3c64 2771 gdbsig = TARGET_SIGSEGV;
d962783e
JL		 2772 break;
2773 case EXCP_SYSCALL:
2774 env->pc += 4; /* 0xc00; */
7fe7231a
TB		 2775 ret = do_syscall(env,
2776 env->gpr[11], /* return value */
2777 env->gpr[3], /* r3 - r7 are params */
2778 env->gpr[4],
2779 env->gpr[5],
2780 env->gpr[6],
2781 env->gpr[7],
2782 env->gpr[8], 0, 0);
2783 if (ret == -TARGET_ERESTARTSYS) {
2784 env->pc -= 4;
2785 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2786 env->gpr[11] = ret;
2787 }
d962783e
JL		 2788 break;
2789 case EXCP_FPE:
120a9848 2790 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
d962783e
JL		 2791 break;
2792 case EXCP_TRAP:
120a9848 2793 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
a86b3c64 2794 gdbsig = TARGET_SIGTRAP;
d962783e
JL		 2795 break;
2796 case EXCP_NR:
120a9848 2797 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
d962783e
JL		 2798 break;
2799 default:
120a9848 2800 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
d962783e 2801 trapnr);
d962783e
JL		 2802 gdbsig = TARGET_SIGILL;
2803 break;
2804 }
2805 if (gdbsig) {
db6b81d4 2806 gdb_handlesig(cs, gdbsig);
d962783e 2807 if (gdbsig != TARGET_SIGTRAP) {
4d1275c2 2808 exit(EXIT_FAILURE);
d962783e
JL		 2809 }
2810 }
2811
2812 process_pending_signals(env);
2813 }
2814}
2815
2816#endif /* TARGET_OPENRISC */
2817
fdf9b3e8 2818#ifdef TARGET_SH4
05390248 2819void cpu_loop(CPUSH4State *env)
fdf9b3e8 2820{
878096ee 2821 CPUState *cs = CPU(sh_env_get_cpu(env));
fdf9b3e8 2822 int trapnr, ret;
c227f099 2823 target_siginfo_t info;
3b46e624 2824
fdf9b3e8 2825 while (1) {
b040bc9c 2826 cpu_exec_start(cs);
ea3e9847 2827 trapnr = cpu_sh4_exec(cs);
b040bc9c 2828 cpu_exec_end(cs);
3b46e624 2829
fdf9b3e8
FB		 2830 switch (trapnr) {
2831 case 0x160:
0b6d3ae0 2832 env->pc += 2;
5fafdf24
TS		 2833 ret = do_syscall(env,
2834 env->gregs[3],
2835 env->gregs[4],
2836 env->gregs[5],
2837 env->gregs[6],
2838 env->gregs[7],
2839 env->gregs[0],
5945cfcb
PM		 2840 env->gregs[1],
2841 0, 0);
ba412496
TB		 2842 if (ret == -TARGET_ERESTARTSYS) {
2843 env->pc -= 2;
2844 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2845 env->gregs[0] = ret;
2846 }
fdf9b3e8 2847 break;
c3b5bc8a
TS		 2848 case EXCP_INTERRUPT:
2849 /* just indicate that signals should be handled asap */
2850 break;
355fb23d
PB		 2851 case EXCP_DEBUG:
2852 {
2853 int sig;
2854
db6b81d4 2855 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
355fb23d
PB		 2856 if (sig)
2857 {
2858 info.si_signo = sig;
2859 info.si_errno = 0;
2860 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2861 queue_signal(env, info.si_signo, &info);
355fb23d
PB		 2862 }
2863 }
2864 break;
c3b5bc8a
TS		 2865 case 0xa0:
2866 case 0xc0:
a86b3c64 2867 info.si_signo = TARGET_SIGSEGV;
c3b5bc8a
TS		 2868 info.si_errno = 0;
2869 info.si_code = TARGET_SEGV_MAPERR;
2870 info._sifields._sigfault._addr = env->tea;
624f7979 2871 queue_signal(env, info.si_signo, &info);
c3b5bc8a
TS		 2872 break;
2873
fdf9b3e8
FB		 2874 default:
2875 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2876 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2877 exit(EXIT_FAILURE);
fdf9b3e8
FB		 2878 }
2879 process_pending_signals (env);
2880 }
2881}
2882#endif
2883
48733d19 2884#ifdef TARGET_CRIS
05390248 2885void cpu_loop(CPUCRISState *env)
48733d19 2886{
878096ee 2887 CPUState *cs = CPU(cris_env_get_cpu(env));
48733d19 2888 int trapnr, ret;
c227f099 2889 target_siginfo_t info;
48733d19
TS		 2890
2891 while (1) {
b040bc9c 2892 cpu_exec_start(cs);
ea3e9847 2893 trapnr = cpu_cris_exec(cs);
b040bc9c 2894 cpu_exec_end(cs);
48733d19
TS		 2895 switch (trapnr) {
2896 case 0xaa:
2897 {
a86b3c64 2898 info.si_signo = TARGET_SIGSEGV;
48733d19
TS		 2899 info.si_errno = 0;
2900 /* XXX: check env->error_code */
2901 info.si_code = TARGET_SEGV_MAPERR;
e00c1e71 2902 info._sifields._sigfault._addr = env->pregs[PR_EDA];
624f7979 2903 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2904 }
2905 break;
b6d3abda
EI		 2906 case EXCP_INTERRUPT:
2907 /* just indicate that signals should be handled asap */
2908 break;
48733d19
TS		 2909 case EXCP_BREAK:
2910 ret = do_syscall(env,
2911 env->regs[9],
2912 env->regs[10],
2913 env->regs[11],
2914 env->regs[12],
2915 env->regs[13],
2916 env->pregs[7],
5945cfcb
PM		 2917 env->pregs[11],
2918 0, 0);
62050865
TB		 2919 if (ret == -TARGET_ERESTARTSYS) {
2920 env->pc -= 2;
2921 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2922 env->regs[10] = ret;
2923 }
48733d19
TS		 2924 break;
2925 case EXCP_DEBUG:
2926 {
2927 int sig;
2928
db6b81d4 2929 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
48733d19
TS		 2930 if (sig)
2931 {
2932 info.si_signo = sig;
2933 info.si_errno = 0;
2934 info.si_code = TARGET_TRAP_BRKPT;
624f7979 2935 queue_signal(env, info.si_signo, &info);
48733d19
TS		 2936 }
2937 }
2938 break;
2939 default:
2940 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 2941 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 2942 exit(EXIT_FAILURE);
48733d19
TS		 2943 }
2944 process_pending_signals (env);
2945 }
2946}
2947#endif
2948
b779e29e 2949#ifdef TARGET_MICROBLAZE
05390248 2950void cpu_loop(CPUMBState *env)
b779e29e 2951{
878096ee 2952 CPUState *cs = CPU(mb_env_get_cpu(env));
b779e29e 2953 int trapnr, ret;
c227f099 2954 target_siginfo_t info;
b779e29e
EI		 2955
2956 while (1) {
b040bc9c 2957 cpu_exec_start(cs);
ea3e9847 2958 trapnr = cpu_mb_exec(cs);
b040bc9c 2959 cpu_exec_end(cs);
b779e29e
EI		 2960 switch (trapnr) {
2961 case 0xaa:
2962 {
a86b3c64 2963 info.si_signo = TARGET_SIGSEGV;
b779e29e
EI		 2964 info.si_errno = 0;
2965 /* XXX: check env->error_code */
2966 info.si_code = TARGET_SEGV_MAPERR;
2967 info._sifields._sigfault._addr = 0;
2968 queue_signal(env, info.si_signo, &info);
2969 }
2970 break;
2971 case EXCP_INTERRUPT:
2972 /* just indicate that signals should be handled asap */
2973 break;
2974 case EXCP_BREAK:
2975 /* Return address is 4 bytes after the call. */
2976 env->regs[14] += 4;
d7dce494 2977 env->sregs[SR_PC] = env->regs[14];
b779e29e
EI		 2978 ret = do_syscall(env,
2979 env->regs[12],
2980 env->regs[5],
2981 env->regs[6],
2982 env->regs[7],
2983 env->regs[8],
2984 env->regs[9],
5945cfcb
PM		 2985 env->regs[10],
2986 0, 0);
4134ecfe
TB		 2987 if (ret == -TARGET_ERESTARTSYS) {
2988 /* Wind back to before the syscall. */
2989 env->sregs[SR_PC] -= 4;
2990 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2991 env->regs[3] = ret;
2992 }
d7749ab7
PM		 2993 /* All syscall exits result in guest r14 being equal to the
2994 * PC we return to, because the kernel syscall exit "rtbd" does
2995 * this. (This is true even for sigreturn(); note that r14 is
2996 * not a userspace-usable register, as the kernel may clobber it
2997 * at any point.)
2998 */
2999 env->regs[14] = env->sregs[SR_PC];
b779e29e 3000 break;
b76da7e3
EI		 3001 case EXCP_HW_EXCP:
3002 env->regs[17] = env->sregs[SR_PC] + 4;
3003 if (env->iflags & D_FLAG) {
3004 env->sregs[SR_ESR] |= 1 << 12;
3005 env->sregs[SR_PC] -= 4;
b4916d7b 3006 /* FIXME: if branch was immed, replay the imm as well. */
b76da7e3
EI		 3007 }
3008
3009 env->iflags &= ~(IMM_FLAG | D_FLAG);
3010
3011 switch (env->sregs[SR_ESR] & 31) {
22a78d64 3012 case ESR_EC_DIVZERO:
a86b3c64 3013 info.si_signo = TARGET_SIGFPE;
22a78d64
EI		 3014 info.si_errno = 0;
3015 info.si_code = TARGET_FPE_FLTDIV;
3016 info._sifields._sigfault._addr = 0;
3017 queue_signal(env, info.si_signo, &info);
3018 break;
b76da7e3 3019 case ESR_EC_FPU:
a86b3c64 3020 info.si_signo = TARGET_SIGFPE;
b76da7e3
EI		 3021 info.si_errno = 0;
3022 if (env->sregs[SR_FSR] & FSR_IO) {
3023 info.si_code = TARGET_FPE_FLTINV;
3024 }
3025 if (env->sregs[SR_FSR] & FSR_DZ) {
3026 info.si_code = TARGET_FPE_FLTDIV;
3027 }
3028 info._sifields._sigfault._addr = 0;
3029 queue_signal(env, info.si_signo, &info);
3030 break;
3031 default:
3032 printf ("Unhandled hw-exception: 0x%x\n",
2e42d52d 3033 env->sregs[SR_ESR] & ESR_EC_MASK);
878096ee 3034 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3035 exit(EXIT_FAILURE);
b76da7e3
EI		 3036 break;
3037 }
3038 break;
b779e29e
EI		 3039 case EXCP_DEBUG:
3040 {
3041 int sig;
3042
db6b81d4 3043 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
b779e29e
EI		 3044 if (sig)
3045 {
3046 info.si_signo = sig;
3047 info.si_errno = 0;
3048 info.si_code = TARGET_TRAP_BRKPT;
3049 queue_signal(env, info.si_signo, &info);
3050 }
3051 }
3052 break;
3053 default:
3054 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3055 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3056 exit(EXIT_FAILURE);
b779e29e
EI		 3057 }
3058 process_pending_signals (env);
3059 }
3060}
3061#endif
3062
e6e5906b
PB		 3063#ifdef TARGET_M68K
3064
3065void cpu_loop(CPUM68KState *env)
3066{
878096ee 3067 CPUState *cs = CPU(m68k_env_get_cpu(env));
e6e5906b
PB		 3068 int trapnr;
3069 unsigned int n;
c227f099 3070 target_siginfo_t info;
0429a971 3071 TaskState *ts = cs->opaque;
3b46e624 3072
e6e5906b 3073 for(;;) {
b040bc9c 3074 cpu_exec_start(cs);
ea3e9847 3075 trapnr = cpu_m68k_exec(cs);
b040bc9c 3076 cpu_exec_end(cs);
e6e5906b
PB		 3077 switch(trapnr) {
3078 case EXCP_ILLEGAL:
3079 {
3080 if (ts->sim_syscalls) {
3081 uint16_t nr;
d8d5119c 3082 get_user_u16(nr, env->pc + 2);
e6e5906b
PB		 3083 env->pc += 4;
3084 do_m68k_simcall(env, nr);
3085 } else {
3086 goto do_sigill;
3087 }
3088 }
3089 break;
a87295e8 3090 case EXCP_HALT_INSN:
e6e5906b 3091 /* Semihosing syscall. */
a87295e8 3092 env->pc += 4;
e6e5906b
PB		 3093 do_m68k_semihosting(env, env->dregs[0]);
3094 break;
3095 case EXCP_LINEA:
3096 case EXCP_LINEF:
3097 case EXCP_UNSUPPORTED:
3098 do_sigill:
a86b3c64 3099 info.si_signo = TARGET_SIGILL;
e6e5906b
PB		 3100 info.si_errno = 0;
3101 info.si_code = TARGET_ILL_ILLOPN;
3102 info._sifields._sigfault._addr = env->pc;
624f7979 3103 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3104 break;
3105 case EXCP_TRAP0:
3106 {
7ccb84a9 3107 abi_long ret;
e6e5906b
PB		 3108 ts->sim_syscalls = 0;
3109 n = env->dregs[0];
3110 env->pc += 2;
7ccb84a9
TB		 3111 ret = do_syscall(env,
3112 n,
3113 env->dregs[1],
3114 env->dregs[2],
3115 env->dregs[3],
3116 env->dregs[4],
3117 env->dregs[5],
3118 env->aregs[0],
3119 0, 0);
3120 if (ret == -TARGET_ERESTARTSYS) {
3121 env->pc -= 2;
3122 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3123 env->dregs[0] = ret;
3124 }
e6e5906b
PB		 3125 }
3126 break;
3127 case EXCP_INTERRUPT:
3128 /* just indicate that signals should be handled asap */
3129 break;
3130 case EXCP_ACCESS:
3131 {
a86b3c64 3132 info.si_signo = TARGET_SIGSEGV;
e6e5906b
PB		 3133 info.si_errno = 0;
3134 /* XXX: check env->error_code */
3135 info.si_code = TARGET_SEGV_MAPERR;
3136 info._sifields._sigfault._addr = env->mmu.ar;
624f7979 3137 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3138 }
3139 break;
3140 case EXCP_DEBUG:
3141 {
3142 int sig;
3143
db6b81d4 3144 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
e6e5906b
PB		 3145 if (sig)
3146 {
3147 info.si_signo = sig;
3148 info.si_errno = 0;
3149 info.si_code = TARGET_TRAP_BRKPT;
624f7979 3150 queue_signal(env, info.si_signo, &info);
e6e5906b
PB		 3151 }
3152 }
3153 break;
3154 default:
120a9848 3155 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
e6e5906b
PB		 3156 abort();
3157 }
3158 process_pending_signals(env);
3159 }
3160}
3161#endif /* TARGET_M68K */
3162
7a3148a9 3163#ifdef TARGET_ALPHA
6910b8f6
RH		 3164static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3165{
3166 target_ulong addr, val, tmp;
3167 target_siginfo_t info;
3168 int ret = 0;
3169
3170 addr = env->lock_addr;
3171 tmp = env->lock_st_addr;
3172 env->lock_addr = -1;
3173 env->lock_st_addr = 0;
3174
3175 start_exclusive();
3176 mmap_lock();
3177
3178 if (addr == tmp) {
3179 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3180 goto do_sigsegv;
3181 }
3182
3183 if (val == env->lock_value) {
3184 tmp = env->ir[reg];
3185 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3186 goto do_sigsegv;
3187 }
3188 ret = 1;
3189 }
3190 }
3191 env->ir[reg] = ret;
3192 env->pc += 4;
3193
3194 mmap_unlock();
3195 end_exclusive();
3196 return;
3197
3198 do_sigsegv:
3199 mmap_unlock();
3200 end_exclusive();
3201
3202 info.si_signo = TARGET_SIGSEGV;
3203 info.si_errno = 0;
3204 info.si_code = TARGET_SEGV_MAPERR;
3205 info._sifields._sigfault._addr = addr;
3206 queue_signal(env, TARGET_SIGSEGV, &info);
3207}
3208
05390248 3209void cpu_loop(CPUAlphaState *env)
7a3148a9 3210{
878096ee 3211 CPUState *cs = CPU(alpha_env_get_cpu(env));
e96efcfc 3212 int trapnr;
c227f099 3213 target_siginfo_t info;
6049f4f8 3214 abi_long sysret;
3b46e624 3215
7a3148a9 3216 while (1) {
b040bc9c 3217 cpu_exec_start(cs);
ea3e9847 3218 trapnr = cpu_alpha_exec(cs);
b040bc9c 3219 cpu_exec_end(cs);
3b46e624 3220
ac316ca4
RH		 3221 /* All of the traps imply a transition through PALcode, which
3222 implies an REI instruction has been executed. Which means
3223 that the intr_flag should be cleared. */
3224 env->intr_flag = 0;
3225
7a3148a9
JM		 3226 switch (trapnr) {
3227 case EXCP_RESET:
3228 fprintf(stderr, "Reset requested. Exit\n");
4d1275c2 3229 exit(EXIT_FAILURE);
7a3148a9
JM		 3230 break;
3231 case EXCP_MCHK:
3232 fprintf(stderr, "Machine check exception. Exit\n");
4d1275c2 3233 exit(EXIT_FAILURE);
7a3148a9 3234 break;
07b6c13b
RH		 3235 case EXCP_SMP_INTERRUPT:
3236 case EXCP_CLK_INTERRUPT:
3237 case EXCP_DEV_INTERRUPT:
5fafdf24 3238 fprintf(stderr, "External interrupt. Exit\n");
4d1275c2 3239 exit(EXIT_FAILURE);
7a3148a9 3240 break;
07b6c13b 3241 case EXCP_MMFAULT:
6910b8f6 3242 env->lock_addr = -1;
6049f4f8
RH		 3243 info.si_signo = TARGET_SIGSEGV;
3244 info.si_errno = 0;
129d8aa5 3245 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
0be1d07c 3246 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
129d8aa5 3247 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3248 queue_signal(env, info.si_signo, &info);
7a3148a9 3249 break;
7a3148a9 3250 case EXCP_UNALIGN:
6910b8f6 3251 env->lock_addr = -1;
6049f4f8
RH		 3252 info.si_signo = TARGET_SIGBUS;
3253 info.si_errno = 0;
3254 info.si_code = TARGET_BUS_ADRALN;
129d8aa5 3255 info._sifields._sigfault._addr = env->trap_arg0;
6049f4f8 3256 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3257 break;
3258 case EXCP_OPCDEC:
6049f4f8 3259 do_sigill:
6910b8f6 3260 env->lock_addr = -1;
6049f4f8
RH		 3261 info.si_signo = TARGET_SIGILL;
3262 info.si_errno = 0;
3263 info.si_code = TARGET_ILL_ILLOPC;
3264 info._sifields._sigfault._addr = env->pc;
3265 queue_signal(env, info.si_signo, &info);
7a3148a9 3266 break;
07b6c13b
RH		 3267 case EXCP_ARITH:
3268 env->lock_addr = -1;
3269 info.si_signo = TARGET_SIGFPE;
3270 info.si_errno = 0;
3271 info.si_code = TARGET_FPE_FLTINV;
3272 info._sifields._sigfault._addr = env->pc;
3273 queue_signal(env, info.si_signo, &info);
3274 break;
7a3148a9 3275 case EXCP_FEN:
6049f4f8 3276 /* No-op. Linux simply re-enables the FPU. */
7a3148a9 3277 break;
07b6c13b 3278 case EXCP_CALL_PAL:
6910b8f6 3279 env->lock_addr = -1;
07b6c13b 3280 switch (env->error_code) {
6049f4f8
RH		 3281 case 0x80:
3282 /* BPT */
3283 info.si_signo = TARGET_SIGTRAP;
3284 info.si_errno = 0;
3285 info.si_code = TARGET_TRAP_BRKPT;
3286 info._sifields._sigfault._addr = env->pc;
3287 queue_signal(env, info.si_signo, &info);
3288 break;
3289 case 0x81:
3290 /* BUGCHK */
3291 info.si_signo = TARGET_SIGTRAP;
3292 info.si_errno = 0;
3293 info.si_code = 0;
3294 info._sifields._sigfault._addr = env->pc;
3295 queue_signal(env, info.si_signo, &info);
3296 break;
3297 case 0x83:
3298 /* CALLSYS */
3299 trapnr = env->ir[IR_V0];
3300 sysret = do_syscall(env, trapnr,
3301 env->ir[IR_A0], env->ir[IR_A1],
3302 env->ir[IR_A2], env->ir[IR_A3],
5945cfcb
PM		 3303 env->ir[IR_A4], env->ir[IR_A5],
3304 0, 0);
338c858c
TB		 3305 if (sysret == -TARGET_ERESTARTSYS) {
3306 env->pc -= 4;
3307 break;
3308 }
3309 if (sysret == -TARGET_QEMU_ESIGRETURN) {
a5b3b13b
RH		 3310 break;
3311 }
3312 /* Syscall writes 0 to V0 to bypass error check, similar
0e141977
RH		 3313 to how this is handled internal to Linux kernel.
3314 (Ab)use trapnr temporarily as boolean indicating error. */
3315 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3316 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3317 env->ir[IR_A3] = trapnr;
6049f4f8
RH		 3318 break;
3319 case 0x86:
3320 /* IMB */
3321 /* ??? We can probably elide the code using page_unprotect
3322 that is checking for self-modifying code. Instead we
3323 could simply call tb_flush here. Until we work out the
3324 changes required to turn off the extra write protection,
3325 this can be a no-op. */
3326 break;
3327 case 0x9E:
3328 /* RDUNIQUE */
3329 /* Handled in the translator for usermode. */
3330 abort();
3331 case 0x9F:
3332 /* WRUNIQUE */
3333 /* Handled in the translator for usermode. */
3334 abort();
3335 case 0xAA:
3336 /* GENTRAP */
3337 info.si_signo = TARGET_SIGFPE;
3338 switch (env->ir[IR_A0]) {
3339 case TARGET_GEN_INTOVF:
3340 info.si_code = TARGET_FPE_INTOVF;
3341 break;
3342 case TARGET_GEN_INTDIV:
3343 info.si_code = TARGET_FPE_INTDIV;
3344 break;
3345 case TARGET_GEN_FLTOVF:
3346 info.si_code = TARGET_FPE_FLTOVF;
3347 break;
3348 case TARGET_GEN_FLTUND:
3349 info.si_code = TARGET_FPE_FLTUND;
3350 break;
3351 case TARGET_GEN_FLTINV:
3352 info.si_code = TARGET_FPE_FLTINV;
3353 break;
3354 case TARGET_GEN_FLTINE:
3355 info.si_code = TARGET_FPE_FLTRES;
3356 break;
3357 case TARGET_GEN_ROPRAND:
3358 info.si_code = 0;
3359 break;
3360 default:
3361 info.si_signo = TARGET_SIGTRAP;
3362 info.si_code = 0;
3363 break;
3364 }
3365 info.si_errno = 0;
3366 info._sifields._sigfault._addr = env->pc;
3367 queue_signal(env, info.si_signo, &info);
3368 break;
3369 default:
3370 goto do_sigill;
3371 }
7a3148a9 3372 break;
7a3148a9 3373 case EXCP_DEBUG:
db6b81d4 3374 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
6049f4f8 3375 if (info.si_signo) {
6910b8f6 3376 env->lock_addr = -1;
6049f4f8
RH		 3377 info.si_errno = 0;
3378 info.si_code = TARGET_TRAP_BRKPT;
3379 queue_signal(env, info.si_signo, &info);
7a3148a9
JM		 3380 }
3381 break;
6910b8f6
RH		 3382 case EXCP_STL_C:
3383 case EXCP_STQ_C:
3384 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3385 break;
d0f20495
RH		 3386 case EXCP_INTERRUPT:
3387 /* Just indicate that signals should be handled asap. */
3388 break;
7a3148a9
JM		 3389 default:
3390 printf ("Unhandled trap: 0x%x\n", trapnr);
878096ee 3391 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3392 exit(EXIT_FAILURE);
7a3148a9
JM		 3393 }
3394 process_pending_signals (env);
3395 }
3396}
3397#endif /* TARGET_ALPHA */
3398
a4c075f1
UH		 3399#ifdef TARGET_S390X
3400void cpu_loop(CPUS390XState *env)
3401{
878096ee 3402 CPUState *cs = CPU(s390_env_get_cpu(env));
d5a103cd 3403 int trapnr, n, sig;
a4c075f1 3404 target_siginfo_t info;
d5a103cd 3405 target_ulong addr;
47405ab6 3406 abi_long ret;
a4c075f1
UH		 3407
3408 while (1) {
b040bc9c 3409 cpu_exec_start(cs);
ea3e9847 3410 trapnr = cpu_s390x_exec(cs);
b040bc9c 3411 cpu_exec_end(cs);
a4c075f1
UH		 3412 switch (trapnr) {
3413 case EXCP_INTERRUPT:
d5a103cd 3414 /* Just indicate that signals should be handled asap. */
a4c075f1 3415 break;
a4c075f1 3416
d5a103cd
RH		 3417 case EXCP_SVC:
3418 n = env->int_svc_code;
3419 if (!n) {
3420 /* syscalls > 255 */
3421 n = env->regs[1];
a4c075f1 3422 }
d5a103cd 3423 env->psw.addr += env->int_svc_ilen;
47405ab6
TB		 3424 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3425 env->regs[4], env->regs[5],
3426 env->regs[6], env->regs[7], 0, 0);
3427 if (ret == -TARGET_ERESTARTSYS) {
3428 env->psw.addr -= env->int_svc_ilen;
3429 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3430 env->regs[2] = ret;
3431 }
a4c075f1 3432 break;
d5a103cd
RH		 3433
3434 case EXCP_DEBUG:
db6b81d4 3435 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
d5a103cd
RH		 3436 if (sig) {
3437 n = TARGET_TRAP_BRKPT;
3438 goto do_signal_pc;
a4c075f1
UH		 3439 }
3440 break;
d5a103cd
RH		 3441 case EXCP_PGM:
3442 n = env->int_pgm_code;
3443 switch (n) {
3444 case PGM_OPERATION:
3445 case PGM_PRIVILEGED:
a86b3c64 3446 sig = TARGET_SIGILL;
d5a103cd
RH		 3447 n = TARGET_ILL_ILLOPC;
3448 goto do_signal_pc;
3449 case PGM_PROTECTION:
3450 case PGM_ADDRESSING:
a86b3c64 3451 sig = TARGET_SIGSEGV;
a4c075f1 3452 /* XXX: check env->error_code */
d5a103cd
RH		 3453 n = TARGET_SEGV_MAPERR;
3454 addr = env->__excp_addr;
3455 goto do_signal;
3456 case PGM_EXECUTE:
3457 case PGM_SPECIFICATION:
3458 case PGM_SPECIAL_OP:
3459 case PGM_OPERAND:
3460 do_sigill_opn:
a86b3c64 3461 sig = TARGET_SIGILL;
d5a103cd
RH		 3462 n = TARGET_ILL_ILLOPN;
3463 goto do_signal_pc;
3464
3465 case PGM_FIXPT_OVERFLOW:
a86b3c64 3466 sig = TARGET_SIGFPE;
d5a103cd
RH		 3467 n = TARGET_FPE_INTOVF;
3468 goto do_signal_pc;
3469 case PGM_FIXPT_DIVIDE:
a86b3c64 3470 sig = TARGET_SIGFPE;
d5a103cd
RH		 3471 n = TARGET_FPE_INTDIV;
3472 goto do_signal_pc;
3473
3474 case PGM_DATA:
3475 n = (env->fpc >> 8) & 0xff;
3476 if (n == 0xff) {
3477 /* compare-and-trap */
3478 goto do_sigill_opn;
3479 } else {
3480 /* An IEEE exception, simulated or otherwise. */
3481 if (n & 0x80) {
3482 n = TARGET_FPE_FLTINV;
3483 } else if (n & 0x40) {
3484 n = TARGET_FPE_FLTDIV;
3485 } else if (n & 0x20) {
3486 n = TARGET_FPE_FLTOVF;
3487 } else if (n & 0x10) {
3488 n = TARGET_FPE_FLTUND;
3489 } else if (n & 0x08) {
3490 n = TARGET_FPE_FLTRES;
3491 } else {
3492 /* ??? Quantum exception; BFP, DFP error. */
3493 goto do_sigill_opn;
3494 }
a86b3c64 3495 sig = TARGET_SIGFPE;
d5a103cd
RH		 3496 goto do_signal_pc;
3497 }
3498
3499 default:
3500 fprintf(stderr, "Unhandled program exception: %#x\n", n);
878096ee 3501 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3502 exit(EXIT_FAILURE);
a4c075f1
UH		 3503 }
3504 break;
d5a103cd
RH		 3505
3506 do_signal_pc:
3507 addr = env->psw.addr;
3508 do_signal:
3509 info.si_signo = sig;
3510 info.si_errno = 0;
3511 info.si_code = n;
3512 info._sifields._sigfault._addr = addr;
3513 queue_signal(env, info.si_signo, &info);
a4c075f1 3514 break;
d5a103cd 3515
a4c075f1 3516 default:
d5a103cd 3517 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
878096ee 3518 cpu_dump_state(cs, stderr, fprintf, 0);
4d1275c2 3519 exit(EXIT_FAILURE);
a4c075f1
UH		 3520 }
3521 process_pending_signals (env);
3522 }
3523}
3524
3525#endif /* TARGET_S390X */
3526
b16189b2
CG		 3527#ifdef TARGET_TILEGX
3528
b16189b2
CG		 3529static void gen_sigill_reg(CPUTLGState *env)
3530{
3531 target_siginfo_t info;
3532
3533 info.si_signo = TARGET_SIGILL;
3534 info.si_errno = 0;
3535 info.si_code = TARGET_ILL_PRVREG;
3536 info._sifields._sigfault._addr = env->pc;
3537 queue_signal(env, info.si_signo, &info);
3538}
3539
a0577d2a 3540static void do_signal(CPUTLGState *env, int signo, int sigcode)
dd8070d8
CG		 3541{
3542 target_siginfo_t info;
3543
a0577d2a 3544 info.si_signo = signo;
dd8070d8 3545 info.si_errno = 0;
dd8070d8 3546 info._sifields._sigfault._addr = env->pc;
a0577d2a
RH		 3547
3548 if (signo == TARGET_SIGSEGV) {
3549 /* The passed in sigcode is a dummy; check for a page mapping
3550 and pass either MAPERR or ACCERR. */
3551 target_ulong addr = env->excaddr;
3552 info._sifields._sigfault._addr = addr;
3553 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3554 sigcode = TARGET_SEGV_MAPERR;
3555 } else {
3556 sigcode = TARGET_SEGV_ACCERR;
3557 }
3558 }
3559 info.si_code = sigcode;
3560
dd8070d8
CG		 3561 queue_signal(env, info.si_signo, &info);
3562}
3563
a0577d2a
RH		 3564static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3565{
3566 env->excaddr = addr;
3567 do_signal(env, TARGET_SIGSEGV, 0);
3568}
3569
0583b233
RH		 3570static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3571{
3572 if (unlikely(reg >= TILEGX_R_COUNT)) {
3573 switch (reg) {
3574 case TILEGX_R_SN:
3575 case TILEGX_R_ZERO:
3576 return;
3577 case TILEGX_R_IDN0:
3578 case TILEGX_R_IDN1:
3579 case TILEGX_R_UDN0:
3580 case TILEGX_R_UDN1:
3581 case TILEGX_R_UDN2:
3582 case TILEGX_R_UDN3:
3583 gen_sigill_reg(env);
3584 return;
3585 default:
3586 g_assert_not_reached();
3587 }
3588 }
3589 env->regs[reg] = val;
3590}
3591
3592/*
3593 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3594 * memory at the address held in the first source register. If the values are
3595 * not equal, then no memory operation is performed. If the values are equal,
3596 * the 8-byte quantity from the second source register is written into memory
3597 * at the address held in the first source register. In either case, the result
3598 * of the instruction is the value read from memory. The compare and write to
3599 * memory are atomic and thus can be used for synchronization purposes. This
3600 * instruction only operates for addresses aligned to a 8-byte boundary.
3601 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3602 *
3603 * Functional Description (64-bit)
3604 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3605 * rf[Dest] = memVal;
3606 * if (memVal == SPR[CmpValueSPR])
3607 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3608 *
3609 * Functional Description (32-bit)
3610 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3611 * rf[Dest] = memVal;
3612 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3613 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3614 *
3615 *
3616 * This function also processes exch and exch4 which need not process SPR.
3617 */
3618static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3619{
3620 target_ulong addr;
3621 target_long val, sprval;
3622
3623 start_exclusive();
3624
3625 addr = env->atomic_srca;
3626 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3627 goto sigsegv_maperr;
3628 }
3629
3630 if (cmp) {
3631 if (quad) {
3632 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3633 } else {
3634 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3635 }
3636 }
3637
3638 if (!cmp || val == sprval) {
3639 target_long valb = env->atomic_srcb;
3640 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3641 goto sigsegv_maperr;
3642 }
3643 }
3644
3645 set_regval(env, env->atomic_dstr, val);
3646 end_exclusive();
3647 return;
3648
3649 sigsegv_maperr:
3650 end_exclusive();
3651 gen_sigsegv_maperr(env, addr);
3652}
3653
3654static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3655{
3656 int8_t write = 1;
3657 target_ulong addr;
3658 target_long val, valb;
3659
3660 start_exclusive();
3661
3662 addr = env->atomic_srca;
3663 valb = env->atomic_srcb;
3664 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3665 goto sigsegv_maperr;
3666 }
3667
3668 switch (trapnr) {
3669 case TILEGX_EXCP_OPCODE_FETCHADD:
3670 case TILEGX_EXCP_OPCODE_FETCHADD4:
3671 valb += val;
3672 break;
3673 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3674 valb += val;
3675 if (valb < 0) {
3676 write = 0;
3677 }
3678 break;
3679 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3680 valb += val;
3681 if ((int32_t)valb < 0) {
3682 write = 0;
3683 }
3684 break;
3685 case TILEGX_EXCP_OPCODE_FETCHAND:
3686 case TILEGX_EXCP_OPCODE_FETCHAND4:
3687 valb &= val;
3688 break;
3689 case TILEGX_EXCP_OPCODE_FETCHOR:
3690 case TILEGX_EXCP_OPCODE_FETCHOR4:
3691 valb |= val;
3692 break;
3693 default:
3694 g_assert_not_reached();
3695 }
3696
3697 if (write) {
3698 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3699 goto sigsegv_maperr;
3700 }
3701 }
3702
3703 set_regval(env, env->atomic_dstr, val);
3704 end_exclusive();
3705 return;
3706
3707 sigsegv_maperr:
3708 end_exclusive();
3709 gen_sigsegv_maperr(env, addr);
3710}
3711
b16189b2
CG		 3712void cpu_loop(CPUTLGState *env)
3713{
3714 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3715 int trapnr;
3716
3717 while (1) {
3718 cpu_exec_start(cs);
3719 trapnr = cpu_tilegx_exec(cs);
3720 cpu_exec_end(cs);
3721 switch (trapnr) {
3722 case TILEGX_EXCP_SYSCALL:
a9175169
PM		 3723 {
3724 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3725 env->regs[0], env->regs[1],
3726 env->regs[2], env->regs[3],
3727 env->regs[4], env->regs[5],
3728 env->regs[6], env->regs[7]);
3729 if (ret == -TARGET_ERESTARTSYS) {
3730 env->pc -= 8;
3731 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3732 env->regs[TILEGX_R_RE] = ret;
3733 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3734 }
b16189b2 3735 break;
a9175169 3736 }
0583b233
RH		 3737 case TILEGX_EXCP_OPCODE_EXCH:
3738 do_exch(env, true, false);
3739 break;
3740 case TILEGX_EXCP_OPCODE_EXCH4:
3741 do_exch(env, false, false);
3742 break;
3743 case TILEGX_EXCP_OPCODE_CMPEXCH:
3744 do_exch(env, true, true);
3745 break;
3746 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3747 do_exch(env, false, true);
3748 break;
3749 case TILEGX_EXCP_OPCODE_FETCHADD:
3750 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3751 case TILEGX_EXCP_OPCODE_FETCHAND:
3752 case TILEGX_EXCP_OPCODE_FETCHOR:
3753 do_fetch(env, trapnr, true);
3754 break;
3755 case TILEGX_EXCP_OPCODE_FETCHADD4:
3756 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3757 case TILEGX_EXCP_OPCODE_FETCHAND4:
3758 case TILEGX_EXCP_OPCODE_FETCHOR4:
3759 do_fetch(env, trapnr, false);
3760 break;
dd8070d8 3761 case TILEGX_EXCP_SIGNAL:
a0577d2a 3762 do_signal(env, env->signo, env->sigcode);
dd8070d8 3763 break;
b16189b2
CG		 3764 case TILEGX_EXCP_REG_IDN_ACCESS:
3765 case TILEGX_EXCP_REG_UDN_ACCESS:
3766 gen_sigill_reg(env);
3767 break;
3768 default:
3769 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3770 g_assert_not_reached();
3771 }
3772 process_pending_signals(env);
3773 }
3774}
3775
3776#endif
3777
a2247f8e 3778THREAD CPUState *thread_cpu;
59faf6d6 3779
edf8e2af
MW		 3780void task_settid(TaskState *ts)
3781{
3782 if (ts->ts_tid == 0) {
edf8e2af 3783 ts->ts_tid = (pid_t)syscall(SYS_gettid);
edf8e2af
MW		 3784 }
3785}
3786
3787void stop_all_tasks(void)
3788{
3789 /*
3790 * We trust that when using NPTL, start_exclusive()
3791 * handles thread stopping correctly.
3792 */
3793 start_exclusive();
3794}
3795
c3a92833 3796/* Assumes contents are already zeroed. */
624f7979
PB		 3797void init_task_state(TaskState *ts)
3798{
624f7979 3799 ts->used = 1;
624f7979 3800}
fc9c5412 3801
30ba0ee5
AF		 3802CPUArchState *cpu_copy(CPUArchState *env)
3803{
ff4700b0 3804 CPUState *cpu = ENV_GET_CPU(env);
2994fd96 3805 CPUState *new_cpu = cpu_init(cpu_model);
61c7480f 3806 CPUArchState *new_env = new_cpu->env_ptr;
30ba0ee5
AF		 3807 CPUBreakpoint *bp;
3808 CPUWatchpoint *wp;
30ba0ee5
AF		 3809
3810 /* Reset non arch specific state */
75a34036 3811 cpu_reset(new_cpu);
30ba0ee5
AF		 3812
3813 memcpy(new_env, env, sizeof(CPUArchState));
3814
3815 /* Clone all break/watchpoints.
3816 Note: Once we support ptrace with hw-debug register access, make sure
3817 BP_CPU break/watchpoints are handled correctly on clone. */
1d085f6c
TB		 3818 QTAILQ_INIT(&new_cpu->breakpoints);
3819 QTAILQ_INIT(&new_cpu->watchpoints);
f0c3c505 3820 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
b3310ab3 3821 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
30ba0ee5 3822 }
ff4700b0 3823 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
05068c0d 3824 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
30ba0ee5 3825 }
30ba0ee5
AF		 3826
3827 return new_env;
3828}
3829
fc9c5412
JS		 3830static void handle_arg_help(const char *arg)
3831{
4d1275c2 3832 usage(EXIT_SUCCESS);
fc9c5412
JS		 3833}
3834
3835static void handle_arg_log(const char *arg)
3836{
3837 int mask;
fc9c5412 3838
4fde1eba 3839 mask = qemu_str_to_log_mask(arg);
fc9c5412 3840 if (!mask) {
59a6fa6e 3841 qemu_print_log_usage(stdout);
4d1275c2 3842 exit(EXIT_FAILURE);
fc9c5412 3843 }
f2937a33 3844 qemu_log_needs_buffers();
24537a01 3845 qemu_set_log(mask);
fc9c5412
JS		 3846}
3847
50171d42
CWR		 3848static void handle_arg_log_filename(const char *arg)
3849{
daa76aa4 3850 qemu_set_log_filename(arg, &error_fatal);
50171d42
CWR		 3851}
3852
fc9c5412
JS		 3853static void handle_arg_set_env(const char *arg)
3854{
3855 char *r, *p, *token;
3856 r = p = strdup(arg);
3857 while ((token = strsep(&p, ",")) != NULL) {
3858 if (envlist_setenv(envlist, token) != 0) {
4d1275c2 3859 usage(EXIT_FAILURE);
fc9c5412
JS		 3860 }
3861 }
3862 free(r);
3863}
3864
3865static void handle_arg_unset_env(const char *arg)
3866{
3867 char *r, *p, *token;
3868 r = p = strdup(arg);
3869 while ((token = strsep(&p, ",")) != NULL) {
3870 if (envlist_unsetenv(envlist, token) != 0) {
4d1275c2 3871 usage(EXIT_FAILURE);
fc9c5412
JS		 3872 }
3873 }
3874 free(r);
3875}
3876
3877static void handle_arg_argv0(const char *arg)
3878{
3879 argv0 = strdup(arg);
3880}
3881
3882static void handle_arg_stack_size(const char *arg)
3883{
3884 char *p;
3885 guest_stack_size = strtoul(arg, &p, 0);
3886 if (guest_stack_size == 0) {
4d1275c2 3887 usage(EXIT_FAILURE);
fc9c5412
JS		 3888 }
3889
3890 if (*p == 'M') {
3891 guest_stack_size *= 1024 * 1024;
3892 } else if (*p == 'k' || *p == 'K') {
3893 guest_stack_size *= 1024;
3894 }
3895}
3896
3897static void handle_arg_ld_prefix(const char *arg)
3898{
3899 interp_prefix = strdup(arg);
3900}
3901
3902static void handle_arg_pagesize(const char *arg)
3903{
3904 qemu_host_page_size = atoi(arg);
3905 if (qemu_host_page_size == 0 ||
3906 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3907 fprintf(stderr, "page size must be a power of two\n");
4d1275c2 3908 exit(EXIT_FAILURE);
fc9c5412
JS		 3909 }
3910}
3911
c5e4a5a9
MR		 3912static void handle_arg_randseed(const char *arg)
3913{
3914 unsigned long long seed;
3915
3916 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3917 fprintf(stderr, "Invalid seed number: %s\n", arg);
4d1275c2 3918 exit(EXIT_FAILURE);
c5e4a5a9
MR		 3919 }
3920 srand(seed);
3921}
3922
fc9c5412
JS		 3923static void handle_arg_gdb(const char *arg)
3924{
3925 gdbstub_port = atoi(arg);
3926}
3927
3928static void handle_arg_uname(const char *arg)
3929{
3930 qemu_uname_release = strdup(arg);
3931}
3932
3933static void handle_arg_cpu(const char *arg)
3934{
3935 cpu_model = strdup(arg);
c8057f95 3936 if (cpu_model == NULL || is_help_option(cpu_model)) {
fc9c5412 3937 /* XXX: implement xxx_cpu_list for targets that still miss it */
e916cbf8
PM		 3938#if defined(cpu_list)
3939 cpu_list(stdout, &fprintf);
fc9c5412 3940#endif
4d1275c2 3941 exit(EXIT_FAILURE);
fc9c5412
JS		 3942 }
3943}
3944
fc9c5412
JS		 3945static void handle_arg_guest_base(const char *arg)
3946{
3947 guest_base = strtol(arg, NULL, 0);
3948 have_guest_base = 1;
3949}
3950
3951static void handle_arg_reserved_va(const char *arg)
3952{
3953 char *p;
3954 int shift = 0;
3955 reserved_va = strtoul(arg, &p, 0);
3956 switch (*p) {
3957 case 'k':
3958 case 'K':
3959 shift = 10;
3960 break;
3961 case 'M':
3962 shift = 20;
3963 break;
3964 case 'G':
3965 shift = 30;
3966 break;
3967 }
3968 if (shift) {
3969 unsigned long unshifted = reserved_va;
3970 p++;
3971 reserved_va <<= shift;
3972 if (((reserved_va >> shift) != unshifted)
3973#if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3974 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3975#endif
3976 ) {
3977 fprintf(stderr, "Reserved virtual address too big\n");
4d1275c2 3978 exit(EXIT_FAILURE);
fc9c5412
JS		 3979 }
3980 }
3981 if (*p) {
3982 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4d1275c2 3983 exit(EXIT_FAILURE);
fc9c5412
JS		 3984 }
3985}
fc9c5412
JS		 3986
3987static void handle_arg_singlestep(const char *arg)
3988{
3989 singlestep = 1;
3990}
3991
3992static void handle_arg_strace(const char *arg)
3993{
3994 do_strace = 1;
3995}
3996
3997static void handle_arg_version(const char *arg)
3998{
2e59915d 3999 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
fc9c5412 4000 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
4d1275c2 4001 exit(EXIT_SUCCESS);
fc9c5412
JS		 4002}
4003
4004struct qemu_argument {
4005 const char *argv;
4006 const char *env;
4007 bool has_arg;
4008 void (*handle_opt)(const char *arg);
4009 const char *example;
4010 const char *help;
4011};
4012
42644cee 4013static const struct qemu_argument arg_table[] = {
fc9c5412
JS		 4014 {"h", "", false, handle_arg_help,
4015 "", "print this help"},
daaf8c8e
MI		 4016 {"help", "", false, handle_arg_help,
4017 "", ""},
fc9c5412
JS		 4018 {"g", "QEMU_GDB", true, handle_arg_gdb,
4019 "port", "wait gdb connection to 'port'"},
4020 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4021 "path", "set the elf interpreter prefix to 'path'"},
4022 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4023 "size", "set the stack size to 'size' bytes"},
4024 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
c8057f95 4025 "model", "select CPU (-cpu help for list)"},
fc9c5412
JS		 4026 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4027 "var=value", "sets targets environment variable (see below)"},
4028 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4029 "var", "unsets targets environment variable (see below)"},
4030 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4031 "argv0", "forces target process argv[0] to be 'argv0'"},
4032 {"r", "QEMU_UNAME", true, handle_arg_uname,
4033 "uname", "set qemu uname release string to 'uname'"},
fc9c5412
JS		 4034 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4035 "address", "set guest_base address to 'address'"},
4036 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4037 "size", "reserve 'size' bytes for guest virtual address space"},
fc9c5412 4038 {"d", "QEMU_LOG", true, handle_arg_log,
989b697d
PM		 4039 "item[,...]", "enable logging of specified items "
4040 "(use '-d help' for a list of items)"},
50171d42 4041 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
989b697d 4042 "logfile", "write logs to 'logfile' (default stderr)"},
fc9c5412
JS		 4043 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4044 "pagesize", "set the host page size to 'pagesize'"},
4045 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4046 "", "run in singlestep mode"},
4047 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4048 "", "log system calls"},
c5e4a5a9
MR		 4049 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4050 "", "Seed for pseudo-random number generator"},
fc9c5412 4051 {"version", "QEMU_VERSION", false, handle_arg_version,
1386d4c0 4052 "", "display version information and exit"},
fc9c5412
JS		 4053 {NULL, NULL, false, NULL, NULL, NULL}
4054};
4055
d03f9c32 4056static void usage(int exitcode)
fc9c5412 4057{
42644cee 4058 const struct qemu_argument *arginfo;
fc9c5412
JS		 4059 int maxarglen;
4060 int maxenvlen;
4061
2e59915d
PB		 4062 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4063 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
fc9c5412
JS		 4064 "\n"
4065 "Options and associated environment variables:\n"
4066 "\n");
4067
63ec54d7
PM		 4068 /* Calculate column widths. We must always have at least enough space
4069 * for the column header.
4070 */
4071 maxarglen = strlen("Argument");
4072 maxenvlen = strlen("Env-variable");
fc9c5412
JS		 4073
4074 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
63ec54d7
PM		 4075 int arglen = strlen(arginfo->argv);
4076 if (arginfo->has_arg) {
4077 arglen += strlen(arginfo->example) + 1;
4078 }
fc9c5412
JS		 4079 if (strlen(arginfo->env) > maxenvlen) {
4080 maxenvlen = strlen(arginfo->env);
4081 }
63ec54d7
PM		 4082 if (arglen > maxarglen) {
4083 maxarglen = arglen;
fc9c5412
JS		 4084 }
4085 }
4086
63ec54d7
PM		 4087 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4088 maxenvlen, "Env-variable");
fc9c5412
JS		 4089
4090 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4091 if (arginfo->has_arg) {
4092 printf("-%s %-*s %-*s %s\n", arginfo->argv,
63ec54d7
PM		 4093 (int)(maxarglen - strlen(arginfo->argv) - 1),
4094 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
fc9c5412 4095 } else {
63ec54d7 4096 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
fc9c5412
JS		 4097 maxenvlen, arginfo->env,
4098 arginfo->help);
4099 }
4100 }
4101
4102 printf("\n"
4103 "Defaults:\n"
4104 "QEMU_LD_PREFIX = %s\n"
989b697d 4105 "QEMU_STACK_SIZE = %ld byte\n",
fc9c5412 4106 interp_prefix,
989b697d 4107 guest_stack_size);
fc9c5412
JS		 4108
4109 printf("\n"
4110 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4111 "QEMU_UNSET_ENV environment variables to set and unset\n"
4112 "environment variables for the target process.\n"
4113 "It is possible to provide several variables by separating them\n"
4114 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4115 "provide the -E and -U options multiple times.\n"
4116 "The following lines are equivalent:\n"
4117 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4118 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4119 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4120 "Note that if you provide several changes to a single variable\n"
4121 "the last change will stay in effect.\n");
4122
d03f9c32 4123 exit(exitcode);
fc9c5412
JS		 4124}
4125
4126static int parse_args(int argc, char **argv)
4127{
4128 const char *r;
4129 int optind;
42644cee 4130 const struct qemu_argument *arginfo;
fc9c5412
JS		 4131
4132 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4133 if (arginfo->env == NULL) {
4134 continue;
4135 }
4136
4137 r = getenv(arginfo->env);
4138 if (r != NULL) {
4139 arginfo->handle_opt(r);
4140 }
4141 }
4142
4143 optind = 1;
4144 for (;;) {
4145 if (optind >= argc) {
4146 break;
4147 }
4148 r = argv[optind];
4149 if (r[0] != '-') {
4150 break;
4151 }
4152 optind++;
4153 r++;
4154 if (!strcmp(r, "-")) {
4155 break;
4156 }
ba02577c
MI		 4157 /* Treat --foo the same as -foo. */
4158 if (r[0] == '-') {
4159 r++;
4160 }
fc9c5412
JS		 4161
4162 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4163 if (!strcmp(r, arginfo->argv)) {
fc9c5412 4164 if (arginfo->has_arg) {
1386d4c0 4165 if (optind >= argc) {
138940bf
MI		 4166 (void) fprintf(stderr,
4167 "qemu: missing argument for option '%s'\n", r);
4d1275c2 4168 exit(EXIT_FAILURE);
1386d4c0
PM		 4169 }
4170 arginfo->handle_opt(argv[optind]);
fc9c5412 4171 optind++;
1386d4c0
PM		 4172 } else {
4173 arginfo->handle_opt(NULL);
fc9c5412 4174 }
fc9c5412
JS		 4175 break;
4176 }
4177 }
4178
4179 /* no option matched the current argv */
4180 if (arginfo->handle_opt == NULL) {
138940bf 4181 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4d1275c2 4182 exit(EXIT_FAILURE);
fc9c5412
JS		 4183 }
4184 }
4185
4186 if (optind >= argc) {
138940bf 4187 (void) fprintf(stderr, "qemu: no user program specified\n");
4d1275c2 4188 exit(EXIT_FAILURE);
fc9c5412
JS		 4189 }
4190
4191 filename = argv[optind];
4192 exec_path = argv[optind];
4193
4194 return optind;
4195}
4196
902b3d5c 4197int main(int argc, char **argv, char **envp)
31e31b8a 4198{
01ffc75b 4199 struct target_pt_regs regs1, *regs = &regs1;
31e31b8a 4200 struct image_info info1, *info = &info1;
edf8e2af 4201 struct linux_binprm bprm;
48e15fc2 4202 TaskState *ts;
9349b4f9 4203 CPUArchState *env;
db6b81d4 4204 CPUState *cpu;
586314f2 4205 int optind;
04a6dfeb 4206 char **target_environ, **wrk;
7d8cec95
AJ		 4207 char **target_argv;
4208 int target_argc;
7d8cec95 4209 int i;
fd4d81dd 4210 int ret;
03cfd8fa 4211 int execfd;
b12b6a18 4212
ce008c1f
AF		 4213 module_call_init(MODULE_INIT_QOM);
4214
04a6dfeb
AJ		 4215 if ((envlist = envlist_create()) == NULL) {
4216 (void) fprintf(stderr, "Unable to allocate envlist\n");
4d1275c2 4217 exit(EXIT_FAILURE);
04a6dfeb
AJ		 4218 }
4219
4220 /* add current environment into the list */
4221 for (wrk = environ; *wrk != NULL; wrk++) {
4222 (void) envlist_setenv(envlist, *wrk);
4223 }
4224
703e0e89
RH		 4225 /* Read the stack limit from the kernel. If it's "unlimited",
4226 then we can do little else besides use the default. */
4227 {
4228 struct rlimit lim;
4229 if (getrlimit(RLIMIT_STACK, &lim) == 0
81bbe906
TY		 4230 && lim.rlim_cur != RLIM_INFINITY
4231 && lim.rlim_cur == (target_long)lim.rlim_cur) {
703e0e89
RH		 4232 guest_stack_size = lim.rlim_cur;
4233 }
4234 }
4235
b1f9be31 4236 cpu_model = NULL;
b5ec5ce0 4237
c5e4a5a9
MR		 4238 srand(time(NULL));
4239
fc9c5412 4240 optind = parse_args(argc, argv);
586314f2 4241
31e31b8a 4242 /* Zero out regs */
01ffc75b 4243 memset(regs, 0, sizeof(struct target_pt_regs));
31e31b8a
FB		 4244
4245 /* Zero out image_info */
4246 memset(info, 0, sizeof(struct image_info));
4247
edf8e2af
MW		 4248 memset(&bprm, 0, sizeof (bprm));
4249
74cd30b8
FB		 4250 /* Scan interp_prefix dir for replacement files. */
4251 init_paths(interp_prefix);
4252
4a24a758
PM		 4253 init_qemu_uname_release();
4254
46027c07 4255 if (cpu_model == NULL) {
aaed909a 4256#if defined(TARGET_I386)
46027c07
FB		 4257#ifdef TARGET_X86_64
4258 cpu_model = "qemu64";
4259#else
4260 cpu_model = "qemu32";
4261#endif
aaed909a 4262#elif defined(TARGET_ARM)
088ab16c 4263 cpu_model = "any";
d2fbca94
GX		 4264#elif defined(TARGET_UNICORE32)
4265 cpu_model = "any";
aaed909a
FB		 4266#elif defined(TARGET_M68K)
4267 cpu_model = "any";
4268#elif defined(TARGET_SPARC)
4269#ifdef TARGET_SPARC64
4270 cpu_model = "TI UltraSparc II";
4271#else
4272 cpu_model = "Fujitsu MB86904";
46027c07 4273#endif
aaed909a
FB		 4274#elif defined(TARGET_MIPS)
4275#if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
74797f40 4276 cpu_model = "5KEf";
aaed909a
FB		 4277#else
4278 cpu_model = "24Kf";
4279#endif
d962783e
JL		 4280#elif defined TARGET_OPENRISC
4281 cpu_model = "or1200";
aaed909a 4282#elif defined(TARGET_PPC)
a74029f6 4283# ifdef TARGET_PPC64
de3f1b98 4284 cpu_model = "POWER8";
a74029f6 4285# else
aaed909a 4286 cpu_model = "750";
a74029f6 4287# endif
91c45a38
RH		 4288#elif defined TARGET_SH4
4289 cpu_model = TYPE_SH7785_CPU;
aaed909a
FB		 4290#else
4291 cpu_model = "any";
4292#endif
4293 }
d5ab9713 4294 tcg_exec_init(0);
83fb7adf
FB		 4295 /* NOTE: we need to init the CPU at this stage to get
4296 qemu_host_page_size */
2994fd96
EH		 4297 cpu = cpu_init(cpu_model);
4298 if (!cpu) {
aaed909a 4299 fprintf(stderr, "Unable to find CPU definition\n");
4d1275c2 4300 exit(EXIT_FAILURE);
aaed909a 4301 }
2994fd96 4302 env = cpu->env_ptr;
0ac46af3 4303 cpu_reset(cpu);
b55a37c9 4304
db6b81d4 4305 thread_cpu = cpu;
3b46e624 4306
b6741956
FB		 4307 if (getenv("QEMU_STRACE")) {
4308 do_strace = 1;
b92c47c1
TS		 4309 }
4310
c5e4a5a9
MR		 4311 if (getenv("QEMU_RAND_SEED")) {
4312 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4313 }
4314
04a6dfeb
AJ		 4315 target_environ = envlist_to_environ(envlist, NULL);
4316 envlist_free(envlist);
b12b6a18 4317
379f6698
PB		 4318 /*
4319 * Now that page sizes are configured in cpu_init() we can do
4320 * proper page alignment for guest_base.
4321 */
4322 guest_base = HOST_PAGE_ALIGN(guest_base);
68a1c816 4323
806d1021
MI		 4324 if (reserved_va || have_guest_base) {
4325 guest_base = init_guest_space(guest_base, reserved_va, 0,
4326 have_guest_base);
4327 if (guest_base == (unsigned long)-1) {
097b8cb8
PM		 4328 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4329 "space for use as guest address space (check your virtual "
4330 "memory ulimit setting or reserve less using -R option)\n",
4331 reserved_va);
4d1275c2 4332 exit(EXIT_FAILURE);
68a1c816 4333 }
97cc7560 4334
806d1021
MI		 4335 if (reserved_va) {
4336 mmap_next_start = reserved_va;
97cc7560
DDAG		 4337 }
4338 }
379f6698
PB		 4339
4340 /*
4341 * Read in mmap_min_addr kernel parameter. This value is used
4342 * When loading the ELF image to determine whether guest_base
14f24e14 4343 * is needed. It is also used in mmap_find_vma.
379f6698 4344 */
14f24e14 4345 {
379f6698
PB		 4346 FILE *fp;
4347
4348 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4349 unsigned long tmp;
4350 if (fscanf(fp, "%lu", &tmp) == 1) {
4351 mmap_min_addr = tmp;
13829020 4352 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
379f6698
PB		 4353 }
4354 fclose(fp);
4355 }
4356 }
379f6698 4357
7d8cec95
AJ		 4358 /*
4359 * Prepare copy of argv vector for target.
4360 */
4361 target_argc = argc - optind;
4362 target_argv = calloc(target_argc + 1, sizeof (char *));
4363 if (target_argv == NULL) {
4364 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4d1275c2 4365 exit(EXIT_FAILURE);
7d8cec95
AJ		 4366 }
4367
4368 /*
4369 * If argv0 is specified (using '-0' switch) we replace
4370 * argv[0] pointer with the given one.
4371 */
4372 i = 0;
4373 if (argv0 != NULL) {
4374 target_argv[i++] = strdup(argv0);
4375 }
4376 for (; i < target_argc; i++) {
4377 target_argv[i] = strdup(argv[optind + i]);
4378 }
4379 target_argv[target_argc] = NULL;
4380
c78d65e8 4381 ts = g_new0(TaskState, 1);
edf8e2af
MW		 4382 init_task_state(ts);
4383 /* build Task State */
4384 ts->info = info;
4385 ts->bprm = &bprm;
0429a971 4386 cpu->opaque = ts;
edf8e2af
MW		 4387 task_settid(ts);
4388
0b959cf5
RH		 4389 execfd = qemu_getauxval(AT_EXECFD);
4390 if (execfd == 0) {
03cfd8fa 4391 execfd = open(filename, O_RDONLY);
0b959cf5
RH		 4392 if (execfd < 0) {
4393 printf("Error while loading %s: %s\n", filename, strerror(errno));
4d1275c2 4394 _exit(EXIT_FAILURE);
0b959cf5 4395 }
03cfd8fa
LV		 4396 }
4397
4398 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
fd4d81dd
AP		 4399 info, &bprm);
4400 if (ret != 0) {
885c1d10 4401 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4d1275c2 4402 _exit(EXIT_FAILURE);
b12b6a18
TS		 4403 }
4404
4405 for (wrk = target_environ; *wrk; wrk++) {
4406 free(*wrk);
31e31b8a 4407 }
3b46e624 4408
b12b6a18
TS		 4409 free(target_environ);
4410
13829020 4411 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
379f6698 4412 qemu_log("guest_base 0x%lx\n", guest_base);
2e77eac6
BS		 4413 log_page_dump();
4414
4415 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4416 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4417 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4418 info->start_code);
4419 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4420 info->start_data);
4421 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4422 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4423 info->start_stack);
4424 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4425 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4426 }
31e31b8a 4427
53a5960a 4428 target_set_brk(info->brk);
31e31b8a 4429 syscall_init();
66fb9763 4430 signal_init();
31e31b8a 4431
9002ec79
RH		 4432 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4433 generating the prologue until now so that the prologue can take
4434 the real value of GUEST_BASE into account. */
4435 tcg_prologue_init(&tcg_ctx);
9002ec79 4436
b346ff46 4437#if defined(TARGET_I386)
3802ce26 4438 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
b98dbc90 4439 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
0514ef2f 4440 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
1bde465e
FB		 4441 env->cr[4] |= CR4_OSFXSR_MASK;
4442 env->hflags |= HF_OSFXSR_MASK;
4443 }
d2fd1af7 4444#ifndef TARGET_ABI32
4dbc422b 4445 /* enable 64 bit mode if possible */
0514ef2f 4446 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4dbc422b 4447 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4d1275c2 4448 exit(EXIT_FAILURE);
4dbc422b 4449 }
d2fd1af7 4450 env->cr[4] |= CR4_PAE_MASK;
4dbc422b 4451 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
d2fd1af7
FB		 4452 env->hflags |= HF_LMA_MASK;
4453#endif
1bde465e 4454
415e561f
FB		 4455 /* flags setup : we activate the IRQs by default as in user mode */
4456 env->eflags |= IF_MASK;
3b46e624 4457
6dbad63e 4458 /* linux register setup */
d2fd1af7 4459#ifndef TARGET_ABI32
84409ddb
JM		 4460 env->regs[R_EAX] = regs->rax;
4461 env->regs[R_EBX] = regs->rbx;
4462 env->regs[R_ECX] = regs->rcx;
4463 env->regs[R_EDX] = regs->rdx;
4464 env->regs[R_ESI] = regs->rsi;
4465 env->regs[R_EDI] = regs->rdi;
4466 env->regs[R_EBP] = regs->rbp;
4467 env->regs[R_ESP] = regs->rsp;
4468 env->eip = regs->rip;
4469#else
0ecfa993
FB		 4470 env->regs[R_EAX] = regs->eax;
4471 env->regs[R_EBX] = regs->ebx;
4472 env->regs[R_ECX] = regs->ecx;
4473 env->regs[R_EDX] = regs->edx;
4474 env->regs[R_ESI] = regs->esi;
4475 env->regs[R_EDI] = regs->edi;
4476 env->regs[R_EBP] = regs->ebp;
4477 env->regs[R_ESP] = regs->esp;
dab2ed99 4478 env->eip = regs->eip;
84409ddb 4479#endif
31e31b8a 4480
f4beb510 4481 /* linux interrupt setup */
e441570f
AZ		 4482#ifndef TARGET_ABI32
4483 env->idt.limit = 511;
4484#else
4485 env->idt.limit = 255;
4486#endif
4487 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4488 PROT_READ|PROT_WRITE,
4489 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4490 idt_table = g2h(env->idt.base);
f4beb510
FB		 4491 set_idt(0, 0);
4492 set_idt(1, 0);
4493 set_idt(2, 0);
4494 set_idt(3, 3);
4495 set_idt(4, 3);
ec95da6c 4496 set_idt(5, 0);
f4beb510
FB		 4497 set_idt(6, 0);
4498 set_idt(7, 0);
4499 set_idt(8, 0);
4500 set_idt(9, 0);
4501 set_idt(10, 0);
4502 set_idt(11, 0);
4503 set_idt(12, 0);
4504 set_idt(13, 0);
4505 set_idt(14, 0);
4506 set_idt(15, 0);
4507 set_idt(16, 0);
4508 set_idt(17, 0);
4509 set_idt(18, 0);
4510 set_idt(19, 0);
4511 set_idt(0x80, 3);
4512
6dbad63e 4513 /* linux segment setup */
8d18e893
FB		 4514 {
4515 uint64_t *gdt_table;
e441570f
AZ		 4516 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4517 PROT_READ|PROT_WRITE,
4518 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
8d18e893 4519 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
e441570f 4520 gdt_table = g2h(env->gdt.base);
d2fd1af7 4521#ifdef TARGET_ABI32
8d18e893
FB		 4522 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4523 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4524 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
d2fd1af7
FB		 4525#else
4526 /* 64 bit code segment */
4527 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4528 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4529 DESC_L_MASK |
4530 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4531#endif
8d18e893
FB		 4532 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4533 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4534 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4535 }
6dbad63e 4536 cpu_x86_load_seg(env, R_CS, __USER_CS);
d2fd1af7
FB		 4537 cpu_x86_load_seg(env, R_SS, __USER_DS);
4538#ifdef TARGET_ABI32
6dbad63e
FB		 4539 cpu_x86_load_seg(env, R_DS, __USER_DS);
4540 cpu_x86_load_seg(env, R_ES, __USER_DS);
6dbad63e
FB		 4541 cpu_x86_load_seg(env, R_FS, __USER_DS);
4542 cpu_x86_load_seg(env, R_GS, __USER_DS);
d6eb40f6
TS		 4543 /* This hack makes Wine work... */
4544 env->segs[R_FS].selector = 0;
d2fd1af7
FB		 4545#else
4546 cpu_x86_load_seg(env, R_DS, 0);
4547 cpu_x86_load_seg(env, R_ES, 0);
4548 cpu_x86_load_seg(env, R_FS, 0);
4549 cpu_x86_load_seg(env, R_GS, 0);
4550#endif
99033cae
AG		 4551#elif defined(TARGET_AARCH64)
4552 {
4553 int i;
4554
4555 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4556 fprintf(stderr,
4557 "The selected ARM CPU does not support 64 bit mode\n");
4d1275c2 4558 exit(EXIT_FAILURE);
99033cae
AG		 4559 }
4560
4561 for (i = 0; i < 31; i++) {
4562 env->xregs[i] = regs->regs[i];
4563 }
4564 env->pc = regs->pc;
4565 env->xregs[31] = regs->sp;
4566 }
b346ff46
FB		 4567#elif defined(TARGET_ARM)
4568 {
4569 int i;
ae087923
PM		 4570 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4571 CPSRWriteByInstr);
b346ff46
FB		 4572 for(i = 0; i < 16; i++) {
4573 env->regs[i] = regs->uregs[i];
4574 }
f9fd40eb 4575#ifdef TARGET_WORDS_BIGENDIAN
d8fd2954
PB		 4576 /* Enable BE8. */
4577 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4578 && (info->elf_flags & EF_ARM_BE8)) {
9c5a7460
PC		 4579 env->uncached_cpsr |= CPSR_E;
4580 env->cp15.sctlr_el[1] |= SCTLR_E0E;
f9fd40eb
PB		 4581 } else {
4582 env->cp15.sctlr_el[1] |= SCTLR_B;
d8fd2954 4583 }
f9fd40eb 4584#endif
b346ff46 4585 }
d2fbca94
GX		 4586#elif defined(TARGET_UNICORE32)
4587 {
4588 int i;
4589 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4590 for (i = 0; i < 32; i++) {
4591 env->regs[i] = regs->uregs[i];
4592 }
4593 }
93ac68bc 4594#elif defined(TARGET_SPARC)
060366c5
FB		 4595 {
4596 int i;
4597 env->pc = regs->pc;
4598 env->npc = regs->npc;
4599 env->y = regs->y;
4600 for(i = 0; i < 8; i++)
4601 env->gregs[i] = regs->u_regs[i];
4602 for(i = 0; i < 8; i++)
4603 env->regwptr[i] = regs->u_regs[i + 8];
4604 }
67867308
FB		 4605#elif defined(TARGET_PPC)
4606 {
4607 int i;
3fc6c082 4608
0411a972
JM		 4609#if defined(TARGET_PPC64)
4610#if defined(TARGET_ABI32)
4611 env->msr &= ~((target_ulong)1 << MSR_SF);
e85e7c6e 4612#else
0411a972
JM		 4613 env->msr |= (target_ulong)1 << MSR_SF;
4614#endif
84409ddb 4615#endif
67867308
FB		 4616 env->nip = regs->nip;
4617 for(i = 0; i < 32; i++) {
4618 env->gpr[i] = regs->gpr[i];
4619 }
4620 }
e6e5906b
PB		 4621#elif defined(TARGET_M68K)
4622 {
e6e5906b
PB		 4623 env->pc = regs->pc;
4624 env->dregs[0] = regs->d0;
4625 env->dregs[1] = regs->d1;
4626 env->dregs[2] = regs->d2;
4627 env->dregs[3] = regs->d3;
4628 env->dregs[4] = regs->d4;
4629 env->dregs[5] = regs->d5;
4630 env->dregs[6] = regs->d6;
4631 env->dregs[7] = regs->d7;
4632 env->aregs[0] = regs->a0;
4633 env->aregs[1] = regs->a1;
4634 env->aregs[2] = regs->a2;
4635 env->aregs[3] = regs->a3;
4636 env->aregs[4] = regs->a4;
4637 env->aregs[5] = regs->a5;
4638 env->aregs[6] = regs->a6;
4639 env->aregs[7] = regs->usp;
4640 env->sr = regs->sr;
4641 ts->sim_syscalls = 1;
4642 }
b779e29e
EI		 4643#elif defined(TARGET_MICROBLAZE)
4644 {
4645 env->regs[0] = regs->r0;
4646 env->regs[1] = regs->r1;
4647 env->regs[2] = regs->r2;
4648 env->regs[3] = regs->r3;
4649 env->regs[4] = regs->r4;
4650 env->regs[5] = regs->r5;
4651 env->regs[6] = regs->r6;
4652 env->regs[7] = regs->r7;
4653 env->regs[8] = regs->r8;
4654 env->regs[9] = regs->r9;
4655 env->regs[10] = regs->r10;
4656 env->regs[11] = regs->r11;
4657 env->regs[12] = regs->r12;
4658 env->regs[13] = regs->r13;
4659 env->regs[14] = regs->r14;
4660 env->regs[15] = regs->r15;
4661 env->regs[16] = regs->r16;
4662 env->regs[17] = regs->r17;
4663 env->regs[18] = regs->r18;
4664 env->regs[19] = regs->r19;
4665 env->regs[20] = regs->r20;
4666 env->regs[21] = regs->r21;
4667 env->regs[22] = regs->r22;
4668 env->regs[23] = regs->r23;
4669 env->regs[24] = regs->r24;
4670 env->regs[25] = regs->r25;
4671 env->regs[26] = regs->r26;
4672 env->regs[27] = regs->r27;
4673 env->regs[28] = regs->r28;
4674 env->regs[29] = regs->r29;
4675 env->regs[30] = regs->r30;
4676 env->regs[31] = regs->r31;
4677 env->sregs[SR_PC] = regs->pc;
4678 }
048f6b4d
FB		 4679#elif defined(TARGET_MIPS)
4680 {
4681 int i;
4682
4683 for(i = 0; i < 32; i++) {
b5dc7732 4684 env->active_tc.gpr[i] = regs->regs[i];
048f6b4d 4685 }
0fddbbf2
NF		 4686 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4687 if (regs->cp0_epc & 1) {
4688 env->hflags |= MIPS_HFLAG_M16;
4689 }
599bc5e8
AM		 4690 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4691 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4692 if ((env->active_fpu.fcr31_rw_bitmask &
4693 (1 << FCR31_NAN2008)) == 0) {
4694 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4695 exit(1);
4696 }
4697 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4698 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4699 } else {
4700 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4701 }
4702 restore_snan_bit_mode(env);
4703 }
048f6b4d 4704 }
d962783e
JL		 4705#elif defined(TARGET_OPENRISC)
4706 {
4707 int i;
4708
4709 for (i = 0; i < 32; i++) {
4710 env->gpr[i] = regs->gpr[i];
4711 }
4712
4713 env->sr = regs->sr;
4714 env->pc = regs->pc;
4715 }
fdf9b3e8
FB		 4716#elif defined(TARGET_SH4)
4717 {
4718 int i;
4719
4720 for(i = 0; i < 16; i++) {
4721 env->gregs[i] = regs->regs[i];
4722 }
4723 env->pc = regs->pc;
4724 }
7a3148a9
JM		 4725#elif defined(TARGET_ALPHA)
4726 {
4727 int i;
4728
4729 for(i = 0; i < 28; i++) {
992f48a0 4730 env->ir[i] = ((abi_ulong *)regs)[i];
7a3148a9 4731 }
dad081ee 4732 env->ir[IR_SP] = regs->usp;
7a3148a9 4733 env->pc = regs->pc;
7a3148a9 4734 }
48733d19
TS		 4735#elif defined(TARGET_CRIS)
4736 {
4737 env->regs[0] = regs->r0;
4738 env->regs[1] = regs->r1;
4739 env->regs[2] = regs->r2;
4740 env->regs[3] = regs->r3;
4741 env->regs[4] = regs->r4;
4742 env->regs[5] = regs->r5;
4743 env->regs[6] = regs->r6;
4744 env->regs[7] = regs->r7;
4745 env->regs[8] = regs->r8;
4746 env->regs[9] = regs->r9;
4747 env->regs[10] = regs->r10;
4748 env->regs[11] = regs->r11;
4749 env->regs[12] = regs->r12;
4750 env->regs[13] = regs->r13;
4751 env->regs[14] = info->start_stack;
4752 env->regs[15] = regs->acr;
4753 env->pc = regs->erp;
4754 }
a4c075f1
UH		 4755#elif defined(TARGET_S390X)
4756 {
4757 int i;
4758 for (i = 0; i < 16; i++) {
4759 env->regs[i] = regs->gprs[i];
4760 }
4761 env->psw.mask = regs->psw.mask;
4762 env->psw.addr = regs->psw.addr;
4763 }
b16189b2
CG		 4764#elif defined(TARGET_TILEGX)
4765 {
4766 int i;
4767 for (i = 0; i < TILEGX_R_COUNT; i++) {
4768 env->regs[i] = regs->regs[i];
4769 }
4770 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4771 env->spregs[i] = 0;
4772 }
4773 env->pc = regs->pc;
4774 }
b346ff46
FB		 4775#else
4776#error unsupported target CPU
4777#endif
31e31b8a 4778
d2fbca94 4779#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
a87295e8
PB		 4780 ts->stack_base = info->start_stack;
4781 ts->heap_base = info->brk;
4782 /* This will be filled in on the first SYS_HEAPINFO call. */
4783 ts->heap_limit = 0;
4784#endif
4785
74c33bed 4786 if (gdbstub_port) {
ff7a981a
PM		 4787 if (gdbserver_start(gdbstub_port) < 0) {
4788 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4789 gdbstub_port);
4d1275c2 4790 exit(EXIT_FAILURE);
ff7a981a 4791 }
db6b81d4 4792 gdb_handlesig(cpu, 0);
1fddef4b 4793 }
1b6b029e
FB		 4794 cpu_loop(env);
4795 /* never exits */
31e31b8a
FB		 4796 return 0;
4797}
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