]> Git Repo - qemu.git/blame - target-xtensa/translate.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
target-xtensa: implement windowed registers
[qemu.git] / target-xtensa / translate.c
CommitLineData
2328826b
MF		 1/*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdio.h>
32
33#include "cpu.h"
34#include "exec-all.h"
35#include "disas.h"
36#include "tcg-op.h"
37#include "qemu-log.h"
38
dedc5eae
MF		 39#include "helpers.h"
40#define GEN_HELPER 1
41#include "helpers.h"
42
43typedef struct DisasContext {
44 const XtensaConfig *config;
45 TranslationBlock *tb;
46 uint32_t pc;
47 uint32_t next_pc;
f0a548b9
MF		 48 int cring;
49 int ring;
dedc5eae
MF		 50 int is_jmp;
51 int singlestep_enabled;
3580ecad
MF		 52
53 bool sar_5bit;
54 bool sar_m32_5bit;
55 bool sar_m32_allocated;
56 TCGv_i32 sar_m32;
dedc5eae
MF		 57} DisasContext;
58
59static TCGv_ptr cpu_env;
60static TCGv_i32 cpu_pc;
61static TCGv_i32 cpu_R[16];
2af3da91
MF		 62static TCGv_i32 cpu_SR[256];
63static TCGv_i32 cpu_UR[256];
dedc5eae
MF		 64
65#include "gen-icount.h"
2328826b 66
2af3da91 67static const char * const sregnames[256] = {
3580ecad 68 [SAR] = "SAR",
809377aa 69 [SCOMPARE1] = "SCOMPARE1",
553e44f9
MF		 70 [WINDOW_BASE] = "WINDOW_BASE",
71 [WINDOW_START] = "WINDOW_START",
40643d7c
MF		 72 [EPC1] = "EPC1",
73 [DEPC] = "DEPC",
74 [EXCSAVE1] = "EXCSAVE1",
f0a548b9 75 [PS] = "PS",
40643d7c
MF		 76 [EXCCAUSE] = "EXCCAUSE",
77 [EXCVADDR] = "EXCVADDR",
2af3da91
MF		 78};
79
80static const char * const uregnames[256] = {
81 [THREADPTR] = "THREADPTR",
82 [FCR] = "FCR",
83 [FSR] = "FSR",
84};
85
2328826b
MF		 86void xtensa_translate_init(void)
87{
dedc5eae
MF		 88 static const char * const regnames[] = {
89 "ar0", "ar1", "ar2", "ar3",
90 "ar4", "ar5", "ar6", "ar7",
91 "ar8", "ar9", "ar10", "ar11",
92 "ar12", "ar13", "ar14", "ar15",
93 };
94 int i;
95
96 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
97 cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
98 offsetof(CPUState, pc), "pc");
99
100 for (i = 0; i < 16; i++) {
101 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
102 offsetof(CPUState, regs[i]),
103 regnames[i]);
104 }
2af3da91
MF		 105
106 for (i = 0; i < 256; ++i) {
107 if (sregnames[i]) {
108 cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
109 offsetof(CPUState, sregs[i]),
110 sregnames[i]);
111 }
112 }
113
114 for (i = 0; i < 256; ++i) {
115 if (uregnames[i]) {
116 cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, uregs[i]),
118 uregnames[i]);
119 }
120 }
dedc5eae
MF		 121#define GEN_HELPER 2
122#include "helpers.h"
123}
124
125static inline bool option_enabled(DisasContext *dc, int opt)
126{
127 return xtensa_option_enabled(dc->config, opt);
128}
129
3580ecad
MF		 130static void init_sar_tracker(DisasContext *dc)
131{
132 dc->sar_5bit = false;
133 dc->sar_m32_5bit = false;
134 dc->sar_m32_allocated = false;
135}
136
137static void reset_sar_tracker(DisasContext *dc)
138{
139 if (dc->sar_m32_allocated) {
140 tcg_temp_free(dc->sar_m32);
141 }
142}
143
144static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
145{
146 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
147 if (dc->sar_m32_5bit) {
148 tcg_gen_discard_i32(dc->sar_m32);
149 }
150 dc->sar_5bit = true;
151 dc->sar_m32_5bit = false;
152}
153
154static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
155{
156 TCGv_i32 tmp = tcg_const_i32(32);
157 if (!dc->sar_m32_allocated) {
158 dc->sar_m32 = tcg_temp_local_new_i32();
159 dc->sar_m32_allocated = true;
160 }
161 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
162 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
163 dc->sar_5bit = false;
164 dc->sar_m32_5bit = true;
165 tcg_temp_free(tmp);
166}
167
dedc5eae
MF		 168static void gen_exception(int excp)
169{
170 TCGv_i32 tmp = tcg_const_i32(excp);
171 gen_helper_exception(tmp);
172 tcg_temp_free(tmp);
173}
174
40643d7c
MF		 175static void gen_exception_cause(DisasContext *dc, uint32_t cause)
176{
177 TCGv_i32 tpc = tcg_const_i32(dc->pc);
178 TCGv_i32 tcause = tcg_const_i32(cause);
179 gen_helper_exception_cause(tpc, tcause);
180 tcg_temp_free(tpc);
181 tcg_temp_free(tcause);
182}
183
184static void gen_check_privilege(DisasContext *dc)
185{
186 if (dc->cring) {
187 gen_exception_cause(dc, PRIVILEGED_CAUSE);
188 }
189}
190
dedc5eae
MF		 191static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
192{
193 tcg_gen_mov_i32(cpu_pc, dest);
194 if (dc->singlestep_enabled) {
195 gen_exception(EXCP_DEBUG);
196 } else {
197 if (slot >= 0) {
198 tcg_gen_goto_tb(slot);
199 tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
200 } else {
201 tcg_gen_exit_tb(0);
202 }
203 }
204 dc->is_jmp = DISAS_UPDATE;
205}
206
67882fd1
MF		 207static void gen_jump(DisasContext *dc, TCGv dest)
208{
209 gen_jump_slot(dc, dest, -1);
210}
211
dedc5eae
MF		 212static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
213{
214 TCGv_i32 tmp = tcg_const_i32(dest);
215 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
216 slot = -1;
217 }
218 gen_jump_slot(dc, tmp, slot);
219 tcg_temp_free(tmp);
220}
221
553e44f9
MF		 222static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
223 int slot)
224{
225 TCGv_i32 tcallinc = tcg_const_i32(callinc);
226
227 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
228 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
229 tcg_temp_free(tcallinc);
230 tcg_gen_movi_i32(cpu_R[callinc << 2],
231 (callinc << 30) | (dc->next_pc & 0x3fffffff));
232 gen_jump_slot(dc, dest, slot);
233}
234
235static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
236{
237 gen_callw_slot(dc, callinc, dest, -1);
238}
239
240static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
241{
242 TCGv_i32 tmp = tcg_const_i32(dest);
243 if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
244 slot = -1;
245 }
246 gen_callw_slot(dc, callinc, tmp, slot);
247 tcg_temp_free(tmp);
248}
249
bd57fb91
MF		 250static void gen_brcond(DisasContext *dc, TCGCond cond,
251 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
252{
253 int label = gen_new_label();
254
255 tcg_gen_brcond_i32(cond, t0, t1, label);
256 gen_jumpi(dc, dc->next_pc, 0);
257 gen_set_label(label);
258 gen_jumpi(dc, dc->pc + offset, 1);
259}
260
261static void gen_brcondi(DisasContext *dc, TCGCond cond,
262 TCGv_i32 t0, uint32_t t1, uint32_t offset)
263{
264 TCGv_i32 tmp = tcg_const_i32(t1);
265 gen_brcond(dc, cond, t0, tmp, offset);
266 tcg_temp_free(tmp);
267}
268
b8132eff
MF		 269static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
270{
271 static void (* const rsr_handler[256])(DisasContext *dc,
272 TCGv_i32 d, uint32_t sr) = {
273 };
274
275 if (sregnames[sr]) {
276 if (rsr_handler[sr]) {
277 rsr_handler[sr](dc, d, sr);
278 } else {
279 tcg_gen_mov_i32(d, cpu_SR[sr]);
280 }
281 } else {
282 qemu_log("RSR %d not implemented, ", sr);
283 }
284}
285
3580ecad
MF		 286static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
287{
288 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
289 if (dc->sar_m32_5bit) {
290 tcg_gen_discard_i32(dc->sar_m32);
291 }
292 dc->sar_5bit = false;
293 dc->sar_m32_5bit = false;
294}
295
553e44f9
MF		 296static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
297{
298 gen_helper_wsr_windowbase(v);
299}
300
f0a548b9
MF		 301static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
302{
303 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
304 PS_UM | PS_EXCM | PS_INTLEVEL;
305
306 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
307 mask |= PS_RING;
308 }
309 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
310 /* This can change mmu index, so exit tb */
311 gen_jumpi(dc, dc->next_pc, -1);
312}
313
b8132eff
MF		 314static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
315{
316 static void (* const wsr_handler[256])(DisasContext *dc,
317 uint32_t sr, TCGv_i32 v) = {
3580ecad 318 [SAR] = gen_wsr_sar,
553e44f9 319 [WINDOW_BASE] = gen_wsr_windowbase,
f0a548b9 320 [PS] = gen_wsr_ps,
b8132eff
MF		 321 };
322
323 if (sregnames[sr]) {
324 if (wsr_handler[sr]) {
325 wsr_handler[sr](dc, sr, s);
326 } else {
327 tcg_gen_mov_i32(cpu_SR[sr], s);
328 }
329 } else {
330 qemu_log("WSR %d not implemented, ", sr);
331 }
332}
333
dedc5eae
MF		 334static void disas_xtensa_insn(DisasContext *dc)
335{
336#define HAS_OPTION(opt) do { \
337 if (!option_enabled(dc, opt)) { \
338 qemu_log("Option %d is not enabled %s:%d\n", \
339 (opt), __FILE__, __LINE__); \
340 goto invalid_opcode; \
341 } \
342 } while (0)
343
91a5bb76
MF		 344#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
345#define RESERVED() do { \
346 qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
347 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
348 goto invalid_opcode; \
349 } while (0)
350
351
dedc5eae
MF		 352#ifdef TARGET_WORDS_BIGENDIAN
353#define OP0 (((b0) & 0xf0) >> 4)
354#define OP1 (((b2) & 0xf0) >> 4)
355#define OP2 ((b2) & 0xf)
356#define RRR_R ((b1) & 0xf)
357#define RRR_S (((b1) & 0xf0) >> 4)
358#define RRR_T ((b0) & 0xf)
359#else
360#define OP0 (((b0) & 0xf))
361#define OP1 (((b2) & 0xf))
362#define OP2 (((b2) & 0xf0) >> 4)
363#define RRR_R (((b1) & 0xf0) >> 4)
364#define RRR_S (((b1) & 0xf))
365#define RRR_T (((b0) & 0xf0) >> 4)
366#endif
367
368#define RRRN_R RRR_R
369#define RRRN_S RRR_S
370#define RRRN_T RRR_T
371
372#define RRI8_R RRR_R
373#define RRI8_S RRR_S
374#define RRI8_T RRR_T
375#define RRI8_IMM8 (b2)
376#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
377
378#ifdef TARGET_WORDS_BIGENDIAN
379#define RI16_IMM16 (((b1) << 8) | (b2))
380#else
381#define RI16_IMM16 (((b2) << 8) | (b1))
382#endif
383
384#ifdef TARGET_WORDS_BIGENDIAN
385#define CALL_N (((b0) & 0xc) >> 2)
386#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
387#else
388#define CALL_N (((b0) & 0x30) >> 4)
389#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
390#endif
391#define CALL_OFFSET_SE \
392 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
393
394#define CALLX_N CALL_N
395#ifdef TARGET_WORDS_BIGENDIAN
396#define CALLX_M ((b0) & 0x3)
397#else
398#define CALLX_M (((b0) & 0xc0) >> 6)
399#endif
400#define CALLX_S RRR_S
401
402#define BRI12_M CALLX_M
403#define BRI12_S RRR_S
404#ifdef TARGET_WORDS_BIGENDIAN
405#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
406#else
407#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
408#endif
409#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
410
411#define BRI8_M BRI12_M
412#define BRI8_R RRI8_R
413#define BRI8_S RRI8_S
414#define BRI8_IMM8 RRI8_IMM8
415#define BRI8_IMM8_SE RRI8_IMM8_SE
416
417#define RSR_SR (b1)
418
419 uint8_t b0 = ldub_code(dc->pc);
420 uint8_t b1 = ldub_code(dc->pc + 1);
421 uint8_t b2 = ldub_code(dc->pc + 2);
422
bd57fb91
MF		 423 static const uint32_t B4CONST[] = {
424 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
425 };
426
427 static const uint32_t B4CONSTU[] = {
428 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
429 };
430
dedc5eae
MF		 431 if (OP0 >= 8) {
432 dc->next_pc = dc->pc + 2;
433 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
434 } else {
435 dc->next_pc = dc->pc + 3;
436 }
437
438 switch (OP0) {
439 case 0: /*QRST*/
440 switch (OP1) {
441 case 0: /*RST0*/
442 switch (OP2) {
443 case 0: /*ST0*/
444 if ((RRR_R & 0xc) == 0x8) {
445 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
446 }
447
448 switch (RRR_R) {
449 case 0: /*SNM0*/
5da4a6a8
MF		 450 switch (CALLX_M) {
451 case 0: /*ILL*/
40643d7c 452 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
5da4a6a8
MF		 453 break;
454
455 case 1: /*reserved*/
91a5bb76 456 RESERVED();
5da4a6a8
MF		 457 break;
458
459 case 2: /*JR*/
460 switch (CALLX_N) {
461 case 0: /*RET*/
462 case 2: /*JX*/
463 gen_jump(dc, cpu_R[CALLX_S]);
464 break;
465
466 case 1: /*RETWw*/
467 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 468 {
469 TCGv_i32 tmp = tcg_const_i32(dc->pc);
470 gen_helper_retw(tmp, tmp);
471 gen_jump(dc, tmp);
472 tcg_temp_free(tmp);
473 }
5da4a6a8
MF		 474 break;
475
476 case 3: /*reserved*/
91a5bb76 477 RESERVED();
5da4a6a8
MF		 478 break;
479 }
480 break;
481
482 case 3: /*CALLX*/
483 switch (CALLX_N) {
484 case 0: /*CALLX0*/
485 {
486 TCGv_i32 tmp = tcg_temp_new_i32();
487 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
488 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
489 gen_jump(dc, tmp);
490 tcg_temp_free(tmp);
491 }
492 break;
493
494 case 1: /*CALLX4w*/
495 case 2: /*CALLX8w*/
496 case 3: /*CALLX12w*/
497 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 498 {
499 TCGv_i32 tmp = tcg_temp_new_i32();
500
501 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
502 gen_callw(dc, CALLX_N, tmp);
503 tcg_temp_free(tmp);
504 }
5da4a6a8
MF		 505 break;
506 }
507 break;
508 }
dedc5eae
MF		 509 break;
510
511 case 1: /*MOVSPw*/
512 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 513 {
514 TCGv_i32 pc = tcg_const_i32(dc->pc);
515 gen_helper_movsp(pc);
516 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
517 tcg_temp_free(pc);
518 }
dedc5eae
MF		 519 break;
520
521 case 2: /*SYNC*/
28067b22
MF		 522 switch (RRR_T) {
523 case 0: /*ISYNC*/
524 break;
525
526 case 1: /*RSYNC*/
527 break;
528
529 case 2: /*ESYNC*/
530 break;
531
532 case 3: /*DSYNC*/
533 break;
534
535 case 8: /*EXCW*/
536 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
537 break;
538
539 case 12: /*MEMW*/
540 break;
541
542 case 13: /*EXTW*/
543 break;
544
545 case 15: /*NOP*/
546 break;
547
548 default: /*reserved*/
549 RESERVED();
550 break;
551 }
91a5bb76
MF		 552 break;
553
554 case 3: /*RFEIx*/
40643d7c
MF		 555 switch (RRR_T) {
556 case 0: /*RFETx*/
557 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
558 switch (RRR_S) {
559 case 0: /*RFEx*/
560 gen_check_privilege(dc);
561 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
562 gen_jump(dc, cpu_SR[EPC1]);
563 break;
564
565 case 1: /*RFUEx*/
566 RESERVED();
567 break;
568
569 case 2: /*RFDEx*/
570 gen_check_privilege(dc);
571 gen_jump(dc, cpu_SR[
572 dc->config->ndepc ? DEPC : EPC1]);
573 break;
574
575 case 4: /*RFWOw*/
576 case 5: /*RFWUw*/
577 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 578 gen_check_privilege(dc);
579 {
580 TCGv_i32 tmp = tcg_const_i32(1);
581
582 tcg_gen_andi_i32(
583 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
584 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
585
586 if (RRR_S == 4) {
587 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
588 cpu_SR[WINDOW_START], tmp);
589 } else {
590 tcg_gen_or_i32(cpu_SR[WINDOW_START],
591 cpu_SR[WINDOW_START], tmp);
592 }
593
594 gen_helper_restore_owb();
595 gen_jump(dc, cpu_SR[EPC1]);
596
597 tcg_temp_free(tmp);
598 }
40643d7c
MF		 599 break;
600
601 default: /*reserved*/
602 RESERVED();
603 break;
604 }
605 break;
606
607 case 1: /*RFIx*/
608 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
609 TBD();
610 break;
611
612 case 2: /*RFME*/
613 TBD();
614 break;
615
616 default: /*reserved*/
617 RESERVED();
618 break;
619
620 }
91a5bb76
MF		 621 break;
622
623 case 4: /*BREAKx*/
624 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
625 TBD();
626 break;
627
628 case 5: /*SYSCALLx*/
629 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
40643d7c
MF		 630 switch (RRR_S) {
631 case 0: /*SYSCALLx*/
632 gen_exception_cause(dc, SYSCALL_CAUSE);
633 break;
634
635 case 1: /*SIMCALL*/
636 TBD();
637 break;
638
639 default:
640 RESERVED();
641 break;
642 }
91a5bb76
MF		 643 break;
644
645 case 6: /*RSILx*/
646 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
40643d7c
MF		 647 gen_check_privilege(dc);
648 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
649 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
650 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS],
651 RRR_S | ~PS_INTLEVEL);
91a5bb76
MF		 652 break;
653
654 case 7: /*WAITIx*/
655 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
656 TBD();
657 break;
658
659 case 8: /*ANY4p*/
660 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
661 TBD();
662 break;
663
664 case 9: /*ALL4p*/
665 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
666 TBD();
dedc5eae
MF		 667 break;
668
91a5bb76
MF		 669 case 10: /*ANY8p*/
670 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
671 TBD();
672 break;
673
674 case 11: /*ALL8p*/
675 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
676 TBD();
677 break;
678
679 default: /*reserved*/
680 RESERVED();
dedc5eae
MF		 681 break;
682
683 }
684 break;
685
686 case 1: /*AND*/
687 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
688 break;
689
690 case 2: /*OR*/
691 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
692 break;
693
694 case 3: /*XOR*/
695 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
696 break;
697
698 case 4: /*ST1*/
3580ecad
MF		 699 switch (RRR_R) {
700 case 0: /*SSR*/
701 gen_right_shift_sar(dc, cpu_R[RRR_S]);
702 break;
703
704 case 1: /*SSL*/
705 gen_left_shift_sar(dc, cpu_R[RRR_S]);
706 break;
707
708 case 2: /*SSA8L*/
709 {
710 TCGv_i32 tmp = tcg_temp_new_i32();
711 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
712 gen_right_shift_sar(dc, tmp);
713 tcg_temp_free(tmp);
714 }
715 break;
716
717 case 3: /*SSA8B*/
718 {
719 TCGv_i32 tmp = tcg_temp_new_i32();
720 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
721 gen_left_shift_sar(dc, tmp);
722 tcg_temp_free(tmp);
723 }
724 break;
725
726 case 4: /*SSAI*/
727 {
728 TCGv_i32 tmp = tcg_const_i32(
729 RRR_S | ((RRR_T & 1) << 4));
730 gen_right_shift_sar(dc, tmp);
731 tcg_temp_free(tmp);
732 }
733 break;
734
735 case 6: /*RER*/
91a5bb76 736 TBD();
3580ecad
MF		 737 break;
738
739 case 7: /*WER*/
91a5bb76 740 TBD();
3580ecad
MF		 741 break;
742
743 case 8: /*ROTWw*/
744 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 745 gen_check_privilege(dc);
746 {
747 TCGv_i32 tmp = tcg_const_i32(
748 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
749 gen_helper_rotw(tmp);
750 tcg_temp_free(tmp);
751 }
3580ecad
MF		 752 break;
753
754 case 14: /*NSAu*/
755 HAS_OPTION(XTENSA_OPTION_MISC_OP);
756 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
757 break;
758
759 case 15: /*NSAUu*/
760 HAS_OPTION(XTENSA_OPTION_MISC_OP);
761 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
762 break;
763
764 default: /*reserved*/
91a5bb76 765 RESERVED();
3580ecad
MF		 766 break;
767 }
dedc5eae
MF		 768 break;
769
770 case 5: /*TLB*/
91a5bb76 771 TBD();
dedc5eae
MF		 772 break;
773
774 case 6: /*RT0*/
f331fe5e
MF		 775 switch (RRR_S) {
776 case 0: /*NEG*/
777 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
778 break;
779
780 case 1: /*ABS*/
781 {
782 int label = gen_new_label();
783 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
784 tcg_gen_brcondi_i32(
785 TCG_COND_GE, cpu_R[RRR_R], 0, label);
786 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
787 gen_set_label(label);
788 }
789 break;
790
791 default: /*reserved*/
91a5bb76 792 RESERVED();
f331fe5e
MF		 793 break;
794 }
dedc5eae
MF		 795 break;
796
797 case 7: /*reserved*/
91a5bb76 798 RESERVED();
dedc5eae
MF		 799 break;
800
801 case 8: /*ADD*/
802 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
803 break;
804
805 case 9: /*ADD**/
806 case 10:
807 case 11:
808 {
809 TCGv_i32 tmp = tcg_temp_new_i32();
810 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
811 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
812 tcg_temp_free(tmp);
813 }
814 break;
815
816 case 12: /*SUB*/
817 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
818 break;
819
820 case 13: /*SUB**/
821 case 14:
822 case 15:
823 {
824 TCGv_i32 tmp = tcg_temp_new_i32();
825 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
826 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
827 tcg_temp_free(tmp);
828 }
829 break;
830 }
831 break;
832
833 case 1: /*RST1*/
3580ecad
MF		 834 switch (OP2) {
835 case 0: /*SLLI*/
836 case 1:
837 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
838 32 - (RRR_T | ((OP2 & 1) << 4)));
839 break;
840
841 case 2: /*SRAI*/
842 case 3:
843 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
844 RRR_S | ((OP2 & 1) << 4));
845 break;
846
847 case 4: /*SRLI*/
848 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
849 break;
850
851 case 6: /*XSR*/
852 {
853 TCGv_i32 tmp = tcg_temp_new_i32();
40643d7c
MF		 854 if (RSR_SR >= 64) {
855 gen_check_privilege(dc);
856 }
3580ecad
MF		 857 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
858 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
859 gen_wsr(dc, RSR_SR, tmp);
860 tcg_temp_free(tmp);
91a5bb76
MF		 861 if (!sregnames[RSR_SR]) {
862 TBD();
863 }
3580ecad
MF		 864 }
865 break;
866
867 /*
868 * Note: 64 bit ops are used here solely because SAR values
869 * have range 0..63
870 */
871#define gen_shift_reg(cmd, reg) do { \
872 TCGv_i64 tmp = tcg_temp_new_i64(); \
873 tcg_gen_extu_i32_i64(tmp, reg); \
874 tcg_gen_##cmd##_i64(v, v, tmp); \
875 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
876 tcg_temp_free_i64(v); \
877 tcg_temp_free_i64(tmp); \
878 } while (0)
879
880#define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
881
882 case 8: /*SRC*/
883 {
884 TCGv_i64 v = tcg_temp_new_i64();
885 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
886 gen_shift(shr);
887 }
888 break;
889
890 case 9: /*SRL*/
891 if (dc->sar_5bit) {
892 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
893 } else {
894 TCGv_i64 v = tcg_temp_new_i64();
895 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
896 gen_shift(shr);
897 }
898 break;
899
900 case 10: /*SLL*/
901 if (dc->sar_m32_5bit) {
902 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
903 } else {
904 TCGv_i64 v = tcg_temp_new_i64();
905 TCGv_i32 s = tcg_const_i32(32);
906 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
907 tcg_gen_andi_i32(s, s, 0x3f);
908 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
909 gen_shift_reg(shl, s);
910 tcg_temp_free(s);
911 }
912 break;
913
914 case 11: /*SRA*/
915 if (dc->sar_5bit) {
916 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
917 } else {
918 TCGv_i64 v = tcg_temp_new_i64();
919 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
920 gen_shift(sar);
921 }
922 break;
923#undef gen_shift
924#undef gen_shift_reg
925
926 case 12: /*MUL16U*/
927 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
928 {
929 TCGv_i32 v1 = tcg_temp_new_i32();
930 TCGv_i32 v2 = tcg_temp_new_i32();
931 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
932 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
933 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
934 tcg_temp_free(v2);
935 tcg_temp_free(v1);
936 }
937 break;
938
939 case 13: /*MUL16S*/
940 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
941 {
942 TCGv_i32 v1 = tcg_temp_new_i32();
943 TCGv_i32 v2 = tcg_temp_new_i32();
944 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
945 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
946 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
947 tcg_temp_free(v2);
948 tcg_temp_free(v1);
949 }
950 break;
951
952 default: /*reserved*/
91a5bb76 953 RESERVED();
3580ecad
MF		 954 break;
955 }
dedc5eae
MF		 956 break;
957
958 case 2: /*RST2*/
f76ebf55
MF		 959 if (OP2 >= 12) {
960 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
961 int label = gen_new_label();
962 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
963 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
964 gen_set_label(label);
965 }
966
967 switch (OP2) {
968 case 8: /*MULLi*/
969 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
970 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
971 break;
972
973 case 10: /*MULUHi*/
974 case 11: /*MULSHi*/
975 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
976 {
977 TCGv_i64 r = tcg_temp_new_i64();
978 TCGv_i64 s = tcg_temp_new_i64();
979 TCGv_i64 t = tcg_temp_new_i64();
980
981 if (OP2 == 10) {
982 tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
983 tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
984 } else {
985 tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
986 tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
987 }
988 tcg_gen_mul_i64(r, s, t);
989 tcg_gen_shri_i64(r, r, 32);
990 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
991
992 tcg_temp_free_i64(r);
993 tcg_temp_free_i64(s);
994 tcg_temp_free_i64(t);
995 }
996 break;
997
998 case 12: /*QUOUi*/
999 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1000 break;
1001
1002 case 13: /*QUOSi*/
1003 case 15: /*REMSi*/
1004 {
1005 int label1 = gen_new_label();
1006 int label2 = gen_new_label();
1007
1008 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1009 label1);
1010 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1011 label1);
1012 tcg_gen_movi_i32(cpu_R[RRR_R],
1013 OP2 == 13 ? 0x80000000 : 0);
1014 tcg_gen_br(label2);
1015 gen_set_label(label1);
1016 if (OP2 == 13) {
1017 tcg_gen_div_i32(cpu_R[RRR_R],
1018 cpu_R[RRR_S], cpu_R[RRR_T]);
1019 } else {
1020 tcg_gen_rem_i32(cpu_R[RRR_R],
1021 cpu_R[RRR_S], cpu_R[RRR_T]);
1022 }
1023 gen_set_label(label2);
1024 }
1025 break;
1026
1027 case 14: /*REMUi*/
1028 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1029 break;
1030
1031 default: /*reserved*/
1032 RESERVED();
1033 break;
1034 }
dedc5eae
MF		 1035 break;
1036
1037 case 3: /*RST3*/
b8132eff
MF		 1038 switch (OP2) {
1039 case 0: /*RSR*/
40643d7c
MF		 1040 if (RSR_SR >= 64) {
1041 gen_check_privilege(dc);
1042 }
b8132eff 1043 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
91a5bb76
MF		 1044 if (!sregnames[RSR_SR]) {
1045 TBD();
1046 }
b8132eff
MF		 1047 break;
1048
1049 case 1: /*WSR*/
40643d7c
MF		 1050 if (RSR_SR >= 64) {
1051 gen_check_privilege(dc);
1052 }
b8132eff 1053 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
91a5bb76
MF		 1054 if (!sregnames[RSR_SR]) {
1055 TBD();
1056 }
b8132eff
MF		 1057 break;
1058
1059 case 2: /*SEXTu*/
1060 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1061 {
1062 int shift = 24 - RRR_T;
1063
1064 if (shift == 24) {
1065 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1066 } else if (shift == 16) {
1067 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1068 } else {
1069 TCGv_i32 tmp = tcg_temp_new_i32();
1070 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1071 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1072 tcg_temp_free(tmp);
1073 }
1074 }
1075 break;
1076
1077 case 3: /*CLAMPSu*/
1078 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1079 {
1080 TCGv_i32 tmp1 = tcg_temp_new_i32();
1081 TCGv_i32 tmp2 = tcg_temp_new_i32();
1082 int label = gen_new_label();
1083
1084 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1085 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1086 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1087 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1088 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label);
1089
1090 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1091 tcg_gen_xori_i32(cpu_R[RRR_R], tmp1,
1092 0xffffffff >> (25 - RRR_T));
1093
1094 gen_set_label(label);
1095
1096 tcg_temp_free(tmp1);
1097 tcg_temp_free(tmp2);
1098 }
1099 break;
1100
1101 case 4: /*MINu*/
1102 case 5: /*MAXu*/
1103 case 6: /*MINUu*/
1104 case 7: /*MAXUu*/
1105 HAS_OPTION(XTENSA_OPTION_MISC_OP);
1106 {
1107 static const TCGCond cond[] = {
1108 TCG_COND_LE,
1109 TCG_COND_GE,
1110 TCG_COND_LEU,
1111 TCG_COND_GEU
1112 };
1113 int label = gen_new_label();
1114
1115 if (RRR_R != RRR_T) {
1116 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1117 tcg_gen_brcond_i32(cond[OP2 - 4],
1118 cpu_R[RRR_S], cpu_R[RRR_T], label);
1119 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1120 } else {
1121 tcg_gen_brcond_i32(cond[OP2 - 4],
1122 cpu_R[RRR_T], cpu_R[RRR_S], label);
1123 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1124 }
1125 gen_set_label(label);
1126 }
1127 break;
1128
1129 case 8: /*MOVEQZ*/
1130 case 9: /*MOVNEZ*/
1131 case 10: /*MOVLTZ*/
1132 case 11: /*MOVGEZ*/
1133 {
1134 static const TCGCond cond[] = {
1135 TCG_COND_NE,
1136 TCG_COND_EQ,
1137 TCG_COND_GE,
1138 TCG_COND_LT
1139 };
1140 int label = gen_new_label();
1141 tcg_gen_brcondi_i32(cond[OP2 - 8], cpu_R[RRR_T], 0, label);
1142 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1143 gen_set_label(label);
1144 }
1145 break;
1146
1147 case 12: /*MOVFp*/
1148 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1149 TBD();
b8132eff
MF		 1150 break;
1151
1152 case 13: /*MOVTp*/
1153 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1154 TBD();
b8132eff
MF		 1155 break;
1156
1157 case 14: /*RUR*/
1158 {
1159 int st = (RRR_S << 4) + RRR_T;
1160 if (uregnames[st]) {
1161 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1162 } else {
1163 qemu_log("RUR %d not implemented, ", st);
91a5bb76 1164 TBD();
b8132eff
MF		 1165 }
1166 }
1167 break;
1168
1169 case 15: /*WUR*/
1170 {
1171 if (uregnames[RSR_SR]) {
1172 tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]);
1173 } else {
1174 qemu_log("WUR %d not implemented, ", RSR_SR);
91a5bb76 1175 TBD();
b8132eff
MF		 1176 }
1177 }
1178 break;
1179
1180 }
dedc5eae
MF		 1181 break;
1182
1183 case 4: /*EXTUI*/
1184 case 5:
3580ecad
MF		 1185 {
1186 int shiftimm = RRR_S | (OP1 << 4);
1187 int maskimm = (1 << (OP2 + 1)) - 1;
1188
1189 TCGv_i32 tmp = tcg_temp_new_i32();
1190 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1191 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1192 tcg_temp_free(tmp);
1193 }
dedc5eae
MF		 1194 break;
1195
1196 case 6: /*CUST0*/
91a5bb76 1197 RESERVED();
dedc5eae
MF		 1198 break;
1199
1200 case 7: /*CUST1*/
91a5bb76 1201 RESERVED();
dedc5eae
MF		 1202 break;
1203
1204 case 8: /*LSCXp*/
1205 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1206 TBD();
dedc5eae
MF		 1207 break;
1208
1209 case 9: /*LSC4*/
553e44f9
MF		 1210 switch (OP2) {
1211 case 0: /*L32E*/
1212 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1213 gen_check_privilege(dc);
1214 {
1215 TCGv_i32 addr = tcg_temp_new_i32();
1216 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1217 (0xffffffc0 | (RRR_R << 2)));
1218 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1219 tcg_temp_free(addr);
1220 }
1221 break;
1222
1223 case 4: /*S32E*/
1224 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1225 gen_check_privilege(dc);
1226 {
1227 TCGv_i32 addr = tcg_temp_new_i32();
1228 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1229 (0xffffffc0 | (RRR_R << 2)));
1230 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1231 tcg_temp_free(addr);
1232 }
1233 break;
1234
1235 default:
1236 RESERVED();
1237 break;
1238 }
dedc5eae
MF		 1239 break;
1240
1241 case 10: /*FP0*/
1242 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1243 TBD();
dedc5eae
MF		 1244 break;
1245
1246 case 11: /*FP1*/
1247 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
91a5bb76 1248 TBD();
dedc5eae
MF		 1249 break;
1250
1251 default: /*reserved*/
91a5bb76 1252 RESERVED();
dedc5eae
MF		 1253 break;
1254 }
1255 break;
1256
1257 case 1: /*L32R*/
1258 {
1259 TCGv_i32 tmp = tcg_const_i32(
1260 (0xfffc0000 | (RI16_IMM16 << 2)) +
1261 ((dc->pc + 3) & ~3));
1262
1263 /* no ext L32R */
1264
f0a548b9 1265 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
dedc5eae
MF		 1266 tcg_temp_free(tmp);
1267 }
1268 break;
1269
1270 case 2: /*LSAI*/
809377aa
MF		 1271#define gen_load_store(type, shift) do { \
1272 TCGv_i32 addr = tcg_temp_new_i32(); \
1273 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
f0a548b9 1274 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
809377aa
MF		 1275 tcg_temp_free(addr); \
1276 } while (0)
1277
1278 switch (RRI8_R) {
1279 case 0: /*L8UI*/
1280 gen_load_store(ld8u, 0);
1281 break;
1282
1283 case 1: /*L16UI*/
1284 gen_load_store(ld16u, 1);
1285 break;
1286
1287 case 2: /*L32I*/
1288 gen_load_store(ld32u, 2);
1289 break;
1290
1291 case 4: /*S8I*/
1292 gen_load_store(st8, 0);
1293 break;
1294
1295 case 5: /*S16I*/
1296 gen_load_store(st16, 1);
1297 break;
1298
1299 case 6: /*S32I*/
1300 gen_load_store(st32, 2);
1301 break;
1302
1303 case 7: /*CACHEc*/
8ffc2d0d
MF		 1304 if (RRI8_T < 8) {
1305 HAS_OPTION(XTENSA_OPTION_DCACHE);
1306 }
1307
1308 switch (RRI8_T) {
1309 case 0: /*DPFRc*/
1310 break;
1311
1312 case 1: /*DPFWc*/
1313 break;
1314
1315 case 2: /*DPFROc*/
1316 break;
1317
1318 case 3: /*DPFWOc*/
1319 break;
1320
1321 case 4: /*DHWBc*/
1322 break;
1323
1324 case 5: /*DHWBIc*/
1325 break;
1326
1327 case 6: /*DHIc*/
1328 break;
1329
1330 case 7: /*DIIc*/
1331 break;
1332
1333 case 8: /*DCEc*/
1334 switch (OP1) {
1335 case 0: /*DPFLl*/
1336 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1337 break;
1338
1339 case 2: /*DHUl*/
1340 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1341 break;
1342
1343 case 3: /*DIUl*/
1344 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
1345 break;
1346
1347 case 4: /*DIWBc*/
1348 HAS_OPTION(XTENSA_OPTION_DCACHE);
1349 break;
1350
1351 case 5: /*DIWBIc*/
1352 HAS_OPTION(XTENSA_OPTION_DCACHE);
1353 break;
1354
1355 default: /*reserved*/
1356 RESERVED();
1357 break;
1358
1359 }
1360 break;
1361
1362 case 12: /*IPFc*/
1363 HAS_OPTION(XTENSA_OPTION_ICACHE);
1364 break;
1365
1366 case 13: /*ICEc*/
1367 switch (OP1) {
1368 case 0: /*IPFLl*/
1369 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1370 break;
1371
1372 case 2: /*IHUl*/
1373 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1374 break;
1375
1376 case 3: /*IIUl*/
1377 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
1378 break;
1379
1380 default: /*reserved*/
1381 RESERVED();
1382 break;
1383 }
1384 break;
1385
1386 case 14: /*IHIc*/
1387 HAS_OPTION(XTENSA_OPTION_ICACHE);
1388 break;
1389
1390 case 15: /*IIIc*/
1391 HAS_OPTION(XTENSA_OPTION_ICACHE);
1392 break;
1393
1394 default: /*reserved*/
1395 RESERVED();
1396 break;
1397 }
809377aa
MF		 1398 break;
1399
1400 case 9: /*L16SI*/
1401 gen_load_store(ld16s, 1);
1402 break;
1403
1404 case 10: /*MOVI*/
1405 tcg_gen_movi_i32(cpu_R[RRI8_T],
1406 RRI8_IMM8 | (RRI8_S << 8) |
1407 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
1408 break;
1409
1410 case 11: /*L32AIy*/
1411 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1412 gen_load_store(ld32u, 2); /*TODO acquire?*/
1413 break;
1414
1415 case 12: /*ADDI*/
1416 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
1417 break;
1418
1419 case 13: /*ADDMI*/
1420 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE << 8);
1421 break;
1422
1423 case 14: /*S32C1Iy*/
1424 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1425 {
1426 int label = gen_new_label();
1427 TCGv_i32 tmp = tcg_temp_local_new_i32();
1428 TCGv_i32 addr = tcg_temp_local_new_i32();
1429
1430 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
1431 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
f0a548b9 1432 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
809377aa
MF		 1433 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
1434 cpu_SR[SCOMPARE1], label);
1435
f0a548b9 1436 tcg_gen_qemu_st32(tmp, addr, dc->cring);
809377aa
MF		 1437
1438 gen_set_label(label);
1439 tcg_temp_free(addr);
1440 tcg_temp_free(tmp);
1441 }
1442 break;
1443
1444 case 15: /*S32RIy*/
1445 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
1446 gen_load_store(st32, 2); /*TODO release?*/
1447 break;
1448
1449 default: /*reserved*/
91a5bb76 1450 RESERVED();
809377aa
MF		 1451 break;
1452 }
dedc5eae 1453 break;
809377aa 1454#undef gen_load_store
dedc5eae
MF		 1455
1456 case 3: /*LSCIp*/
1457 HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
91a5bb76 1458 TBD();
dedc5eae
MF		 1459 break;
1460
1461 case 4: /*MAC16d*/
1462 HAS_OPTION(XTENSA_OPTION_MAC16);
91a5bb76 1463 TBD();
dedc5eae
MF		 1464 break;
1465
1466 case 5: /*CALLN*/
1467 switch (CALL_N) {
1468 case 0: /*CALL0*/
1469 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1470 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
1471 break;
1472
1473 case 1: /*CALL4w*/
1474 case 2: /*CALL8w*/
1475 case 3: /*CALL12w*/
1476 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1477 gen_callwi(dc, CALL_N,
1478 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
dedc5eae
MF		 1479 break;
1480 }
1481 break;
1482
1483 case 6: /*SI*/
1484 switch (CALL_N) {
1485 case 0: /*J*/
1486 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
1487 break;
1488
bd57fb91
MF		 1489 case 1: /*BZ*/
1490 {
1491 static const TCGCond cond[] = {
1492 TCG_COND_EQ, /*BEQZ*/
1493 TCG_COND_NE, /*BNEZ*/
1494 TCG_COND_LT, /*BLTZ*/
1495 TCG_COND_GE, /*BGEZ*/
1496 };
1497
1498 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
1499 4 + BRI12_IMM12_SE);
1500 }
1501 break;
1502
1503 case 2: /*BI0*/
1504 {
1505 static const TCGCond cond[] = {
1506 TCG_COND_EQ, /*BEQI*/
1507 TCG_COND_NE, /*BNEI*/
1508 TCG_COND_LT, /*BLTI*/
1509 TCG_COND_GE, /*BGEI*/
1510 };
1511
1512 gen_brcondi(dc, cond[BRI8_M & 3],
1513 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
1514 }
1515 break;
1516
1517 case 3: /*BI1*/
1518 switch (BRI8_M) {
1519 case 0: /*ENTRYw*/
1520 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1521 {
1522 TCGv_i32 pc = tcg_const_i32(dc->pc);
1523 TCGv_i32 s = tcg_const_i32(BRI12_S);
1524 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
1525 gen_helper_entry(pc, s, imm);
1526 tcg_temp_free(imm);
1527 tcg_temp_free(s);
1528 tcg_temp_free(pc);
1529 }
bd57fb91
MF		 1530 break;
1531
1532 case 1: /*B1*/
1533 switch (BRI8_R) {
1534 case 0: /*BFp*/
1535 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1536 TBD();
bd57fb91
MF		 1537 break;
1538
1539 case 1: /*BTp*/
1540 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
91a5bb76 1541 TBD();
bd57fb91
MF		 1542 break;
1543
1544 case 8: /*LOOP*/
91a5bb76 1545 TBD();
bd57fb91
MF		 1546 break;
1547
1548 case 9: /*LOOPNEZ*/
91a5bb76 1549 TBD();
bd57fb91
MF		 1550 break;
1551
1552 case 10: /*LOOPGTZ*/
91a5bb76 1553 TBD();
bd57fb91
MF		 1554 break;
1555
1556 default: /*reserved*/
91a5bb76 1557 RESERVED();
bd57fb91
MF		 1558 break;
1559
1560 }
1561 break;
1562
1563 case 2: /*BLTUI*/
1564 case 3: /*BGEUI*/
1565 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
1566 cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
1567 break;
1568 }
1569 break;
1570
dedc5eae
MF		 1571 }
1572 break;
1573
1574 case 7: /*B*/
bd57fb91
MF		 1575 {
1576 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
1577
1578 switch (RRI8_R & 7) {
1579 case 0: /*BNONE*/ /*BANY*/
1580 {
1581 TCGv_i32 tmp = tcg_temp_new_i32();
1582 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1583 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1584 tcg_temp_free(tmp);
1585 }
1586 break;
1587
1588 case 1: /*BEQ*/ /*BNE*/
1589 case 2: /*BLT*/ /*BGE*/
1590 case 3: /*BLTU*/ /*BGEU*/
1591 {
1592 static const TCGCond cond[] = {
1593 [1] = TCG_COND_EQ,
1594 [2] = TCG_COND_LT,
1595 [3] = TCG_COND_LTU,
1596 [9] = TCG_COND_NE,
1597 [10] = TCG_COND_GE,
1598 [11] = TCG_COND_GEU,
1599 };
1600 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
1601 4 + RRI8_IMM8_SE);
1602 }
1603 break;
1604
1605 case 4: /*BALL*/ /*BNALL*/
1606 {
1607 TCGv_i32 tmp = tcg_temp_new_i32();
1608 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
1609 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
1610 4 + RRI8_IMM8_SE);
1611 tcg_temp_free(tmp);
1612 }
1613 break;
1614
1615 case 5: /*BBC*/ /*BBS*/
1616 {
1617 TCGv_i32 bit = tcg_const_i32(1);
1618 TCGv_i32 tmp = tcg_temp_new_i32();
1619 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
1620 tcg_gen_shl_i32(bit, bit, tmp);
1621 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
1622 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1623 tcg_temp_free(tmp);
1624 tcg_temp_free(bit);
1625 }
1626 break;
1627
1628 case 6: /*BBCI*/ /*BBSI*/
1629 case 7:
1630 {
1631 TCGv_i32 tmp = tcg_temp_new_i32();
1632 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
1633 1 << (((RRI8_R & 1) << 4) | RRI8_T));
1634 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
1635 tcg_temp_free(tmp);
1636 }
1637 break;
1638
1639 }
1640 }
dedc5eae
MF		 1641 break;
1642
67882fd1
MF		 1643#define gen_narrow_load_store(type) do { \
1644 TCGv_i32 addr = tcg_temp_new_i32(); \
1645 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
f0a548b9 1646 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
67882fd1
MF		 1647 tcg_temp_free(addr); \
1648 } while (0)
1649
dedc5eae 1650 case 8: /*L32I.Nn*/
67882fd1 1651 gen_narrow_load_store(ld32u);
dedc5eae
MF		 1652 break;
1653
1654 case 9: /*S32I.Nn*/
67882fd1 1655 gen_narrow_load_store(st32);
dedc5eae 1656 break;
67882fd1 1657#undef gen_narrow_load_store
dedc5eae
MF		 1658
1659 case 10: /*ADD.Nn*/
67882fd1 1660 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae
MF		 1661 break;
1662
1663 case 11: /*ADDI.Nn*/
67882fd1 1664 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae
MF		 1665 break;
1666
1667 case 12: /*ST2n*/
67882fd1
MF		 1668 if (RRRN_T < 8) { /*MOVI.Nn*/
1669 tcg_gen_movi_i32(cpu_R[RRRN_S],
1670 RRRN_R | (RRRN_T << 4) |
1671 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
1672 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
bd57fb91
MF		 1673 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
1674
1675 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
1676 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
67882fd1 1677 }
dedc5eae
MF		 1678 break;
1679
1680 case 13: /*ST3n*/
67882fd1
MF		 1681 switch (RRRN_R) {
1682 case 0: /*MOV.Nn*/
1683 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
1684 break;
1685
1686 case 15: /*S3*/
1687 switch (RRRN_T) {
1688 case 0: /*RET.Nn*/
1689 gen_jump(dc, cpu_R[0]);
1690 break;
1691
1692 case 1: /*RETW.Nn*/
91a5bb76 1693 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
553e44f9
MF		 1694 {
1695 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1696 gen_helper_retw(tmp, tmp);
1697 gen_jump(dc, tmp);
1698 tcg_temp_free(tmp);
1699 }
67882fd1
MF		 1700 break;
1701
1702 case 2: /*BREAK.Nn*/
91a5bb76 1703 TBD();
67882fd1
MF		 1704 break;
1705
1706 case 3: /*NOP.Nn*/
1707 break;
1708
1709 case 6: /*ILL.Nn*/
40643d7c 1710 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
67882fd1
MF		 1711 break;
1712
1713 default: /*reserved*/
91a5bb76 1714 RESERVED();
67882fd1
MF		 1715 break;
1716 }
1717 break;
1718
1719 default: /*reserved*/
91a5bb76 1720 RESERVED();
67882fd1
MF		 1721 break;
1722 }
dedc5eae
MF		 1723 break;
1724
1725 default: /*reserved*/
91a5bb76 1726 RESERVED();
dedc5eae
MF		 1727 break;
1728 }
1729
1730 dc->pc = dc->next_pc;
1731 return;
1732
1733invalid_opcode:
1734 qemu_log("INVALID(pc = %08x)\n", dc->pc);
1735 dc->pc = dc->next_pc;
1736#undef HAS_OPTION
1737}
1738
1739static void check_breakpoint(CPUState *env, DisasContext *dc)
1740{
1741 CPUBreakpoint *bp;
1742
1743 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1744 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1745 if (bp->pc == dc->pc) {
1746 tcg_gen_movi_i32(cpu_pc, dc->pc);
1747 gen_exception(EXCP_DEBUG);
1748 dc->is_jmp = DISAS_UPDATE;
1749 }
1750 }
1751 }
1752}
1753
1754static void gen_intermediate_code_internal(
1755 CPUState *env, TranslationBlock *tb, int search_pc)
1756{
1757 DisasContext dc;
1758 int insn_count = 0;
1759 int j, lj = -1;
1760 uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1761 int max_insns = tb->cflags & CF_COUNT_MASK;
1762 uint32_t pc_start = tb->pc;
1763 uint32_t next_page_start =
1764 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1765
1766 if (max_insns == 0) {
1767 max_insns = CF_COUNT_MASK;
1768 }
1769
1770 dc.config = env->config;
1771 dc.singlestep_enabled = env->singlestep_enabled;
1772 dc.tb = tb;
1773 dc.pc = pc_start;
f0a548b9
MF		 1774 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
1775 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
dedc5eae
MF		 1776 dc.is_jmp = DISAS_NEXT;
1777
3580ecad
MF		 1778 init_sar_tracker(&dc);
1779
dedc5eae
MF		 1780 gen_icount_start();
1781
40643d7c
MF		 1782 if (env->singlestep_enabled && env->exception_taken) {
1783 env->exception_taken = 0;
1784 tcg_gen_movi_i32(cpu_pc, dc.pc);
1785 gen_exception(EXCP_DEBUG);
1786 }
1787
dedc5eae
MF		 1788 do {
1789 check_breakpoint(env, &dc);
1790
1791 if (search_pc) {
1792 j = gen_opc_ptr - gen_opc_buf;
1793 if (lj < j) {
1794 lj++;
1795 while (lj < j) {
1796 gen_opc_instr_start[lj++] = 0;
1797 }
1798 }
1799 gen_opc_pc[lj] = dc.pc;
1800 gen_opc_instr_start[lj] = 1;
1801 gen_opc_icount[lj] = insn_count;
1802 }
1803
1804 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
1805 tcg_gen_debug_insn_start(dc.pc);
1806 }
1807
1808 disas_xtensa_insn(&dc);
1809 ++insn_count;
1810 if (env->singlestep_enabled) {
1811 tcg_gen_movi_i32(cpu_pc, dc.pc);
1812 gen_exception(EXCP_DEBUG);
1813 break;
1814 }
1815 } while (dc.is_jmp == DISAS_NEXT &&
1816 insn_count < max_insns &&
1817 dc.pc < next_page_start &&
1818 gen_opc_ptr < gen_opc_end);
1819
3580ecad
MF		 1820 reset_sar_tracker(&dc);
1821
dedc5eae
MF		 1822 if (dc.is_jmp == DISAS_NEXT) {
1823 gen_jumpi(&dc, dc.pc, 0);
1824 }
1825 gen_icount_end(tb, insn_count);
1826 *gen_opc_ptr = INDEX_op_end;
1827
1828 if (!search_pc) {
1829 tb->size = dc.pc - pc_start;
1830 tb->icount = insn_count;
1831 }
2328826b
MF		 1832}
1833
1834void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
1835{
dedc5eae 1836 gen_intermediate_code_internal(env, tb, 0);
2328826b
MF		 1837}
1838
1839void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
1840{
dedc5eae 1841 gen_intermediate_code_internal(env, tb, 1);
2328826b
MF		 1842}
1843
1844void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1845 int flags)
1846{
2af3da91
MF		 1847 int i, j;
1848
1849 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
1850
1851 for (i = j = 0; i < 256; ++i) {
1852 if (sregnames[i]) {
1853 cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
1854 (j++ % 4) == 3 ? '\n' : ' ');
1855 }
1856 }
1857
1858 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
1859
1860 for (i = j = 0; i < 256; ++i) {
1861 if (uregnames[i]) {
1862 cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
1863 (j++ % 4) == 3 ? '\n' : ' ');
1864 }
1865 }
2328826b 1866
2af3da91 1867 cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b
MF		 1868
1869 for (i = 0; i < 16; ++i) {
1870 cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
1871 (i % 4) == 3 ? '\n' : ' ');
1872 }
553e44f9
MF		 1873
1874 cpu_fprintf(f, "\n");
1875
1876 for (i = 0; i < env->config->nareg; ++i) {
1877 cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i],
1878 (i % 4) == 3 ? '\n' : ' ');
1879 }
2328826b
MF		 1880}
1881
1882void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
1883{
1884 env->pc = gen_opc_pc[pc_pos];
1885}
Empty description
This page took 0.236377 seconds and 4 git commands to generate.