[qemu.git] / target-xtensa / translate.c

/*
 * Xtensa ISA:
 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
 *
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <stdio.h>

#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
#include "qemu-log.h"

#include "helpers.h"
#define GEN_HELPER 1
#include "helpers.h"

typedef struct DisasContext {
    const XtensaConfig *config;
    TranslationBlock *tb;
    uint32_t pc;
    uint32_t next_pc;
    int is_jmp;
    int singlestep_enabled;
} DisasContext;

static TCGv_ptr cpu_env;
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_R[16];
static TCGv_i32 cpu_SR[256];
static TCGv_i32 cpu_UR[256];

#include "gen-icount.h"

static const char * const sregnames[256] = {
};

static const char * const uregnames[256] = {
    [THREADPTR] = "THREADPTR",
    [FCR] = "FCR",
    [FSR] = "FSR",
};

void xtensa_translate_init(void)
{
    static const char * const regnames[] = {
        "ar0", "ar1", "ar2", "ar3",
        "ar4", "ar5", "ar6", "ar7",
        "ar8", "ar9", "ar10", "ar11",
        "ar12", "ar13", "ar14", "ar15",
    };
    int i;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
    cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
            offsetof(CPUState, pc), "pc");

    for (i = 0; i < 16; i++) {
        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
                offsetof(CPUState, regs[i]),
                regnames[i]);
    }

    for (i = 0; i < 256; ++i) {
        if (sregnames[i]) {
            cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
                    offsetof(CPUState, sregs[i]),
                    sregnames[i]);
        }
    }

    for (i = 0; i < 256; ++i) {
        if (uregnames[i]) {
            cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
                    offsetof(CPUState, uregs[i]),
                    uregnames[i]);
        }
    }
#define GEN_HELPER 2
#include "helpers.h"
}

static inline bool option_enabled(DisasContext *dc, int opt)
{
    return xtensa_option_enabled(dc->config, opt);
}

static void gen_exception(int excp)
{
    TCGv_i32 tmp = tcg_const_i32(excp);
    gen_helper_exception(tmp);
    tcg_temp_free(tmp);
}

static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
{
    tcg_gen_mov_i32(cpu_pc, dest);
    if (dc->singlestep_enabled) {
        gen_exception(EXCP_DEBUG);
    } else {
        if (slot >= 0) {
            tcg_gen_goto_tb(slot);
            tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
        } else {
            tcg_gen_exit_tb(0);
        }
    }
    dc->is_jmp = DISAS_UPDATE;
}

static void gen_jump(DisasContext *dc, TCGv dest)
{
    gen_jump_slot(dc, dest, -1);
}

static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
    TCGv_i32 tmp = tcg_const_i32(dest);
    if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
        slot = -1;
    }
    gen_jump_slot(dc, tmp, slot);
    tcg_temp_free(tmp);
}

static void gen_brcond(DisasContext *dc, TCGCond cond,
        TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
{
    int label = gen_new_label();

    tcg_gen_brcond_i32(cond, t0, t1, label);
    gen_jumpi(dc, dc->next_pc, 0);
    gen_set_label(label);
    gen_jumpi(dc, dc->pc + offset, 1);
}

static void gen_brcondi(DisasContext *dc, TCGCond cond,
        TCGv_i32 t0, uint32_t t1, uint32_t offset)
{
    TCGv_i32 tmp = tcg_const_i32(t1);
    gen_brcond(dc, cond, t0, tmp, offset);
    tcg_temp_free(tmp);
}

static void disas_xtensa_insn(DisasContext *dc)
{
#define HAS_OPTION(opt) do { \
        if (!option_enabled(dc, opt)) { \
            qemu_log("Option %d is not enabled %s:%d\n", \
                    (opt), __FILE__, __LINE__); \
            goto invalid_opcode; \
        } \
    } while (0)

#ifdef TARGET_WORDS_BIGENDIAN
#define OP0 (((b0) & 0xf0) >> 4)
#define OP1 (((b2) & 0xf0) >> 4)
#define OP2 ((b2) & 0xf)
#define RRR_R ((b1) & 0xf)
#define RRR_S (((b1) & 0xf0) >> 4)
#define RRR_T ((b0) & 0xf)
#else
#define OP0 (((b0) & 0xf))
#define OP1 (((b2) & 0xf))
#define OP2 (((b2) & 0xf0) >> 4)
#define RRR_R (((b1) & 0xf0) >> 4)
#define RRR_S (((b1) & 0xf))
#define RRR_T (((b0) & 0xf0) >> 4)
#endif

#define RRRN_R RRR_R
#define RRRN_S RRR_S
#define RRRN_T RRR_T

#define RRI8_R RRR_R
#define RRI8_S RRR_S
#define RRI8_T RRR_T
#define RRI8_IMM8 (b2)
#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)

#ifdef TARGET_WORDS_BIGENDIAN
#define RI16_IMM16 (((b1) << 8) | (b2))
#else
#define RI16_IMM16 (((b2) << 8) | (b1))
#endif

#ifdef TARGET_WORDS_BIGENDIAN
#define CALL_N (((b0) & 0xc) >> 2)
#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
#else
#define CALL_N (((b0) & 0x30) >> 4)
#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
#endif
#define CALL_OFFSET_SE \
    (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)

#define CALLX_N CALL_N
#ifdef TARGET_WORDS_BIGENDIAN
#define CALLX_M ((b0) & 0x3)
#else
#define CALLX_M (((b0) & 0xc0) >> 6)
#endif
#define CALLX_S RRR_S

#define BRI12_M CALLX_M
#define BRI12_S RRR_S
#ifdef TARGET_WORDS_BIGENDIAN
#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
#else
#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
#endif
#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)

#define BRI8_M BRI12_M
#define BRI8_R RRI8_R
#define BRI8_S RRI8_S
#define BRI8_IMM8 RRI8_IMM8
#define BRI8_IMM8_SE RRI8_IMM8_SE

#define RSR_SR (b1)

    uint8_t b0 = ldub_code(dc->pc);
    uint8_t b1 = ldub_code(dc->pc + 1);
    uint8_t b2 = ldub_code(dc->pc + 2);

    static const uint32_t B4CONST[] = {
        0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
    };

    static const uint32_t B4CONSTU[] = {
        32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
    };

    if (OP0 >= 8) {
        dc->next_pc = dc->pc + 2;
        HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
    } else {
        dc->next_pc = dc->pc + 3;
    }

    switch (OP0) {
    case 0: /*QRST*/
        switch (OP1) {
        case 0: /*RST0*/
            switch (OP2) {
            case 0: /*ST0*/
                if ((RRR_R & 0xc) == 0x8) {
                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);
                }

                switch (RRR_R) {
                case 0: /*SNM0*/
                    switch (CALLX_M) {
                    case 0: /*ILL*/
                        break;

                    case 1: /*reserved*/
                        break;

                    case 2: /*JR*/
                        switch (CALLX_N) {
                        case 0: /*RET*/
                        case 2: /*JX*/
                            gen_jump(dc, cpu_R[CALLX_S]);
                            break;

                        case 1: /*RETWw*/
                            HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
                            break;

                        case 3: /*reserved*/
                            break;
                        }
                        break;

                    case 3: /*CALLX*/
                        switch (CALLX_N) {
                        case 0: /*CALLX0*/
                            {
                                TCGv_i32 tmp = tcg_temp_new_i32();
                                tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
                                tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
                                gen_jump(dc, tmp);
                                tcg_temp_free(tmp);
                            }
                            break;

                        case 1: /*CALLX4w*/
                        case 2: /*CALLX8w*/
                        case 3: /*CALLX12w*/
                            HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
                            break;
                        }
                        break;
                    }
                    break;

                case 1: /*MOVSPw*/
                    HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
                    break;

                case 2: /*SYNC*/
                    break;

                case 3:
                    break;

                }
                break;

            case 1: /*AND*/
                tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 2: /*OR*/
                tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 3: /*XOR*/
                tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 4: /*ST1*/
                break;

            case 5: /*TLB*/
                break;

            case 6: /*RT0*/
                switch (RRR_S) {
                case 0: /*NEG*/
                    tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
                    break;

                case 1: /*ABS*/
                    {
                        int label = gen_new_label();
                        tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
                        tcg_gen_brcondi_i32(
                                TCG_COND_GE, cpu_R[RRR_R], 0, label);
                        tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
                        gen_set_label(label);
                    }
                    break;

                default: /*reserved*/
                    break;
                }
                break;

            case 7: /*reserved*/
                break;

            case 8: /*ADD*/
                tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 9: /*ADD**/
            case 10:
            case 11:
                {
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
                    tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
                    tcg_temp_free(tmp);
                }
                break;

            case 12: /*SUB*/
                tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 13: /*SUB**/
            case 14:
            case 15:
                {
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
                    tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
                    tcg_temp_free(tmp);
                }
                break;
            }
            break;

        case 1: /*RST1*/
            break;

        case 2: /*RST2*/
            break;

        case 3: /*RST3*/
            break;

        case 4: /*EXTUI*/
        case 5:
            break;

        case 6: /*CUST0*/
            break;

        case 7: /*CUST1*/
            break;

        case 8: /*LSCXp*/
            HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
            break;

        case 9: /*LSC4*/
            break;

        case 10: /*FP0*/
            HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
            break;

        case 11: /*FP1*/
            HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
            break;

        default: /*reserved*/
            break;
        }
        break;

    case 1: /*L32R*/
        {
            TCGv_i32 tmp = tcg_const_i32(
                    (0xfffc0000 | (RI16_IMM16 << 2)) +
                    ((dc->pc + 3) & ~3));

            /* no ext L32R */

            tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
            tcg_temp_free(tmp);
        }
        break;

    case 2: /*LSAI*/
        break;

    case 3: /*LSCIp*/
        HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
        break;

    case 4: /*MAC16d*/
        HAS_OPTION(XTENSA_OPTION_MAC16);
        break;

    case 5: /*CALLN*/
        switch (CALL_N) {
        case 0: /*CALL0*/
            tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
            gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
            break;

        case 1: /*CALL4w*/
        case 2: /*CALL8w*/
        case 3: /*CALL12w*/
            HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
            break;
        }
        break;

    case 6: /*SI*/
        switch (CALL_N) {
        case 0: /*J*/
            gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
            break;

        case 1: /*BZ*/
            {
                static const TCGCond cond[] = {
                    TCG_COND_EQ, /*BEQZ*/
                    TCG_COND_NE, /*BNEZ*/
                    TCG_COND_LT, /*BLTZ*/
                    TCG_COND_GE, /*BGEZ*/
                };

                gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
                        4 + BRI12_IMM12_SE);
            }
            break;

        case 2: /*BI0*/
            {
                static const TCGCond cond[] = {
                    TCG_COND_EQ, /*BEQI*/
                    TCG_COND_NE, /*BNEI*/
                    TCG_COND_LT, /*BLTI*/
                    TCG_COND_GE, /*BGEI*/
                };

                gen_brcondi(dc, cond[BRI8_M & 3],
                        cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
            }
            break;

        case 3: /*BI1*/
            switch (BRI8_M) {
            case 0: /*ENTRYw*/
                HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
                break;

            case 1: /*B1*/
                switch (BRI8_R) {
                case 0: /*BFp*/
                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);
                    break;

                case 1: /*BTp*/
                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);
                    break;

                case 8: /*LOOP*/
                    break;

                case 9: /*LOOPNEZ*/
                    break;

                case 10: /*LOOPGTZ*/
                    break;

                default: /*reserved*/
                    break;

                }
                break;

            case 2: /*BLTUI*/
            case 3: /*BGEUI*/
                gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
                        cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
                break;
            }
            break;

        }
        break;

    case 7: /*B*/
        {
            TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;

            switch (RRI8_R & 7) {
            case 0: /*BNONE*/ /*BANY*/
                {
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
                    gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
                    tcg_temp_free(tmp);
                }
                break;

            case 1: /*BEQ*/ /*BNE*/
            case 2: /*BLT*/ /*BGE*/
            case 3: /*BLTU*/ /*BGEU*/
                {
                    static const TCGCond cond[] = {
                        [1] = TCG_COND_EQ,
                        [2] = TCG_COND_LT,
                        [3] = TCG_COND_LTU,
                        [9] = TCG_COND_NE,
                        [10] = TCG_COND_GE,
                        [11] = TCG_COND_GEU,
                    };
                    gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
                            4 + RRI8_IMM8_SE);
                }
                break;

            case 4: /*BALL*/ /*BNALL*/
                {
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
                    gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
                            4 + RRI8_IMM8_SE);
                    tcg_temp_free(tmp);
                }
                break;

            case 5: /*BBC*/ /*BBS*/
                {
                    TCGv_i32 bit = tcg_const_i32(1);
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
                    tcg_gen_shl_i32(bit, bit, tmp);
                    tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
                    gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
                    tcg_temp_free(tmp);
                    tcg_temp_free(bit);
                }
                break;

            case 6: /*BBCI*/ /*BBSI*/
            case 7:
                {
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
                            1 << (((RRI8_R & 1) << 4) | RRI8_T));
                    gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
                    tcg_temp_free(tmp);
                }
                break;

            }
        }
        break;

#define gen_narrow_load_store(type) do { \
            TCGv_i32 addr = tcg_temp_new_i32(); \
            tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
            tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
            tcg_temp_free(addr); \
        } while (0)

    case 8: /*L32I.Nn*/
        gen_narrow_load_store(ld32u);
        break;

    case 9: /*S32I.Nn*/
        gen_narrow_load_store(st32);
        break;
#undef gen_narrow_load_store

    case 10: /*ADD.Nn*/
        tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
        break;

    case 11: /*ADDI.Nn*/
        tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
        break;

    case 12: /*ST2n*/
        if (RRRN_T < 8) { /*MOVI.Nn*/
            tcg_gen_movi_i32(cpu_R[RRRN_S],
                    RRRN_R | (RRRN_T << 4) |
                    ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
        } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
            TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;

            gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
                    4 + (RRRN_R | ((RRRN_T & 3) << 4)));
        }
        break;

    case 13: /*ST3n*/
        switch (RRRN_R) {
        case 0: /*MOV.Nn*/
            tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
            break;

        case 15: /*S3*/
            switch (RRRN_T) {
            case 0: /*RET.Nn*/
                gen_jump(dc, cpu_R[0]);
                break;

            case 1: /*RETW.Nn*/
                break;

            case 2: /*BREAK.Nn*/
                break;

            case 3: /*NOP.Nn*/
                break;

            case 6: /*ILL.Nn*/
                break;

            default: /*reserved*/
                break;
            }
            break;

        default: /*reserved*/
            break;
        }
        break;

    default: /*reserved*/
        break;
    }

    dc->pc = dc->next_pc;
    return;

invalid_opcode:
    qemu_log("INVALID(pc = %08x)\n", dc->pc);
    dc->pc = dc->next_pc;
#undef HAS_OPTION
}

static void check_breakpoint(CPUState *env, DisasContext *dc)
{
    CPUBreakpoint *bp;

    if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
        QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
            if (bp->pc == dc->pc) {
                tcg_gen_movi_i32(cpu_pc, dc->pc);
                gen_exception(EXCP_DEBUG);
                dc->is_jmp = DISAS_UPDATE;
             }
        }
    }
}

static void gen_intermediate_code_internal(
        CPUState *env, TranslationBlock *tb, int search_pc)
{
    DisasContext dc;
    int insn_count = 0;
    int j, lj = -1;
    uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
    int max_insns = tb->cflags & CF_COUNT_MASK;
    uint32_t pc_start = tb->pc;
    uint32_t next_page_start =
        (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    if (max_insns == 0) {
        max_insns = CF_COUNT_MASK;
    }

    dc.config = env->config;
    dc.singlestep_enabled = env->singlestep_enabled;
    dc.tb = tb;
    dc.pc = pc_start;
    dc.is_jmp = DISAS_NEXT;

    gen_icount_start();

    do {
        check_breakpoint(env, &dc);

        if (search_pc) {
            j = gen_opc_ptr - gen_opc_buf;
            if (lj < j) {
                lj++;
                while (lj < j) {
                    gen_opc_instr_start[lj++] = 0;
                }
            }
            gen_opc_pc[lj] = dc.pc;
            gen_opc_instr_start[lj] = 1;
            gen_opc_icount[lj] = insn_count;
        }

        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
            tcg_gen_debug_insn_start(dc.pc);
        }

        disas_xtensa_insn(&dc);
        ++insn_count;
        if (env->singlestep_enabled) {
            tcg_gen_movi_i32(cpu_pc, dc.pc);
            gen_exception(EXCP_DEBUG);
            break;
        }
    } while (dc.is_jmp == DISAS_NEXT &&
            insn_count < max_insns &&
            dc.pc < next_page_start &&
            gen_opc_ptr < gen_opc_end);

    if (dc.is_jmp == DISAS_NEXT) {
        gen_jumpi(&dc, dc.pc, 0);
    }
    gen_icount_end(tb, insn_count);
    *gen_opc_ptr = INDEX_op_end;

    if (!search_pc) {
        tb->size = dc.pc - pc_start;
        tb->icount = insn_count;
    }
}

void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
{
    gen_intermediate_code_internal(env, tb, 0);
}

void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
{
    gen_intermediate_code_internal(env, tb, 1);
}

void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
        int flags)
{
    int i, j;

    cpu_fprintf(f, "PC=%08x\n\n", env->pc);

    for (i = j = 0; i < 256; ++i) {
        if (sregnames[i]) {
            cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
                    (j++ % 4) == 3 ? '\n' : ' ');
        }
    }

    cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");

    for (i = j = 0; i < 256; ++i) {
        if (uregnames[i]) {
            cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
                    (j++ % 4) == 3 ? '\n' : ' ');
        }
    }

    cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");

    for (i = 0; i < 16; ++i) {
        cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
                (i % 4) == 3 ? '\n' : ' ');
    }
}

void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
{
    env->pc = gen_opc_pc[pc_pos];
}
Commit	Line	Data
2328826b MF	1	/*
	2	* Xtensa ISA:
	3	* http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
	4	*
	5	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	6	* All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or without
	9	* modification, are permitted provided that the following conditions are met:
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in the
	14	* documentation and/or other materials provided with the distribution.
	15	* * Neither the name of the Open Source and Linux Lab nor the
	16	* names of its contributors may be used to endorse or promote products
	17	* derived from this software without specific prior written permission.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	23	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	26	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	29	*/
	30
	31	#include <stdio.h>
	32
	33	#include "cpu.h"
	34	#include "exec-all.h"
	35	#include "disas.h"
	36	#include "tcg-op.h"
	37	#include "qemu-log.h"
	38
dedc5eae MF	39	#include "helpers.h"
	40	#define GEN_HELPER 1
	41	#include "helpers.h"
	42
	43	typedef struct DisasContext {
	44	const XtensaConfig *config;
	45	TranslationBlock *tb;
	46	uint32_t pc;
	47	uint32_t next_pc;
	48	int is_jmp;
	49	int singlestep_enabled;
	50	} DisasContext;
	51
	52	static TCGv_ptr cpu_env;
	53	static TCGv_i32 cpu_pc;
	54	static TCGv_i32 cpu_R[16];
2af3da91 MF	55	static TCGv_i32 cpu_SR[256];
2af3da91 MF	56	static TCGv_i32 cpu_UR[256];
dedc5eae MF	57
dedc5eae MF	58	#include "gen-icount.h"
2328826b	59
2af3da91 MF	60	static const char * const sregnames[256] = {
	61	};
	62
	63	static const char * const uregnames[256] = {
	64	[THREADPTR] = "THREADPTR",
	65	[FCR] = "FCR",
	66	[FSR] = "FSR",
	67	};
	68
2328826b MF	69	void xtensa_translate_init(void)
2328826b MF	70	{
dedc5eae MF	71	static const char * const regnames[] = {
	72	"ar0", "ar1", "ar2", "ar3",
	73	"ar4", "ar5", "ar6", "ar7",
	74	"ar8", "ar9", "ar10", "ar11",
	75	"ar12", "ar13", "ar14", "ar15",
	76	};
	77	int i;
	78
	79	cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
	80	cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
	81	offsetof(CPUState, pc), "pc");
	82
	83	for (i = 0; i < 16; i++) {
	84	cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
	85	offsetof(CPUState, regs[i]),
	86	regnames[i]);
	87	}
2af3da91 MF	88
	89	for (i = 0; i < 256; ++i) {
	90	if (sregnames[i]) {
	91	cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
	92	offsetof(CPUState, sregs[i]),
	93	sregnames[i]);
	94	}
	95	}
	96
	97	for (i = 0; i < 256; ++i) {
	98	if (uregnames[i]) {
	99	cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
	100	offsetof(CPUState, uregs[i]),
	101	uregnames[i]);
	102	}
	103	}
dedc5eae MF	104	#define GEN_HELPER 2
	105	#include "helpers.h"
	106	}
	107
	108	static inline bool option_enabled(DisasContext *dc, int opt)
	109	{
	110	return xtensa_option_enabled(dc->config, opt);
	111	}
	112
	113	static void gen_exception(int excp)
	114	{
	115	TCGv_i32 tmp = tcg_const_i32(excp);
	116	gen_helper_exception(tmp);
	117	tcg_temp_free(tmp);
	118	}
	119
	120	static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
	121	{
	122	tcg_gen_mov_i32(cpu_pc, dest);
	123	if (dc->singlestep_enabled) {
	124	gen_exception(EXCP_DEBUG);
	125	} else {
	126	if (slot >= 0) {
	127	tcg_gen_goto_tb(slot);
	128	tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
	129	} else {
	130	tcg_gen_exit_tb(0);
	131	}
	132	}
	133	dc->is_jmp = DISAS_UPDATE;
	134	}
	135
67882fd1 MF	136	static void gen_jump(DisasContext *dc, TCGv dest)
	137	{
	138	gen_jump_slot(dc, dest, -1);
	139	}
	140
dedc5eae MF	141	static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
	142	{
	143	TCGv_i32 tmp = tcg_const_i32(dest);
	144	if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
	145	slot = -1;
	146	}
	147	gen_jump_slot(dc, tmp, slot);
	148	tcg_temp_free(tmp);
	149	}
	150
bd57fb91 MF	151	static void gen_brcond(DisasContext *dc, TCGCond cond,
	152	TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
	153	{
	154	int label = gen_new_label();
	155
	156	tcg_gen_brcond_i32(cond, t0, t1, label);
	157	gen_jumpi(dc, dc->next_pc, 0);
	158	gen_set_label(label);
	159	gen_jumpi(dc, dc->pc + offset, 1);
	160	}
	161
	162	static void gen_brcondi(DisasContext *dc, TCGCond cond,
	163	TCGv_i32 t0, uint32_t t1, uint32_t offset)
	164	{
	165	TCGv_i32 tmp = tcg_const_i32(t1);
	166	gen_brcond(dc, cond, t0, tmp, offset);
	167	tcg_temp_free(tmp);
	168	}
	169
dedc5eae MF	170	static void disas_xtensa_insn(DisasContext *dc)
	171	{
	172	#define HAS_OPTION(opt) do { \
	173	if (!option_enabled(dc, opt)) { \
	174	qemu_log("Option %d is not enabled %s:%d\n", \
	175	(opt), __FILE__, __LINE__); \
	176	goto invalid_opcode; \
	177	} \
	178	} while (0)
	179
	180	#ifdef TARGET_WORDS_BIGENDIAN
	181	#define OP0 (((b0) & 0xf0) >> 4)
	182	#define OP1 (((b2) & 0xf0) >> 4)
	183	#define OP2 ((b2) & 0xf)
	184	#define RRR_R ((b1) & 0xf)
	185	#define RRR_S (((b1) & 0xf0) >> 4)
	186	#define RRR_T ((b0) & 0xf)
	187	#else
	188	#define OP0 (((b0) & 0xf))
	189	#define OP1 (((b2) & 0xf))
	190	#define OP2 (((b2) & 0xf0) >> 4)
	191	#define RRR_R (((b1) & 0xf0) >> 4)
	192	#define RRR_S (((b1) & 0xf))
	193	#define RRR_T (((b0) & 0xf0) >> 4)
	194	#endif
	195
	196	#define RRRN_R RRR_R
	197	#define RRRN_S RRR_S
	198	#define RRRN_T RRR_T
	199
	200	#define RRI8_R RRR_R
	201	#define RRI8_S RRR_S
	202	#define RRI8_T RRR_T
	203	#define RRI8_IMM8 (b2)
	204	#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) \| RRI8_IMM8)
	205
	206	#ifdef TARGET_WORDS_BIGENDIAN
	207	#define RI16_IMM16 (((b1) << 8) \| (b2))
	208	#else
	209	#define RI16_IMM16 (((b2) << 8) \| (b1))
	210	#endif
	211
	212	#ifdef TARGET_WORDS_BIGENDIAN
	213	#define CALL_N (((b0) & 0xc) >> 2)
	214	#define CALL_OFFSET ((((b0) & 0x3) << 16) \| ((b1) << 8) \| (b2))
	215	#else
	216	#define CALL_N (((b0) & 0x30) >> 4)
	217	#define CALL_OFFSET ((((b0) & 0xc0) >> 6) \| ((b1) << 2) \| ((b2) << 10))
	218	#endif
	219	#define CALL_OFFSET_SE \
	220	(((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) \| CALL_OFFSET)
	221
	222	#define CALLX_N CALL_N
	223	#ifdef TARGET_WORDS_BIGENDIAN
	224	#define CALLX_M ((b0) & 0x3)
	225	#else
	226	#define CALLX_M (((b0) & 0xc0) >> 6)
	227	#endif
	228	#define CALLX_S RRR_S
	229
	230	#define BRI12_M CALLX_M
	231	#define BRI12_S RRR_S
	232	#ifdef TARGET_WORDS_BIGENDIAN
	233	#define BRI12_IMM12 ((((b1) & 0xf) << 8) \| (b2))
234	#else
235	#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) \| ((b2) << 4))
236	#endif
237	#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) \| BRI12_IMM12)
238
239	#define BRI8_M BRI12_M
240	#define BRI8_R RRI8_R
241	#define BRI8_S RRI8_S
242	#define BRI8_IMM8 RRI8_IMM8
243	#define BRI8_IMM8_SE RRI8_IMM8_SE
244
245	#define RSR_SR (b1)
246
247	uint8_t b0 = ldub_code(dc->pc);
248	uint8_t b1 = ldub_code(dc->pc + 1);
249	uint8_t b2 = ldub_code(dc->pc + 2);
250
bd57fb91 MF	251	static const uint32_t B4CONST[] = {
	252	0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
	253	};
	254
	255	static const uint32_t B4CONSTU[] = {
	256	32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
	257	};
	258
dedc5eae MF	259	if (OP0 >= 8) {
	260	dc->next_pc = dc->pc + 2;
	261	HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
	262	} else {
	263	dc->next_pc = dc->pc + 3;
	264	}
	265
	266	switch (OP0) {
	267	case 0: /QRST/
	268	switch (OP1) {
	269	case 0: /RST0/
	270	switch (OP2) {
	271	case 0: /ST0/
	272	if ((RRR_R & 0xc) == 0x8) {
	273	HAS_OPTION(XTENSA_OPTION_BOOLEAN);
	274	}
	275
	276	switch (RRR_R) {
	277	case 0: /SNM0/
5da4a6a8 MF	278	switch (CALLX_M) {
	279	case 0: /ILL/
	280	break;
	281
	282	case 1: /reserved/
	283	break;
	284
	285	case 2: /JR/
	286	switch (CALLX_N) {
	287	case 0: /RET/
	288	case 2: /JX/
	289	gen_jump(dc, cpu_R[CALLX_S]);
	290	break;
	291
	292	case 1: /RETWw/
	293	HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
	294	break;
	295
	296	case 3: /reserved/
	297	break;
	298	}
	299	break;
	300
	301	case 3: /CALLX/
	302	switch (CALLX_N) {
	303	case 0: /CALLX0/
	304	{
	305	TCGv_i32 tmp = tcg_temp_new_i32();
	306	tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
	307	tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
	308	gen_jump(dc, tmp);
	309	tcg_temp_free(tmp);
	310	}
	311	break;
	312
	313	case 1: /CALLX4w/
	314	case 2: /CALLX8w/
	315	case 3: /CALLX12w/
	316	HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
	317	break;
	318	}
	319	break;
	320	}
dedc5eae MF	321	break;
	322
	323	case 1: /MOVSPw/
	324	HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
	325	break;
	326
	327	case 2: /SYNC/
	328	break;
	329
	330	case 3:
	331	break;
	332
	333	}
	334	break;
	335
	336	case 1: /AND/
	337	tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
	338	break;
	339
	340	case 2: /OR/
	341	tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
	342	break;
	343
	344	case 3: /XOR/
	345	tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
	346	break;
	347
	348	case 4: /ST1/
	349	break;
	350
	351	case 5: /TLB/
	352	break;
	353
	354	case 6: /RT0/
f331fe5e MF	355	switch (RRR_S) {
	356	case 0: /NEG/
	357	tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
	358	break;
	359
	360	case 1: /ABS/
	361	{
	362	int label = gen_new_label();
	363	tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
	364	tcg_gen_brcondi_i32(
	365	TCG_COND_GE, cpu_R[RRR_R], 0, label);
	366	tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
	367	gen_set_label(label);
	368	}
	369	break;
	370
	371	default: /reserved/
	372	break;
	373	}
dedc5eae MF	374	break;
	375
	376	case 7: /reserved/
	377	break;
	378
	379	case 8: /ADD/
	380	tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
	381	break;
	382
	383	case 9: /ADD*/
	384	case 10:
	385	case 11:
	386	{
	387	TCGv_i32 tmp = tcg_temp_new_i32();
	388	tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
	389	tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
	390	tcg_temp_free(tmp);
	391	}
	392	break;
	393
	394	case 12: /SUB/
	395	tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
	396	break;
	397
	398	case 13: /SUB*/
	399	case 14:
	400	case 15:
	401	{
	402	TCGv_i32 tmp = tcg_temp_new_i32();
	403	tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
	404	tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
	405	tcg_temp_free(tmp);
	406	}
	407	break;
	408	}
	409	break;
	410
	411	case 1: /RST1/
	412	break;
	413
	414	case 2: /RST2/
	415	break;
	416
	417	case 3: /RST3/
	418	break;
	419
	420	case 4: /EXTUI/
	421	case 5:
	422	break;
	423
	424	case 6: /CUST0/
	425	break;
	426
	427	case 7: /CUST1/
	428	break;
	429
	430	case 8: /LSCXp/
	431	HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
	432	break;
	433
	434	case 9: /LSC4/
	435	break;
	436
	437	case 10: /FP0/
438	HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
439	break;
440
441	case 11: /FP1/
442	HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
443	break;
444
445	default: /reserved/
446	break;
447	}
448	break;
449
450	case 1: /L32R/
451	{
452	TCGv_i32 tmp = tcg_const_i32(
453	(0xfffc0000 \| (RI16_IMM16 << 2)) +
454	((dc->pc + 3) & ~3));
455
456	/* no ext L32R */
457
458	tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
459	tcg_temp_free(tmp);
460	}
461	break;
462
463	case 2: /LSAI/
464	break;
465
466	case 3: /LSCIp/
467	HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
468	break;
469
470	case 4: /MAC16d/
471	HAS_OPTION(XTENSA_OPTION_MAC16);
472	break;
473
474	case 5: /CALLN/
475	switch (CALL_N) {
476	case 0: /CALL0/
477	tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
478	gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
479	break;
480
481	case 1: /CALL4w/
482	case 2: /CALL8w/
483	case 3: /CALL12w/
484	HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
485	break;
486	}
487	break;
488
489	case 6: /SI/
490	switch (CALL_N) {
491	case 0: /J/
492	gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
493	break;
494
bd57fb91 MF	495	case 1: /BZ/
	496	{
	497	static const TCGCond cond[] = {
	498	TCG_COND_EQ, /BEQZ/
	499	TCG_COND_NE, /BNEZ/
	500	TCG_COND_LT, /BLTZ/
	501	TCG_COND_GE, /BGEZ/
	502	};
	503
	504	gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
	505	4 + BRI12_IMM12_SE);
	506	}
	507	break;
	508
	509	case 2: /BI0/
	510	{
	511	static const TCGCond cond[] = {
	512	TCG_COND_EQ, /BEQI/
	513	TCG_COND_NE, /BNEI/
	514	TCG_COND_LT, /BLTI/
	515	TCG_COND_GE, /BGEI/
	516	};
	517
	518	gen_brcondi(dc, cond[BRI8_M & 3],
	519	cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
	520	}
	521	break;
	522
	523	case 3: /BI1/
	524	switch (BRI8_M) {
	525	case 0: /ENTRYw/
	526	HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
	527	break;
	528
	529	case 1: /B1/
	530	switch (BRI8_R) {
	531	case 0: /BFp/
	532	HAS_OPTION(XTENSA_OPTION_BOOLEAN);
	533	break;
	534
	535	case 1: /BTp/
	536	HAS_OPTION(XTENSA_OPTION_BOOLEAN);
	537	break;
	538
	539	case 8: /LOOP/
	540	break;
	541
	542	case 9: /LOOPNEZ/
	543	break;
	544
	545	case 10: /LOOPGTZ/
	546	break;
	547
	548	default: /reserved/
	549	break;
	550
	551	}
	552	break;
	553
	554	case 2: /BLTUI/
	555	case 3: /BGEUI/
	556	gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
	557	cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
	558	break;
559	}
560	break;
561
dedc5eae MF	562	}
	563	break;
	564
	565	case 7: /B/
bd57fb91 MF	566	{
	567	TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
	568
	569	switch (RRI8_R & 7) {
	570	case 0: /BNONE/ /BANY/
	571	{
	572	TCGv_i32 tmp = tcg_temp_new_i32();
	573	tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
	574	gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
	575	tcg_temp_free(tmp);
	576	}
	577	break;
	578
	579	case 1: /BEQ/ /BNE/
	580	case 2: /BLT/ /BGE/
	581	case 3: /BLTU/ /BGEU/
	582	{
	583	static const TCGCond cond[] = {
	584	[1] = TCG_COND_EQ,
	585	[2] = TCG_COND_LT,
	586	[3] = TCG_COND_LTU,
	587	[9] = TCG_COND_NE,
	588	[10] = TCG_COND_GE,
	589	[11] = TCG_COND_GEU,
	590	};
	591	gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
	592	4 + RRI8_IMM8_SE);
	593	}
	594	break;
	595
	596	case 4: /BALL/ /BNALL/
	597	{
	598	TCGv_i32 tmp = tcg_temp_new_i32();
	599	tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
	600	gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
	601	4 + RRI8_IMM8_SE);
	602	tcg_temp_free(tmp);
	603	}
	604	break;
	605
	606	case 5: /BBC/ /BBS/
	607	{
	608	TCGv_i32 bit = tcg_const_i32(1);
	609	TCGv_i32 tmp = tcg_temp_new_i32();
	610	tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
	611	tcg_gen_shl_i32(bit, bit, tmp);
	612	tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
	613	gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
	614	tcg_temp_free(tmp);
	615	tcg_temp_free(bit);
	616	}
	617	break;
	618
	619	case 6: /BBCI/ /BBSI/
	620	case 7:
	621	{
	622	TCGv_i32 tmp = tcg_temp_new_i32();
	623	tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
	624	1 << (((RRI8_R & 1) << 4) \| RRI8_T));
	625	gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
	626	tcg_temp_free(tmp);
	627	}
	628	break;
	629
630	}
631	}
dedc5eae MF	632	break;
dedc5eae MF	633
67882fd1 MF	634	#define gen_narrow_load_store(type) do { \
	635	TCGv_i32 addr = tcg_temp_new_i32(); \
	636	tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
	637	tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
	638	tcg_temp_free(addr); \
	639	} while (0)
	640
dedc5eae	641	case 8: /L32I.Nn/
67882fd1	642	gen_narrow_load_store(ld32u);
dedc5eae MF	643	break;
	644
	645	case 9: /S32I.Nn/
67882fd1	646	gen_narrow_load_store(st32);
dedc5eae	647	break;
67882fd1	648	#undef gen_narrow_load_store
dedc5eae MF	649
dedc5eae MF	650	case 10: /ADD.Nn/
67882fd1	651	tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae MF	652	break;
	653
	654	case 11: /ADDI.Nn/
67882fd1	655	tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae MF	656	break;
	657
	658	case 12: /ST2n/
67882fd1 MF	659	if (RRRN_T < 8) { /MOVI.Nn/
	660	tcg_gen_movi_i32(cpu_R[RRRN_S],
	661	RRRN_R \| (RRRN_T << 4) \|
	662	((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
	663	} else { /BEQZ.Nn/ /BNEZ.Nn/
bd57fb91 MF	664	TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
	665
	666	gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
	667	4 + (RRRN_R \| ((RRRN_T & 3) << 4)));
67882fd1	668	}
dedc5eae MF	669	break;
	670
	671	case 13: /ST3n/
67882fd1 MF	672	switch (RRRN_R) {
	673	case 0: /MOV.Nn/
	674	tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
	675	break;
	676
	677	case 15: /S3/
	678	switch (RRRN_T) {
	679	case 0: /RET.Nn/
	680	gen_jump(dc, cpu_R[0]);
	681	break;
	682
	683	case 1: /RETW.Nn/
	684	break;
	685
	686	case 2: /BREAK.Nn/
	687	break;
	688
	689	case 3: /NOP.Nn/
	690	break;
	691
	692	case 6: /ILL.Nn/
	693	break;
	694
	695	default: /reserved/
	696	break;
	697	}
	698	break;
	699
	700	default: /reserved/
	701	break;
	702	}
dedc5eae MF	703	break;
	704
	705	default: /reserved/
	706	break;
	707	}
	708
	709	dc->pc = dc->next_pc;
	710	return;
	711
	712	invalid_opcode:
	713	qemu_log("INVALID(pc = %08x)\n", dc->pc);
	714	dc->pc = dc->next_pc;
	715	#undef HAS_OPTION
	716	}
	717
	718	static void check_breakpoint(CPUState env, DisasContext dc)
	719	{
	720	CPUBreakpoint *bp;
	721
	722	if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
	723	QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
	724	if (bp->pc == dc->pc) {
	725	tcg_gen_movi_i32(cpu_pc, dc->pc);
	726	gen_exception(EXCP_DEBUG);
	727	dc->is_jmp = DISAS_UPDATE;
	728	}
	729	}
	730	}
	731	}
	732
	733	static void gen_intermediate_code_internal(
	734	CPUState env, TranslationBlock tb, int search_pc)
	735	{
	736	DisasContext dc;
	737	int insn_count = 0;
	738	int j, lj = -1;
	739	uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
	740	int max_insns = tb->cflags & CF_COUNT_MASK;
	741	uint32_t pc_start = tb->pc;
	742	uint32_t next_page_start =
	743	(pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
	744
	745	if (max_insns == 0) {
	746	max_insns = CF_COUNT_MASK;
	747	}
	748
	749	dc.config = env->config;
	750	dc.singlestep_enabled = env->singlestep_enabled;
	751	dc.tb = tb;
	752	dc.pc = pc_start;
	753	dc.is_jmp = DISAS_NEXT;
	754
	755	gen_icount_start();
	756
	757	do {
	758	check_breakpoint(env, &dc);
	759
	760	if (search_pc) {
	761	j = gen_opc_ptr - gen_opc_buf;
	762	if (lj < j) {
	763	lj++;
	764	while (lj < j) {
	765	gen_opc_instr_start[lj++] = 0;
	766	}
767	}
768	gen_opc_pc[lj] = dc.pc;
769	gen_opc_instr_start[lj] = 1;
770	gen_opc_icount[lj] = insn_count;
771	}
772
773	if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
774	tcg_gen_debug_insn_start(dc.pc);
775	}
776
777	disas_xtensa_insn(&dc);
778	++insn_count;
779	if (env->singlestep_enabled) {
780	tcg_gen_movi_i32(cpu_pc, dc.pc);
781	gen_exception(EXCP_DEBUG);
782	break;
783	}
784	} while (dc.is_jmp == DISAS_NEXT &&
785	insn_count < max_insns &&
786	dc.pc < next_page_start &&
787	gen_opc_ptr < gen_opc_end);
788
789	if (dc.is_jmp == DISAS_NEXT) {
790	gen_jumpi(&dc, dc.pc, 0);
791	}
792	gen_icount_end(tb, insn_count);
793	*gen_opc_ptr = INDEX_op_end;
794
795	if (!search_pc) {
796	tb->size = dc.pc - pc_start;
797	tb->icount = insn_count;
798	}
2328826b MF	799	}
	800
	801	void gen_intermediate_code(CPUState env, TranslationBlock tb)
	802	{
dedc5eae	803	gen_intermediate_code_internal(env, tb, 0);
2328826b MF	804	}
	805
	806	void gen_intermediate_code_pc(CPUState env, TranslationBlock tb)
	807	{
dedc5eae	808	gen_intermediate_code_internal(env, tb, 1);
2328826b MF	809	}
	810
	811	void cpu_dump_state(CPUState env, FILE f, fprintf_function cpu_fprintf,
	812	int flags)
	813	{
2af3da91 MF	814	int i, j;
	815
	816	cpu_fprintf(f, "PC=%08x\n\n", env->pc);
	817
	818	for (i = j = 0; i < 256; ++i) {
	819	if (sregnames[i]) {
	820	cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
	821	(j++ % 4) == 3 ? '\n' : ' ');
	822	}
	823	}
	824
	825	cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
	826
	827	for (i = j = 0; i < 256; ++i) {
	828	if (uregnames[i]) {
	829	cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
	830	(j++ % 4) == 3 ? '\n' : ' ');
	831	}
	832	}
2328826b	833
2af3da91	834	cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
2328826b MF	835
	836	for (i = 0; i < 16; ++i) {
	837	cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
	838	(i % 4) == 3 ? '\n' : ' ');
	839	}
	840	}
	841
	842	void restore_state_to_opc(CPUState env, TranslationBlock tb, int pc_pos)
	843	{
	844	env->pc = gen_opc_pc[pc_pos];
	845	}