[qemu.git] / target-xtensa / translate.c

/*
 * Xtensa ISA:
 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
 *
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <stdio.h>

#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
#include "qemu-log.h"

#include "helpers.h"
#define GEN_HELPER 1
#include "helpers.h"

typedef struct DisasContext {
    const XtensaConfig *config;
    TranslationBlock *tb;
    uint32_t pc;
    uint32_t next_pc;
    int is_jmp;
    int singlestep_enabled;
} DisasContext;

static TCGv_ptr cpu_env;
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_R[16];

#include "gen-icount.h"

void xtensa_translate_init(void)
{
    static const char * const regnames[] = {
        "ar0", "ar1", "ar2", "ar3",
        "ar4", "ar5", "ar6", "ar7",
        "ar8", "ar9", "ar10", "ar11",
        "ar12", "ar13", "ar14", "ar15",
    };
    int i;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
    cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
            offsetof(CPUState, pc), "pc");

    for (i = 0; i < 16; i++) {
        cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
                offsetof(CPUState, regs[i]),
                regnames[i]);
    }
#define GEN_HELPER 2
#include "helpers.h"
}

static inline bool option_enabled(DisasContext *dc, int opt)
{
    return xtensa_option_enabled(dc->config, opt);
}

static void gen_exception(int excp)
{
    TCGv_i32 tmp = tcg_const_i32(excp);
    gen_helper_exception(tmp);
    tcg_temp_free(tmp);
}

static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
{
    tcg_gen_mov_i32(cpu_pc, dest);
    if (dc->singlestep_enabled) {
        gen_exception(EXCP_DEBUG);
    } else {
        if (slot >= 0) {
            tcg_gen_goto_tb(slot);
            tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
        } else {
            tcg_gen_exit_tb(0);
        }
    }
    dc->is_jmp = DISAS_UPDATE;
}

static void gen_jump(DisasContext *dc, TCGv dest)
{
    gen_jump_slot(dc, dest, -1);
}

static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
    TCGv_i32 tmp = tcg_const_i32(dest);
    if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
        slot = -1;
    }
    gen_jump_slot(dc, tmp, slot);
    tcg_temp_free(tmp);
}

static void disas_xtensa_insn(DisasContext *dc)
{
#define HAS_OPTION(opt) do { \
        if (!option_enabled(dc, opt)) { \
            qemu_log("Option %d is not enabled %s:%d\n", \
                    (opt), __FILE__, __LINE__); \
            goto invalid_opcode; \
        } \
    } while (0)

#ifdef TARGET_WORDS_BIGENDIAN
#define OP0 (((b0) & 0xf0) >> 4)
#define OP1 (((b2) & 0xf0) >> 4)
#define OP2 ((b2) & 0xf)
#define RRR_R ((b1) & 0xf)
#define RRR_S (((b1) & 0xf0) >> 4)
#define RRR_T ((b0) & 0xf)
#else
#define OP0 (((b0) & 0xf))
#define OP1 (((b2) & 0xf))
#define OP2 (((b2) & 0xf0) >> 4)
#define RRR_R (((b1) & 0xf0) >> 4)
#define RRR_S (((b1) & 0xf))
#define RRR_T (((b0) & 0xf0) >> 4)
#endif

#define RRRN_R RRR_R
#define RRRN_S RRR_S
#define RRRN_T RRR_T

#define RRI8_R RRR_R
#define RRI8_S RRR_S
#define RRI8_T RRR_T
#define RRI8_IMM8 (b2)
#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)

#ifdef TARGET_WORDS_BIGENDIAN
#define RI16_IMM16 (((b1) << 8) | (b2))
#else
#define RI16_IMM16 (((b2) << 8) | (b1))
#endif

#ifdef TARGET_WORDS_BIGENDIAN
#define CALL_N (((b0) & 0xc) >> 2)
#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
#else
#define CALL_N (((b0) & 0x30) >> 4)
#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
#endif
#define CALL_OFFSET_SE \
    (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)

#define CALLX_N CALL_N
#ifdef TARGET_WORDS_BIGENDIAN
#define CALLX_M ((b0) & 0x3)
#else
#define CALLX_M (((b0) & 0xc0) >> 6)
#endif
#define CALLX_S RRR_S

#define BRI12_M CALLX_M
#define BRI12_S RRR_S
#ifdef TARGET_WORDS_BIGENDIAN
#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
#else
#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
#endif
#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)

#define BRI8_M BRI12_M
#define BRI8_R RRI8_R
#define BRI8_S RRI8_S
#define BRI8_IMM8 RRI8_IMM8
#define BRI8_IMM8_SE RRI8_IMM8_SE

#define RSR_SR (b1)

    uint8_t b0 = ldub_code(dc->pc);
    uint8_t b1 = ldub_code(dc->pc + 1);
    uint8_t b2 = ldub_code(dc->pc + 2);

    if (OP0 >= 8) {
        dc->next_pc = dc->pc + 2;
        HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
    } else {
        dc->next_pc = dc->pc + 3;
    }

    switch (OP0) {
    case 0: /*QRST*/
        switch (OP1) {
        case 0: /*RST0*/
            switch (OP2) {
            case 0: /*ST0*/
                if ((RRR_R & 0xc) == 0x8) {
                    HAS_OPTION(XTENSA_OPTION_BOOLEAN);
                }

                switch (RRR_R) {
                case 0: /*SNM0*/
                    break;

                case 1: /*MOVSPw*/
                    HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
                    break;

                case 2: /*SYNC*/
                    break;

                case 3:
                    break;

                }
                break;

            case 1: /*AND*/
                tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 2: /*OR*/
                tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 3: /*XOR*/
                tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 4: /*ST1*/
                break;

            case 5: /*TLB*/
                break;

            case 6: /*RT0*/
                break;

            case 7: /*reserved*/
                break;

            case 8: /*ADD*/
                tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 9: /*ADD**/
            case 10:
            case 11:
                {
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
                    tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
                    tcg_temp_free(tmp);
                }
                break;

            case 12: /*SUB*/
                tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
                break;

            case 13: /*SUB**/
            case 14:
            case 15:
                {
                    TCGv_i32 tmp = tcg_temp_new_i32();
                    tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
                    tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
                    tcg_temp_free(tmp);
                }
                break;
            }
            break;

        case 1: /*RST1*/
            break;

        case 2: /*RST2*/
            break;

        case 3: /*RST3*/
            break;

        case 4: /*EXTUI*/
        case 5:
            break;

        case 6: /*CUST0*/
            break;

        case 7: /*CUST1*/
            break;

        case 8: /*LSCXp*/
            HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
            break;

        case 9: /*LSC4*/
            break;

        case 10: /*FP0*/
            HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
            break;

        case 11: /*FP1*/
            HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
            break;

        default: /*reserved*/
            break;
        }
        break;

    case 1: /*L32R*/
        {
            TCGv_i32 tmp = tcg_const_i32(
                    (0xfffc0000 | (RI16_IMM16 << 2)) +
                    ((dc->pc + 3) & ~3));

            /* no ext L32R */

            tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
            tcg_temp_free(tmp);
        }
        break;

    case 2: /*LSAI*/
        break;

    case 3: /*LSCIp*/
        HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
        break;

    case 4: /*MAC16d*/
        HAS_OPTION(XTENSA_OPTION_MAC16);
        break;

    case 5: /*CALLN*/
        switch (CALL_N) {
        case 0: /*CALL0*/
            tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
            gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
            break;

        case 1: /*CALL4w*/
        case 2: /*CALL8w*/
        case 3: /*CALL12w*/
            HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
            break;
        }
        break;

    case 6: /*SI*/
        switch (CALL_N) {
        case 0: /*J*/
            gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
            break;

        }
        break;

    case 7: /*B*/
        break;

#define gen_narrow_load_store(type) do { \
            TCGv_i32 addr = tcg_temp_new_i32(); \
            tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
            tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
            tcg_temp_free(addr); \
        } while (0)

    case 8: /*L32I.Nn*/
        gen_narrow_load_store(ld32u);
        break;

    case 9: /*S32I.Nn*/
        gen_narrow_load_store(st32);
        break;
#undef gen_narrow_load_store

    case 10: /*ADD.Nn*/
        tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
        break;

    case 11: /*ADDI.Nn*/
        tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
        break;

    case 12: /*ST2n*/
        if (RRRN_T < 8) { /*MOVI.Nn*/
            tcg_gen_movi_i32(cpu_R[RRRN_S],
                    RRRN_R | (RRRN_T << 4) |
                    ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
        } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
        }
        break;

    case 13: /*ST3n*/
        switch (RRRN_R) {
        case 0: /*MOV.Nn*/
            tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
            break;

        case 15: /*S3*/
            switch (RRRN_T) {
            case 0: /*RET.Nn*/
                gen_jump(dc, cpu_R[0]);
                break;

            case 1: /*RETW.Nn*/
                break;

            case 2: /*BREAK.Nn*/
                break;

            case 3: /*NOP.Nn*/
                break;

            case 6: /*ILL.Nn*/
                break;

            default: /*reserved*/
                break;
            }
            break;

        default: /*reserved*/
            break;
        }
        break;

    default: /*reserved*/
        break;
    }

    dc->pc = dc->next_pc;
    return;

invalid_opcode:
    qemu_log("INVALID(pc = %08x)\n", dc->pc);
    dc->pc = dc->next_pc;
#undef HAS_OPTION
}

static void check_breakpoint(CPUState *env, DisasContext *dc)
{
    CPUBreakpoint *bp;

    if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
        QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
            if (bp->pc == dc->pc) {
                tcg_gen_movi_i32(cpu_pc, dc->pc);
                gen_exception(EXCP_DEBUG);
                dc->is_jmp = DISAS_UPDATE;
             }
        }
    }
}

static void gen_intermediate_code_internal(
        CPUState *env, TranslationBlock *tb, int search_pc)
{
    DisasContext dc;
    int insn_count = 0;
    int j, lj = -1;
    uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
    int max_insns = tb->cflags & CF_COUNT_MASK;
    uint32_t pc_start = tb->pc;
    uint32_t next_page_start =
        (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;

    if (max_insns == 0) {
        max_insns = CF_COUNT_MASK;
    }

    dc.config = env->config;
    dc.singlestep_enabled = env->singlestep_enabled;
    dc.tb = tb;
    dc.pc = pc_start;
    dc.is_jmp = DISAS_NEXT;

    gen_icount_start();

    do {
        check_breakpoint(env, &dc);

        if (search_pc) {
            j = gen_opc_ptr - gen_opc_buf;
            if (lj < j) {
                lj++;
                while (lj < j) {
                    gen_opc_instr_start[lj++] = 0;
                }
            }
            gen_opc_pc[lj] = dc.pc;
            gen_opc_instr_start[lj] = 1;
            gen_opc_icount[lj] = insn_count;
        }

        if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
            tcg_gen_debug_insn_start(dc.pc);
        }

        disas_xtensa_insn(&dc);
        ++insn_count;
        if (env->singlestep_enabled) {
            tcg_gen_movi_i32(cpu_pc, dc.pc);
            gen_exception(EXCP_DEBUG);
            break;
        }
    } while (dc.is_jmp == DISAS_NEXT &&
            insn_count < max_insns &&
            dc.pc < next_page_start &&
            gen_opc_ptr < gen_opc_end);

    if (dc.is_jmp == DISAS_NEXT) {
        gen_jumpi(&dc, dc.pc, 0);
    }
    gen_icount_end(tb, insn_count);
    *gen_opc_ptr = INDEX_op_end;

    if (!search_pc) {
        tb->size = dc.pc - pc_start;
        tb->icount = insn_count;
    }
}

void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
{
    gen_intermediate_code_internal(env, tb, 0);
}

void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
{
    gen_intermediate_code_internal(env, tb, 1);
}

void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
        int flags)
{
    int i;

    cpu_fprintf(f, "PC=%08x\n", env->pc);

    for (i = 0; i < 16; ++i) {
        cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
                (i % 4) == 3 ? '\n' : ' ');
    }
}

void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
{
    env->pc = gen_opc_pc[pc_pos];
}
Commit	Line	Data
2328826b MF	1	/*
	2	* Xtensa ISA:
	3	* http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
	4	*
	5	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	6	* All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or without
	9	* modification, are permitted provided that the following conditions are met:
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in the
	14	* documentation and/or other materials provided with the distribution.
	15	* * Neither the name of the Open Source and Linux Lab nor the
	16	* names of its contributors may be used to endorse or promote products
	17	* derived from this software without specific prior written permission.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	23	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	26	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	29	*/
	30
	31	#include <stdio.h>
	32
	33	#include "cpu.h"
	34	#include "exec-all.h"
	35	#include "disas.h"
	36	#include "tcg-op.h"
	37	#include "qemu-log.h"
	38
dedc5eae MF	39	#include "helpers.h"
	40	#define GEN_HELPER 1
	41	#include "helpers.h"
	42
	43	typedef struct DisasContext {
	44	const XtensaConfig *config;
	45	TranslationBlock *tb;
	46	uint32_t pc;
	47	uint32_t next_pc;
	48	int is_jmp;
	49	int singlestep_enabled;
	50	} DisasContext;
	51
	52	static TCGv_ptr cpu_env;
	53	static TCGv_i32 cpu_pc;
	54	static TCGv_i32 cpu_R[16];
	55
	56	#include "gen-icount.h"
2328826b MF	57
	58	void xtensa_translate_init(void)
	59	{
dedc5eae MF	60	static const char * const regnames[] = {
	61	"ar0", "ar1", "ar2", "ar3",
	62	"ar4", "ar5", "ar6", "ar7",
	63	"ar8", "ar9", "ar10", "ar11",
	64	"ar12", "ar13", "ar14", "ar15",
	65	};
	66	int i;
	67
	68	cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
	69	cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
	70	offsetof(CPUState, pc), "pc");
	71
	72	for (i = 0; i < 16; i++) {
	73	cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
	74	offsetof(CPUState, regs[i]),
	75	regnames[i]);
	76	}
	77	#define GEN_HELPER 2
	78	#include "helpers.h"
	79	}
	80
	81	static inline bool option_enabled(DisasContext *dc, int opt)
	82	{
	83	return xtensa_option_enabled(dc->config, opt);
	84	}
	85
	86	static void gen_exception(int excp)
	87	{
	88	TCGv_i32 tmp = tcg_const_i32(excp);
	89	gen_helper_exception(tmp);
	90	tcg_temp_free(tmp);
	91	}
	92
	93	static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
	94	{
	95	tcg_gen_mov_i32(cpu_pc, dest);
	96	if (dc->singlestep_enabled) {
	97	gen_exception(EXCP_DEBUG);
	98	} else {
	99	if (slot >= 0) {
	100	tcg_gen_goto_tb(slot);
	101	tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
	102	} else {
	103	tcg_gen_exit_tb(0);
	104	}
	105	}
	106	dc->is_jmp = DISAS_UPDATE;
	107	}
	108
67882fd1 MF	109	static void gen_jump(DisasContext *dc, TCGv dest)
	110	{
	111	gen_jump_slot(dc, dest, -1);
	112	}
	113
dedc5eae MF	114	static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
	115	{
	116	TCGv_i32 tmp = tcg_const_i32(dest);
	117	if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
	118	slot = -1;
	119	}
	120	gen_jump_slot(dc, tmp, slot);
	121	tcg_temp_free(tmp);
	122	}
	123
	124	static void disas_xtensa_insn(DisasContext *dc)
	125	{
	126	#define HAS_OPTION(opt) do { \
	127	if (!option_enabled(dc, opt)) { \
	128	qemu_log("Option %d is not enabled %s:%d\n", \
	129	(opt), __FILE__, __LINE__); \
	130	goto invalid_opcode; \
	131	} \
	132	} while (0)
	133
	134	#ifdef TARGET_WORDS_BIGENDIAN
	135	#define OP0 (((b0) & 0xf0) >> 4)
	136	#define OP1 (((b2) & 0xf0) >> 4)
	137	#define OP2 ((b2) & 0xf)
	138	#define RRR_R ((b1) & 0xf)
	139	#define RRR_S (((b1) & 0xf0) >> 4)
	140	#define RRR_T ((b0) & 0xf)
	141	#else
	142	#define OP0 (((b0) & 0xf))
	143	#define OP1 (((b2) & 0xf))
	144	#define OP2 (((b2) & 0xf0) >> 4)
	145	#define RRR_R (((b1) & 0xf0) >> 4)
	146	#define RRR_S (((b1) & 0xf))
	147	#define RRR_T (((b0) & 0xf0) >> 4)
	148	#endif
	149
	150	#define RRRN_R RRR_R
	151	#define RRRN_S RRR_S
	152	#define RRRN_T RRR_T
	153
	154	#define RRI8_R RRR_R
	155	#define RRI8_S RRR_S
	156	#define RRI8_T RRR_T
	157	#define RRI8_IMM8 (b2)
	158	#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) \| RRI8_IMM8)
	159
	160	#ifdef TARGET_WORDS_BIGENDIAN
	161	#define RI16_IMM16 (((b1) << 8) \| (b2))
	162	#else
	163	#define RI16_IMM16 (((b2) << 8) \| (b1))
	164	#endif
	165
	166	#ifdef TARGET_WORDS_BIGENDIAN
	167	#define CALL_N (((b0) & 0xc) >> 2)
	168	#define CALL_OFFSET ((((b0) & 0x3) << 16) \| ((b1) << 8) \| (b2))
	169	#else
	170	#define CALL_N (((b0) & 0x30) >> 4)
	171	#define CALL_OFFSET ((((b0) & 0xc0) >> 6) \| ((b1) << 2) \| ((b2) << 10))
	172	#endif
	173	#define CALL_OFFSET_SE \
	174	(((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) \| CALL_OFFSET)
	175
	176	#define CALLX_N CALL_N
	177	#ifdef TARGET_WORDS_BIGENDIAN
178	#define CALLX_M ((b0) & 0x3)
179	#else
180	#define CALLX_M (((b0) & 0xc0) >> 6)
181	#endif
182	#define CALLX_S RRR_S
183
184	#define BRI12_M CALLX_M
185	#define BRI12_S RRR_S
186	#ifdef TARGET_WORDS_BIGENDIAN
187	#define BRI12_IMM12 ((((b1) & 0xf) << 8) \| (b2))
188	#else
189	#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) \| ((b2) << 4))
190	#endif
191	#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) \| BRI12_IMM12)
192
193	#define BRI8_M BRI12_M
194	#define BRI8_R RRI8_R
195	#define BRI8_S RRI8_S
196	#define BRI8_IMM8 RRI8_IMM8
197	#define BRI8_IMM8_SE RRI8_IMM8_SE
198
199	#define RSR_SR (b1)
200
201	uint8_t b0 = ldub_code(dc->pc);
202	uint8_t b1 = ldub_code(dc->pc + 1);
203	uint8_t b2 = ldub_code(dc->pc + 2);
204
205	if (OP0 >= 8) {
206	dc->next_pc = dc->pc + 2;
207	HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
208	} else {
209	dc->next_pc = dc->pc + 3;
210	}
211
212	switch (OP0) {
213	case 0: /QRST/
214	switch (OP1) {
215	case 0: /RST0/
216	switch (OP2) {
217	case 0: /ST0/
218	if ((RRR_R & 0xc) == 0x8) {
219	HAS_OPTION(XTENSA_OPTION_BOOLEAN);
220	}
221
222	switch (RRR_R) {
223	case 0: /SNM0/
224	break;
225
226	case 1: /MOVSPw/
227	HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
228	break;
229
230	case 2: /SYNC/
231	break;
232
233	case 3:
234	break;
235
236	}
237	break;
238
239	case 1: /AND/
240	tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
241	break;
242
243	case 2: /OR/
244	tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
245	break;
246
247	case 3: /XOR/
248	tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
249	break;
250
251	case 4: /ST1/
252	break;
253
254	case 5: /TLB/
255	break;
256
257	case 6: /RT0/
258	break;
259
260	case 7: /reserved/
261	break;
262
263	case 8: /ADD/
264	tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
265	break;
266
267	case 9: /ADD*/
268	case 10:
269	case 11:
270	{
271	TCGv_i32 tmp = tcg_temp_new_i32();
272	tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
273	tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
274	tcg_temp_free(tmp);
275	}
276	break;
277
278	case 12: /SUB/
279	tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
280	break;
281
282	case 13: /SUB*/
283	case 14:
284	case 15:
285	{
286	TCGv_i32 tmp = tcg_temp_new_i32();
287	tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
288	tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
289	tcg_temp_free(tmp);
290	}
291	break;
292	}
293	break;
294
295	case 1: /RST1/
296	break;
297
298	case 2: /RST2/
299	break;
300
301	case 3: /RST3/
302	break;
303
304	case 4: /EXTUI/
305	case 5:
306	break;
307
308	case 6: /CUST0/
309	break;
310
311	case 7: /CUST1/
312	break;
313
314	case 8: /LSCXp/
315	HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
316	break;
317
318	case 9: /LSC4/
319	break;
320
321	case 10: /FP0/
322	HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
323	break;
324
325	case 11: /FP1/
326	HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
327	break;
328
329	default: /reserved/
330	break;
331	}
332	break;
333
334	case 1: /L32R/
335	{
336	TCGv_i32 tmp = tcg_const_i32(
337	(0xfffc0000 \| (RI16_IMM16 << 2)) +
338	((dc->pc + 3) & ~3));
339
340	/* no ext L32R */
341
342	tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
343	tcg_temp_free(tmp);
344	}
345	break;
346
347	case 2: /LSAI/
348	break;
349
350	case 3: /LSCIp/
351	HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
352	break;
353
354	case 4: /MAC16d/
355	HAS_OPTION(XTENSA_OPTION_MAC16);
356	break;
357
358	case 5: /CALLN/
359	switch (CALL_N) {
360	case 0: /CALL0/
361	tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
362	gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
363	break;
364
365	case 1: /CALL4w/
366	case 2: /CALL8w/
367	case 3: /CALL12w/
368	HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
369	break;
370	}
371	break;
372
373	case 6: /SI/
374	switch (CALL_N) {
375	case 0: /J/
376	gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
377	break;
378
379	}
380	break;
381
382	case 7: /B/
383	break;
384
67882fd1 MF	385	#define gen_narrow_load_store(type) do { \
	386	TCGv_i32 addr = tcg_temp_new_i32(); \
	387	tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
	388	tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
	389	tcg_temp_free(addr); \
	390	} while (0)
	391
dedc5eae	392	case 8: /L32I.Nn/
67882fd1	393	gen_narrow_load_store(ld32u);
dedc5eae MF	394	break;
	395
	396	case 9: /S32I.Nn/
67882fd1	397	gen_narrow_load_store(st32);
dedc5eae	398	break;
67882fd1	399	#undef gen_narrow_load_store
dedc5eae MF	400
dedc5eae MF	401	case 10: /ADD.Nn/
67882fd1	402	tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
dedc5eae MF	403	break;
	404
	405	case 11: /ADDI.Nn/
67882fd1	406	tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
dedc5eae MF	407	break;
	408
	409	case 12: /ST2n/
67882fd1 MF	410	if (RRRN_T < 8) { /MOVI.Nn/
	411	tcg_gen_movi_i32(cpu_R[RRRN_S],
	412	RRRN_R \| (RRRN_T << 4) \|
	413	((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
	414	} else { /BEQZ.Nn/ /BNEZ.Nn/
	415	}
dedc5eae MF	416	break;
	417
	418	case 13: /ST3n/
67882fd1 MF	419	switch (RRRN_R) {
	420	case 0: /MOV.Nn/
	421	tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
	422	break;
	423
	424	case 15: /S3/
	425	switch (RRRN_T) {
	426	case 0: /RET.Nn/
	427	gen_jump(dc, cpu_R[0]);
	428	break;
	429
	430	case 1: /RETW.Nn/
	431	break;
	432
	433	case 2: /BREAK.Nn/
	434	break;
	435
	436	case 3: /NOP.Nn/
	437	break;
	438
	439	case 6: /ILL.Nn/
	440	break;
	441
	442	default: /reserved/
	443	break;
	444	}
	445	break;
	446
	447	default: /reserved/
	448	break;
	449	}
dedc5eae MF	450	break;
	451
	452	default: /reserved/
	453	break;
	454	}
	455
	456	dc->pc = dc->next_pc;
	457	return;
	458
	459	invalid_opcode:
	460	qemu_log("INVALID(pc = %08x)\n", dc->pc);
	461	dc->pc = dc->next_pc;
	462	#undef HAS_OPTION
	463	}
	464
	465	static void check_breakpoint(CPUState env, DisasContext dc)
	466	{
	467	CPUBreakpoint *bp;
	468
	469	if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
	470	QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
	471	if (bp->pc == dc->pc) {
	472	tcg_gen_movi_i32(cpu_pc, dc->pc);
	473	gen_exception(EXCP_DEBUG);
	474	dc->is_jmp = DISAS_UPDATE;
	475	}
	476	}
	477	}
	478	}
	479
	480	static void gen_intermediate_code_internal(
	481	CPUState env, TranslationBlock tb, int search_pc)
	482	{
	483	DisasContext dc;
	484	int insn_count = 0;
	485	int j, lj = -1;
	486	uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
	487	int max_insns = tb->cflags & CF_COUNT_MASK;
	488	uint32_t pc_start = tb->pc;
	489	uint32_t next_page_start =
	490	(pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
	491
	492	if (max_insns == 0) {
	493	max_insns = CF_COUNT_MASK;
	494	}
	495
	496	dc.config = env->config;
	497	dc.singlestep_enabled = env->singlestep_enabled;
	498	dc.tb = tb;
	499	dc.pc = pc_start;
	500	dc.is_jmp = DISAS_NEXT;
	501
	502	gen_icount_start();
	503
	504	do {
	505	check_breakpoint(env, &dc);
	506
	507	if (search_pc) {
	508	j = gen_opc_ptr - gen_opc_buf;
	509	if (lj < j) {
	510	lj++;
	511	while (lj < j) {
	512	gen_opc_instr_start[lj++] = 0;
	513	}
514	}
515	gen_opc_pc[lj] = dc.pc;
516	gen_opc_instr_start[lj] = 1;
517	gen_opc_icount[lj] = insn_count;
518	}
519
520	if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
521	tcg_gen_debug_insn_start(dc.pc);
522	}
523
524	disas_xtensa_insn(&dc);
525	++insn_count;
526	if (env->singlestep_enabled) {
527	tcg_gen_movi_i32(cpu_pc, dc.pc);
528	gen_exception(EXCP_DEBUG);
529	break;
530	}
531	} while (dc.is_jmp == DISAS_NEXT &&
532	insn_count < max_insns &&
533	dc.pc < next_page_start &&
534	gen_opc_ptr < gen_opc_end);
535
536	if (dc.is_jmp == DISAS_NEXT) {
537	gen_jumpi(&dc, dc.pc, 0);
538	}
539	gen_icount_end(tb, insn_count);
540	*gen_opc_ptr = INDEX_op_end;
541
542	if (!search_pc) {
543	tb->size = dc.pc - pc_start;
544	tb->icount = insn_count;
545	}
2328826b MF	546	}
	547
	548	void gen_intermediate_code(CPUState env, TranslationBlock tb)
	549	{
dedc5eae	550	gen_intermediate_code_internal(env, tb, 0);
2328826b MF	551	}
	552
	553	void gen_intermediate_code_pc(CPUState env, TranslationBlock tb)
	554	{
dedc5eae	555	gen_intermediate_code_internal(env, tb, 1);
2328826b MF	556	}
	557
	558	void cpu_dump_state(CPUState env, FILE f, fprintf_function cpu_fprintf,
	559	int flags)
	560	{
	561	int i;
	562
	563	cpu_fprintf(f, "PC=%08x\n", env->pc);
	564
	565	for (i = 0; i < 16; ++i) {
	566	cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
	567	(i % 4) == 3 ? '\n' : ' ');
	568	}
	569	}
	570
	571	void restore_state_to_opc(CPUState env, TranslationBlock tb, int pc_pos)
	572	{
	573	env->pc = gen_opc_pc[pc_pos];
	574	}