[qemu.git] / hw / pci-host / uninorth.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"

#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
#define U3_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)

typedef struct UNINState {
    PCIHostState parent_obj;

    MemoryRegion pci_mmio;
    MemoryRegion pci_hole;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return (irq_num + (pci_dev->devfn >> 3)) & 3;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ctz32(reg & 0xfffff800);
        if (slot == 32) {
            slot = -1; /* XXX: should this be 0? */
        }
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    UNIN_DPRINTF("write addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
                 addr, len, val);
    pci_data_write(phb->bus,
                   unin_get_config_reg(phb->config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, hwaddr addr,
                               unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    uint32_t val;

    val = pci_data_read(phb->bus,
                        unin_get_config_reg(phb->config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
                 addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}


static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth U3 AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth internal bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(s);
    d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x10000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

#if 0
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(h->bus, PCI_DEVFN(14, 0),
                      "uni-north-internal-pci");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return h->bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(dev);
    d = U3_AGP_HOST_BRIDGE(dev);

    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(h->bus, 11 << 3, "u3-agp");

    return h->bus;
}

static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    /*
     * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
     * memory space with base 0x80000000, size 0x10000000 for Apple's
     * AppleMacRiscPCI driver
     */
    d->config[0x48] = 0x0;
    d->config[0x49] = 0x0;
    d->config[0x4a] = 0x0;
    d->config[0x4b] = 0x1;
}

static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
}

static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_main_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_main_pci_host_info = {
    .name = "uni-north-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_main_pci_host_class_init,
};

static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = u3_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo u3_agp_pci_host_info = {
    .name = "u3-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = u3_agp_pci_host_class_init,
};

static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_agp_pci_host_info = {
    .name = "uni-north-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_agp_pci_host_class_init,
};

static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_internal_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_internal_pci_host_info = {
    .name = "uni-north-internal-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_internal_pci_host_class_init,
};

static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_main_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_main_info = {
    .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_main_class_init,
};

static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_u3_agp_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_u3_agp_info = {
    .name          = TYPE_U3_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_u3_agp_class_init,
};

static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_agp_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_agp_info = {
    .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_agp_class_init,
};

static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_internal_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_internal_info = {
    .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_internal_class_init,
};

static void unin_register_types(void)
{
    type_register_static(&unin_main_pci_host_info);
    type_register_static(&u3_agp_pci_host_info);
    type_register_static(&unin_agp_pci_host_info);
    type_register_static(&unin_internal_pci_host_info);

    type_register_static(&pci_unin_main_info);
    type_register_static(&pci_u3_agp_info);
    type_register_static(&pci_unin_agp_info);
    type_register_static(&pci_unin_internal_info);
}

type_init(unin_register_types)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0d75590d	24	#include "qemu/osdep.h"
83c9f4ca PB	25	#include "hw/hw.h"
	26	#include "hw/ppc/mac.h"
	27	#include "hw/pci/pci.h"
	28	#include "hw/pci/pci_host.h"
87ecb68b	29
f3902383 BS	30	/* debug UniNorth */
	31	//#define DEBUG_UNIN
	32
	33	#ifdef DEBUG_UNIN
001faf32 BS	34	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	35	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	36	#else
001faf32	37	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	38	#endif
f3902383 BS	39
fa0be69a AG	40	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	41
57fd7b7f AF	42	#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
	43	#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
	44	#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
	45	#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
	46
	47	#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
	48	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
	49	#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
	50	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
	51	#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
	52	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
	53	#define U3_AGP_HOST_BRIDGE(obj) \
	54	OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
	55
2e29bd04	56	typedef struct UNINState {
67c332fd	57	PCIHostState parent_obj;
57fd7b7f	58
46f3069c BS	59	MemoryRegion pci_mmio;
46f3069c BS	60	MemoryRegion pci_hole;
2e29bd04	61	} UNINState;
502a5395	62
d2b59317	63	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	64	{
39d97e14	65	return (irq_num + (pci_dev->devfn >> 3)) & 3;
d2b59317 PB	66	}
d2b59317 PB	67
5d4e84c8	68	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	69	{
5d4e84c8 JQ	70	qemu_irq *pic = opaque;
5d4e84c8 JQ	71
fa0be69a AG	72	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	73	unin_irq_line[irq_num], level);
	74	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	75	}
502a5395 PB	76
d86f0e32 AG	77	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	78	{
	79	uint32_t retval;
	80
	81	if (reg & (1u << 31)) {
	82	/* XXX OpenBIOS compatibility hack */
	83	retval = reg \| (addr & 3);
	84	} else if (reg & 1) {
	85	/* CFA1 style */
	86	retval = (reg & ~7u) \| (addr & 7);
	87	} else {
	88	uint32_t slot, func;
	89
	90	/* Grab CFA0 style values */
5863d374 SH	91	slot = ctz32(reg & 0xfffff800);
	92	if (slot == 32) {
	93	slot = -1; /* XXX: should this be 0? */
	94	}
d86f0e32 AG	95	func = (reg >> 8) & 7;
	96
	97	/* ... and then convert them to x86 format */
	98	/* config pointer */
	99	retval = (reg & (0xff - 7)) \| (addr & 7);
	100	/* slot */
	101	retval \|= slot << 11;
	102	/* fn */
	103	retval \|= func << 8;
	104	}
	105
	106
	107	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	108	reg, addr, retval);
	109
	110	return retval;
	111	}
	112
a8170e5e	113	static void unin_data_write(void *opaque, hwaddr addr,
d0ed8076	114	uint64_t val, unsigned len)
d86f0e32	115	{
d0ed8076	116	UNINState *s = opaque;
67c332fd	117	PCIHostState *phb = PCI_HOST_BRIDGE(s);
2f448e41	118	UNIN_DPRINTF("write addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
d0ed8076	119	addr, len, val);
67c332fd AF	120	pci_data_write(phb->bus,
67c332fd AF	121	unin_get_config_reg(phb->config_reg, addr),
d86f0e32 AG	122	val, len);
	123	}
	124
a8170e5e	125	static uint64_t unin_data_read(void *opaque, hwaddr addr,
d0ed8076	126	unsigned len)
d86f0e32	127	{
d0ed8076	128	UNINState *s = opaque;
67c332fd	129	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d86f0e32 AG	130	uint32_t val;
d86f0e32 AG	131
67c332fd AF	132	val = pci_data_read(phb->bus,
67c332fd AF	133	unin_get_config_reg(phb->config_reg, addr),
d86f0e32	134	len);
2f448e41	135	UNIN_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
d0ed8076	136	addr, len, val);
d86f0e32 AG	137	return val;
	138	}
	139
d0ed8076 AK	140	static const MemoryRegionOps unin_data_ops = {
	141	.read = unin_data_read,
	142	.write = unin_data_write,
	143	.endianness = DEVICE_LITTLE_ENDIAN,
	144	};
	145
81a322d4	146	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395	147	{
ff452ace	148	PCIHostState *h;
502a5395 PB	149
	150	/* Use values found on a real PowerMac */
	151	/* Uninorth main bus */
8558d942	152	h = PCI_HOST_BRIDGE(dev);
502a5395	153
40c5dce9	154	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	155	dev, "pci-conf-idx", 0x1000);
40c5dce9	156	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	157	"pci-conf-data", 0x1000);
57fd7b7f AF	158	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	159	sysbus_init_mmio(dev, &h->data_mem);
2e29bd04	160
81a322d4	161	return 0;
2e29bd04 BS	162	}
2e29bd04 BS	163
d0ed8076	164
0f921197 AG	165	static int pci_u3_agp_init_device(SysBusDevice *dev)
0f921197 AG	166	{
ff452ace	167	PCIHostState *h;
0f921197 AG	168
0f921197 AG	169	/* Uninorth U3 AGP bus */
8558d942	170	h = PCI_HOST_BRIDGE(dev);
0f921197	171
40c5dce9	172	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	173	dev, "pci-conf-idx", 0x1000);
40c5dce9	174	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	175	"pci-conf-data", 0x1000);
57fd7b7f AF	176	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	177	sysbus_init_mmio(dev, &h->data_mem);
0f921197	178
0f921197 AG	179	return 0;
	180	}
	181
81a322d4	182	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04	183	{
ff452ace	184	PCIHostState *h;
2e29bd04 BS	185
2e29bd04 BS	186	/* Uninorth AGP bus */
8558d942	187	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	188
40c5dce9	189	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	190	dev, "pci-conf-idx", 0x1000);
40c5dce9	191	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	192	dev, "pci-conf-data", 0x1000);
	193	sysbus_init_mmio(dev, &h->conf_mem);
	194	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	195	return 0;
2e29bd04 BS	196	}
2e29bd04 BS	197
81a322d4	198	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04	199	{
ff452ace	200	PCIHostState *h;
2e29bd04 BS	201
2e29bd04 BS	202	/* Uninorth internal bus */
8558d942	203	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	204
40c5dce9	205	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	206	dev, "pci-conf-idx", 0x1000);
40c5dce9	207	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	208	dev, "pci-conf-data", 0x1000);
	209	sysbus_init_mmio(dev, &h->conf_mem);
	210	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	211	return 0;
2e29bd04 BS	212	}
2e29bd04 BS	213
aee97b84 AK	214	PCIBus pci_pmac_init(qemu_irq pic,
	215	MemoryRegion *address_space_mem,
	216	MemoryRegion *address_space_io)
2e29bd04 BS	217	{
	218	DeviceState *dev;
	219	SysBusDevice *s;
ff452ace	220	PCIHostState *h;
2e29bd04 BS	221	UNINState *d;
	222
	223	/* Use values found on a real PowerMac */
	224	/* Uninorth main bus */
57fd7b7f	225	dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
e23a1b33	226	qdev_init_nofail(dev);
57fd7b7f	227	s = SYS_BUS_DEVICE(dev);
8558d942	228	h = PCI_HOST_BRIDGE(s);
57fd7b7f	229	d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
40c5dce9 PB	230	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	231	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
1be88255	232	0x80000000ULL, 0x10000000ULL);
46f3069c BS	233	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	234	&d->pci_hole);
	235
8a0e1104	236	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	237	pci_unin_set_irq, pci_unin_map_irq,
	238	pic,
	239	&d->pci_mmio,
	240	address_space_io,
60a0e443	241	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
2e29bd04	242
60398748	243	#if 0
57fd7b7f	244	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
60398748	245	#endif
2e29bd04 BS	246
	247	sysbus_mmio_map(s, 0, 0xf2800000);
	248	sysbus_mmio_map(s, 1, 0xf2c00000);
	249
	250	/* DEC 21154 bridge */
	251	#if 0
	252	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
57fd7b7f	253	pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	254	#endif
	255
	256	/* Uninorth AGP bus */
57fd7b7f AF	257	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
57fd7b7f AF	258	dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
d27d06f2	259	qdev_init_nofail(dev);
57fd7b7f	260	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	261	sysbus_mmio_map(s, 0, 0xf0800000);
d27d06f2 BS	262	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	263
	264	/* Uninorth internal bus */
	265	#if 0
	266	/* XXX: not needed for now */
57fd7b7f	267	pci_create_simple(h->bus, PCI_DEVFN(14, 0),
70f9c987	268	"uni-north-internal-pci");
57fd7b7f	269	dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
d27d06f2	270	qdev_init_nofail(dev);
57fd7b7f	271	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	272	sysbus_mmio_map(s, 0, 0xf4800000);
d27d06f2 BS	273	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	274	#endif
2e29bd04 BS	275
57fd7b7f	276	return h->bus;
2e29bd04 BS	277	}
2e29bd04 BS	278
aee97b84 AK	279	PCIBus pci_pmac_u3_init(qemu_irq pic,
	280	MemoryRegion *address_space_mem,
	281	MemoryRegion *address_space_io)
0f921197 AG	282	{
	283	DeviceState *dev;
	284	SysBusDevice *s;
ff452ace	285	PCIHostState *h;
0f921197 AG	286	UNINState *d;
	287
	288	/* Uninorth AGP bus */
	289
57fd7b7f	290	dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
0f921197	291	qdev_init_nofail(dev);
57fd7b7f	292	s = SYS_BUS_DEVICE(dev);
8558d942	293	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	294	d = U3_AGP_HOST_BRIDGE(dev);
0f921197	295
40c5dce9 PB	296	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	297	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
46f3069c BS	298	0x80000000ULL, 0x70000000ULL);
	299	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	300	&d->pci_hole);
	301
8a0e1104	302	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	303	pci_unin_set_irq, pci_unin_map_irq,
	304	pic,
	305	&d->pci_mmio,
	306	address_space_io,
60a0e443	307	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
0f921197 AG	308
	309	sysbus_mmio_map(s, 0, 0xf0800000);
	310	sysbus_mmio_map(s, 1, 0xf0c00000);
	311
57fd7b7f	312	pci_create_simple(h->bus, 11 << 3, "u3-agp");
0f921197	313
57fd7b7f	314	return h->bus;
0f921197 AG	315	}
0f921197 AG	316
9af21dbe	317	static void unin_main_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	318	{
502a5395 PB	319	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	320	d->config[0x0D] = 0x10; // latency_timer
502a5395	321	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04	322	}
502a5395	323
9af21dbe	324	static void unin_agp_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	325	{
502a5395 PB	326	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	327	d->config[0x0D] = 0x10; // latency_timer
502a5395	328	// d->config[0x34] = 0x80; // capabilities_pointer
98ae3b27 JA	329	/*
	330	* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
	331	* memory space with base 0x80000000, size 0x10000000 for Apple's
	332	* AppleMacRiscPCI driver
	333	*/
	334	d->config[0x48] = 0x0;
	335	d->config[0x49] = 0x0;
	336	d->config[0x4a] = 0x0;
	337	d->config[0x4b] = 0x1;
2e29bd04	338	}
502a5395	339
9af21dbe	340	static void u3_agp_pci_host_realize(PCIDevice d, Error *errp)
0f921197	341	{
0f921197 AG	342	/* cache line size */
	343	d->config[0x0C] = 0x08;
	344	/* latency timer */
	345	d->config[0x0D] = 0x10;
0f921197 AG	346	}
0f921197 AG	347
9af21dbe	348	static void unin_internal_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	349	{
502a5395 PB	350	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	351	d->config[0x0D] = 0x10; // latency_timer
502a5395	352	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04 BS	353	}
2e29bd04 BS	354
40021f08 AL	355	static void unin_main_pci_host_class_init(ObjectClass klass, void data)
	356	{
	357	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	358	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	359
9af21dbe	360	k->realize = unin_main_pci_host_realize;
40021f08 AL	361	k->vendor_id = PCI_VENDOR_ID_APPLE;
	362	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
	363	k->revision = 0x00;
	364	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	365	/*
	366	* PCI-facing part of the host bridge, not usable without the
	367	* host-facing part, which can't be device_add'ed, yet.
	368	*/
	369	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	370	}
40021f08 AL	371
4240abff	372	static const TypeInfo unin_main_pci_host_info = {
40021f08	373	.name = "uni-north-pci",
39bffca2 AL	374	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	375	.instance_size = sizeof(PCIDevice),
40021f08	376	.class_init = unin_main_pci_host_class_init,
2e29bd04 BS	377	};
2e29bd04 BS	378
40021f08 AL	379	static void u3_agp_pci_host_class_init(ObjectClass klass, void data)
	380	{
	381	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	382	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	383
9af21dbe	384	k->realize = u3_agp_pci_host_realize;
40021f08 AL	385	k->vendor_id = PCI_VENDOR_ID_APPLE;
	386	k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
	387	k->revision = 0x00;
	388	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	389	/*
	390	* PCI-facing part of the host bridge, not usable without the
	391	* host-facing part, which can't be device_add'ed, yet.
	392	*/
	393	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	394	}
40021f08 AL	395
4240abff	396	static const TypeInfo u3_agp_pci_host_info = {
40021f08	397	.name = "u3-agp",
39bffca2 AL	398	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	399	.instance_size = sizeof(PCIDevice),
40021f08	400	.class_init = u3_agp_pci_host_class_init,
0f921197 AG	401	};
0f921197 AG	402
40021f08 AL	403	static void unin_agp_pci_host_class_init(ObjectClass klass, void data)
	404	{
	405	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	406	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	407
9af21dbe	408	k->realize = unin_agp_pci_host_realize;
40021f08 AL	409	k->vendor_id = PCI_VENDOR_ID_APPLE;
	410	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
	411	k->revision = 0x00;
	412	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	413	/*
	414	* PCI-facing part of the host bridge, not usable without the
	415	* host-facing part, which can't be device_add'ed, yet.
	416	*/
	417	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	418	}
40021f08 AL	419
4240abff	420	static const TypeInfo unin_agp_pci_host_info = {
40021f08	421	.name = "uni-north-agp",
39bffca2 AL	422	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	423	.instance_size = sizeof(PCIDevice),
40021f08	424	.class_init = unin_agp_pci_host_class_init,
2e29bd04 BS	425	};
2e29bd04 BS	426
40021f08 AL	427	static void unin_internal_pci_host_class_init(ObjectClass klass, void data)
	428	{
	429	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	430	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	431
9af21dbe	432	k->realize = unin_internal_pci_host_realize;
40021f08 AL	433	k->vendor_id = PCI_VENDOR_ID_APPLE;
	434	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
	435	k->revision = 0x00;
	436	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	437	/*
	438	* PCI-facing part of the host bridge, not usable without the
	439	* host-facing part, which can't be device_add'ed, yet.
	440	*/
	441	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	442	}
40021f08 AL	443
4240abff	444	static const TypeInfo unin_internal_pci_host_info = {
40021f08	445	.name = "uni-north-internal-pci",
39bffca2 AL	446	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	447	.instance_size = sizeof(PCIDevice),
40021f08	448	.class_init = unin_internal_pci_host_class_init,
2e29bd04 BS	449	};
2e29bd04 BS	450
999e12bb AL	451	static void pci_unin_main_class_init(ObjectClass klass, void data)
	452	{
	453	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	454	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	455
999e12bb AL	456	sbc->init = pci_unin_main_init_device;
1d16f86a	457	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	458	}
999e12bb AL	459
4240abff	460	static const TypeInfo pci_unin_main_info = {
57fd7b7f	461	.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
8558d942	462	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	463	.instance_size = sizeof(UNINState),
39bffca2 AL	464	.class_init = pci_unin_main_class_init,
70f9c987 AF	465	};
70f9c987 AF	466
999e12bb AL	467	static void pci_u3_agp_class_init(ObjectClass klass, void data)
	468	{
	469	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	470	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	471
999e12bb AL	472	sbc->init = pci_u3_agp_init_device;
1d16f86a	473	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	474	}
999e12bb AL	475
4240abff	476	static const TypeInfo pci_u3_agp_info = {
57fd7b7f	477	.name = TYPE_U3_AGP_HOST_BRIDGE,
8558d942	478	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	479	.instance_size = sizeof(UNINState),
39bffca2 AL	480	.class_init = pci_u3_agp_class_init,
70f9c987 AF	481	};
70f9c987 AF	482
999e12bb AL	483	static void pci_unin_agp_class_init(ObjectClass klass, void data)
	484	{
	485	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	486	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	487
999e12bb AL	488	sbc->init = pci_unin_agp_init_device;
1d16f86a	489	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	490	}
999e12bb AL	491
4240abff	492	static const TypeInfo pci_unin_agp_info = {
57fd7b7f	493	.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
8558d942	494	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	495	.instance_size = sizeof(UNINState),
39bffca2 AL	496	.class_init = pci_unin_agp_class_init,
70f9c987 AF	497	};
70f9c987 AF	498
999e12bb AL	499	static void pci_unin_internal_class_init(ObjectClass klass, void data)
	500	{
	501	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	502	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	503
999e12bb AL	504	sbc->init = pci_unin_internal_init_device;
1d16f86a	505	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	506	}
999e12bb AL	507
4240abff	508	static const TypeInfo pci_unin_internal_info = {
57fd7b7f	509	.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
8558d942	510	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	511	.instance_size = sizeof(UNINState),
39bffca2 AL	512	.class_init = pci_unin_internal_class_init,
70f9c987 AF	513	};
70f9c987 AF	514
83f7d43a	515	static void unin_register_types(void)
2e29bd04	516	{
39bffca2 AL	517	type_register_static(&unin_main_pci_host_info);
	518	type_register_static(&u3_agp_pci_host_info);
	519	type_register_static(&unin_agp_pci_host_info);
	520	type_register_static(&unin_internal_pci_host_info);
	521
	522	type_register_static(&pci_unin_main_info);
	523	type_register_static(&pci_u3_agp_info);
	524	type_register_static(&pci_unin_agp_info);
	525	type_register_static(&pci_unin_internal_info);
502a5395	526	}
2e29bd04	527
83f7d43a	528	type_init(unin_register_types)