[qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"
#include "pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

typedef struct UNINState {
    SysBusDevice busdev;
    PCIHostState host_state;
    MemoryRegion pci_mmio;
    MemoryRegion pci_hole;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static void pci_unin_reset(void *opaque)
{
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ffs(reg & 0xfffff800) - 1;
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
                 addr, len, val);
    pci_data_write(s->host_state.bus,
                   unin_get_config_reg(s->host_state.config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
                               unsigned len)
{
    UNINState *s = opaque;
    uint32_t val;

    val = pci_data_read(s->host_state.bus,
                        unin_get_config_reg(s->host_state.config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
                 addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    UNINState *s;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = FROM_SYSBUS(UNINState, dev);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);

    qemu_register_reset(pci_unin_reset, &s->host_state);
    return 0;
}


static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;

    /* Uninorth U3 AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);

    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;

    /* Uninorth AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
                          &s->host_state, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    UNINState *s;

    /* Uninorth internal bus */
    s = FROM_SYSBUS(UNINState, dev);

    memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
                          &s->host_state, "pci-conf-idx", 0x1000);
    memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
                          &s->host_state, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &s->host_state.conf_mem);
    sysbus_init_mmio(dev, &s->host_state.data_mem);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "uni-north");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);
    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic,
                                         &d->pci_mmio,
                                         address_space_io,
                                         PCI_DEVFN(11, 0), 4);

#if 0
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, "uni-north-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
    dev = qdev_create(NULL, "uni-north-pci");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return d->host_state.bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, "u3-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);

    memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic,
                                         &d->pci_mmio,
                                         address_space_io,
                                         PCI_DEVFN(11, 0), 4);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int u3_agp_pci_host_init(PCIDevice *d)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "uni-north",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo u3_agp_pci_host_info = {
    .qdev.name = "u3-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = u3_agp_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "uni-north-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static void unin_register_devices(void)
{
    sysbus_register_dev("uni-north", sizeof(UNINState),
                        pci_unin_main_init_device);
    pci_qdev_register(&unin_main_pci_host_info);
    sysbus_register_dev("u3-agp", sizeof(UNINState),
                        pci_u3_agp_init_device);
    pci_qdev_register(&u3_agp_pci_host_info);
    sysbus_register_dev("uni-north-agp", sizeof(UNINState),
                        pci_unin_agp_init_device);
    pci_qdev_register(&unin_agp_pci_host_info);
    sysbus_register_dev("uni-north-pci", sizeof(UNINState),
                        pci_unin_internal_init_device);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
4f5e19e6	27	#include "pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
2e29bd04 BS	41	typedef struct UNINState {
	42	SysBusDevice busdev;
	43	PCIHostState host_state;
46f3069c BS	44	MemoryRegion pci_mmio;
46f3069c BS	45	MemoryRegion pci_hole;
2e29bd04	46	} UNINState;
502a5395	47
d2b59317	48	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	49	{
fa0be69a AG	50	int retval;
	51	int devfn = pci_dev->devfn & 0x00FFFFFF;
	52
	53	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	54
	55	return retval;
d2b59317 PB	56	}
d2b59317 PB	57
5d4e84c8	58	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	59	{
5d4e84c8 JQ	60	qemu_irq *pic = opaque;
5d4e84c8 JQ	61
fa0be69a AG	62	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	63	unin_irq_line[irq_num], level);
	64	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	65	}
502a5395 PB	66
f3902383 BS	67	static void pci_unin_reset(void *opaque)
	68	{
	69	}
	70
d86f0e32 AG	71	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	72	{
	73	uint32_t retval;
	74
	75	if (reg & (1u << 31)) {
	76	/* XXX OpenBIOS compatibility hack */
	77	retval = reg \| (addr & 3);
	78	} else if (reg & 1) {
	79	/* CFA1 style */
	80	retval = (reg & ~7u) \| (addr & 7);
	81	} else {
	82	uint32_t slot, func;
	83
	84	/* Grab CFA0 style values */
	85	slot = ffs(reg & 0xfffff800) - 1;
	86	func = (reg >> 8) & 7;
	87
	88	/* ... and then convert them to x86 format */
	89	/* config pointer */
	90	retval = (reg & (0xff - 7)) \| (addr & 7);
	91	/* slot */
	92	retval \|= slot << 11;
	93	/* fn */
	94	retval \|= func << 8;
	95	}
	96
	97
	98	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	99	reg, addr, retval);
	100
	101	return retval;
	102	}
	103
d0ed8076 AK	104	static void unin_data_write(void *opaque, target_phys_addr_t addr,
d0ed8076 AK	105	uint64_t val, unsigned len)
d86f0e32	106	{
d0ed8076 AK	107	UNINState *s = opaque;
	108	UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
	109	addr, len, val);
d86f0e32 AG	110	pci_data_write(s->host_state.bus,
	111	unin_get_config_reg(s->host_state.config_reg, addr),
	112	val, len);
	113	}
	114
d0ed8076 AK	115	static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
d0ed8076 AK	116	unsigned len)
d86f0e32	117	{
d0ed8076	118	UNINState *s = opaque;
d86f0e32 AG	119	uint32_t val;
	120
	121	val = pci_data_read(s->host_state.bus,
	122	unin_get_config_reg(s->host_state.config_reg, addr),
	123	len);
d0ed8076 AK	124	UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
d0ed8076 AK	125	addr, len, val);
d86f0e32 AG	126	return val;
	127	}
	128
d0ed8076 AK	129	static const MemoryRegionOps unin_data_ops = {
	130	.read = unin_data_read,
	131	.write = unin_data_write,
	132	.endianness = DEVICE_LITTLE_ENDIAN,
	133	};
	134
81a322d4	135	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 PB	136	{
502a5395 PB	137	UNINState *s;
502a5395 PB	138
	139	/* Use values found on a real PowerMac */
	140	/* Uninorth main bus */
2e29bd04	141	s = FROM_SYSBUS(UNINState, dev);
502a5395	142
d0ed8076 AK	143	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	144	&s->host_state, "pci-conf-idx", 0x1000);
	145	memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
	146	"pci-conf-data", 0x1000);
750ecd44 AK	147	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	148	sysbus_init_mmio(dev, &s->host_state.data_mem);
2e29bd04	149
2e29bd04	150	qemu_register_reset(pci_unin_reset, &s->host_state);
81a322d4	151	return 0;
2e29bd04 BS	152	}
2e29bd04 BS	153
d0ed8076	154
0f921197 AG	155	static int pci_u3_agp_init_device(SysBusDevice *dev)
	156	{
	157	UNINState *s;
0f921197 AG	158
	159	/* Uninorth U3 AGP bus */
	160	s = FROM_SYSBUS(UNINState, dev);
	161
d0ed8076 AK	162	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	163	&s->host_state, "pci-conf-idx", 0x1000);
	164	memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
	165	"pci-conf-data", 0x1000);
750ecd44 AK	166	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	167	sysbus_init_mmio(dev, &s->host_state.data_mem);
0f921197	168
0f921197 AG	169	qemu_register_reset(pci_unin_reset, &s->host_state);
	170
	171	return 0;
	172	}
	173
81a322d4	174	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 BS	175	{
2e29bd04 BS	176	UNINState *s;
2e29bd04 BS	177
	178	/* Uninorth AGP bus */
	179	s = FROM_SYSBUS(UNINState, dev);
	180
d0ed8076 AK	181	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	182	&s->host_state, "pci-conf-idx", 0x1000);
	183	memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
	184	&s->host_state, "pci-conf-data", 0x1000);
750ecd44 AK	185	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	186	sysbus_init_mmio(dev, &s->host_state.data_mem);
81a322d4	187	return 0;
2e29bd04 BS	188	}
2e29bd04 BS	189
81a322d4	190	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 BS	191	{
2e29bd04 BS	192	UNINState *s;
2e29bd04 BS	193
	194	/* Uninorth internal bus */
	195	s = FROM_SYSBUS(UNINState, dev);
	196
d0ed8076 AK	197	memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
	198	&s->host_state, "pci-conf-idx", 0x1000);
	199	memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
	200	&s->host_state, "pci-conf-data", 0x1000);
750ecd44 AK	201	sysbus_init_mmio(dev, &s->host_state.conf_mem);
750ecd44 AK	202	sysbus_init_mmio(dev, &s->host_state.data_mem);
81a322d4	203	return 0;
2e29bd04 BS	204	}
2e29bd04 BS	205
aee97b84 AK	206	PCIBus pci_pmac_init(qemu_irq pic,
	207	MemoryRegion *address_space_mem,
	208	MemoryRegion *address_space_io)
2e29bd04 BS	209	{
	210	DeviceState *dev;
	211	SysBusDevice *s;
	212	UNINState *d;
	213
	214	/* Use values found on a real PowerMac */
	215	/* Uninorth main bus */
18dd19a7	216	dev = qdev_create(NULL, "uni-north");
e23a1b33	217	qdev_init_nofail(dev);
2e29bd04 BS	218	s = sysbus_from_qdev(dev);
2e29bd04 BS	219	d = FROM_SYSBUS(UNINState, s);
46f3069c BS	220	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	221	memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
	222	0x80000000ULL, 0x70000000ULL);
	223	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	224	&d->pci_hole);
	225
cdd0935c	226	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
2e29bd04	227	pci_unin_set_irq, pci_unin_map_irq,
aee97b84	228	pic,
46f3069c	229	&d->pci_mmio,
aee97b84	230	address_space_io,
1e39101c	231	PCI_DEVFN(11, 0), 4);
2e29bd04	232
60398748	233	#if 0
520128bd	234	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
60398748	235	#endif
2e29bd04 BS	236
	237	sysbus_mmio_map(s, 0, 0xf2800000);
	238	sysbus_mmio_map(s, 1, 0xf2c00000);
	239
	240	/* DEC 21154 bridge */
	241	#if 0
	242	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
520128bd	243	pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	244	#endif
	245
	246	/* Uninorth AGP bus */
520128bd	247	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
18dd19a7	248	dev = qdev_create(NULL, "uni-north-agp");
d27d06f2 BS	249	qdev_init_nofail(dev);
	250	s = sysbus_from_qdev(dev);
	251	sysbus_mmio_map(s, 0, 0xf0800000);
	252	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	253
	254	/* Uninorth internal bus */
	255	#if 0
	256	/* XXX: not needed for now */
520128bd	257	pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
18dd19a7	258	dev = qdev_create(NULL, "uni-north-pci");
d27d06f2 BS	259	qdev_init_nofail(dev);
	260	s = sysbus_from_qdev(dev);
	261	sysbus_mmio_map(s, 0, 0xf4800000);
	262	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	263	#endif
	264
	265	return d->host_state.bus;
	266	}
	267
aee97b84 AK	268	PCIBus pci_pmac_u3_init(qemu_irq pic,
	269	MemoryRegion *address_space_mem,
	270	MemoryRegion *address_space_io)
0f921197 AG	271	{
	272	DeviceState *dev;
	273	SysBusDevice *s;
	274	UNINState *d;
	275
	276	/* Uninorth AGP bus */
	277
	278	dev = qdev_create(NULL, "u3-agp");
	279	qdev_init_nofail(dev);
	280	s = sysbus_from_qdev(dev);
	281	d = FROM_SYSBUS(UNINState, s);
	282
46f3069c BS	283	memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
	284	memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
	285	0x80000000ULL, 0x70000000ULL);
	286	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	287	&d->pci_hole);
	288
0f921197 AG	289	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
0f921197 AG	290	pci_unin_set_irq, pci_unin_map_irq,
aee97b84	291	pic,
46f3069c	292	&d->pci_mmio,
aee97b84	293	address_space_io,
1e39101c	294	PCI_DEVFN(11, 0), 4);
0f921197 AG	295
	296	sysbus_mmio_map(s, 0, 0xf0800000);
	297	sysbus_mmio_map(s, 1, 0xf0c00000);
	298
	299	pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
	300
	301	return d->host_state.bus;
	302	}
	303
81a322d4	304	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	305	{
502a5395 PB	306	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	307	d->config[0x0D] = 0x10; // latency_timer
502a5395	308	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	309	return 0;
2e29bd04	310	}
502a5395	311
81a322d4	312	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	313	{
502a5395 PB	314	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	315	d->config[0x0D] = 0x10; // latency_timer
502a5395	316	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	317	return 0;
2e29bd04	318	}
502a5395	319
0f921197 AG	320	static int u3_agp_pci_host_init(PCIDevice *d)
0f921197 AG	321	{
0f921197 AG	322	/* cache line size */
	323	d->config[0x0C] = 0x08;
	324	/* latency timer */
	325	d->config[0x0D] = 0x10;
0f921197 AG	326	return 0;
	327	}
	328
81a322d4	329	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	330	{
502a5395 PB	331	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	332	d->config[0x0D] = 0x10; // latency_timer
502a5395	333	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	334	return 0;
2e29bd04 BS	335	}
	336
	337	static PCIDeviceInfo unin_main_pci_host_info = {
18dd19a7	338	.qdev.name = "uni-north",
2e29bd04 BS	339	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	340	.init = unin_main_pci_host_init,
d7b61ecc IY	341	.vendor_id = PCI_VENDOR_ID_APPLE,
	342	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
	343	.revision = 0x00,
	344	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	345	};
2e29bd04 BS	346
0f921197 AG	347	static PCIDeviceInfo u3_agp_pci_host_info = {
	348	.qdev.name = "u3-agp",
	349	.qdev.size = sizeof(PCIDevice),
	350	.init = u3_agp_pci_host_init,
d7b61ecc IY	351	.vendor_id = PCI_VENDOR_ID_APPLE,
	352	.device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
	353	.revision = 0x00,
	354	.class_id = PCI_CLASS_BRIDGE_HOST,
0f921197 AG	355	};
0f921197 AG	356
2e29bd04	357	static PCIDeviceInfo unin_agp_pci_host_info = {
18dd19a7	358	.qdev.name = "uni-north-agp",
2e29bd04 BS	359	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	360	.init = unin_agp_pci_host_init,
d7b61ecc IY	361	.vendor_id = PCI_VENDOR_ID_APPLE,
	362	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
	363	.revision = 0x00,
	364	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	365	};
	366
	367	static PCIDeviceInfo unin_internal_pci_host_info = {
18dd19a7	368	.qdev.name = "uni-north-pci",
2e29bd04 BS	369	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	370	.init = unin_internal_pci_host_init,
d7b61ecc IY	371	.vendor_id = PCI_VENDOR_ID_APPLE,
	372	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
	373	.revision = 0x00,
	374	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	375	};
	376
	377	static void unin_register_devices(void)
	378	{
18dd19a7	379	sysbus_register_dev("uni-north", sizeof(UNINState),
2e29bd04 BS	380	pci_unin_main_init_device);
2e29bd04 BS	381	pci_qdev_register(&unin_main_pci_host_info);
0f921197 AG	382	sysbus_register_dev("u3-agp", sizeof(UNINState),
	383	pci_u3_agp_init_device);
	384	pci_qdev_register(&u3_agp_pci_host_info);
18dd19a7	385	sysbus_register_dev("uni-north-agp", sizeof(UNINState),
2e29bd04 BS	386	pci_unin_agp_init_device);
2e29bd04 BS	387	pci_qdev_register(&unin_agp_pci_host_info);
18dd19a7	388	sysbus_register_dev("uni-north-pci", sizeof(UNINState),
2e29bd04 BS	389	pci_unin_internal_init_device);
2e29bd04 BS	390	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	391	}
2e29bd04 BS	392
2e29bd04 BS	393	device_init(unin_register_devices)