[qemu.git] / hw / pci-host / uninorth.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"

#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
#define U3_AGP_HOST_BRIDGE(obj) \
    OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)

typedef struct UNINState {
    PCIHostState parent_obj;

    MemoryRegion pci_mmio;
    MemoryRegion pci_hole;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ctz32(reg & 0xfffff800);
        if (slot == 32) {
            slot = -1; /* XXX: should this be 0? */
        }
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
                 addr, len, val);
    pci_data_write(phb->bus,
                   unin_get_config_reg(phb->config_reg, addr),
                   val, len);
}

static uint64_t unin_data_read(void *opaque, hwaddr addr,
                               unsigned len)
{
    UNINState *s = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(s);
    uint32_t val;

    val = pci_data_read(phb->bus,
                        unin_get_config_reg(phb->config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
                 addr, len, val);
    return val;
}

static const MemoryRegionOps unin_data_ops = {
    .read = unin_data_read,
    .write = unin_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}


static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth U3 AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
                          "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth AGP bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    PCIHostState *h;

    /* Uninorth internal bus */
    h = PCI_HOST_BRIDGE(dev);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
                          dev, "pci-conf-idx", 0x1000);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
                          dev, "pci-conf-data", 0x1000);
    sysbus_init_mmio(dev, &h->conf_mem);
    sysbus_init_mmio(dev, &h->data_mem);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(s);
    d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x10000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

#if 0
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(h->bus, PCI_DEVFN(14, 0),
                      "uni-north-internal-pci");
    dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return h->bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    PCIHostState *h;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    h = PCI_HOST_BRIDGE(dev);
    d = U3_AGP_HOST_BRIDGE(dev);

    memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
    memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
                             0x80000000ULL, 0x70000000ULL);
    memory_region_add_subregion(address_space_mem, 0x80000000ULL,
                                &d->pci_hole);

    h->bus = pci_register_bus(dev, NULL,
                              pci_unin_set_irq, pci_unin_map_irq,
                              pic,
                              &d->pci_mmio,
                              address_space_io,
                              PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(h->bus, 11 << 3, "u3-agp");

    return h->bus;
}

static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
}

static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
}

static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
}

static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_main_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_main_pci_host_info = {
    .name = "uni-north-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_main_pci_host_class_init,
};

static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = u3_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo u3_agp_pci_host_info = {
    .name = "u3-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = u3_agp_pci_host_class_init,
};

static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_agp_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_agp_pci_host_info = {
    .name = "uni-north-agp",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_agp_pci_host_class_init,
};

static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize   = unin_internal_pci_host_realize;
    k->vendor_id = PCI_VENDOR_ID_APPLE;
    k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
    k->revision  = 0x00;
    k->class_id  = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo unin_internal_pci_host_info = {
    .name = "uni-north-internal-pci",
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init = unin_internal_pci_host_class_init,
};

static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_main_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_main_info = {
    .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_main_class_init,
};

static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_u3_agp_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_u3_agp_info = {
    .name          = TYPE_U3_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_u3_agp_class_init,
};

static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_agp_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_agp_info = {
    .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_agp_class_init,
};

static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = pci_unin_internal_init_device;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

static const TypeInfo pci_unin_internal_info = {
    .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(UNINState),
    .class_init    = pci_unin_internal_class_init,
};

static void unin_register_types(void)
{
    type_register_static(&unin_main_pci_host_info);
    type_register_static(&u3_agp_pci_host_info);
    type_register_static(&unin_agp_pci_host_info);
    type_register_static(&unin_internal_pci_host_info);

    type_register_static(&pci_unin_main_info);
    type_register_static(&pci_u3_agp_info);
    type_register_static(&pci_unin_agp_info);
    type_register_static(&pci_unin_internal_info);
}

type_init(unin_register_types)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0d75590d	24	#include "qemu/osdep.h"
83c9f4ca PB	25	#include "hw/hw.h"
	26	#include "hw/ppc/mac.h"
	27	#include "hw/pci/pci.h"
	28	#include "hw/pci/pci_host.h"
87ecb68b	29
f3902383 BS	30	/* debug UniNorth */
	31	//#define DEBUG_UNIN
	32
	33	#ifdef DEBUG_UNIN
001faf32 BS	34	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	35	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	36	#else
001faf32	37	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	38	#endif
f3902383 BS	39
fa0be69a AG	40	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	41
57fd7b7f AF	42	#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
	43	#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
	44	#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
	45	#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
	46
	47	#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
	48	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
	49	#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
	50	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
	51	#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
	52	OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
	53	#define U3_AGP_HOST_BRIDGE(obj) \
	54	OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
	55
2e29bd04	56	typedef struct UNINState {
67c332fd	57	PCIHostState parent_obj;
57fd7b7f	58
46f3069c BS	59	MemoryRegion pci_mmio;
46f3069c BS	60	MemoryRegion pci_hole;
2e29bd04	61	} UNINState;
502a5395	62
d2b59317	63	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	64	{
fa0be69a AG	65	int retval;
	66	int devfn = pci_dev->devfn & 0x00FFFFFF;
	67
	68	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	69
	70	return retval;
d2b59317 PB	71	}
d2b59317 PB	72
5d4e84c8	73	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	74	{
5d4e84c8 JQ	75	qemu_irq *pic = opaque;
5d4e84c8 JQ	76
fa0be69a AG	77	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	78	unin_irq_line[irq_num], level);
	79	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	80	}
502a5395 PB	81
d86f0e32 AG	82	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	83	{
	84	uint32_t retval;
	85
	86	if (reg & (1u << 31)) {
	87	/* XXX OpenBIOS compatibility hack */
	88	retval = reg \| (addr & 3);
	89	} else if (reg & 1) {
	90	/* CFA1 style */
	91	retval = (reg & ~7u) \| (addr & 7);
	92	} else {
	93	uint32_t slot, func;
	94
	95	/* Grab CFA0 style values */
5863d374 SH	96	slot = ctz32(reg & 0xfffff800);
	97	if (slot == 32) {
	98	slot = -1; /* XXX: should this be 0? */
	99	}
d86f0e32 AG	100	func = (reg >> 8) & 7;
	101
	102	/* ... and then convert them to x86 format */
	103	/* config pointer */
	104	retval = (reg & (0xff - 7)) \| (addr & 7);
	105	/* slot */
	106	retval \|= slot << 11;
	107	/* fn */
	108	retval \|= func << 8;
	109	}
	110
	111
	112	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	113	reg, addr, retval);
	114
	115	return retval;
	116	}
	117
a8170e5e	118	static void unin_data_write(void *opaque, hwaddr addr,
d0ed8076	119	uint64_t val, unsigned len)
d86f0e32	120	{
d0ed8076	121	UNINState *s = opaque;
67c332fd	122	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d0ed8076 AK	123	UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
d0ed8076 AK	124	addr, len, val);
67c332fd AF	125	pci_data_write(phb->bus,
67c332fd AF	126	unin_get_config_reg(phb->config_reg, addr),
d86f0e32 AG	127	val, len);
	128	}
	129
a8170e5e	130	static uint64_t unin_data_read(void *opaque, hwaddr addr,
d0ed8076	131	unsigned len)
d86f0e32	132	{
d0ed8076	133	UNINState *s = opaque;
67c332fd	134	PCIHostState *phb = PCI_HOST_BRIDGE(s);
d86f0e32 AG	135	uint32_t val;
d86f0e32 AG	136
67c332fd AF	137	val = pci_data_read(phb->bus,
67c332fd AF	138	unin_get_config_reg(phb->config_reg, addr),
d86f0e32	139	len);
d0ed8076 AK	140	UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
d0ed8076 AK	141	addr, len, val);
d86f0e32 AG	142	return val;
	143	}
	144
d0ed8076 AK	145	static const MemoryRegionOps unin_data_ops = {
	146	.read = unin_data_read,
	147	.write = unin_data_write,
	148	.endianness = DEVICE_LITTLE_ENDIAN,
	149	};
	150
81a322d4	151	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395	152	{
ff452ace	153	PCIHostState *h;
502a5395 PB	154
	155	/* Use values found on a real PowerMac */
	156	/* Uninorth main bus */
8558d942	157	h = PCI_HOST_BRIDGE(dev);
502a5395	158
40c5dce9	159	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	160	dev, "pci-conf-idx", 0x1000);
40c5dce9	161	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	162	"pci-conf-data", 0x1000);
57fd7b7f AF	163	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	164	sysbus_init_mmio(dev, &h->data_mem);
2e29bd04	165
81a322d4	166	return 0;
2e29bd04 BS	167	}
2e29bd04 BS	168
d0ed8076	169
0f921197 AG	170	static int pci_u3_agp_init_device(SysBusDevice *dev)
0f921197 AG	171	{
ff452ace	172	PCIHostState *h;
0f921197 AG	173
0f921197 AG	174	/* Uninorth U3 AGP bus */
8558d942	175	h = PCI_HOST_BRIDGE(dev);
0f921197	176
40c5dce9	177	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	178	dev, "pci-conf-idx", 0x1000);
40c5dce9	179	memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
d0ed8076	180	"pci-conf-data", 0x1000);
57fd7b7f AF	181	sysbus_init_mmio(dev, &h->conf_mem);
57fd7b7f AF	182	sysbus_init_mmio(dev, &h->data_mem);
0f921197	183
0f921197 AG	184	return 0;
	185	}
	186
81a322d4	187	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04	188	{
ff452ace	189	PCIHostState *h;
2e29bd04 BS	190
2e29bd04 BS	191	/* Uninorth AGP bus */
8558d942	192	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	193
40c5dce9	194	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	195	dev, "pci-conf-idx", 0x1000);
40c5dce9	196	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	197	dev, "pci-conf-data", 0x1000);
	198	sysbus_init_mmio(dev, &h->conf_mem);
	199	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	200	return 0;
2e29bd04 BS	201	}
2e29bd04 BS	202
81a322d4	203	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04	204	{
ff452ace	205	PCIHostState *h;
2e29bd04 BS	206
2e29bd04 BS	207	/* Uninorth internal bus */
8558d942	208	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	209
40c5dce9	210	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
57fd7b7f	211	dev, "pci-conf-idx", 0x1000);
40c5dce9	212	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
57fd7b7f AF	213	dev, "pci-conf-data", 0x1000);
	214	sysbus_init_mmio(dev, &h->conf_mem);
	215	sysbus_init_mmio(dev, &h->data_mem);
81a322d4	216	return 0;
2e29bd04 BS	217	}
2e29bd04 BS	218
aee97b84 AK	219	PCIBus pci_pmac_init(qemu_irq pic,
	220	MemoryRegion *address_space_mem,
	221	MemoryRegion *address_space_io)
2e29bd04 BS	222	{
	223	DeviceState *dev;
	224	SysBusDevice *s;
ff452ace	225	PCIHostState *h;
2e29bd04 BS	226	UNINState *d;
	227
	228	/* Use values found on a real PowerMac */
	229	/* Uninorth main bus */
57fd7b7f	230	dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
e23a1b33	231	qdev_init_nofail(dev);
57fd7b7f	232	s = SYS_BUS_DEVICE(dev);
8558d942	233	h = PCI_HOST_BRIDGE(s);
57fd7b7f	234	d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
40c5dce9 PB	235	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	236	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
1be88255	237	0x80000000ULL, 0x10000000ULL);
46f3069c BS	238	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	239	&d->pci_hole);
	240
8a0e1104	241	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	242	pci_unin_set_irq, pci_unin_map_irq,
	243	pic,
	244	&d->pci_mmio,
	245	address_space_io,
60a0e443	246	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
2e29bd04	247
60398748	248	#if 0
57fd7b7f	249	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
60398748	250	#endif
2e29bd04 BS	251
	252	sysbus_mmio_map(s, 0, 0xf2800000);
	253	sysbus_mmio_map(s, 1, 0xf2c00000);
	254
	255	/* DEC 21154 bridge */
	256	#if 0
	257	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
57fd7b7f	258	pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	259	#endif
	260
	261	/* Uninorth AGP bus */
57fd7b7f AF	262	pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
57fd7b7f AF	263	dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
d27d06f2	264	qdev_init_nofail(dev);
57fd7b7f	265	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	266	sysbus_mmio_map(s, 0, 0xf0800000);
d27d06f2 BS	267	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	268
	269	/* Uninorth internal bus */
	270	#if 0
	271	/* XXX: not needed for now */
57fd7b7f	272	pci_create_simple(h->bus, PCI_DEVFN(14, 0),
70f9c987	273	"uni-north-internal-pci");
57fd7b7f	274	dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
d27d06f2	275	qdev_init_nofail(dev);
57fd7b7f	276	s = SYS_BUS_DEVICE(dev);
d27d06f2 BS	277	sysbus_mmio_map(s, 0, 0xf4800000);
d27d06f2 BS	278	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	279	#endif
2e29bd04 BS	280
57fd7b7f	281	return h->bus;
2e29bd04 BS	282	}
2e29bd04 BS	283
aee97b84 AK	284	PCIBus pci_pmac_u3_init(qemu_irq pic,
	285	MemoryRegion *address_space_mem,
	286	MemoryRegion *address_space_io)
0f921197 AG	287	{
	288	DeviceState *dev;
	289	SysBusDevice *s;
ff452ace	290	PCIHostState *h;
0f921197 AG	291	UNINState *d;
	292
	293	/* Uninorth AGP bus */
	294
57fd7b7f	295	dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
0f921197	296	qdev_init_nofail(dev);
57fd7b7f	297	s = SYS_BUS_DEVICE(dev);
8558d942	298	h = PCI_HOST_BRIDGE(dev);
57fd7b7f	299	d = U3_AGP_HOST_BRIDGE(dev);
0f921197	300
40c5dce9 PB	301	memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
40c5dce9 PB	302	memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
46f3069c BS	303	0x80000000ULL, 0x70000000ULL);
	304	memory_region_add_subregion(address_space_mem, 0x80000000ULL,
	305	&d->pci_hole);
	306
8a0e1104	307	h->bus = pci_register_bus(dev, NULL,
57fd7b7f AF	308	pci_unin_set_irq, pci_unin_map_irq,
	309	pic,
	310	&d->pci_mmio,
	311	address_space_io,
60a0e443	312	PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
0f921197 AG	313
	314	sysbus_mmio_map(s, 0, 0xf0800000);
	315	sysbus_mmio_map(s, 1, 0xf0c00000);
	316
57fd7b7f	317	pci_create_simple(h->bus, 11 << 3, "u3-agp");
0f921197	318
57fd7b7f	319	return h->bus;
0f921197 AG	320	}
0f921197 AG	321
9af21dbe	322	static void unin_main_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	323	{
502a5395 PB	324	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	325	d->config[0x0D] = 0x10; // latency_timer
502a5395	326	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04	327	}
502a5395	328
9af21dbe	329	static void unin_agp_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	330	{
502a5395 PB	331	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	332	d->config[0x0D] = 0x10; // latency_timer
502a5395	333	// d->config[0x34] = 0x80; // capabilities_pointer
2e29bd04	334	}
502a5395	335
9af21dbe	336	static void u3_agp_pci_host_realize(PCIDevice d, Error *errp)
0f921197	337	{
0f921197 AG	338	/* cache line size */
	339	d->config[0x0C] = 0x08;
	340	/* latency timer */
	341	d->config[0x0D] = 0x10;
0f921197 AG	342	}
0f921197 AG	343
9af21dbe	344	static void unin_internal_pci_host_realize(PCIDevice d, Error *errp)
2e29bd04	345	{
502a5395 PB	346	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	347	d->config[0x0D] = 0x10; // latency_timer
502a5395	348	d->config[0x34] = 0x00; // capabilities_pointer
2e29bd04 BS	349	}
2e29bd04 BS	350
40021f08 AL	351	static void unin_main_pci_host_class_init(ObjectClass klass, void data)
	352	{
	353	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	354	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	355
9af21dbe	356	k->realize = unin_main_pci_host_realize;
40021f08 AL	357	k->vendor_id = PCI_VENDOR_ID_APPLE;
	358	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
	359	k->revision = 0x00;
	360	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	361	/*
	362	* PCI-facing part of the host bridge, not usable without the
	363	* host-facing part, which can't be device_add'ed, yet.
	364	*/
	365	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	366	}
40021f08 AL	367
4240abff	368	static const TypeInfo unin_main_pci_host_info = {
40021f08	369	.name = "uni-north-pci",
39bffca2 AL	370	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	371	.instance_size = sizeof(PCIDevice),
40021f08	372	.class_init = unin_main_pci_host_class_init,
2e29bd04 BS	373	};
2e29bd04 BS	374
40021f08 AL	375	static void u3_agp_pci_host_class_init(ObjectClass klass, void data)
	376	{
	377	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	378	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	379
9af21dbe	380	k->realize = u3_agp_pci_host_realize;
40021f08 AL	381	k->vendor_id = PCI_VENDOR_ID_APPLE;
	382	k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
	383	k->revision = 0x00;
	384	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	385	/*
	386	* PCI-facing part of the host bridge, not usable without the
	387	* host-facing part, which can't be device_add'ed, yet.
	388	*/
	389	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	390	}
40021f08 AL	391
4240abff	392	static const TypeInfo u3_agp_pci_host_info = {
40021f08	393	.name = "u3-agp",
39bffca2 AL	394	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	395	.instance_size = sizeof(PCIDevice),
40021f08	396	.class_init = u3_agp_pci_host_class_init,
0f921197 AG	397	};
0f921197 AG	398
40021f08 AL	399	static void unin_agp_pci_host_class_init(ObjectClass klass, void data)
	400	{
	401	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	402	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	403
9af21dbe	404	k->realize = unin_agp_pci_host_realize;
40021f08 AL	405	k->vendor_id = PCI_VENDOR_ID_APPLE;
	406	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
	407	k->revision = 0x00;
	408	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	409	/*
	410	* PCI-facing part of the host bridge, not usable without the
	411	* host-facing part, which can't be device_add'ed, yet.
	412	*/
	413	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	414	}
40021f08 AL	415
4240abff	416	static const TypeInfo unin_agp_pci_host_info = {
40021f08	417	.name = "uni-north-agp",
39bffca2 AL	418	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	419	.instance_size = sizeof(PCIDevice),
40021f08	420	.class_init = unin_agp_pci_host_class_init,
2e29bd04 BS	421	};
2e29bd04 BS	422
40021f08 AL	423	static void unin_internal_pci_host_class_init(ObjectClass klass, void data)
	424	{
	425	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
08c58f92	426	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	427
9af21dbe	428	k->realize = unin_internal_pci_host_realize;
40021f08 AL	429	k->vendor_id = PCI_VENDOR_ID_APPLE;
	430	k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
	431	k->revision = 0x00;
	432	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	433	/*
	434	* PCI-facing part of the host bridge, not usable without the
	435	* host-facing part, which can't be device_add'ed, yet.
	436	*/
	437	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	438	}
40021f08 AL	439
4240abff	440	static const TypeInfo unin_internal_pci_host_info = {
40021f08	441	.name = "uni-north-internal-pci",
39bffca2 AL	442	.parent = TYPE_PCI_DEVICE,
39bffca2 AL	443	.instance_size = sizeof(PCIDevice),
40021f08	444	.class_init = unin_internal_pci_host_class_init,
2e29bd04 BS	445	};
2e29bd04 BS	446
999e12bb AL	447	static void pci_unin_main_class_init(ObjectClass klass, void data)
	448	{
	449	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	450	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	451
999e12bb AL	452	sbc->init = pci_unin_main_init_device;
1d16f86a	453	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	454	}
999e12bb AL	455
4240abff	456	static const TypeInfo pci_unin_main_info = {
57fd7b7f	457	.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
8558d942	458	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	459	.instance_size = sizeof(UNINState),
39bffca2 AL	460	.class_init = pci_unin_main_class_init,
70f9c987 AF	461	};
70f9c987 AF	462
999e12bb AL	463	static void pci_u3_agp_class_init(ObjectClass klass, void data)
	464	{
	465	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	466	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	467
999e12bb AL	468	sbc->init = pci_u3_agp_init_device;
1d16f86a	469	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	470	}
999e12bb AL	471
4240abff	472	static const TypeInfo pci_u3_agp_info = {
57fd7b7f	473	.name = TYPE_U3_AGP_HOST_BRIDGE,
8558d942	474	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	475	.instance_size = sizeof(UNINState),
39bffca2 AL	476	.class_init = pci_u3_agp_class_init,
70f9c987 AF	477	};
70f9c987 AF	478
999e12bb AL	479	static void pci_unin_agp_class_init(ObjectClass klass, void data)
	480	{
	481	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	482	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	483
999e12bb AL	484	sbc->init = pci_unin_agp_init_device;
1d16f86a	485	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	486	}
999e12bb AL	487
4240abff	488	static const TypeInfo pci_unin_agp_info = {
57fd7b7f	489	.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
8558d942	490	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	491	.instance_size = sizeof(UNINState),
39bffca2 AL	492	.class_init = pci_unin_agp_class_init,
70f9c987 AF	493	};
70f9c987 AF	494
999e12bb AL	495	static void pci_unin_internal_class_init(ObjectClass klass, void data)
	496	{
	497	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1d16f86a	498	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	499
999e12bb AL	500	sbc->init = pci_unin_internal_init_device;
1d16f86a	501	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
999e12bb AL	502	}
999e12bb AL	503
4240abff	504	static const TypeInfo pci_unin_internal_info = {
57fd7b7f	505	.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
8558d942	506	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	507	.instance_size = sizeof(UNINState),
39bffca2 AL	508	.class_init = pci_unin_internal_class_init,
70f9c987 AF	509	};
70f9c987 AF	510
83f7d43a	511	static void unin_register_types(void)
2e29bd04	512	{
39bffca2 AL	513	type_register_static(&unin_main_pci_host_info);
	514	type_register_static(&u3_agp_pci_host_info);
	515	type_register_static(&unin_agp_pci_host_info);
	516	type_register_static(&unin_internal_pci_host_info);
	517
	518	type_register_static(&pci_unin_main_info);
	519	type_register_static(&pci_u3_agp_info);
	520	type_register_static(&pci_unin_agp_info);
	521	type_register_static(&pci_unin_internal_info);
502a5395	522	}
2e29bd04	523
83f7d43a	524	type_init(unin_register_types)