[qemu.git] / target / arm / internals.h

/*
 * QEMU ARM CPU -- internal functions and types
 *
 * Copyright (c) 2014 Linaro Ltd
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see
 * <http://www.gnu.org/licenses/gpl-2.0.html>
 *
 * This header defines functions, types, etc which need to be shared
 * between different source files within target/arm/ but which are
 * private to it and not required by the rest of QEMU.
 */

#ifndef TARGET_ARM_INTERNALS_H
#define TARGET_ARM_INTERNALS_H

#include "hw/registerfields.h"

/* register banks for CPU modes */
#define BANK_USRSYS 0
#define BANK_SVC    1
#define BANK_ABT    2
#define BANK_UND    3
#define BANK_IRQ    4
#define BANK_FIQ    5
#define BANK_HYP    6
#define BANK_MON    7

static inline bool excp_is_internal(int excp)
{
    /* Return true if this exception number represents a QEMU-internal
     * exception that will not be passed to the guest.
     */
    return excp == EXCP_INTERRUPT
        || excp == EXCP_HLT
        || excp == EXCP_DEBUG
        || excp == EXCP_HALTED
        || excp == EXCP_EXCEPTION_EXIT
        || excp == EXCP_KERNEL_TRAP
        || excp == EXCP_SEMIHOST;
}

/* Scale factor for generic timers, ie number of ns per tick.
 * This gives a 62.5MHz timer.
 */
#define GTIMER_SCALE 16

/* Bit definitions for the v7M CONTROL register */
FIELD(V7M_CONTROL, NPRIV, 0, 1)
FIELD(V7M_CONTROL, SPSEL, 1, 1)
FIELD(V7M_CONTROL, FPCA, 2, 1)
FIELD(V7M_CONTROL, SFPA, 3, 1)

/* Bit definitions for v7M exception return payload */
FIELD(V7M_EXCRET, ES, 0, 1)
FIELD(V7M_EXCRET, RES0, 1, 1)
FIELD(V7M_EXCRET, SPSEL, 2, 1)
FIELD(V7M_EXCRET, MODE, 3, 1)
FIELD(V7M_EXCRET, FTYPE, 4, 1)
FIELD(V7M_EXCRET, DCRS, 5, 1)
FIELD(V7M_EXCRET, S, 6, 1)
FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */

/* Minimum value which is a magic number for exception return */
#define EXC_RETURN_MIN_MAGIC 0xff000000
/* Minimum number which is a magic number for function or exception return
 * when using v8M security extension
 */
#define FNC_RETURN_MIN_MAGIC 0xfefffffe

/* We use a few fake FSR values for internal purposes in M profile.
 * M profile cores don't have A/R format FSRs, but currently our
 * get_phys_addr() code assumes A/R profile and reports failures via
 * an A/R format FSR value. We then translate that into the proper
 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
 * Mostly the FSR values we use for this are those defined for v7PMSA,
 * since we share some of that codepath. A few kinds of fault are
 * only for M profile and have no A/R equivalent, though, so we have
 * to pick a value from the reserved range (which we never otherwise
 * generate) to use for these.
 * These values will never be visible to the guest.
 */
#define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
#define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */

/*
 * For AArch64, map a given EL to an index in the banked_spsr array.
 * Note that this mapping and the AArch32 mapping defined in bank_number()
 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
 * mandated mapping between each other.
 */
static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
{
    static const unsigned int map[4] = {
        [1] = BANK_SVC, /* EL1.  */
        [2] = BANK_HYP, /* EL2.  */
        [3] = BANK_MON, /* EL3.  */
    };
    assert(el >= 1 && el <= 3);
    return map[el];
}

/* Map CPU modes onto saved register banks.  */
static inline int bank_number(int mode)
{
    switch (mode) {
    case ARM_CPU_MODE_USR:
    case ARM_CPU_MODE_SYS:
        return BANK_USRSYS;
    case ARM_CPU_MODE_SVC:
        return BANK_SVC;
    case ARM_CPU_MODE_ABT:
        return BANK_ABT;
    case ARM_CPU_MODE_UND:
        return BANK_UND;
    case ARM_CPU_MODE_IRQ:
        return BANK_IRQ;
    case ARM_CPU_MODE_FIQ:
        return BANK_FIQ;
    case ARM_CPU_MODE_HYP:
        return BANK_HYP;
    case ARM_CPU_MODE_MON:
        return BANK_MON;
    }
    g_assert_not_reached();
}

void switch_mode(CPUARMState *, int);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);

enum arm_fprounding {
    FPROUNDING_TIEEVEN,
    FPROUNDING_POSINF,
    FPROUNDING_NEGINF,
    FPROUNDING_ZERO,
    FPROUNDING_TIEAWAY,
    FPROUNDING_ODD
};

int arm_rmode_to_sf(int rmode);

static inline void aarch64_save_sp(CPUARMState *env, int el)
{
    if (env->pstate & PSTATE_SP) {
        env->sp_el[el] = env->xregs[31];
    } else {
        env->sp_el[0] = env->xregs[31];
    }
}

static inline void aarch64_restore_sp(CPUARMState *env, int el)
{
    if (env->pstate & PSTATE_SP) {
        env->xregs[31] = env->sp_el[el];
    } else {
        env->xregs[31] = env->sp_el[0];
    }
}

static inline void update_spsel(CPUARMState *env, uint32_t imm)
{
    unsigned int cur_el = arm_current_el(env);
    /* Update PSTATE SPSel bit; this requires us to update the
     * working stack pointer in xregs[31].
     */
    if (!((imm ^ env->pstate) & PSTATE_SP)) {
        return;
    }
    aarch64_save_sp(env, cur_el);
    env->pstate = deposit32(env->pstate, 0, 1, imm);

    /* We rely on illegal updates to SPsel from EL0 to get trapped
     * at translation time.
     */
    assert(cur_el >= 1 && cur_el <= 3);
    aarch64_restore_sp(env, cur_el);
}

/*
 * arm_pamax
 * @cpu: ARMCPU
 *
 * Returns the implementation defined bit-width of physical addresses.
 * The ARMv8 reference manuals refer to this as PAMax().
 */
static inline unsigned int arm_pamax(ARMCPU *cpu)
{
    static const unsigned int pamax_map[] = {
        [0] = 32,
        [1] = 36,
        [2] = 40,
        [3] = 42,
        [4] = 44,
        [5] = 48,
    };
    unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);

    /* id_aa64mmfr0 is a read-only register so values outside of the
     * supported mappings can be considered an implementation error.  */
    assert(parange < ARRAY_SIZE(pamax_map));
    return pamax_map[parange];
}

/* Return true if extended addresses are enabled.
 * This is always the case if our translation regime is 64 bit,
 * but depends on TTBCR.EAE for 32 bit.
 */
static inline bool extended_addresses_enabled(CPUARMState *env)
{
    TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
    return arm_el_is_aa64(env, 1) ||
           (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
}

/* Valid Syndrome Register EC field values */
enum arm_exception_class {
    EC_UNCATEGORIZED          = 0x00,
    EC_WFX_TRAP               = 0x01,
    EC_CP15RTTRAP             = 0x03,
    EC_CP15RRTTRAP            = 0x04,
    EC_CP14RTTRAP             = 0x05,
    EC_CP14DTTRAP             = 0x06,
    EC_ADVSIMDFPACCESSTRAP    = 0x07,
    EC_FPIDTRAP               = 0x08,
    EC_CP14RRTTRAP            = 0x0c,
    EC_ILLEGALSTATE           = 0x0e,
    EC_AA32_SVC               = 0x11,
    EC_AA32_HVC               = 0x12,
    EC_AA32_SMC               = 0x13,
    EC_AA64_SVC               = 0x15,
    EC_AA64_HVC               = 0x16,
    EC_AA64_SMC               = 0x17,
    EC_SYSTEMREGISTERTRAP     = 0x18,
    EC_INSNABORT              = 0x20,
    EC_INSNABORT_SAME_EL      = 0x21,
    EC_PCALIGNMENT            = 0x22,
    EC_DATAABORT              = 0x24,
    EC_DATAABORT_SAME_EL      = 0x25,
    EC_SPALIGNMENT            = 0x26,
    EC_AA32_FPTRAP            = 0x28,
    EC_AA64_FPTRAP            = 0x2c,
    EC_SERROR                 = 0x2f,
    EC_BREAKPOINT             = 0x30,
    EC_BREAKPOINT_SAME_EL     = 0x31,
    EC_SOFTWARESTEP           = 0x32,
    EC_SOFTWARESTEP_SAME_EL   = 0x33,
    EC_WATCHPOINT             = 0x34,
    EC_WATCHPOINT_SAME_EL     = 0x35,
    EC_AA32_BKPT              = 0x38,
    EC_VECTORCATCH            = 0x3a,
    EC_AA64_BKPT              = 0x3c,
};

#define ARM_EL_EC_SHIFT 26
#define ARM_EL_IL_SHIFT 25
#define ARM_EL_ISV_SHIFT 24
#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)

/* Utility functions for constructing various kinds of syndrome value.
 * Note that in general we follow the AArch64 syndrome values; in a
 * few cases the value in HSR for exceptions taken to AArch32 Hyp
 * mode differs slightly, so if we ever implemented Hyp mode then the
 * syndrome value would need some massaging on exception entry.
 * (One example of this is that AArch64 defaults to IL bit set for
 * exceptions which don't specifically indicate information about the
 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 */
static inline uint32_t syn_uncategorized(void)
{
    return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
}

static inline uint32_t syn_aa64_svc(uint32_t imm16)
{
    return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
}

static inline uint32_t syn_aa64_hvc(uint32_t imm16)
{
    return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
}

static inline uint32_t syn_aa64_smc(uint32_t imm16)
{
    return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
}

static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
{
    return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
        | (is_16bit ? 0 : ARM_EL_IL);
}

static inline uint32_t syn_aa32_hvc(uint32_t imm16)
{
    return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
}

static inline uint32_t syn_aa32_smc(void)
{
    return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
}

static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
{
    return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
}

static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
{
    return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
        | (is_16bit ? 0 : ARM_EL_IL);
}

static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
                                           int crn, int crm, int rt,
                                           int isread)
{
    return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
        | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
        | (crm << 1) | isread;
}

static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
                                        int crn, int crm, int rt, int isread,
                                        bool is_16bit)
{
    return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
        | (is_16bit ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
        | (crn << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
                                        int crn, int crm, int rt, int isread,
                                        bool is_16bit)
{
    return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
        | (is_16bit ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
        | (crn << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
                                         int rt, int rt2, int isread,
                                         bool is_16bit)
{
    return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
        | (is_16bit ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc1 << 16)
        | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
                                         int rt, int rt2, int isread,
                                         bool is_16bit)
{
    return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
        | (is_16bit ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc1 << 16)
        | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
{
    return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
        | (is_16bit ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20);
}

static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
{
    return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
}

static inline uint32_t syn_data_abort_no_iss(int same_el,
                                             int ea, int cm, int s1ptw,
                                             int wnr, int fsc)
{
    return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
           | ARM_EL_IL
           | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
}

static inline uint32_t syn_data_abort_with_iss(int same_el,
                                               int sas, int sse, int srt,
                                               int sf, int ar,
                                               int ea, int cm, int s1ptw,
                                               int wnr, int fsc,
                                               bool is_16bit)
{
    return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
           | (is_16bit ? 0 : ARM_EL_IL)
           | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
           | (sf << 15) | (ar << 14)
           | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
}

static inline uint32_t syn_swstep(int same_el, int isv, int ex)
{
    return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
}

static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
{
    return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
}

static inline uint32_t syn_breakpoint(int same_el)
{
    return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | ARM_EL_IL | 0x22;
}

static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
{
    return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
           (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
           (cv << 24) | (cond << 20) | ti;
}

/* Update a QEMU watchpoint based on the information the guest has set in the
 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 */
void hw_watchpoint_update(ARMCPU *cpu, int n);
/* Update the QEMU watchpoints for every guest watchpoint. This does a
 * complete delete-and-reinstate of the QEMU watchpoint list and so is
 * suitable for use after migration or on reset.
 */
void hw_watchpoint_update_all(ARMCPU *cpu);
/* Update a QEMU breakpoint based on the information the guest has set in the
 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 */
void hw_breakpoint_update(ARMCPU *cpu, int n);
/* Update the QEMU breakpoints for every guest breakpoint. This does a
 * complete delete-and-reinstate of the QEMU breakpoint list and so is
 * suitable for use after migration or on reset.
 */
void hw_breakpoint_update_all(ARMCPU *cpu);

/* Callback function for checking if a watchpoint should trigger. */
bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);

/* Adjust addresses (in BE32 mode) before testing against watchpoint
 * addresses.
 */
vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);

/* Callback function for when a watchpoint or breakpoint triggers. */
void arm_debug_excp_handler(CPUState *cs);

#ifdef CONFIG_USER_ONLY
static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
{
    return false;
}
#else
/* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
/* Actually handle a PSCI call */
void arm_handle_psci_call(ARMCPU *cpu);
#endif

/**
 * arm_clear_exclusive: clear the exclusive monitor
 * @env: CPU env
 * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
 */
static inline void arm_clear_exclusive(CPUARMState *env)
{
    env->exclusive_addr = -1;
}

/**
 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
 * @s2addr: Address that caused a fault at stage 2
 * @stage2: True if we faulted at stage 2
 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
 * @ea: True if we should set the EA (external abort type) bit in syndrome
 */
typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
struct ARMMMUFaultInfo {
    target_ulong s2addr;
    bool stage2;
    bool s1ptw;
    bool ea;
};

/* Do a page table walk and add page to TLB if possible */
bool arm_tlb_fill(CPUState *cpu, vaddr address,
                  MMUAccessType access_type, int mmu_idx,
                  uint32_t *fsr, ARMMMUFaultInfo *fi);

/* Return true if the stage 1 translation regime is using LPAE format page
 * tables */
bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);

/* Raise a data fault alignment exception for the specified virtual address */
void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
                                 MMUAccessType access_type,
                                 int mmu_idx, uintptr_t retaddr);

/* arm_cpu_do_transaction_failed: handle a memory system error response
 * (eg "no device/memory present at address") by raising an external abort
 * exception
 */
void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                   vaddr addr, unsigned size,
                                   MMUAccessType access_type,
                                   int mmu_idx, MemTxAttrs attrs,
                                   MemTxResult response, uintptr_t retaddr);

/* Call the EL change hook if one has been registered */
static inline void arm_call_el_change_hook(ARMCPU *cpu)
{
    if (cpu->el_change_hook) {
        cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
    }
}

/* Return true if this address translation regime is secure */
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{
    switch (mmu_idx) {
    case ARMMMUIdx_S12NSE0:
    case ARMMMUIdx_S12NSE1:
    case ARMMMUIdx_S1NSE0:
    case ARMMMUIdx_S1NSE1:
    case ARMMMUIdx_S1E2:
    case ARMMMUIdx_S2NS:
    case ARMMMUIdx_MPriv:
    case ARMMMUIdx_MNegPri:
    case ARMMMUIdx_MUser:
        return false;
    case ARMMMUIdx_S1E3:
    case ARMMMUIdx_S1SE0:
    case ARMMMUIdx_S1SE1:
    case ARMMMUIdx_MSPriv:
    case ARMMMUIdx_MSNegPri:
    case ARMMMUIdx_MSUser:
        return true;
    default:
        g_assert_not_reached();
    }
}

#endif
Commit	Line	Data
ccd38087 PM	1	/*
	2	* QEMU ARM CPU -- internal functions and types
	3	*
	4	* Copyright (c) 2014 Linaro Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see
	18	* <http://www.gnu.org/licenses/gpl-2.0.html>
	19	*
	20	* This header defines functions, types, etc which need to be shared
fcf5ef2a	21	* between different source files within target/arm/ but which are
ccd38087 PM	22	* private to it and not required by the rest of QEMU.
	23	*/
	24
	25	#ifndef TARGET_ARM_INTERNALS_H
	26	#define TARGET_ARM_INTERNALS_H
	27
abc24d86 MD	28	#include "hw/registerfields.h"
abc24d86 MD	29
99a99c1f SB	30	/* register banks for CPU modes */
	31	#define BANK_USRSYS 0
	32	#define BANK_SVC 1
	33	#define BANK_ABT 2
	34	#define BANK_UND 3
	35	#define BANK_IRQ 4
	36	#define BANK_FIQ 5
	37	#define BANK_HYP 6
	38	#define BANK_MON 7
	39
d4a2dc67 PM	40	static inline bool excp_is_internal(int excp)
	41	{
	42	/* Return true if this exception number represents a QEMU-internal
	43	* exception that will not be passed to the guest.
	44	*/
	45	return excp == EXCP_INTERRUPT
	46	\|\| excp == EXCP_HLT
	47	\|\| excp == EXCP_DEBUG
	48	\|\| excp == EXCP_HALTED
	49	\|\| excp == EXCP_EXCEPTION_EXIT
	50	\|\| excp == EXCP_KERNEL_TRAP
05188cc7	51	\|\| excp == EXCP_SEMIHOST;
d4a2dc67 PM	52	}
d4a2dc67 PM	53
ccd38087 PM	54	/* Scale factor for generic timers, ie number of ns per tick.
	55	* This gives a 62.5MHz timer.
	56	*/
	57	#define GTIMER_SCALE 16
	58
abc24d86 MD	59	/* Bit definitions for the v7M CONTROL register */
	60	FIELD(V7M_CONTROL, NPRIV, 0, 1)
	61	FIELD(V7M_CONTROL, SPSEL, 1, 1)
	62	FIELD(V7M_CONTROL, FPCA, 2, 1)
3e3fa230	63	FIELD(V7M_CONTROL, SFPA, 3, 1)
abc24d86	64
4d1e7a47 PM	65	/* Bit definitions for v7M exception return payload */
	66	FIELD(V7M_EXCRET, ES, 0, 1)
	67	FIELD(V7M_EXCRET, RES0, 1, 1)
	68	FIELD(V7M_EXCRET, SPSEL, 2, 1)
	69	FIELD(V7M_EXCRET, MODE, 3, 1)
	70	FIELD(V7M_EXCRET, FTYPE, 4, 1)
	71	FIELD(V7M_EXCRET, DCRS, 5, 1)
	72	FIELD(V7M_EXCRET, S, 6, 1)
	73	FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
	74
d02a8698 PM	75	/* Minimum value which is a magic number for exception return */
	76	#define EXC_RETURN_MIN_MAGIC 0xff000000
	77	/* Minimum number which is a magic number for function or exception return
	78	* when using v8M security extension
	79	*/
	80	#define FNC_RETURN_MIN_MAGIC 0xfefffffe
	81
35337cc3 PM	82	/* We use a few fake FSR values for internal purposes in M profile.
	83	* M profile cores don't have A/R format FSRs, but currently our
	84	* get_phys_addr() code assumes A/R profile and reports failures via
	85	* an A/R format FSR value. We then translate that into the proper
	86	* M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
	87	* Mostly the FSR values we use for this are those defined for v7PMSA,
	88	* since we share some of that codepath. A few kinds of fault are
	89	* only for M profile and have no A/R equivalent, though, so we have
	90	* to pick a value from the reserved range (which we never otherwise
	91	* generate) to use for these.
	92	* These values will never be visible to the guest.
	93	*/
	94	#define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
	95	#define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
	96
2a923c4d EI	97	/*
2a923c4d EI	98	* For AArch64, map a given EL to an index in the banked_spsr array.
7847f9ea PM	99	* Note that this mapping and the AArch32 mapping defined in bank_number()
	100	* must agree such that the AArch64<->AArch32 SPSRs have the architecturally
	101	* mandated mapping between each other.
2a923c4d EI	102	*/
	103	static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
	104	{
	105	static const unsigned int map[4] = {
99a99c1f SB	106	[1] = BANK_SVC, /* EL1. */
	107	[2] = BANK_HYP, /* EL2. */
	108	[3] = BANK_MON, /* EL3. */
2a923c4d EI	109	};
	110	assert(el >= 1 && el <= 3);
	111	return map[el];
	112	}
	113
c766568d PM	114	/* Map CPU modes onto saved register banks. */
	115	static inline int bank_number(int mode)
	116	{
	117	switch (mode) {
	118	case ARM_CPU_MODE_USR:
	119	case ARM_CPU_MODE_SYS:
	120	return BANK_USRSYS;
	121	case ARM_CPU_MODE_SVC:
	122	return BANK_SVC;
	123	case ARM_CPU_MODE_ABT:
	124	return BANK_ABT;
	125	case ARM_CPU_MODE_UND:
	126	return BANK_UND;
	127	case ARM_CPU_MODE_IRQ:
	128	return BANK_IRQ;
	129	case ARM_CPU_MODE_FIQ:
	130	return BANK_FIQ;
	131	case ARM_CPU_MODE_HYP:
	132	return BANK_HYP;
	133	case ARM_CPU_MODE_MON:
	134	return BANK_MON;
	135	}
	136	g_assert_not_reached();
	137	}
	138
ccd38087 PM	139	void switch_mode(CPUARMState *, int);
	140	void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
	141	void arm_translate_init(void);
	142
	143	enum arm_fprounding {
	144	FPROUNDING_TIEEVEN,
	145	FPROUNDING_POSINF,
	146	FPROUNDING_NEGINF,
	147	FPROUNDING_ZERO,
	148	FPROUNDING_TIEAWAY,
	149	FPROUNDING_ODD
	150	};
	151
	152	int arm_rmode_to_sf(int rmode);
	153
9208b961 EI	154	static inline void aarch64_save_sp(CPUARMState *env, int el)
	155	{
	156	if (env->pstate & PSTATE_SP) {
	157	env->sp_el[el] = env->xregs[31];
	158	} else {
	159	env->sp_el[0] = env->xregs[31];
	160	}
	161	}
	162
	163	static inline void aarch64_restore_sp(CPUARMState *env, int el)
	164	{
	165	if (env->pstate & PSTATE_SP) {
	166	env->xregs[31] = env->sp_el[el];
	167	} else {
	168	env->xregs[31] = env->sp_el[0];
	169	}
	170	}
	171
f502cfc2 PM	172	static inline void update_spsel(CPUARMState *env, uint32_t imm)
f502cfc2 PM	173	{
dcbff19b	174	unsigned int cur_el = arm_current_el(env);
f502cfc2 PM	175	/* Update PSTATE SPSel bit; this requires us to update the
	176	* working stack pointer in xregs[31].
	177	*/
	178	if (!((imm ^ env->pstate) & PSTATE_SP)) {
	179	return;
	180	}
9208b961	181	aarch64_save_sp(env, cur_el);
f502cfc2 PM	182	env->pstate = deposit32(env->pstate, 0, 1, imm);
f502cfc2 PM	183
61d4b215 EI	184	/* We rely on illegal updates to SPsel from EL0 to get trapped
61d4b215 EI	185	* at translation time.
f502cfc2	186	*/
61d4b215	187	assert(cur_el >= 1 && cur_el <= 3);
9208b961	188	aarch64_restore_sp(env, cur_el);
f502cfc2 PM	189	}
f502cfc2 PM	190
1853d5a9 EI	191	/*
	192	* arm_pamax
	193	* @cpu: ARMCPU
	194	*
	195	* Returns the implementation defined bit-width of physical addresses.
	196	* The ARMv8 reference manuals refer to this as PAMax().
	197	*/
	198	static inline unsigned int arm_pamax(ARMCPU *cpu)
	199	{
	200	static const unsigned int pamax_map[] = {
	201	[0] = 32,
	202	[1] = 36,
	203	[2] = 40,
	204	[3] = 42,
	205	[4] = 44,
	206	[5] = 48,
	207	};
	208	unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
	209
	210	/* id_aa64mmfr0 is a read-only register so values outside of the
	211	* supported mappings can be considered an implementation error. */
	212	assert(parange < ARRAY_SIZE(pamax_map));
	213	return pamax_map[parange];
	214	}
	215
73c5211b PM	216	/* Return true if extended addresses are enabled.
	217	* This is always the case if our translation regime is 64 bit,
	218	* but depends on TTBCR.EAE for 32 bit.
	219	*/
	220	static inline bool extended_addresses_enabled(CPUARMState *env)
	221	{
11f136ee FA	222	TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
	223	return arm_el_is_aa64(env, 1) \|\|
	224	(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
73c5211b PM	225	}
73c5211b PM	226
8bcbf37c PM	227	/* Valid Syndrome Register EC field values */
	228	enum arm_exception_class {
	229	EC_UNCATEGORIZED = 0x00,
	230	EC_WFX_TRAP = 0x01,
	231	EC_CP15RTTRAP = 0x03,
	232	EC_CP15RRTTRAP = 0x04,
	233	EC_CP14RTTRAP = 0x05,
	234	EC_CP14DTTRAP = 0x06,
	235	EC_ADVSIMDFPACCESSTRAP = 0x07,
	236	EC_FPIDTRAP = 0x08,
	237	EC_CP14RRTTRAP = 0x0c,
	238	EC_ILLEGALSTATE = 0x0e,
	239	EC_AA32_SVC = 0x11,
	240	EC_AA32_HVC = 0x12,
	241	EC_AA32_SMC = 0x13,
	242	EC_AA64_SVC = 0x15,
	243	EC_AA64_HVC = 0x16,
	244	EC_AA64_SMC = 0x17,
	245	EC_SYSTEMREGISTERTRAP = 0x18,
	246	EC_INSNABORT = 0x20,
	247	EC_INSNABORT_SAME_EL = 0x21,
	248	EC_PCALIGNMENT = 0x22,
	249	EC_DATAABORT = 0x24,
	250	EC_DATAABORT_SAME_EL = 0x25,
	251	EC_SPALIGNMENT = 0x26,
	252	EC_AA32_FPTRAP = 0x28,
	253	EC_AA64_FPTRAP = 0x2c,
	254	EC_SERROR = 0x2f,
	255	EC_BREAKPOINT = 0x30,
	256	EC_BREAKPOINT_SAME_EL = 0x31,
	257	EC_SOFTWARESTEP = 0x32,
	258	EC_SOFTWARESTEP_SAME_EL = 0x33,
	259	EC_WATCHPOINT = 0x34,
	260	EC_WATCHPOINT_SAME_EL = 0x35,
	261	EC_AA32_BKPT = 0x38,
	262	EC_VECTORCATCH = 0x3a,
	263	EC_AA64_BKPT = 0x3c,
	264	};
	265
	266	#define ARM_EL_EC_SHIFT 26
	267	#define ARM_EL_IL_SHIFT 25
094d028a	268	#define ARM_EL_ISV_SHIFT 24
8bcbf37c	269	#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
094d028a	270	#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
8bcbf37c PM	271
	272	/* Utility functions for constructing various kinds of syndrome value.
	273	* Note that in general we follow the AArch64 syndrome values; in a
	274	* few cases the value in HSR for exceptions taken to AArch32 Hyp
	275	* mode differs slightly, so if we ever implemented Hyp mode then the
	276	* syndrome value would need some massaging on exception entry.
	277	* (One example of this is that AArch64 defaults to IL bit set for
	278	* exceptions which don't specifically indicate information about the
	279	* trapping instruction, whereas AArch32 defaults to IL bit clear.)
	280	*/
	281	static inline uint32_t syn_uncategorized(void)
	282	{
	283	return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) \| ARM_EL_IL;
	284	}
	285
	286	static inline uint32_t syn_aa64_svc(uint32_t imm16)
	287	{
	288	return (EC_AA64_SVC << ARM_EL_EC_SHIFT) \| ARM_EL_IL \| (imm16 & 0xffff);
	289	}
	290
35979d71 EI	291	static inline uint32_t syn_aa64_hvc(uint32_t imm16)
	292	{
	293	return (EC_AA64_HVC << ARM_EL_EC_SHIFT) \| ARM_EL_IL \| (imm16 & 0xffff);
	294	}
	295
e0d6e6a5 EI	296	static inline uint32_t syn_aa64_smc(uint32_t imm16)
	297	{
	298	return (EC_AA64_SMC << ARM_EL_EC_SHIFT) \| ARM_EL_IL \| (imm16 & 0xffff);
	299	}
	300
fc05f4a6	301	static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
8bcbf37c PM	302	{
8bcbf37c PM	303	return (EC_AA32_SVC << ARM_EL_EC_SHIFT) \| (imm16 & 0xffff)
fc05f4a6	304	\| (is_16bit ? 0 : ARM_EL_IL);
8bcbf37c PM	305	}
8bcbf37c PM	306
37e6456e PM	307	static inline uint32_t syn_aa32_hvc(uint32_t imm16)
	308	{
	309	return (EC_AA32_HVC << ARM_EL_EC_SHIFT) \| ARM_EL_IL \| (imm16 & 0xffff);
	310	}
	311
	312	static inline uint32_t syn_aa32_smc(void)
	313	{
	314	return (EC_AA32_SMC << ARM_EL_EC_SHIFT) \| ARM_EL_IL;
	315	}
	316
8bcbf37c PM	317	static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
	318	{
	319	return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) \| ARM_EL_IL \| (imm16 & 0xffff);
	320	}
	321
fc05f4a6	322	static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
8bcbf37c PM	323	{
8bcbf37c PM	324	return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) \| (imm16 & 0xffff)
fc05f4a6	325	\| (is_16bit ? 0 : ARM_EL_IL);
8bcbf37c PM	326	}
	327
	328	static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
	329	int crn, int crm, int rt,
	330	int isread)
	331	{
	332	return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) \| ARM_EL_IL
	333	\| (op0 << 20) \| (op2 << 17) \| (op1 << 14) \| (crn << 10) \| (rt << 5)
	334	\| (crm << 1) \| isread;
	335	}
	336
	337	static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
	338	int crn, int crm, int rt, int isread,
fc05f4a6	339	bool is_16bit)
8bcbf37c PM	340	{
8bcbf37c PM	341	return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
fc05f4a6	342	\| (is_16bit ? 0 : ARM_EL_IL)
8bcbf37c PM	343	\| (cv << 24) \| (cond << 20) \| (opc2 << 17) \| (opc1 << 14)
	344	\| (crn << 10) \| (rt << 5) \| (crm << 1) \| isread;
	345	}
	346
	347	static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
	348	int crn, int crm, int rt, int isread,
fc05f4a6	349	bool is_16bit)
8bcbf37c PM	350	{
8bcbf37c PM	351	return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
fc05f4a6	352	\| (is_16bit ? 0 : ARM_EL_IL)
8bcbf37c PM	353	\| (cv << 24) \| (cond << 20) \| (opc2 << 17) \| (opc1 << 14)
	354	\| (crn << 10) \| (rt << 5) \| (crm << 1) \| isread;
	355	}
	356
	357	static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
	358	int rt, int rt2, int isread,
fc05f4a6	359	bool is_16bit)
8bcbf37c PM	360	{
8bcbf37c PM	361	return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
fc05f4a6	362	\| (is_16bit ? 0 : ARM_EL_IL)
8bcbf37c PM	363	\| (cv << 24) \| (cond << 20) \| (opc1 << 16)
	364	\| (rt2 << 10) \| (rt << 5) \| (crm << 1) \| isread;
	365	}
	366
	367	static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
	368	int rt, int rt2, int isread,
fc05f4a6	369	bool is_16bit)
8bcbf37c PM	370	{
8bcbf37c PM	371	return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
fc05f4a6	372	\| (is_16bit ? 0 : ARM_EL_IL)
8bcbf37c PM	373	\| (cv << 24) \| (cond << 20) \| (opc1 << 16)
	374	\| (rt2 << 10) \| (rt << 5) \| (crm << 1) \| isread;
	375	}
	376
fc05f4a6	377	static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
8c6afa6a PM	378	{
8c6afa6a PM	379	return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
fc05f4a6	380	\| (is_16bit ? 0 : ARM_EL_IL)
8c6afa6a PM	381	\| (cv << 24) \| (cond << 20);
	382	}
	383
00892383 RH	384	static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
	385	{
	386	return (EC_INSNABORT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
04ce861e	387	\| ARM_EL_IL \| (ea << 9) \| (s1ptw << 7) \| fsc;
00892383 RH	388	}
00892383 RH	389
094d028a PM	390	static inline uint32_t syn_data_abort_no_iss(int same_el,
	391	int ea, int cm, int s1ptw,
	392	int wnr, int fsc)
00892383 RH	393	{
00892383 RH	394	return (EC_DATAABORT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
094d028a PM	395	\| ARM_EL_IL
	396	\| (ea << 9) \| (cm << 8) \| (s1ptw << 7) \| (wnr << 6) \| fsc;
	397	}
	398
	399	static inline uint32_t syn_data_abort_with_iss(int same_el,
	400	int sas, int sse, int srt,
	401	int sf, int ar,
	402	int ea, int cm, int s1ptw,
	403	int wnr, int fsc,
	404	bool is_16bit)
	405	{
	406	return (EC_DATAABORT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
	407	\| (is_16bit ? 0 : ARM_EL_IL)
	408	\| ARM_EL_ISV \| (sas << 22) \| (sse << 21) \| (srt << 16)
	409	\| (sf << 15) \| (ar << 14)
	410	\| (ea << 9) \| (cm << 8) \| (s1ptw << 7) \| (wnr << 6) \| fsc;
00892383 RH	411	}
00892383 RH	412
7ea47fe7 PM	413	static inline uint32_t syn_swstep(int same_el, int isv, int ex)
	414	{
	415	return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
04ce861e	416	\| ARM_EL_IL \| (isv << 24) \| (ex << 6) \| 0x22;
7ea47fe7 PM	417	}
7ea47fe7 PM	418
3ff6fc91 PM	419	static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
	420	{
	421	return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
04ce861e	422	\| ARM_EL_IL \| (cm << 8) \| (wnr << 6) \| 0x22;
3ff6fc91 PM	423	}
3ff6fc91 PM	424
0eacea70 PM	425	static inline uint32_t syn_breakpoint(int same_el)
	426	{
	427	return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
	428	\| ARM_EL_IL \| 0x22;
	429	}
	430
58803318	431	static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
06fbb2fd GB	432	{
06fbb2fd GB	433	return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) \|
58803318	434	(is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) \|
06fbb2fd GB	435	(cv << 24) \| (cond << 20) \| ti;
	436	}
	437
9ee98ce8 PM	438	/* Update a QEMU watchpoint based on the information the guest has set in the
	439	* DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
	440	*/
	441	void hw_watchpoint_update(ARMCPU *cpu, int n);
	442	/* Update the QEMU watchpoints for every guest watchpoint. This does a
	443	* complete delete-and-reinstate of the QEMU watchpoint list and so is
	444	* suitable for use after migration or on reset.
	445	*/
	446	void hw_watchpoint_update_all(ARMCPU *cpu);
46747d15 PM	447	/* Update a QEMU breakpoint based on the information the guest has set in the
	448	* DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
	449	*/
	450	void hw_breakpoint_update(ARMCPU *cpu, int n);
	451	/* Update the QEMU breakpoints for every guest breakpoint. This does a
	452	* complete delete-and-reinstate of the QEMU breakpoint list and so is
	453	* suitable for use after migration or on reset.
	454	*/
	455	void hw_breakpoint_update_all(ARMCPU *cpu);
9ee98ce8	456
3826121d SF	457	/* Callback function for checking if a watchpoint should trigger. */
	458	bool arm_debug_check_watchpoint(CPUState cs, CPUWatchpoint wp);
	459
40612000 JB	460	/* Adjust addresses (in BE32 mode) before testing against watchpoint
	461	* addresses.
	462	*/
	463	vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
	464
3ff6fc91 PM	465	/* Callback function for when a watchpoint or breakpoint triggers. */
	466	void arm_debug_excp_handler(CPUState *cs);
	467
98128601 RH	468	#ifdef CONFIG_USER_ONLY
	469	static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
	470	{
	471	return false;
	472	}
	473	#else
	474	/* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
	475	bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
	476	/* Actually handle a PSCI call */
	477	void arm_handle_psci_call(ARMCPU *cpu);
	478	#endif
	479
dc3c4c14 PM	480	/**
	481	* arm_clear_exclusive: clear the exclusive monitor
	482	* @env: CPU env
	483	* Clear the CPU's exclusive monitor, like the guest CLREX instruction.
	484	*/
	485	static inline void arm_clear_exclusive(CPUARMState *env)
	486	{
	487	env->exclusive_addr = -1;
	488	}
	489
e14b5a23 EI	490	/**
	491	* ARMMMUFaultInfo: Information describing an ARM MMU Fault
	492	* @s2addr: Address that caused a fault at stage 2
	493	* @stage2: True if we faulted at stage 2
	494	* @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
c528af7a	495	* @ea: True if we should set the EA (external abort type) bit in syndrome
e14b5a23 EI	496	*/
	497	typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
	498	struct ARMMMUFaultInfo {
	499	target_ulong s2addr;
	500	bool stage2;
	501	bool s1ptw;
c528af7a	502	bool ea;
e14b5a23 EI	503	};
e14b5a23 EI	504
8c6084bf	505	/* Do a page table walk and add page to TLB if possible */
03ae85f8 PM	506	bool arm_tlb_fill(CPUState *cpu, vaddr address,
03ae85f8 PM	507	MMUAccessType access_type, int mmu_idx,
e14b5a23	508	uint32_t fsr, ARMMMUFaultInfo fi);
8c6084bf	509
deb2db99 AR	510	/* Return true if the stage 1 translation regime is using LPAE format page
	511	* tables */
	512	bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
30901475 AB	513
30901475 AB	514	/* Raise a data fault alignment exception for the specified virtual address */
b35399bb SS	515	void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
	516	MMUAccessType access_type,
	517	int mmu_idx, uintptr_t retaddr);
30901475	518
c79c0a31 PM	519	/* arm_cpu_do_transaction_failed: handle a memory system error response
	520	* (eg "no device/memory present at address") by raising an external abort
	521	* exception
	522	*/
	523	void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
	524	vaddr addr, unsigned size,
	525	MMUAccessType access_type,
	526	int mmu_idx, MemTxAttrs attrs,
	527	MemTxResult response, uintptr_t retaddr);
	528
bd7d00fc PM	529	/* Call the EL change hook if one has been registered */
	530	static inline void arm_call_el_change_hook(ARMCPU *cpu)
	531	{
	532	if (cpu->el_change_hook) {
	533	cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
	534	}
	535	}
	536
61fcd69b PM	537	/* Return true if this address translation regime is secure */
	538	static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
	539	{
	540	switch (mmu_idx) {
	541	case ARMMMUIdx_S12NSE0:
	542	case ARMMMUIdx_S12NSE1:
	543	case ARMMMUIdx_S1NSE0:
	544	case ARMMMUIdx_S1NSE1:
	545	case ARMMMUIdx_S1E2:
	546	case ARMMMUIdx_S2NS:
	547	case ARMMMUIdx_MPriv:
	548	case ARMMMUIdx_MNegPri:
	549	case ARMMMUIdx_MUser:
	550	return false;
	551	case ARMMMUIdx_S1E3:
	552	case ARMMMUIdx_S1SE0:
	553	case ARMMMUIdx_S1SE1:
	554	case ARMMMUIdx_MSPriv:
	555	case ARMMMUIdx_MSNegPri:
	556	case ARMMMUIdx_MSUser:
	557	return true;
	558	default:
	559	g_assert_not_reached();
	560	}
	561	}
	562
ccd38087	563	#endif