[qemu.git] / target-arm / internals.h

/*
 * QEMU ARM CPU -- internal functions and types
 *
 * Copyright (c) 2014 Linaro Ltd
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see
 * <http://www.gnu.org/licenses/gpl-2.0.html>
 *
 * This header defines functions, types, etc which need to be shared
 * between different source files within target-arm/ but which are
 * private to it and not required by the rest of QEMU.
 */

#ifndef TARGET_ARM_INTERNALS_H
#define TARGET_ARM_INTERNALS_H

static inline bool excp_is_internal(int excp)
{
    /* Return true if this exception number represents a QEMU-internal
     * exception that will not be passed to the guest.
     */
    return excp == EXCP_INTERRUPT
        || excp == EXCP_HLT
        || excp == EXCP_DEBUG
        || excp == EXCP_HALTED
        || excp == EXCP_EXCEPTION_EXIT
        || excp == EXCP_KERNEL_TRAP
        || excp == EXCP_STREX;
}

/* Exception names for debug logging; note that not all of these
 * precisely correspond to architectural exceptions.
 */
static const char * const excnames[] = {
    [EXCP_UDEF] = "Undefined Instruction",
    [EXCP_SWI] = "SVC",
    [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
    [EXCP_DATA_ABORT] = "Data Abort",
    [EXCP_IRQ] = "IRQ",
    [EXCP_FIQ] = "FIQ",
    [EXCP_BKPT] = "Breakpoint",
    [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
    [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
    [EXCP_STREX] = "QEMU intercept of STREX",
};

static inline void arm_log_exception(int idx)
{
    if (qemu_loglevel_mask(CPU_LOG_INT)) {
        const char *exc = NULL;

        if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
            exc = excnames[idx];
        }
        if (!exc) {
            exc = "unknown";
        }
        qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
    }
}

/* Scale factor for generic timers, ie number of ns per tick.
 * This gives a 62.5MHz timer.
 */
#define GTIMER_SCALE 16

/*
 * For AArch64, map a given EL to an index in the banked_spsr array.
 */
static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
{
    static const unsigned int map[4] = {
        [1] = 0, /* EL1.  */
        [2] = 6, /* EL2.  */
        [3] = 7, /* EL3.  */
    };
    assert(el >= 1 && el <= 3);
    return map[el];
}

int bank_number(int mode);
void switch_mode(CPUARMState *, int);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);

enum arm_fprounding {
    FPROUNDING_TIEEVEN,
    FPROUNDING_POSINF,
    FPROUNDING_NEGINF,
    FPROUNDING_ZERO,
    FPROUNDING_TIEAWAY,
    FPROUNDING_ODD
};

int arm_rmode_to_sf(int rmode);

static inline void aarch64_save_sp(CPUARMState *env, int el)
{
    if (env->pstate & PSTATE_SP) {
        env->sp_el[el] = env->xregs[31];
    } else {
        env->sp_el[0] = env->xregs[31];
    }
}

static inline void aarch64_restore_sp(CPUARMState *env, int el)
{
    if (env->pstate & PSTATE_SP) {
        env->xregs[31] = env->sp_el[el];
    } else {
        env->xregs[31] = env->sp_el[0];
    }
}

static inline void update_spsel(CPUARMState *env, uint32_t imm)
{
    unsigned int cur_el = arm_current_pl(env);
    /* Update PSTATE SPSel bit; this requires us to update the
     * working stack pointer in xregs[31].
     */
    if (!((imm ^ env->pstate) & PSTATE_SP)) {
        return;
    }
    aarch64_save_sp(env, cur_el);
    env->pstate = deposit32(env->pstate, 0, 1, imm);

    /* We rely on illegal updates to SPsel from EL0 to get trapped
     * at translation time.
     */
    assert(cur_el >= 1 && cur_el <= 3);
    aarch64_restore_sp(env, cur_el);
}

/* Return true if extended addresses are enabled.
 * This is always the case if our translation regime is 64 bit,
 * but depends on TTBCR.EAE for 32 bit.
 */
static inline bool extended_addresses_enabled(CPUARMState *env)
{
    return arm_el_is_aa64(env, 1)
        || ((arm_feature(env, ARM_FEATURE_LPAE)
             && (env->cp15.c2_control & TTBCR_EAE)));
}

/* Valid Syndrome Register EC field values */
enum arm_exception_class {
    EC_UNCATEGORIZED          = 0x00,
    EC_WFX_TRAP               = 0x01,
    EC_CP15RTTRAP             = 0x03,
    EC_CP15RRTTRAP            = 0x04,
    EC_CP14RTTRAP             = 0x05,
    EC_CP14DTTRAP             = 0x06,
    EC_ADVSIMDFPACCESSTRAP    = 0x07,
    EC_FPIDTRAP               = 0x08,
    EC_CP14RRTTRAP            = 0x0c,
    EC_ILLEGALSTATE           = 0x0e,
    EC_AA32_SVC               = 0x11,
    EC_AA32_HVC               = 0x12,
    EC_AA32_SMC               = 0x13,
    EC_AA64_SVC               = 0x15,
    EC_AA64_HVC               = 0x16,
    EC_AA64_SMC               = 0x17,
    EC_SYSTEMREGISTERTRAP     = 0x18,
    EC_INSNABORT              = 0x20,
    EC_INSNABORT_SAME_EL      = 0x21,
    EC_PCALIGNMENT            = 0x22,
    EC_DATAABORT              = 0x24,
    EC_DATAABORT_SAME_EL      = 0x25,
    EC_SPALIGNMENT            = 0x26,
    EC_AA32_FPTRAP            = 0x28,
    EC_AA64_FPTRAP            = 0x2c,
    EC_SERROR                 = 0x2f,
    EC_BREAKPOINT             = 0x30,
    EC_BREAKPOINT_SAME_EL     = 0x31,
    EC_SOFTWARESTEP           = 0x32,
    EC_SOFTWARESTEP_SAME_EL   = 0x33,
    EC_WATCHPOINT             = 0x34,
    EC_WATCHPOINT_SAME_EL     = 0x35,
    EC_AA32_BKPT              = 0x38,
    EC_VECTORCATCH            = 0x3a,
    EC_AA64_BKPT              = 0x3c,
};

#define ARM_EL_EC_SHIFT 26
#define ARM_EL_IL_SHIFT 25
#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)

/* Utility functions for constructing various kinds of syndrome value.
 * Note that in general we follow the AArch64 syndrome values; in a
 * few cases the value in HSR for exceptions taken to AArch32 Hyp
 * mode differs slightly, so if we ever implemented Hyp mode then the
 * syndrome value would need some massaging on exception entry.
 * (One example of this is that AArch64 defaults to IL bit set for
 * exceptions which don't specifically indicate information about the
 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 */
static inline uint32_t syn_uncategorized(void)
{
    return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
}

static inline uint32_t syn_aa64_svc(uint32_t imm16)
{
    return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
}

static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
{
    return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
        | (is_thumb ? 0 : ARM_EL_IL);
}

static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
{
    return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
}

static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
{
    return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
        | (is_thumb ? 0 : ARM_EL_IL);
}

static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
                                           int crn, int crm, int rt,
                                           int isread)
{
    return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
        | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
        | (crm << 1) | isread;
}

static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
                                        int crn, int crm, int rt, int isread,
                                        bool is_thumb)
{
    return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
        | (is_thumb ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
        | (crn << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
                                        int crn, int crm, int rt, int isread,
                                        bool is_thumb)
{
    return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
        | (is_thumb ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
        | (crn << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
                                         int rt, int rt2, int isread,
                                         bool is_thumb)
{
    return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
        | (is_thumb ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc1 << 16)
        | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
                                         int rt, int rt2, int isread,
                                         bool is_thumb)
{
    return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
        | (is_thumb ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20) | (opc1 << 16)
        | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
}

static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
{
    return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
        | (is_thumb ? 0 : ARM_EL_IL)
        | (cv << 24) | (cond << 20);
}

static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
{
    return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | (ea << 9) | (s1ptw << 7) | fsc;
}

static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
                                      int wnr, int fsc)
{
    return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
}

static inline uint32_t syn_swstep(int same_el, int isv, int ex)
{
    return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | (isv << 24) | (ex << 6) | 0x22;
}

static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
{
    return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | (cm << 8) | (wnr << 6) | 0x22;
}

static inline uint32_t syn_breakpoint(int same_el)
{
    return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
        | ARM_EL_IL | 0x22;
}

/* Update a QEMU watchpoint based on the information the guest has set in the
 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 */
void hw_watchpoint_update(ARMCPU *cpu, int n);
/* Update the QEMU watchpoints for every guest watchpoint. This does a
 * complete delete-and-reinstate of the QEMU watchpoint list and so is
 * suitable for use after migration or on reset.
 */
void hw_watchpoint_update_all(ARMCPU *cpu);
/* Update a QEMU breakpoint based on the information the guest has set in the
 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 */
void hw_breakpoint_update(ARMCPU *cpu, int n);
/* Update the QEMU breakpoints for every guest breakpoint. This does a
 * complete delete-and-reinstate of the QEMU breakpoint list and so is
 * suitable for use after migration or on reset.
 */
void hw_breakpoint_update_all(ARMCPU *cpu);

/* Callback function for when a watchpoint or breakpoint triggers. */
void arm_debug_excp_handler(CPUState *cs);

#endif
Commit	Line	Data
ccd38087 PM	1	/*
	2	* QEMU ARM CPU -- internal functions and types
	3	*
	4	* Copyright (c) 2014 Linaro Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see
	18	* <http://www.gnu.org/licenses/gpl-2.0.html>
	19	*
	20	* This header defines functions, types, etc which need to be shared
	21	* between different source files within target-arm/ but which are
	22	* private to it and not required by the rest of QEMU.
	23	*/
	24
	25	#ifndef TARGET_ARM_INTERNALS_H
	26	#define TARGET_ARM_INTERNALS_H
	27
d4a2dc67 PM	28	static inline bool excp_is_internal(int excp)
	29	{
	30	/* Return true if this exception number represents a QEMU-internal
	31	* exception that will not be passed to the guest.
	32	*/
	33	return excp == EXCP_INTERRUPT
	34	\|\| excp == EXCP_HLT
	35	\|\| excp == EXCP_DEBUG
	36	\|\| excp == EXCP_HALTED
	37	\|\| excp == EXCP_EXCEPTION_EXIT
	38	\|\| excp == EXCP_KERNEL_TRAP
	39	\|\| excp == EXCP_STREX;
	40	}
	41
2f2a00ae PM	42	/* Exception names for debug logging; note that not all of these
	43	* precisely correspond to architectural exceptions.
	44	*/
	45	static const char * const excnames[] = {
	46	[EXCP_UDEF] = "Undefined Instruction",
	47	[EXCP_SWI] = "SVC",
	48	[EXCP_PREFETCH_ABORT] = "Prefetch Abort",
	49	[EXCP_DATA_ABORT] = "Data Abort",
	50	[EXCP_IRQ] = "IRQ",
	51	[EXCP_FIQ] = "FIQ",
	52	[EXCP_BKPT] = "Breakpoint",
	53	[EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
	54	[EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
	55	[EXCP_STREX] = "QEMU intercept of STREX",
	56	};
	57
	58	static inline void arm_log_exception(int idx)
	59	{
	60	if (qemu_loglevel_mask(CPU_LOG_INT)) {
	61	const char *exc = NULL;
	62
	63	if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
	64	exc = excnames[idx];
	65	}
	66	if (!exc) {
	67	exc = "unknown";
	68	}
	69	qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
	70	}
	71	}
	72
ccd38087 PM	73	/* Scale factor for generic timers, ie number of ns per tick.
	74	* This gives a 62.5MHz timer.
	75	*/
	76	#define GTIMER_SCALE 16
	77
2a923c4d EI	78	/*
	79	* For AArch64, map a given EL to an index in the banked_spsr array.
	80	*/
	81	static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
	82	{
	83	static const unsigned int map[4] = {
	84	[1] = 0, /* EL1. */
	85	[2] = 6, /* EL2. */
	86	[3] = 7, /* EL3. */
	87	};
	88	assert(el >= 1 && el <= 3);
	89	return map[el];
	90	}
	91
ccd38087 PM	92	int bank_number(int mode);
	93	void switch_mode(CPUARMState *, int);
	94	void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
	95	void arm_translate_init(void);
	96
	97	enum arm_fprounding {
	98	FPROUNDING_TIEEVEN,
	99	FPROUNDING_POSINF,
	100	FPROUNDING_NEGINF,
	101	FPROUNDING_ZERO,
	102	FPROUNDING_TIEAWAY,
	103	FPROUNDING_ODD
	104	};
	105
	106	int arm_rmode_to_sf(int rmode);
	107
9208b961 EI	108	static inline void aarch64_save_sp(CPUARMState *env, int el)
	109	{
	110	if (env->pstate & PSTATE_SP) {
	111	env->sp_el[el] = env->xregs[31];
	112	} else {
	113	env->sp_el[0] = env->xregs[31];
	114	}
	115	}
	116
	117	static inline void aarch64_restore_sp(CPUARMState *env, int el)
	118	{
	119	if (env->pstate & PSTATE_SP) {
	120	env->xregs[31] = env->sp_el[el];
	121	} else {
	122	env->xregs[31] = env->sp_el[0];
	123	}
	124	}
	125
f502cfc2 PM	126	static inline void update_spsel(CPUARMState *env, uint32_t imm)
f502cfc2 PM	127	{
61d4b215	128	unsigned int cur_el = arm_current_pl(env);
f502cfc2 PM	129	/* Update PSTATE SPSel bit; this requires us to update the
	130	* working stack pointer in xregs[31].
	131	*/
	132	if (!((imm ^ env->pstate) & PSTATE_SP)) {
	133	return;
	134	}
9208b961	135	aarch64_save_sp(env, cur_el);
f502cfc2 PM	136	env->pstate = deposit32(env->pstate, 0, 1, imm);
f502cfc2 PM	137
61d4b215 EI	138	/* We rely on illegal updates to SPsel from EL0 to get trapped
61d4b215 EI	139	* at translation time.
f502cfc2	140	*/
61d4b215	141	assert(cur_el >= 1 && cur_el <= 3);
9208b961	142	aarch64_restore_sp(env, cur_el);
f502cfc2 PM	143	}
f502cfc2 PM	144
73c5211b PM	145	/* Return true if extended addresses are enabled.
	146	* This is always the case if our translation regime is 64 bit,
	147	* but depends on TTBCR.EAE for 32 bit.
	148	*/
	149	static inline bool extended_addresses_enabled(CPUARMState *env)
	150	{
	151	return arm_el_is_aa64(env, 1)
	152	\|\| ((arm_feature(env, ARM_FEATURE_LPAE)
	153	&& (env->cp15.c2_control & TTBCR_EAE)));
	154	}
	155
8bcbf37c PM	156	/* Valid Syndrome Register EC field values */
	157	enum arm_exception_class {
	158	EC_UNCATEGORIZED = 0x00,
	159	EC_WFX_TRAP = 0x01,
	160	EC_CP15RTTRAP = 0x03,
	161	EC_CP15RRTTRAP = 0x04,
	162	EC_CP14RTTRAP = 0x05,
	163	EC_CP14DTTRAP = 0x06,
	164	EC_ADVSIMDFPACCESSTRAP = 0x07,
	165	EC_FPIDTRAP = 0x08,
	166	EC_CP14RRTTRAP = 0x0c,
	167	EC_ILLEGALSTATE = 0x0e,
	168	EC_AA32_SVC = 0x11,
	169	EC_AA32_HVC = 0x12,
	170	EC_AA32_SMC = 0x13,
	171	EC_AA64_SVC = 0x15,
	172	EC_AA64_HVC = 0x16,
	173	EC_AA64_SMC = 0x17,
	174	EC_SYSTEMREGISTERTRAP = 0x18,
	175	EC_INSNABORT = 0x20,
	176	EC_INSNABORT_SAME_EL = 0x21,
	177	EC_PCALIGNMENT = 0x22,
	178	EC_DATAABORT = 0x24,
	179	EC_DATAABORT_SAME_EL = 0x25,
	180	EC_SPALIGNMENT = 0x26,
	181	EC_AA32_FPTRAP = 0x28,
	182	EC_AA64_FPTRAP = 0x2c,
	183	EC_SERROR = 0x2f,
	184	EC_BREAKPOINT = 0x30,
	185	EC_BREAKPOINT_SAME_EL = 0x31,
	186	EC_SOFTWARESTEP = 0x32,
	187	EC_SOFTWARESTEP_SAME_EL = 0x33,
	188	EC_WATCHPOINT = 0x34,
	189	EC_WATCHPOINT_SAME_EL = 0x35,
	190	EC_AA32_BKPT = 0x38,
	191	EC_VECTORCATCH = 0x3a,
	192	EC_AA64_BKPT = 0x3c,
	193	};
	194
	195	#define ARM_EL_EC_SHIFT 26
	196	#define ARM_EL_IL_SHIFT 25
	197	#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
	198
	199	/* Utility functions for constructing various kinds of syndrome value.
	200	* Note that in general we follow the AArch64 syndrome values; in a
	201	* few cases the value in HSR for exceptions taken to AArch32 Hyp
	202	* mode differs slightly, so if we ever implemented Hyp mode then the
	203	* syndrome value would need some massaging on exception entry.
	204	* (One example of this is that AArch64 defaults to IL bit set for
	205	* exceptions which don't specifically indicate information about the
	206	* trapping instruction, whereas AArch32 defaults to IL bit clear.)
	207	*/
	208	static inline uint32_t syn_uncategorized(void)
	209	{
	210	return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) \| ARM_EL_IL;
	211	}
	212
	213	static inline uint32_t syn_aa64_svc(uint32_t imm16)
	214	{
	215	return (EC_AA64_SVC << ARM_EL_EC_SHIFT) \| ARM_EL_IL \| (imm16 & 0xffff);
	216	}
	217
	218	static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
	219	{
220	return (EC_AA32_SVC << ARM_EL_EC_SHIFT) \| (imm16 & 0xffff)
221	\| (is_thumb ? 0 : ARM_EL_IL);
222	}
223
224	static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
225	{
226	return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) \| ARM_EL_IL \| (imm16 & 0xffff);
227	}
228
229	static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
230	{
231	return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) \| (imm16 & 0xffff)
232	\| (is_thumb ? 0 : ARM_EL_IL);
233	}
234
235	static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
236	int crn, int crm, int rt,
237	int isread)
238	{
239	return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) \| ARM_EL_IL
240	\| (op0 << 20) \| (op2 << 17) \| (op1 << 14) \| (crn << 10) \| (rt << 5)
241	\| (crm << 1) \| isread;
242	}
243
244	static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
245	int crn, int crm, int rt, int isread,
246	bool is_thumb)
247	{
248	return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
249	\| (is_thumb ? 0 : ARM_EL_IL)
250	\| (cv << 24) \| (cond << 20) \| (opc2 << 17) \| (opc1 << 14)
251	\| (crn << 10) \| (rt << 5) \| (crm << 1) \| isread;
252	}
253
254	static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
255	int crn, int crm, int rt, int isread,
256	bool is_thumb)
257	{
258	return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
259	\| (is_thumb ? 0 : ARM_EL_IL)
260	\| (cv << 24) \| (cond << 20) \| (opc2 << 17) \| (opc1 << 14)
261	\| (crn << 10) \| (rt << 5) \| (crm << 1) \| isread;
262	}
263
264	static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
265	int rt, int rt2, int isread,
266	bool is_thumb)
267	{
268	return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
269	\| (is_thumb ? 0 : ARM_EL_IL)
270	\| (cv << 24) \| (cond << 20) \| (opc1 << 16)
271	\| (rt2 << 10) \| (rt << 5) \| (crm << 1) \| isread;
272	}
273
274	static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
275	int rt, int rt2, int isread,
276	bool is_thumb)
277	{
278	return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
279	\| (is_thumb ? 0 : ARM_EL_IL)
280	\| (cv << 24) \| (cond << 20) \| (opc1 << 16)
281	\| (rt2 << 10) \| (rt << 5) \| (crm << 1) \| isread;
282	}
283
8c6afa6a PM	284	static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
	285	{
	286	return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
	287	\| (is_thumb ? 0 : ARM_EL_IL)
	288	\| (cv << 24) \| (cond << 20);
	289	}
	290
00892383 RH	291	static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
	292	{
	293	return (EC_INSNABORT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
	294	\| (ea << 9) \| (s1ptw << 7) \| fsc;
	295	}
	296
	297	static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
	298	int wnr, int fsc)
	299	{
	300	return (EC_DATAABORT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
	301	\| (ea << 9) \| (cm << 8) \| (s1ptw << 7) \| (wnr << 6) \| fsc;
	302	}
	303
7ea47fe7 PM	304	static inline uint32_t syn_swstep(int same_el, int isv, int ex)
	305	{
	306	return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
	307	\| (isv << 24) \| (ex << 6) \| 0x22;
	308	}
	309
3ff6fc91 PM	310	static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
	311	{
	312	return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
	313	\| (cm << 8) \| (wnr << 6) \| 0x22;
	314	}
	315
0eacea70 PM	316	static inline uint32_t syn_breakpoint(int same_el)
	317	{
	318	return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) \| (same_el << ARM_EL_EC_SHIFT)
	319	\| ARM_EL_IL \| 0x22;
	320	}
	321
9ee98ce8 PM	322	/* Update a QEMU watchpoint based on the information the guest has set in the
	323	* DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
	324	*/
	325	void hw_watchpoint_update(ARMCPU *cpu, int n);
	326	/* Update the QEMU watchpoints for every guest watchpoint. This does a
	327	* complete delete-and-reinstate of the QEMU watchpoint list and so is
	328	* suitable for use after migration or on reset.
	329	*/
	330	void hw_watchpoint_update_all(ARMCPU *cpu);
46747d15 PM	331	/* Update a QEMU breakpoint based on the information the guest has set in the
	332	* DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
	333	*/
	334	void hw_breakpoint_update(ARMCPU *cpu, int n);
	335	/* Update the QEMU breakpoints for every guest breakpoint. This does a
	336	* complete delete-and-reinstate of the QEMU breakpoint list and so is
	337	* suitable for use after migration or on reset.
	338	*/
	339	void hw_breakpoint_update_all(ARMCPU *cpu);
9ee98ce8	340
3ff6fc91 PM	341	/* Callback function for when a watchpoint or breakpoint triggers. */
	342	void arm_debug_excp_handler(CPUState *cs);
	343
ccd38087	344	#endif