]> Git Repo - qemu.git/blame - hw/net/rtl8139.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qdev: set properties with device_class_set_props()
[qemu.git] / hw / net / rtl8139.c
CommitLineData
a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
b6af0975 46 * when strictly needed (required for
05447803 47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f 51/* For crc32 */
0b8fa32f 52
e8d40465 53#include "qemu/osdep.h"
2c406b8f
BP		 54#include <zlib.h>
55
83c9f4ca 56#include "hw/pci/pci.h"
a27bd6c7 57#include "hw/qdev-properties.h"
d6454270 58#include "migration/vmstate.h"
9c17d615 59#include "sysemu/dma.h"
0b8fa32f 60#include "qemu/module.h"
1de7afc9 61#include "qemu/timer.h"
1422e32d 62#include "net/net.h"
5d61721a 63#include "net/eth.h"
9c17d615 64#include "sysemu/sysemu.h"
a41b2ff2 65
a41b2ff2
PB		 66/* debug RTL8139 card */
67//#define DEBUG_RTL8139 1
68
37b9ab92 69#define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */
6cadb320 70
a41b2ff2
PB		 71#define SET_MASKED(input, mask, curr) \
72 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
73
74/* arg % size for size which is a power of 2 */
75#define MOD2(input, size) \
76 ( ( input ) & ( size - 1 ) )
77
18dabfd1 78#define ETHER_TYPE_LEN 2
18dabfd1
BP		 79#define ETH_MTU 1500
80
81#define VLAN_TCI_LEN 2
82#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
83
6cadb320 84#if defined (DEBUG_RTL8139)
7cdeb319
BP		 85# define DPRINTF(fmt, ...) \
86 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 87#else
c6a0487b 88static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 89{
90 return 0;
91}
6cadb320
FB		 92#endif
93
39257515
PC		 94#define TYPE_RTL8139 "rtl8139"
95
96#define RTL8139(obj) \
97 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139)
98
a41b2ff2
PB		 99/* Symbolic offsets to registers. */
100enum RTL8139_registers {
101 MAC0 = 0, /* Ethernet hardware address. */
102 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 103 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
104 /* Dump Tally Conter control register(64bit). C+ mode only */
105 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 106 RxBuf = 0x30,
107 ChipCmd = 0x37,
108 RxBufPtr = 0x38,
109 RxBufAddr = 0x3A,
110 IntrMask = 0x3C,
111 IntrStatus = 0x3E,
112 TxConfig = 0x40,
113 RxConfig = 0x44,
114 Timer = 0x48, /* A general-purpose counter. */
115 RxMissed = 0x4C, /* 24 bits valid, write clears. */
116 Cfg9346 = 0x50,
117 Config0 = 0x51,
118 Config1 = 0x52,
119 FlashReg = 0x54,
120 MediaStatus = 0x58,
121 Config3 = 0x59,
122 Config4 = 0x5A, /* absent on RTL-8139A */
123 HltClk = 0x5B,
124 MultiIntr = 0x5C,
125 PCIRevisionID = 0x5E,
126 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
127 BasicModeCtrl = 0x62,
128 BasicModeStatus = 0x64,
129 NWayAdvert = 0x66,
130 NWayLPAR = 0x68,
131 NWayExpansion = 0x6A,
132 /* Undocumented registers, but required for proper operation. */
133 FIFOTMS = 0x70, /* FIFO Control and test. */
134 CSCR = 0x74, /* Chip Status and Configuration Register. */
135 PARA78 = 0x78,
136 PARA7c = 0x7c, /* Magic transceiver parameter register. */
137 Config5 = 0xD8, /* absent on RTL-8139A */
138 /* C+ mode */
139 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
140 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
141 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
142 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
143 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
144 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
145 TxThresh = 0xEC, /* Early Tx threshold */
146};
147
148enum ClearBitMasks {
149 MultiIntrClear = 0xF000,
150 ChipCmdClear = 0xE2,
151 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
152};
153
154enum ChipCmdBits {
155 CmdReset = 0x10,
156 CmdRxEnb = 0x08,
157 CmdTxEnb = 0x04,
158 RxBufEmpty = 0x01,
159};
160
161/* C+ mode */
162enum CplusCmdBits {
6cadb320
FB		 163 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
164 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
165 CPlusRxEnb = 0x0002,
166 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 167};
168
169/* Interrupt register bits, using my own meaningful names. */
170enum IntrStatusBits {
171 PCIErr = 0x8000,
172 PCSTimeout = 0x4000,
173 RxFIFOOver = 0x40,
9e12c5af 174 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
a41b2ff2
PB		 175 RxOverflow = 0x10,
176 TxErr = 0x08,
177 TxOK = 0x04,
178 RxErr = 0x02,
179 RxOK = 0x01,
180
181 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
182};
183
184enum TxStatusBits {
185 TxHostOwns = 0x2000,
186 TxUnderrun = 0x4000,
187 TxStatOK = 0x8000,
188 TxOutOfWindow = 0x20000000,
189 TxAborted = 0x40000000,
190 TxCarrierLost = 0x80000000,
191};
192enum RxStatusBits {
193 RxMulticast = 0x8000,
194 RxPhysical = 0x4000,
195 RxBroadcast = 0x2000,
196 RxBadSymbol = 0x0020,
197 RxRunt = 0x0010,
198 RxTooLong = 0x0008,
199 RxCRCErr = 0x0004,
200 RxBadAlign = 0x0002,
201 RxStatusOK = 0x0001,
202};
203
204/* Bits in RxConfig. */
205enum rx_mode_bits {
206 AcceptErr = 0x20,
207 AcceptRunt = 0x10,
208 AcceptBroadcast = 0x08,
209 AcceptMulticast = 0x04,
210 AcceptMyPhys = 0x02,
211 AcceptAllPhys = 0x01,
212};
213
214/* Bits in TxConfig. */
215enum tx_config_bits {
216
217 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
218 TxIFGShift = 24,
219 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
220 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
221 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
222 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
223
224 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
225 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
226 TxClearAbt = (1 << 0), /* Clear abort (WO) */
227 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
228 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
229
230 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
231};
232
233
234/* Transmit Status of All Descriptors (TSAD) Register */
235enum TSAD_bits {
236 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
237 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
238 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
239 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
240 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
241 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
242 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
243 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
244 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
245 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
246 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
247 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
248 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
249 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
250 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
251 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
252};
253
254
255/* Bits in Config1 */
256enum Config1Bits {
257 Cfg1_PM_Enable = 0x01,
258 Cfg1_VPD_Enable = 0x02,
259 Cfg1_PIO = 0x04,
260 Cfg1_MMIO = 0x08,
261 LWAKE = 0x10, /* not on 8139, 8139A */
262 Cfg1_Driver_Load = 0x20,
263 Cfg1_LED0 = 0x40,
264 Cfg1_LED1 = 0x80,
265 SLEEP = (1 << 1), /* only on 8139, 8139A */
266 PWRDN = (1 << 0), /* only on 8139, 8139A */
267};
268
269/* Bits in Config3 */
270enum Config3Bits {
271 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
272 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
273 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
274 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
275 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
276 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
277 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
278 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
279};
280
281/* Bits in Config4 */
282enum Config4Bits {
283 LWPTN = (1 << 2), /* not on 8139, 8139A */
284};
285
286/* Bits in Config5 */
287enum Config5Bits {
288 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
289 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
290 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
291 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
292 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
293 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
294 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
295};
296
297enum RxConfigBits {
298 /* rx fifo threshold */
299 RxCfgFIFOShift = 13,
300 RxCfgFIFONone = (7 << RxCfgFIFOShift),
301
302 /* Max DMA burst */
303 RxCfgDMAShift = 8,
304 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
305
306 /* rx ring buffer length */
307 RxCfgRcv8K = 0,
308 RxCfgRcv16K = (1 << 11),
309 RxCfgRcv32K = (1 << 12),
310 RxCfgRcv64K = (1 << 11) | (1 << 12),
311
312 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
313 RxNoWrap = (1 << 7),
314};
315
316/* Twister tuning parameters from RealTek.
317 Completely undocumented, but required to tune bad links on some boards. */
318/*
319enum CSCRBits {
320 CSCR_LinkOKBit = 0x0400,
321 CSCR_LinkChangeBit = 0x0800,
322 CSCR_LinkStatusBits = 0x0f000,
323 CSCR_LinkDownOffCmd = 0x003c0,
324 CSCR_LinkDownCmd = 0x0f3c0,
325*/
326enum CSCRBits {
5fafdf24 327 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 328 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
329 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
330 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 331 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 332 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
333 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
334 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
335 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
336};
337
338enum Cfg9346Bits {
eb46c5ed
JW		 339 Cfg9346_Normal = 0x00,
340 Cfg9346_Autoload = 0x40,
341 Cfg9346_Programming = 0x80,
342 Cfg9346_ConfigWrite = 0xC0,
a41b2ff2
PB		 343};
344
345typedef enum {
346 CH_8139 = 0,
347 CH_8139_K,
348 CH_8139A,
349 CH_8139A_G,
350 CH_8139B,
351 CH_8130,
352 CH_8139C,
353 CH_8100,
354 CH_8100B_8139D,
355 CH_8101,
c227f099 356} chip_t;
a41b2ff2
PB		 357
358enum chip_flags {
359 HasHltClk = (1 << 0),
360 HasLWake = (1 << 1),
361};
362
363#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
364 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
365#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
366
6cadb320
FB		 367#define RTL8139_PCI_REVID_8139 0x10
368#define RTL8139_PCI_REVID_8139CPLUS 0x20
369
370#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
371
a41b2ff2
PB		 372/* Size is 64 * 16bit words */
373#define EEPROM_9346_ADDR_BITS 6
374#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
375#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
376
377enum Chip9346Operation
378{
379 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
380 Chip9346_op_read = 0x80, /* 10 AAAAAA */
381 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
382 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
383 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
384 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
385 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
386};
387
388enum Chip9346Mode
389{
390 Chip9346_none = 0,
391 Chip9346_enter_command_mode,
392 Chip9346_read_command,
393 Chip9346_data_read, /* from output register */
394 Chip9346_data_write, /* to input register, then to contents at specified address */
395 Chip9346_data_write_all, /* to input register, then filling contents */
396};
397
398typedef struct EEprom9346
399{
400 uint16_t contents[EEPROM_9346_SIZE];
401 int mode;
402 uint32_t tick;
403 uint8_t address;
404 uint16_t input;
405 uint16_t output;
406
407 uint8_t eecs;
408 uint8_t eesk;
409 uint8_t eedi;
410 uint8_t eedo;
411} EEprom9346;
412
6cadb320
FB		 413typedef struct RTL8139TallyCounters
414{
415 /* Tally counters */
416 uint64_t TxOk;
417 uint64_t RxOk;
418 uint64_t TxERR;
419 uint32_t RxERR;
420 uint16_t MissPkt;
421 uint16_t FAE;
422 uint32_t Tx1Col;
423 uint32_t TxMCol;
424 uint64_t RxOkPhy;
425 uint64_t RxOkBrd;
426 uint32_t RxOkMul;
427 uint16_t TxAbt;
428 uint16_t TxUndrn;
429} RTL8139TallyCounters;
430
431/* Clears all tally counters */
432static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
433
a41b2ff2 434typedef struct RTL8139State {
88a411a8
AF		 435 /*< private >*/
436 PCIDevice parent_obj;
437 /*< public >*/
438
a41b2ff2
PB		 439 uint8_t phys[8]; /* mac address */
440 uint8_t mult[8]; /* multicast mask array */
441
6cadb320 442 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 443 uint32_t TxAddr[4]; /* TxAddr0 */
444 uint32_t RxBuf; /* Receive buffer */
445 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
446 uint32_t RxBufPtr;
447 uint32_t RxBufAddr;
448
449 uint16_t IntrStatus;
450 uint16_t IntrMask;
451
452 uint32_t TxConfig;
453 uint32_t RxConfig;
454 uint32_t RxMissed;
455
456 uint16_t CSCR;
457
458 uint8_t Cfg9346;
459 uint8_t Config0;
460 uint8_t Config1;
461 uint8_t Config3;
462 uint8_t Config4;
463 uint8_t Config5;
464
465 uint8_t clock_enabled;
466 uint8_t bChipCmdState;
467
468 uint16_t MultiIntr;
469
470 uint16_t BasicModeCtrl;
471 uint16_t BasicModeStatus;
472 uint16_t NWayAdvert;
473 uint16_t NWayLPAR;
474 uint16_t NWayExpansion;
475
476 uint16_t CpCmd;
477 uint8_t TxThresh;
478
1673ad51 479 NICState *nic;
254111ec 480 NICConf conf;
a41b2ff2
PB		 481
482 /* C ring mode */
483 uint32_t currTxDesc;
484
485 /* C+ mode */
2c3891ab
AL		 486 uint32_t cplus_enabled;
487
a41b2ff2
PB		 488 uint32_t currCPlusRxDesc;
489 uint32_t currCPlusTxDesc;
490
491 uint32_t RxRingAddrLO;
492 uint32_t RxRingAddrHI;
493
494 EEprom9346 eeprom;
6cadb320
FB		 495
496 uint32_t TCTR;
497 uint32_t TimerInt;
498 int64_t TCTR_base;
499
500 /* Tally counters */
501 RTL8139TallyCounters tally_counters;
502
503 /* Non-persistent data */
504 uint8_t *cplus_txbuffer;
505 int cplus_txbuffer_len;
506 int cplus_txbuffer_offset;
507
508 /* PCI interrupt timer */
509 QEMUTimer *timer;
510
bd80f3fc
AK		 511 MemoryRegion bar_io;
512 MemoryRegion bar_mem;
513
c574ba5a
AW		 514 /* Support migration to/from old versions */
515 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 516} RTL8139State;
517
3ada003a
EGM		 518/* Writes tally counters to memory via DMA */
519static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
520
237c255c 521static void rtl8139_set_next_tctr_time(RTL8139State *s);
05447803 522
9596ebb7 523static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 524{
7cdeb319 525 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 526
527 switch (command & Chip9346_op_mask)
528 {
529 case Chip9346_op_read:
530 {
531 eeprom->address = command & EEPROM_9346_ADDR_MASK;
532 eeprom->output = eeprom->contents[eeprom->address];
533 eeprom->eedo = 0;
534 eeprom->tick = 0;
535 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 536 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
537 eeprom->address, eeprom->output);
a41b2ff2
PB		 538 }
539 break;
540
541 case Chip9346_op_write:
542 {
543 eeprom->address = command & EEPROM_9346_ADDR_MASK;
544 eeprom->input = 0;
545 eeprom->tick = 0;
546 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 547 DPRINTF("eeprom begin write to address 0x%02x\n",
548 eeprom->address);
a41b2ff2
PB		 549 }
550 break;
551 default:
552 eeprom->mode = Chip9346_none;
553 switch (command & Chip9346_op_ext_mask)
554 {
555 case Chip9346_op_write_enable:
7cdeb319 556 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 557 break;
558 case Chip9346_op_write_all:
7cdeb319 559 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 560 break;
561 case Chip9346_op_write_disable:
7cdeb319 562 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 563 break;
564 }
565 break;
566 }
567}
568
9596ebb7 569static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 570{
571 int bit = eeprom->eedi?1:0;
572
573 ++ eeprom->tick;
574
7cdeb319
BP		 575 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
576 eeprom->eedo);
a41b2ff2
PB		 577
578 switch (eeprom->mode)
579 {
580 case Chip9346_enter_command_mode:
581 if (bit)
582 {
583 eeprom->mode = Chip9346_read_command;
584 eeprom->tick = 0;
585 eeprom->input = 0;
7cdeb319 586 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 587 }
588 break;
589
590 case Chip9346_read_command:
591 eeprom->input = (eeprom->input << 1) | (bit & 1);
592 if (eeprom->tick == 8)
593 {
594 prom9346_decode_command(eeprom, eeprom->input & 0xff);
595 }
596 break;
597
598 case Chip9346_data_read:
599 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
600 eeprom->output <<= 1;
601 if (eeprom->tick == 16)
602 {
6cadb320
FB		 603#if 1
604 // the FreeBSD drivers (rl and re) don't explicitly toggle
605 // CS between reads (or does setting Cfg9346 to 0 count too?),
606 // so we need to enter wait-for-command state here
607 eeprom->mode = Chip9346_enter_command_mode;
608 eeprom->input = 0;
609 eeprom->tick = 0;
610
7cdeb319 611 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 612#else
613 // original behaviour
a41b2ff2
PB		 614 ++eeprom->address;
615 eeprom->address &= EEPROM_9346_ADDR_MASK;
616 eeprom->output = eeprom->contents[eeprom->address];
617 eeprom->tick = 0;
618
7cdeb319
BP		 619 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
620 eeprom->address, eeprom->output);
a41b2ff2
PB		 621#endif
622 }
623 break;
624
625 case Chip9346_data_write:
626 eeprom->input = (eeprom->input << 1) | (bit & 1);
627 if (eeprom->tick == 16)
628 {
7cdeb319
BP		 629 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
630 eeprom->address, eeprom->input);
6cadb320 631
a41b2ff2
PB		 632 eeprom->contents[eeprom->address] = eeprom->input;
633 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
634 eeprom->tick = 0;
635 eeprom->input = 0;
636 }
637 break;
638
639 case Chip9346_data_write_all:
640 eeprom->input = (eeprom->input << 1) | (bit & 1);
641 if (eeprom->tick == 16)
642 {
643 int i;
644 for (i = 0; i < EEPROM_9346_SIZE; i++)
645 {
646 eeprom->contents[i] = eeprom->input;
647 }
7cdeb319 648 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 649
a41b2ff2
PB		 650 eeprom->mode = Chip9346_enter_command_mode;
651 eeprom->tick = 0;
652 eeprom->input = 0;
653 }
654 break;
655
656 default:
657 break;
658 }
659}
660
9596ebb7 661static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 662{
663 EEprom9346 *eeprom = &s->eeprom;
664 if (!eeprom->eecs)
665 return 0;
666
667 return eeprom->eedo;
668}
669
9596ebb7
PB		 670/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
671static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 672{
673 EEprom9346 *eeprom = &s->eeprom;
674 uint8_t old_eecs = eeprom->eecs;
675 uint8_t old_eesk = eeprom->eesk;
676
677 eeprom->eecs = eecs;
678 eeprom->eesk = eesk;
679 eeprom->eedi = eedi;
680
7cdeb319
BP		 681 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
682 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 683
684 if (!old_eecs && eecs)
685 {
686 /* Synchronize start */
687 eeprom->tick = 0;
688 eeprom->input = 0;
689 eeprom->output = 0;
690 eeprom->mode = Chip9346_enter_command_mode;
691
7cdeb319 692 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 693 }
694
695 if (!eecs)
696 {
7cdeb319 697 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 698 return;
699 }
700
701 if (!old_eesk && eesk)
702 {
703 /* SK front rules */
704 prom9346_shift_clock(eeprom);
705 }
706}
707
708static void rtl8139_update_irq(RTL8139State *s)
709{
88a411a8 710 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 711 int isr;
712 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 713
7cdeb319
BP		 714 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
715 s->IntrMask);
6cadb320 716
9e64f8a3 717 pci_set_irq(d, (isr != 0));
a41b2ff2
PB		 718}
719
a41b2ff2
PB		 720static int rtl8139_RxWrap(RTL8139State *s)
721{
722 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
723 return (s->RxConfig & (1 << 7));
724}
725
726static int rtl8139_receiver_enabled(RTL8139State *s)
727{
728 return s->bChipCmdState & CmdRxEnb;
729}
730
731static int rtl8139_transmitter_enabled(RTL8139State *s)
732{
733 return s->bChipCmdState & CmdTxEnb;
734}
735
736static int rtl8139_cp_receiver_enabled(RTL8139State *s)
737{
738 return s->CpCmd & CPlusRxEnb;
739}
740
741static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
742{
743 return s->CpCmd & CPlusTxEnb;
744}
745
746static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
747{
88a411a8
AF		 748 PCIDevice *d = PCI_DEVICE(s);
749
a41b2ff2
PB		 750 if (s->RxBufAddr + size > s->RxBufferSize)
751 {
752 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
753
754 /* write packet data */
ccf1d14a 755 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 756 {
7cdeb319 757 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 758
759 if (size > wrapped)
760 {
88a411a8 761 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
3ada003a 762 buf, size-wrapped);
a41b2ff2
PB		 763 }
764
765 /* reset buffer pointer */
766 s->RxBufAddr = 0;
767
88a411a8 768 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
3ada003a 769 buf + (size-wrapped), wrapped);
a41b2ff2
PB		 770
771 s->RxBufAddr = wrapped;
772
773 return;
774 }
775 }
776
777 /* non-wrapping path or overwrapping enabled */
88a411a8 778 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
a41b2ff2
PB		 779
780 s->RxBufAddr += size;
781}
782
783#define MIN_BUF_SIZE 60
3ada003a 784static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2 785{
4be403c8 786 return low | ((uint64_t)high << 32);
a41b2ff2
PB		 787}
788
fcce6fd2
JW		 789/* Workaround for buggy guest driver such as linux who allocates rx
790 * rings after the receiver were enabled. */
791static bool rtl8139_cp_rx_valid(RTL8139State *s)
792{
793 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
794}
795
4e68f7a0 796static int rtl8139_can_receive(NetClientState *nc)
a41b2ff2 797{
cc1f0f45 798 RTL8139State *s = qemu_get_nic_opaque(nc);
a41b2ff2
PB		 799 int avail;
800
aa1f17c1 801 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 802 if (!s->clock_enabled)
803 return 1;
804 if (!rtl8139_receiver_enabled(s))
805 return 1;
806
fcce6fd2 807 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
a41b2ff2
PB		 808 /* ??? Flow control not implemented in c+ mode.
809 This is a hack to work around slirp deficiencies anyway. */
810 return 1;
811 } else {
812 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
813 s->RxBufferSize);
fee9d348 814 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow));
a41b2ff2
PB		 815 }
816}
817
4e68f7a0 818static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 819{
cc1f0f45 820 RTL8139State *s = qemu_get_nic_opaque(nc);
88a411a8 821 PCIDevice *d = PCI_DEVICE(s);
18dabfd1 822 /* size is the length of the buffer passed to the driver */
1a326646 823 size_t size = size_;
18dabfd1 824 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 825
826 uint32_t packet_header = 0;
827
18dabfd1 828 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 829 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 830 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
831
1a326646 832 DPRINTF(">>> received len=%zu\n", size);
a41b2ff2
PB		 833
834 /* test if board clock is stopped */
835 if (!s->clock_enabled)
836 {
7cdeb319 837 DPRINTF("stopped ==========================\n");
4f1c942b 838 return -1;
a41b2ff2
PB		 839 }
840
841 /* first check if receiver is enabled */
842
843 if (!rtl8139_receiver_enabled(s))
844 {
7cdeb319 845 DPRINTF("receiver disabled ================\n");
4f1c942b 846 return -1;
a41b2ff2
PB		 847 }
848
849 /* XXX: check this */
850 if (s->RxConfig & AcceptAllPhys) {
851 /* promiscuous: receive all */
7cdeb319 852 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 853
854 } else {
855 if (!memcmp(buf, broadcast_macaddr, 6)) {
856 /* broadcast address */
857 if (!(s->RxConfig & AcceptBroadcast))
858 {
7cdeb319 859 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 860
861 /* update tally counter */
862 ++s->tally_counters.RxERR;
863
4f1c942b 864 return size;
a41b2ff2
PB		 865 }
866
867 packet_header |= RxBroadcast;
868
7cdeb319 869 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 870
871 /* update tally counter */
872 ++s->tally_counters.RxOkBrd;
873
a41b2ff2
PB		 874 } else if (buf[0] & 0x01) {
875 /* multicast */
876 if (!(s->RxConfig & AcceptMulticast))
877 {
7cdeb319 878 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 879
880 /* update tally counter */
881 ++s->tally_counters.RxERR;
882
4f1c942b 883 return size;
a41b2ff2
PB		 884 }
885
e7a58fc7 886 int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
a41b2ff2
PB		 887
888 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
889 {
7cdeb319 890 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 891
892 /* update tally counter */
893 ++s->tally_counters.RxERR;
894
4f1c942b 895 return size;
a41b2ff2
PB		 896 }
897
898 packet_header |= RxMulticast;
899
7cdeb319 900 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 901
902 /* update tally counter */
903 ++s->tally_counters.RxOkMul;
904
a41b2ff2 905 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 906 s->phys[1] == buf[1] &&
907 s->phys[2] == buf[2] &&
908 s->phys[3] == buf[3] &&
909 s->phys[4] == buf[4] &&
a41b2ff2
PB		 910 s->phys[5] == buf[5]) {
911 /* match */
912 if (!(s->RxConfig & AcceptMyPhys))
913 {
7cdeb319 914 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 915
916 /* update tally counter */
917 ++s->tally_counters.RxERR;
918
4f1c942b 919 return size;
a41b2ff2
PB		 920 }
921
922 packet_header |= RxPhysical;
923
7cdeb319 924 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 925
926 /* update tally counter */
927 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 928
929 } else {
930
7cdeb319 931 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 932
933 /* update tally counter */
934 ++s->tally_counters.RxERR;
935
4f1c942b 936 return size;
a41b2ff2
PB		 937 }
938 }
939
18dabfd1
BP		 940 /* if too small buffer, then expand it
941 * Include some tailroom in case a vlan tag is later removed. */
942 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 943 memcpy(buf1, buf, size);
18dabfd1 944 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 945 buf = buf1;
18dabfd1
BP		 946 if (size < MIN_BUF_SIZE) {
947 size = MIN_BUF_SIZE;
948 }
a41b2ff2
PB		 949 }
950
951 if (rtl8139_cp_receiver_enabled(s))
952 {
fcce6fd2
JW		 953 if (!rtl8139_cp_rx_valid(s)) {
954 return size;
955 }
956
7cdeb319 957 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 958
959 /* begin C+ receiver mode */
960
961/* w0 ownership flag */
962#define CP_RX_OWN (1<<31)
963/* w0 end of ring flag */
964#define CP_RX_EOR (1<<30)
965/* w0 bits 0...12 : buffer size */
966#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
967/* w1 tag available flag */
968#define CP_RX_TAVA (1<<16)
969/* w1 bits 0...15 : VLAN tag */
970#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
971/* w2 low 32bit of Rx buffer ptr */
972/* w3 high 32bit of Rx buffer ptr */
973
974 int descriptor = s->currCPlusRxDesc;
3ada003a 975 dma_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 976
977 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
978 cplus_rx_ring_desc += 16 * descriptor;
979
7cdeb319 980 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
3ada003a 981 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
7cdeb319 982 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 983
984 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
985
88a411a8 986 pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
a41b2ff2 987 rxdw0 = le32_to_cpu(val);
88a411a8 988 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
a41b2ff2 989 rxdw1 = le32_to_cpu(val);
88a411a8 990 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
a41b2ff2 991 rxbufLO = le32_to_cpu(val);
88a411a8 992 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
a41b2ff2
PB		 993 rxbufHI = le32_to_cpu(val);
994
7cdeb319
BP		 995 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
996 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 997
998 if (!(rxdw0 & CP_RX_OWN))
999 {
7cdeb319
BP		 1000 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1001 descriptor);
6cadb320 1002
a41b2ff2
PB		 1003 s->IntrStatus |= RxOverflow;
1004 ++s->RxMissed;
6cadb320
FB		 1005
1006 /* update tally counter */
1007 ++s->tally_counters.RxERR;
1008 ++s->tally_counters.MissPkt;
1009
a41b2ff2 1010 rtl8139_update_irq(s);
4f1c942b 1011 return size_;
a41b2ff2
PB		 1012 }
1013
1014 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1015
18dabfd1 1016 /* write VLAN info to descriptor variables. */
6960bfca
PM		 1017 if (s->CpCmd & CPlusRxVLAN &&
1018 lduw_be_p(&buf[ETH_ALEN * 2]) == ETH_P_VLAN) {
1bf11332 1019 dot1q_buf = &buf[ETH_ALEN * 2];
18dabfd1
BP		 1020 size -= VLAN_HLEN;
1021 /* if too small buffer, use the tailroom added duing expansion */
1022 if (size < MIN_BUF_SIZE) {
1023 size = MIN_BUF_SIZE;
1024 }
1025
1026 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1027 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
6960bfca 1028 rxdw1 |= CP_RX_TAVA | lduw_le_p(&dot1q_buf[ETHER_TYPE_LEN]);
18dabfd1 1029
7cdeb319 1030 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
6960bfca 1031 lduw_be_p(&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1032 } else {
1033 /* reset VLAN tag flag */
1034 rxdw1 &= ~CP_RX_TAVA;
1035 }
1036
6cadb320
FB		 1037 /* TODO: scatter the packet over available receive ring descriptors space */
1038
a41b2ff2
PB		 1039 if (size+4 > rx_space)
1040 {
1a326646 1041 DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n",
7cdeb319 1042 descriptor, rx_space, size);
6cadb320 1043
a41b2ff2
PB		 1044 s->IntrStatus |= RxOverflow;
1045 ++s->RxMissed;
6cadb320
FB		 1046
1047 /* update tally counter */
1048 ++s->tally_counters.RxERR;
1049 ++s->tally_counters.MissPkt;
1050
a41b2ff2 1051 rtl8139_update_irq(s);
4f1c942b 1052 return size_;
a41b2ff2
PB		 1053 }
1054
3ada003a 1055 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1056
1057 /* receive/copy to target memory */
18dabfd1 1058 if (dot1q_buf) {
1bf11332
SH		 1059 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN);
1060 pci_dma_write(d, rx_addr + 2 * ETH_ALEN,
1061 buf + 2 * ETH_ALEN + VLAN_HLEN,
1062 size - 2 * ETH_ALEN);
18dabfd1 1063 } else {
88a411a8 1064 pci_dma_write(d, rx_addr, buf, size);
18dabfd1 1065 }
a41b2ff2 1066
6cadb320
FB		 1067 if (s->CpCmd & CPlusRxChkSum)
1068 {
1069 /* do some packet checksumming */
1070 }
1071
a41b2ff2 1072 /* write checksum */
18dabfd1 1073 val = cpu_to_le32(crc32(0, buf, size_));
88a411a8 1074 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
a41b2ff2
PB		 1075
1076/* first segment of received packet flag */
1077#define CP_RX_STATUS_FS (1<<29)
1078/* last segment of received packet flag */
1079#define CP_RX_STATUS_LS (1<<28)
1080/* multicast packet flag */
1081#define CP_RX_STATUS_MAR (1<<26)
1082/* physical-matching packet flag */
1083#define CP_RX_STATUS_PAM (1<<25)
1084/* broadcast packet flag */
1085#define CP_RX_STATUS_BAR (1<<24)
1086/* runt packet flag */
1087#define CP_RX_STATUS_RUNT (1<<19)
1088/* crc error flag */
1089#define CP_RX_STATUS_CRC (1<<18)
1090/* IP checksum error flag */
1091#define CP_RX_STATUS_IPF (1<<15)
1092/* UDP checksum error flag */
1093#define CP_RX_STATUS_UDPF (1<<14)
1094/* TCP checksum error flag */
1095#define CP_RX_STATUS_TCPF (1<<13)
1096
1097 /* transfer ownership to target */
1098 rxdw0 &= ~CP_RX_OWN;
1099
1100 /* set first segment bit */
1101 rxdw0 |= CP_RX_STATUS_FS;
1102
1103 /* set last segment bit */
1104 rxdw0 |= CP_RX_STATUS_LS;
1105
1106 /* set received packet type flags */
1107 if (packet_header & RxBroadcast)
1108 rxdw0 |= CP_RX_STATUS_BAR;
1109 if (packet_header & RxMulticast)
1110 rxdw0 |= CP_RX_STATUS_MAR;
1111 if (packet_header & RxPhysical)
1112 rxdw0 |= CP_RX_STATUS_PAM;
1113
1114 /* set received size */
1115 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1116 rxdw0 |= (size+4);
1117
a41b2ff2
PB		 1118 /* update ring data */
1119 val = cpu_to_le32(rxdw0);
88a411a8 1120 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1121 val = cpu_to_le32(rxdw1);
88a411a8 1122 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1123
6cadb320
FB		 1124 /* update tally counter */
1125 ++s->tally_counters.RxOk;
1126
a41b2ff2
PB		 1127 /* seek to next Rx descriptor */
1128 if (rxdw0 & CP_RX_EOR)
1129 {
1130 s->currCPlusRxDesc = 0;
1131 }
1132 else
1133 {
1134 ++s->currCPlusRxDesc;
1135 }
1136
7cdeb319 1137 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1138
1139 }
1140 else
1141 {
7cdeb319 1142 DPRINTF("in ring Rx mode ================\n");
6cadb320 1143
a41b2ff2
PB		 1144 /* begin ring receiver mode */
1145 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1146
1147 /* if receiver buffer is empty then avail == 0 */
1148
fabdcd33
VY		 1149#define RX_ALIGN(x) (((x) + 3) & ~0x3)
1150
1151 if (avail != 0 && RX_ALIGN(size + 8) >= avail)
a41b2ff2 1152 {
7cdeb319 1153 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1a326646 1154 "read 0x%04x === available 0x%04x need 0x%04zx\n",
7cdeb319 1155 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1156
a41b2ff2
PB		 1157 s->IntrStatus |= RxOverflow;
1158 ++s->RxMissed;
1159 rtl8139_update_irq(s);
26c4e7ca 1160 return 0;
a41b2ff2
PB		 1161 }
1162
1163 packet_header |= RxStatusOK;
1164
1165 packet_header |= (((size+4) << 16) & 0xffff0000);
1166
1167 /* write header */
1168 uint32_t val = cpu_to_le32(packet_header);
1169
1170 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1171
1172 rtl8139_write_buffer(s, buf, size);
1173
1174 /* write checksum */
ccf1d14a 1175 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1176 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1177
1178 /* correct buffer write pointer */
fabdcd33 1179 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize);
a41b2ff2
PB		 1180
1181 /* now we can signal we have received something */
1182
7cdeb319
BP		 1183 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1184 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1185 }
1186
1187 s->IntrStatus |= RxOK;
6cadb320
FB		 1188
1189 if (do_interrupt)
1190 {
1191 rtl8139_update_irq(s);
1192 }
4f1c942b
MM		 1193
1194 return size_;
6cadb320
FB		 1195}
1196
4e68f7a0 1197static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1198{
1673ad51 1199 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1200}
1201
1202static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1203{
1204 s->RxBufferSize = bufferSize;
1205 s->RxBufPtr = 0;
1206 s->RxBufAddr = 0;
1207}
1208
30a3e701
HP		 1209static void rtl8139_reset_phy(RTL8139State *s)
1210{
1211 s->BasicModeStatus = 0x7809;
1212 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1213 /* preserve link state */
1214 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
1215
1216 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1217 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1218 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1219
1220 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1221}
1222
7f23f812 1223static void rtl8139_reset(DeviceState *d)
a41b2ff2 1224{
39257515 1225 RTL8139State *s = RTL8139(d);
a41b2ff2
PB		 1226 int i;
1227
1228 /* restore MAC address */
254111ec 1229 memcpy(s->phys, s->conf.macaddr.a, 6);
655d3b63 1230 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
a41b2ff2
PB		 1231
1232 /* reset interrupt mask */
1233 s->IntrStatus = 0;
1234 s->IntrMask = 0;
1235
1236 rtl8139_update_irq(s);
1237
a41b2ff2
PB		 1238 /* mark all status registers as owned by host */
1239 for (i = 0; i < 4; ++i)
1240 {
1241 s->TxStatus[i] = TxHostOwns;
1242 }
1243
1244 s->currTxDesc = 0;
1245 s->currCPlusRxDesc = 0;
1246 s->currCPlusTxDesc = 0;
1247
1248 s->RxRingAddrLO = 0;
1249 s->RxRingAddrHI = 0;
1250
1251 s->RxBuf = 0;
1252
1253 rtl8139_reset_rxring(s, 8192);
1254
1255 /* ACK the reset */
1256 s->TxConfig = 0;
1257
1258#if 0
1259// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1260 s->clock_enabled = 0;
1261#else
6cadb320 1262 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1263 s->clock_enabled = 1;
1264#endif
1265
1266 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1267
1268 /* set initial state data */
1269 s->Config0 = 0x0; /* No boot ROM */
1270 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1271 s->Config3 = 0x1; /* fast back-to-back compatible */
1272 s->Config5 = 0x0;
1273
a41b2ff2 1274 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1275 s->cplus_enabled = 0;
1276
a41b2ff2
PB		 1277// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1278// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1279 s->BasicModeCtrl = 0x1000; // autonegotiation
1280
30a3e701 1281 rtl8139_reset_phy(s);
6cadb320
FB		 1282
1283 /* also reset timer and disable timer interrupt */
1284 s->TCTR = 0;
1285 s->TimerInt = 0;
1286 s->TCTR_base = 0;
237c255c 1287 rtl8139_set_next_tctr_time(s);
6cadb320
FB		 1288
1289 /* reset tally counters */
1290 RTL8139TallyCounters_clear(&s->tally_counters);
1291}
1292
b1d8e52e 1293static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1294{
1295 counters->TxOk = 0;
1296 counters->RxOk = 0;
1297 counters->TxERR = 0;
1298 counters->RxERR = 0;
1299 counters->MissPkt = 0;
1300 counters->FAE = 0;
1301 counters->Tx1Col = 0;
1302 counters->TxMCol = 0;
1303 counters->RxOkPhy = 0;
1304 counters->RxOkBrd = 0;
1305 counters->RxOkMul = 0;
1306 counters->TxAbt = 0;
1307 counters->TxUndrn = 0;
1308}
1309
3ada003a 1310static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
6cadb320 1311{
88a411a8 1312 PCIDevice *d = PCI_DEVICE(s);
3ada003a 1313 RTL8139TallyCounters *tally_counters = &s->tally_counters;
6cadb320
FB		 1314 uint16_t val16;
1315 uint32_t val32;
1316 uint64_t val64;
1317
1318 val64 = cpu_to_le64(tally_counters->TxOk);
88a411a8 1319 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
6cadb320
FB		 1320
1321 val64 = cpu_to_le64(tally_counters->RxOk);
88a411a8 1322 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
6cadb320
FB		 1323
1324 val64 = cpu_to_le64(tally_counters->TxERR);
88a411a8 1325 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
6cadb320
FB		 1326
1327 val32 = cpu_to_le32(tally_counters->RxERR);
88a411a8 1328 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
6cadb320
FB		 1329
1330 val16 = cpu_to_le16(tally_counters->MissPkt);
88a411a8 1331 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
6cadb320
FB		 1332
1333 val16 = cpu_to_le16(tally_counters->FAE);
88a411a8 1334 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
6cadb320
FB		 1335
1336 val32 = cpu_to_le32(tally_counters->Tx1Col);
88a411a8 1337 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
6cadb320
FB		 1338
1339 val32 = cpu_to_le32(tally_counters->TxMCol);
88a411a8 1340 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
6cadb320
FB		 1341
1342 val64 = cpu_to_le64(tally_counters->RxOkPhy);
88a411a8 1343 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
6cadb320
FB		 1344
1345 val64 = cpu_to_le64(tally_counters->RxOkBrd);
88a411a8 1346 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
6cadb320
FB		 1347
1348 val32 = cpu_to_le32(tally_counters->RxOkMul);
88a411a8 1349 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
6cadb320
FB		 1350
1351 val16 = cpu_to_le16(tally_counters->TxAbt);
88a411a8 1352 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
6cadb320
FB		 1353
1354 val16 = cpu_to_le16(tally_counters->TxUndrn);
88a411a8 1355 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
6cadb320
FB		 1356}
1357
a41b2ff2
PB		 1358static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1359{
39257515
PC		 1360 DeviceState *d = DEVICE(s);
1361
a41b2ff2
PB		 1362 val &= 0xff;
1363
7cdeb319 1364 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1365
1366 if (val & CmdReset)
1367 {
7cdeb319 1368 DPRINTF("ChipCmd reset\n");
39257515 1369 rtl8139_reset(d);
a41b2ff2
PB		 1370 }
1371 if (val & CmdRxEnb)
1372 {
7cdeb319 1373 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1374
1375 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1376 }
1377 if (val & CmdTxEnb)
1378 {
7cdeb319 1379 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1380
1381 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1382 }
1383
ebabb67a 1384 /* mask unwritable bits */
a41b2ff2
PB		 1385 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1386
1387 /* Deassert reset pin before next read */
1388 val &= ~CmdReset;
1389
1390 s->bChipCmdState = val;
1391}
1392
1393static int rtl8139_RxBufferEmpty(RTL8139State *s)
1394{
1395 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1396
1397 if (unread != 0)
1398 {
7cdeb319 1399 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1400 return 0;
1401 }
1402
7cdeb319 1403 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1404
1405 return 1;
1406}
1407
1408static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1409{
1410 uint32_t ret = s->bChipCmdState;
1411
1412 if (rtl8139_RxBufferEmpty(s))
1413 ret |= RxBufEmpty;
1414
7cdeb319 1415 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1416
1417 return ret;
1418}
1419
1420static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1421{
1422 val &= 0xffff;
1423
7cdeb319 1424 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1425
2c3891ab
AL		 1426 s->cplus_enabled = 1;
1427
ebabb67a 1428 /* mask unwritable bits */
a41b2ff2
PB		 1429 val = SET_MASKED(val, 0xff84, s->CpCmd);
1430
1431 s->CpCmd = val;
1432}
1433
1434static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1435{
1436 uint32_t ret = s->CpCmd;
1437
7cdeb319 1438 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1439
1440 return ret;
1441}
1442
1443static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1444{
7cdeb319 1445 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1446}
1447
1448static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1449{
1450 uint32_t ret = 0;
1451
7cdeb319 1452 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1453
1454 return ret;
1455}
1456
ebabb67a 1457static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2 1458{
eb46c5ed 1459 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
a41b2ff2
PB		 1460 {
1461 return 1;
1462 }
1463
7cdeb319 1464 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1465
1466 return 0;
1467}
1468
1469static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1470{
1471 val &= 0xffff;
1472
7cdeb319 1473 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1474
ebabb67a 1475 /* mask unwritable bits */
30a3e701 1476 uint32_t mask = 0xccff;
a41b2ff2 1477
ebabb67a 1478 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1479 {
1480 /* Speed setting and autonegotiation enable bits are read-only */
1481 mask |= 0x3000;
1482 /* Duplex mode setting is read-only */
1483 mask |= 0x0100;
1484 }
1485
30a3e701
HP		 1486 if (val & 0x8000) {
1487 /* Reset PHY */
1488 rtl8139_reset_phy(s);
1489 }
1490
a41b2ff2
PB		 1491 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1492
1493 s->BasicModeCtrl = val;
1494}
1495
1496static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1497{
1498 uint32_t ret = s->BasicModeCtrl;
1499
7cdeb319 1500 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1501
1502 return ret;
1503}
1504
1505static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1506{
1507 val &= 0xffff;
1508
7cdeb319 1509 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1510
ebabb67a 1511 /* mask unwritable bits */
a41b2ff2
PB		 1512 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1513
1514 s->BasicModeStatus = val;
1515}
1516
1517static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1518{
1519 uint32_t ret = s->BasicModeStatus;
1520
7cdeb319 1521 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1522
1523 return ret;
1524}
1525
1526static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1527{
39257515
PC		 1528 DeviceState *d = DEVICE(s);
1529
a41b2ff2
PB		 1530 val &= 0xff;
1531
7cdeb319 1532 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1533
ebabb67a 1534 /* mask unwritable bits */
a41b2ff2
PB		 1535 val = SET_MASKED(val, 0x31, s->Cfg9346);
1536
1537 uint32_t opmode = val & 0xc0;
1538 uint32_t eeprom_val = val & 0xf;
1539
1540 if (opmode == 0x80) {
1541 /* eeprom access */
1542 int eecs = (eeprom_val & 0x08)?1:0;
1543 int eesk = (eeprom_val & 0x04)?1:0;
1544 int eedi = (eeprom_val & 0x02)?1:0;
1545 prom9346_set_wire(s, eecs, eesk, eedi);
1546 } else if (opmode == 0x40) {
1547 /* Reset. */
1548 val = 0;
39257515 1549 rtl8139_reset(d);
a41b2ff2
PB		 1550 }
1551
1552 s->Cfg9346 = val;
1553}
1554
1555static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1556{
1557 uint32_t ret = s->Cfg9346;
1558
1559 uint32_t opmode = ret & 0xc0;
1560
1561 if (opmode == 0x80)
1562 {
1563 /* eeprom access */
1564 int eedo = prom9346_get_wire(s);
1565 if (eedo)
1566 {
1567 ret |= 0x01;
1568 }
1569 else
1570 {
1571 ret &= ~0x01;
1572 }
1573 }
1574
7cdeb319 1575 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1576
1577 return ret;
1578}
1579
1580static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1581{
1582 val &= 0xff;
1583
7cdeb319 1584 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1585
ebabb67a 1586 if (!rtl8139_config_writable(s)) {
a41b2ff2 1587 return;
ebabb67a 1588 }
a41b2ff2 1589
ebabb67a 1590 /* mask unwritable bits */
a41b2ff2
PB		 1591 val = SET_MASKED(val, 0xf8, s->Config0);
1592
1593 s->Config0 = val;
1594}
1595
1596static uint32_t rtl8139_Config0_read(RTL8139State *s)
1597{
1598 uint32_t ret = s->Config0;
1599
7cdeb319 1600 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1601
1602 return ret;
1603}
1604
1605static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1606{
1607 val &= 0xff;
1608
7cdeb319 1609 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1610
ebabb67a 1611 if (!rtl8139_config_writable(s)) {
a41b2ff2 1612 return;
ebabb67a 1613 }
a41b2ff2 1614
ebabb67a 1615 /* mask unwritable bits */
a41b2ff2
PB		 1616 val = SET_MASKED(val, 0xC, s->Config1);
1617
1618 s->Config1 = val;
1619}
1620
1621static uint32_t rtl8139_Config1_read(RTL8139State *s)
1622{
1623 uint32_t ret = s->Config1;
1624
7cdeb319 1625 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1626
1627 return ret;
1628}
1629
1630static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1631{
1632 val &= 0xff;
1633
7cdeb319 1634 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1635
ebabb67a 1636 if (!rtl8139_config_writable(s)) {
a41b2ff2 1637 return;
ebabb67a 1638 }
a41b2ff2 1639
ebabb67a 1640 /* mask unwritable bits */
a41b2ff2
PB		 1641 val = SET_MASKED(val, 0x8F, s->Config3);
1642
1643 s->Config3 = val;
1644}
1645
1646static uint32_t rtl8139_Config3_read(RTL8139State *s)
1647{
1648 uint32_t ret = s->Config3;
1649
7cdeb319 1650 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1651
1652 return ret;
1653}
1654
1655static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1656{
1657 val &= 0xff;
1658
7cdeb319 1659 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1660
ebabb67a 1661 if (!rtl8139_config_writable(s)) {
a41b2ff2 1662 return;
ebabb67a 1663 }
a41b2ff2 1664
ebabb67a 1665 /* mask unwritable bits */
a41b2ff2
PB		 1666 val = SET_MASKED(val, 0x0a, s->Config4);
1667
1668 s->Config4 = val;
1669}
1670
1671static uint32_t rtl8139_Config4_read(RTL8139State *s)
1672{
1673 uint32_t ret = s->Config4;
1674
7cdeb319 1675 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1676
1677 return ret;
1678}
1679
1680static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1681{
1682 val &= 0xff;
1683
7cdeb319 1684 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1685
ebabb67a 1686 /* mask unwritable bits */
a41b2ff2
PB		 1687 val = SET_MASKED(val, 0x80, s->Config5);
1688
1689 s->Config5 = val;
1690}
1691
1692static uint32_t rtl8139_Config5_read(RTL8139State *s)
1693{
1694 uint32_t ret = s->Config5;
1695
7cdeb319 1696 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1697
1698 return ret;
1699}
1700
1701static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1702{
1703 if (!rtl8139_transmitter_enabled(s))
1704 {
7cdeb319 1705 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1706 return;
1707 }
1708
7cdeb319 1709 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1710
1711 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1712
1713 s->TxConfig = val;
1714}
1715
1716static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1717{
7cdeb319 1718 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1719
1720 uint32_t tc = s->TxConfig;
1721 tc &= 0xFFFFFF00;
1722 tc |= (val & 0x000000FF);
1723 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1724}
1725
1726static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1727{
1728 uint32_t ret = s->TxConfig;
1729
7cdeb319 1730 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1731
1732 return ret;
1733}
1734
1735static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1736{
7cdeb319 1737 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1738
ebabb67a 1739 /* mask unwritable bits */
a41b2ff2
PB		 1740 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1741
1742 s->RxConfig = val;
1743
1744 /* reset buffer size and read/write pointers */
1745 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1746
7cdeb319 1747 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1748}
1749
1750static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1751{
1752 uint32_t ret = s->RxConfig;
1753
7cdeb319 1754 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1755
1756 return ret;
1757}
1758
bf6b87a8
BP		 1759static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1760 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1761{
bf6b87a8 1762 struct iovec *iov = NULL;
b0af8440 1763 struct iovec vlan_iov[3];
bf6b87a8 1764
718da2b9
FB		 1765 if (!size)
1766 {
7cdeb319 1767 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1768 return;
1769 }
1770
1bf11332 1771 if (dot1q_buf && size >= ETH_ALEN * 2) {
bf6b87a8 1772 iov = (struct iovec[3]) {
1bf11332 1773 { .iov_base = buf, .iov_len = ETH_ALEN * 2 },
bf6b87a8 1774 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1bf11332
SH		 1775 { .iov_base = buf + ETH_ALEN * 2,
1776 .iov_len = size - ETH_ALEN * 2 },
bf6b87a8 1777 };
b0af8440
GA		 1778
1779 memcpy(vlan_iov, iov, sizeof(vlan_iov));
1780 iov = vlan_iov;
bf6b87a8
BP		 1781 }
1782
718da2b9
FB		 1783 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1784 {
bf6b87a8
BP		 1785 size_t buf2_size;
1786 uint8_t *buf2;
1787
1788 if (iov) {
1789 buf2_size = iov_size(iov, 3);
7267c094 1790 buf2 = g_malloc(buf2_size);
dcf6f5e1 1791 iov_to_buf(iov, 3, 0, buf2, buf2_size);
bf6b87a8
BP		 1792 buf = buf2;
1793 }
1794
7cdeb319 1795 DPRINTF("+++ transmit loopback mode\n");
b356f76d 1796 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt);
bf6b87a8
BP		 1797
1798 if (iov) {
7267c094 1799 g_free(buf2);
bf6b87a8 1800 }
718da2b9
FB		 1801 }
1802 else
1803 {
bf6b87a8 1804 if (iov) {
b356f76d 1805 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
bf6b87a8 1806 } else {
b356f76d 1807 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
bf6b87a8 1808 }
718da2b9
FB		 1809 }
1810}
1811
a41b2ff2
PB		 1812static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1813{
1814 if (!rtl8139_transmitter_enabled(s))
1815 {
7cdeb319
BP		 1816 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1817 "disabled\n", descriptor);
a41b2ff2
PB		 1818 return 0;
1819 }
1820
1821 if (s->TxStatus[descriptor] & TxHostOwns)
1822 {
7cdeb319
BP		 1823 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1824 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1825 return 0;
1826 }
1827
7cdeb319 1828 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2 1829
88a411a8 1830 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 1831 int txsize = s->TxStatus[descriptor] & 0x1fff;
1832 uint8_t txbuffer[0x2000];
1833
7cdeb319
BP		 1834 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1835 txsize, s->TxAddr[descriptor]);
a41b2ff2 1836
88a411a8 1837 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1838
1839 /* Mark descriptor as transferred */
1840 s->TxStatus[descriptor] |= TxHostOwns;
1841 s->TxStatus[descriptor] |= TxStatOK;
1842
bf6b87a8 1843 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1844
7cdeb319
BP		 1845 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1846 descriptor);
a41b2ff2
PB		 1847
1848 /* update interrupt */
1849 s->IntrStatus |= TxOK;
1850 rtl8139_update_irq(s);
1851
1852 return 1;
1853}
1854
718da2b9
FB		 1855#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1856
718da2b9
FB		 1857/* produces ones' complement sum of data */
1858static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1859{
1860 uint32_t result = 0;
1861
1862 for (; len > 1; data+=2, len-=2)
1863 {
1864 result += *(uint16_t*)data;
1865 }
1866
1867 /* add the remainder byte */
1868 if (len)
1869 {
1870 uint8_t odd[2] = {*data, 0};
1871 result += *(uint16_t*)odd;
1872 }
1873
1874 while (result>>16)
1875 result = (result & 0xffff) + (result >> 16);
1876
1877 return result;
1878}
1879
1880static uint16_t ip_checksum(void *data, size_t len)
1881{
1882 return ~ones_complement_sum((uint8_t*)data, len);
1883}
1884
a41b2ff2
PB		 1885static int rtl8139_cplus_transmit_one(RTL8139State *s)
1886{
1887 if (!rtl8139_transmitter_enabled(s))
1888 {
7cdeb319 1889 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1890 return 0;
1891 }
1892
1893 if (!rtl8139_cp_transmitter_enabled(s))
1894 {
7cdeb319 1895 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1896 return 0 ;
1897 }
1898
88a411a8 1899 PCIDevice *d = PCI_DEVICE(s);
a41b2ff2
PB		 1900 int descriptor = s->currCPlusTxDesc;
1901
3ada003a 1902 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
a41b2ff2
PB		 1903
1904 /* Normal priority ring */
1905 cplus_tx_ring_desc += 16 * descriptor;
1906
7cdeb319 1907 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
4abf12f4 1908 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
7cdeb319 1909 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1910
1911 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1912
88a411a8 1913 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1914 txdw0 = le32_to_cpu(val);
88a411a8 1915 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1916 txdw1 = le32_to_cpu(val);
88a411a8 1917 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
a41b2ff2 1918 txbufLO = le32_to_cpu(val);
88a411a8 1919 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
a41b2ff2
PB		 1920 txbufHI = le32_to_cpu(val);
1921
7cdeb319
BP		 1922 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1923 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1924
1925/* w0 ownership flag */
1926#define CP_TX_OWN (1<<31)
1927/* w0 end of ring flag */
1928#define CP_TX_EOR (1<<30)
1929/* first segment of received packet flag */
1930#define CP_TX_FS (1<<29)
1931/* last segment of received packet flag */
1932#define CP_TX_LS (1<<28)
1933/* large send packet flag */
1934#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1935/* large send MSS mask, bits 16...25 */
1936#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1937
a41b2ff2
PB		 1938/* IP checksum offload flag */
1939#define CP_TX_IPCS (1<<18)
1940/* UDP checksum offload flag */
1941#define CP_TX_UDPCS (1<<17)
1942/* TCP checksum offload flag */
1943#define CP_TX_TCPCS (1<<16)
1944
1945/* w0 bits 0...15 : buffer size */
1946#define CP_TX_BUFFER_SIZE (1<<16)
1947#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 1948/* w1 add tag flag */
1949#define CP_TX_TAGC (1<<17)
1950/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 1951#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1952/* w2 low 32bit of Rx buffer ptr */
1953/* w3 high 32bit of Rx buffer ptr */
1954
1955/* set after transmission */
1956/* FIFO underrun flag */
1957#define CP_TX_STATUS_UNF (1<<25)
1958/* transmit error summary flag, valid if set any of three below */
1959#define CP_TX_STATUS_TES (1<<23)
1960/* out-of-window collision flag */
1961#define CP_TX_STATUS_OWC (1<<22)
1962/* link failure flag */
1963#define CP_TX_STATUS_LNKF (1<<21)
1964/* excessive collisions flag */
1965#define CP_TX_STATUS_EXC (1<<20)
1966
1967 if (!(txdw0 & CP_TX_OWN))
1968 {
7cdeb319 1969 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 1970 return 0 ;
1971 }
1972
7cdeb319 1973 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 1974
1975 if (txdw0 & CP_TX_FS)
1976 {
7cdeb319
BP		 1977 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
1978 "descriptor\n", descriptor);
6cadb320
FB		 1979
1980 /* reset internal buffer offset */
1981 s->cplus_txbuffer_offset = 0;
1982 }
a41b2ff2
PB		 1983
1984 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
3ada003a 1985 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 1986
6cadb320
FB		 1987 /* make sure we have enough space to assemble the packet */
1988 if (!s->cplus_txbuffer)
1989 {
1990 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 1991 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 1992 s->cplus_txbuffer_offset = 0;
718da2b9 1993
7cdeb319
BP		 1994 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
1995 s->cplus_txbuffer_len);
6cadb320
FB		 1996 }
1997
cde31a0e 1998 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
6cadb320 1999 {
cde31a0e
JW		 2000 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2001 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2002 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2003 "length to %d\n", txsize);
6cadb320
FB		 2004 }
2005
6cadb320
FB		 2006 /* append more data to the packet */
2007
7cdeb319 2008 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
3ada003a
EGM		 2009 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2010 s->cplus_txbuffer_offset);
6cadb320 2011
88a411a8 2012 pci_dma_read(d, tx_addr,
3ada003a 2013 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
6cadb320
FB		 2014 s->cplus_txbuffer_offset += txsize;
2015
2016 /* seek to next Rx descriptor */
2017 if (txdw0 & CP_TX_EOR)
2018 {
2019 s->currCPlusTxDesc = 0;
2020 }
2021 else
2022 {
2023 ++s->currCPlusTxDesc;
2024 if (s->currCPlusTxDesc >= 64)
2025 s->currCPlusTxDesc = 0;
2026 }
a41b2ff2
PB		 2027
2028 /* transfer ownership to target */
91731d5f 2029 txdw0 &= ~CP_TX_OWN;
a41b2ff2
PB		 2030
2031 /* reset error indicator bits */
2032 txdw0 &= ~CP_TX_STATUS_UNF;
2033 txdw0 &= ~CP_TX_STATUS_TES;
2034 txdw0 &= ~CP_TX_STATUS_OWC;
2035 txdw0 &= ~CP_TX_STATUS_LNKF;
2036 txdw0 &= ~CP_TX_STATUS_EXC;
2037
2038 /* update ring data */
2039 val = cpu_to_le32(txdw0);
88a411a8 2040 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2041
6cadb320
FB		 2042 /* Now decide if descriptor being processed is holding the last segment of packet */
2043 if (txdw0 & CP_TX_LS)
a41b2ff2 2044 {
bf6b87a8
BP		 2045 uint8_t dot1q_buffer_space[VLAN_HLEN];
2046 uint16_t *dot1q_buffer;
2047
7cdeb319
BP		 2048 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2049 descriptor);
6cadb320
FB		 2050
2051 /* can transfer fully assembled packet */
2052
2053 uint8_t *saved_buffer = s->cplus_txbuffer;
2054 int saved_size = s->cplus_txbuffer_offset;
2055 int saved_buffer_len = s->cplus_txbuffer_len;
2056
bf6b87a8
BP		 2057 /* create vlan tag */
2058 if (txdw1 & CP_TX_TAGC) {
2059 /* the vlan tag is in BE byte order in the descriptor
2060 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2061 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2062 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2063
2064 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
1bf11332 2065 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN);
bf6b87a8
BP		 2066 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2067 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2068 } else {
2069 dot1q_buffer = NULL;
2070 }
2071
6cadb320
FB		 2072 /* reset the card space to protect from recursive call */
2073 s->cplus_txbuffer = NULL;
2074 s->cplus_txbuffer_offset = 0;
2075 s->cplus_txbuffer_len = 0;
2076
718da2b9 2077 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2078 {
7cdeb319 2079 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2080
e1c120a9 2081 /* Large enough for Ethernet and IP headers? */
5d61721a 2082 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) {
e1c120a9
SH		 2083 goto skip_offload;
2084 }
2085
6cadb320 2086 /* ip packet header */
5d61721a 2087 struct ip_header *ip = NULL;
6cadb320 2088 int hlen = 0;
718da2b9
FB		 2089 uint8_t ip_protocol = 0;
2090 uint16_t ip_data_len = 0;
6cadb320 2091
660f11be 2092 uint8_t *eth_payload_data = NULL;
718da2b9 2093 size_t eth_payload_len = 0;
6cadb320 2094
718da2b9 2095 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
39b8e7dc 2096 if (proto != ETH_P_IP)
6cadb320 2097 {
39b8e7dc 2098 goto skip_offload;
6cadb320
FB		 2099 }
2100
39b8e7dc
SH		 2101 DPRINTF("+++ C+ mode has IP packet\n");
2102
26c0114d
SH		 2103 /* Note on memory alignment: eth_payload_data is 16-bit aligned
2104 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is
2105 * even. 32-bit accesses must use ldl/stl wrappers to avoid
2106 * unaligned accesses.
2107 */
39b8e7dc
SH		 2108 eth_payload_data = saved_buffer + ETH_HLEN;
2109 eth_payload_len = saved_size - ETH_HLEN;
2110
5d61721a 2111 ip = (struct ip_header*)eth_payload_data;
39b8e7dc
SH		 2112
2113 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2114 DPRINTF("+++ C+ mode packet has bad IP version %d "
2115 "expected %d\n", IP_HEADER_VERSION(ip),
2116 IP_HEADER_VERSION_4);
2117 goto skip_offload;
2118 }
2119
1bf11332 2120 hlen = IP_HDR_GET_LEN(ip);
5d61721a 2121 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) {
03247d43
SH		 2122 goto skip_offload;
2123 }
2124
39b8e7dc 2125 ip_protocol = ip->ip_p;
c6296ea8
SH		 2126
2127 ip_data_len = be16_to_cpu(ip->ip_len);
2128 if (ip_data_len < hlen || ip_data_len > eth_payload_len) {
2129 goto skip_offload;
2130 }
2131 ip_data_len -= hlen;
39b8e7dc 2132
d6812d60 2133 if (txdw0 & CP_TX_IPCS)
6cadb320 2134 {
d6812d60 2135 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2136
03247d43
SH		 2137 ip->ip_sum = 0;
2138 ip->ip_sum = ip_checksum(ip, hlen);
2139 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2140 hlen, ip->ip_sum);
d6812d60 2141 }
ec48c774 2142
d6812d60
SH		 2143 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2144 {
4240be45
SH		 2145 /* Large enough for the TCP header? */
2146 if (ip_data_len < sizeof(tcp_header)) {
2147 goto skip_offload;
2148 }
2149
d6812d60 2150 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
6cadb320 2151
d6812d60
SH		 2152 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2153 "frame data %d specified MSS=%d\n", ETH_MTU,
2154 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2155
d6812d60
SH		 2156 int tcp_send_offset = 0;
2157 int send_count = 0;
6cadb320 2158
d6812d60
SH		 2159 /* maximum IP header length is 60 bytes */
2160 uint8_t saved_ip_header[60];
718da2b9 2161
d6812d60
SH		 2162 /* save IP header template; data area is used in tcp checksum calculation */
2163 memcpy(saved_ip_header, eth_payload_data, hlen);
718da2b9 2164
d6812d60
SH		 2165 /* a placeholder for checksum calculation routine in tcp case */
2166 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2167 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
718da2b9 2168
d6812d60
SH		 2169 /* pointer to TCP header */
2170 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
718da2b9 2171
d6812d60 2172 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
718da2b9 2173
8357946b
SH		 2174 /* Invalid TCP data offset? */
2175 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) {
2176 goto skip_offload;
2177 }
2178
d6812d60
SH		 2179 /* ETH_MTU = ip header len + tcp header len + payload */
2180 int tcp_data_len = ip_data_len - tcp_hlen;
2181 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
718da2b9 2182
d6812d60
SH		 2183 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2184 "data len %d TCP chunk size %d\n", ip_data_len,
2185 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9 2186
d6812d60
SH		 2187 /* note the cycle below overwrites IP header data,
2188 but restores it from saved_ip_header before sending packet */
718da2b9 2189
d6812d60 2190 int is_last_frame = 0;
718da2b9 2191
d6812d60 2192 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
718da2b9 2193 {
d6812d60 2194 uint16_t chunk_size = tcp_chunk_size;
718da2b9 2195
d6812d60
SH		 2196 /* check if this is the last frame */
2197 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2198 {
2199 is_last_frame = 1;
2200 chunk_size = tcp_data_len - tcp_send_offset;
2201 }
718da2b9 2202
d6812d60 2203 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
26c0114d 2204 ldl_be_p(&p_tcp_hdr->th_seq));
6cadb320
FB		 2205
2206 /* add 4 TCP pseudoheader fields */
2207 /* copy IP source and destination fields */
718da2b9 2208 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2209
d6812d60
SH		 2210 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2211 "packet with %d bytes data\n", tcp_hlen +
2212 chunk_size);
2213
2214 if (tcp_send_offset)
6cadb320 2215 {
d6812d60
SH		 2216 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2217 }
6cadb320 2218
d6812d60
SH		 2219 /* keep PUSH and FIN flags only for the last frame */
2220 if (!is_last_frame)
2221 {
1bf11332 2222 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN);
d6812d60 2223 }
6cadb320 2224
d6812d60
SH		 2225 /* recalculate TCP checksum */
2226 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2227 p_tcpip_hdr->zeros = 0;
2228 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2229 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
6cadb320 2230
d6812d60 2231 p_tcp_hdr->th_sum = 0;
6cadb320 2232
d6812d60
SH		 2233 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2234 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2235 tcp_checksum);
6cadb320 2236
d6812d60 2237 p_tcp_hdr->th_sum = tcp_checksum;
6cadb320 2238
d6812d60
SH		 2239 /* restore IP header */
2240 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320 2241
d6812d60
SH		 2242 /* set IP data length and recalculate IP checksum */
2243 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
6cadb320 2244
d6812d60
SH		 2245 /* increment IP id for subsequent frames */
2246 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
6cadb320 2247
d6812d60
SH		 2248 ip->ip_sum = 0;
2249 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2250 DPRINTF("+++ C+ mode TSO IP header len=%d "
2251 "checksum=%04x\n", hlen, ip->ip_sum);
6cadb320 2252
d6812d60
SH		 2253 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2254 DPRINTF("+++ C+ mode TSO transferring packet size "
2255 "%d\n", tso_send_size);
2256 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2257 0, (uint8_t *) dot1q_buffer);
6cadb320 2258
d6812d60 2259 /* add transferred count to TCP sequence number */
26c0114d
SH		 2260 stl_be_p(&p_tcp_hdr->th_seq,
2261 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq));
d6812d60 2262 ++send_count;
6cadb320 2263 }
d6812d60
SH		 2264
2265 /* Stop sending this frame */
2266 saved_size = 0;
2267 }
2268 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2269 {
2270 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2271
2272 /* maximum IP header length is 60 bytes */
2273 uint8_t saved_ip_header[60];
2274 memcpy(saved_ip_header, eth_payload_data, hlen);
2275
2276 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2277 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2278
2279 /* add 4 TCP pseudoheader fields */
2280 /* copy IP source and destination fields */
2281 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2282
2283 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2284 {
2285 DPRINTF("+++ C+ mode calculating TCP checksum for "
2286 "packet with %d bytes data\n", ip_data_len);
2287
2288 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2289 p_tcpip_hdr->zeros = 0;
2290 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2291 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2292
2293 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2294
2295 p_tcp_hdr->th_sum = 0;
2296
2297 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2298 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2299 tcp_checksum);
2300
2301 p_tcp_hdr->th_sum = tcp_checksum;
2302 }
2303 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2304 {
2305 DPRINTF("+++ C+ mode calculating UDP checksum for "
2306 "packet with %d bytes data\n", ip_data_len);
2307
2308 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2309 p_udpip_hdr->zeros = 0;
2310 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2311 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2312
2313 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2314
2315 p_udp_hdr->uh_sum = 0;
2316
2317 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2318 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2319 udp_checksum);
2320
2321 p_udp_hdr->uh_sum = udp_checksum;
2322 }
2323
2324 /* restore IP header */
2325 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2326 }
2327 }
2328
39b8e7dc 2329skip_offload:
6cadb320
FB		 2330 /* update tally counter */
2331 ++s->tally_counters.TxOk;
2332
7cdeb319 2333 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2334
bf6b87a8
BP		 2335 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2336 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2337
2338 /* restore card space if there was no recursion and reset offset */
2339 if (!s->cplus_txbuffer)
2340 {
2341 s->cplus_txbuffer = saved_buffer;
2342 s->cplus_txbuffer_len = saved_buffer_len;
2343 s->cplus_txbuffer_offset = 0;
2344 }
2345 else
2346 {
7267c094 2347 g_free(saved_buffer);
6cadb320 2348 }
a41b2ff2
PB		 2349 }
2350 else
2351 {
7cdeb319 2352 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2353 }
2354
a41b2ff2
PB		 2355 return 1;
2356}
2357
2358static void rtl8139_cplus_transmit(RTL8139State *s)
2359{
2360 int txcount = 0;
2361
c7c35916 2362 while (txcount < 64 && rtl8139_cplus_transmit_one(s))
a41b2ff2
PB		 2363 {
2364 ++txcount;
2365 }
2366
2367 /* Mark transfer completed */
2368 if (!txcount)
2369 {
7cdeb319
BP		 2370 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2371 s->currCPlusTxDesc);
a41b2ff2
PB		 2372 }
2373 else
2374 {
2375 /* update interrupt status */
2376 s->IntrStatus |= TxOK;
2377 rtl8139_update_irq(s);
2378 }
2379}
2380
2381static void rtl8139_transmit(RTL8139State *s)
2382{
2383 int descriptor = s->currTxDesc, txcount = 0;
2384
2385 /*while*/
2386 if (rtl8139_transmit_one(s, descriptor))
2387 {
2388 ++s->currTxDesc;
2389 s->currTxDesc %= 4;
2390 ++txcount;
2391 }
2392
2393 /* Mark transfer completed */
2394 if (!txcount)
2395 {
7cdeb319
BP		 2396 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2397 s->currTxDesc);
a41b2ff2
PB		 2398 }
2399}
2400
2401static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2402{
2403
2404 int descriptor = txRegOffset/4;
6cadb320
FB		 2405
2406 /* handle C+ transmit mode register configuration */
2407
2c3891ab 2408 if (s->cplus_enabled)
6cadb320 2409 {
7cdeb319
BP		 2410 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2411 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2412
2413 /* handle Dump Tally Counters command */
2414 s->TxStatus[descriptor] = val;
2415
2416 if (descriptor == 0 && (val & 0x8))
2417 {
a8170e5e 2418 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2419
2420 /* dump tally counters to specified memory location */
3ada003a 2421 RTL8139TallyCounters_dma_write(s, tc_addr);
6cadb320
FB		 2422
2423 /* mark dump completed */
2424 s->TxStatus[0] &= ~0x8;
2425 }
2426
2427 return;
2428 }
2429
7cdeb319
BP		 2430 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2431 txRegOffset, val, descriptor);
a41b2ff2
PB		 2432
2433 /* mask only reserved bits */
2434 val &= ~0xff00c000; /* these bits are reset on write */
2435 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2436
2437 s->TxStatus[descriptor] = val;
2438
2439 /* attempt to start transmission */
2440 rtl8139_transmit(s);
2441}
2442
3e48dd4a
SH		 2443static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2444 uint32_t base, uint8_t addr,
2445 int size)
a41b2ff2 2446{
3e48dd4a 2447 uint32_t reg = (addr - base) / 4;
afe0a595
JW		 2448 uint32_t offset = addr & 0x3;
2449 uint32_t ret = 0;
2450
2451 if (addr & (size - 1)) {
3e48dd4a
SH		 2452 DPRINTF("not implemented read for TxStatus/TxAddr "
2453 "addr=0x%x size=0x%x\n", addr, size);
afe0a595
JW		 2454 return ret;
2455 }
a41b2ff2 2456
afe0a595
JW		 2457 switch (size) {
2458 case 1: /* fall through */
2459 case 2: /* fall through */
2460 case 4:
bdc62e62 2461 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
3e48dd4a
SH		 2462 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2463 reg, addr, size, ret);
afe0a595
JW		 2464 break;
2465 default:
3e48dd4a 2466 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
afe0a595
JW		 2467 break;
2468 }
a41b2ff2
PB		 2469
2470 return ret;
2471}
2472
2473static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2474{
2475 uint16_t ret = 0;
2476
2477 /* Simulate TSAD, it is read only anyway */
2478
2479 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2480 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2481 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2482 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2483
2484 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2485 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2486 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2487 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2488
a41b2ff2
PB		 2489 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2490 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2491 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2492 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2493
a41b2ff2
PB		 2494 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2495 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2496 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2497 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2498
a41b2ff2 2499
7cdeb319 2500 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2501
2502 return ret;
2503}
2504
2505static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2506{
2507 uint16_t ret = s->CSCR;
2508
7cdeb319 2509 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2510
2511 return ret;
2512}
2513
2514static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2515{
7cdeb319 2516 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2517
290a0933 2518 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2519}
2520
2521static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2522{
290a0933 2523 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2524
7cdeb319 2525 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2526
2527 return ret;
2528}
2529
2530static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2531{
7cdeb319 2532 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2533
2534 /* this value is off by 16 */
2535 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2536
00b7ade8
SH		 2537 /* more buffer space may be available so try to receive */
2538 qemu_flush_queued_packets(qemu_get_queue(s->nic));
2539
7cdeb319
BP		 2540 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2541 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2542}
2543
2544static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2545{
2546 /* this value is off by 16 */
2547 uint32_t ret = s->RxBufPtr - 0x10;
2548
7cdeb319 2549 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2550
2551 return ret;
2552}
2553
2554static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2555{
2556 /* this value is NOT off by 16 */
2557 uint32_t ret = s->RxBufAddr;
2558
7cdeb319 2559 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2560
2561 return ret;
2562}
2563
2564static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2565{
7cdeb319 2566 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2567
2568 s->RxBuf = val;
2569
2570 /* may need to reset rxring here */
2571}
2572
2573static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2574{
2575 uint32_t ret = s->RxBuf;
2576
7cdeb319 2577 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2578
2579 return ret;
2580}
2581
2582static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2583{
7cdeb319 2584 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2585
ebabb67a 2586 /* mask unwritable bits */
a41b2ff2
PB		 2587 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2588
2589 s->IntrMask = val;
2590
2591 rtl8139_update_irq(s);
05447803 2592
a41b2ff2
PB		 2593}
2594
2595static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2596{
2597 uint32_t ret = s->IntrMask;
2598
7cdeb319 2599 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2600
2601 return ret;
2602}
2603
2604static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2605{
7cdeb319 2606 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2607
2608#if 0
2609
2610 /* writing to ISR has no effect */
2611
2612 return;
2613
2614#else
2615 uint16_t newStatus = s->IntrStatus & ~val;
2616
ebabb67a 2617 /* mask unwritable bits */
a41b2ff2
PB		 2618 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2619
2620 /* writing 1 to interrupt status register bit clears it */
2621 s->IntrStatus = 0;
2622 rtl8139_update_irq(s);
2623
2624 s->IntrStatus = newStatus;
237c255c 2625 rtl8139_set_next_tctr_time(s);
a41b2ff2 2626 rtl8139_update_irq(s);
05447803 2627
a41b2ff2
PB		 2628#endif
2629}
2630
2631static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2632{
2633 uint32_t ret = s->IntrStatus;
2634
7cdeb319 2635 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2636
2637#if 0
2638
2639 /* reading ISR clears all interrupts */
2640 s->IntrStatus = 0;
2641
2642 rtl8139_update_irq(s);
2643
2644#endif
2645
2646 return ret;
2647}
2648
2649static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2650{
7cdeb319 2651 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2652
ebabb67a 2653 /* mask unwritable bits */
a41b2ff2
PB		 2654 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2655
2656 s->MultiIntr = val;
2657}
2658
2659static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2660{
2661 uint32_t ret = s->MultiIntr;
2662
7cdeb319 2663 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2664
2665 return ret;
2666}
2667
2668static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2669{
2670 RTL8139State *s = opaque;
2671
a41b2ff2
PB		 2672 switch (addr)
2673 {
90d131fb
MT		 2674 case MAC0 ... MAC0+4:
2675 s->phys[addr - MAC0] = val;
2676 break;
2677 case MAC0+5:
23c37c37
AK		 2678 s->phys[addr - MAC0] = val;
2679 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2680 break;
a41b2ff2
PB		 2681 case MAC0+6 ... MAC0+7:
2682 /* reserved */
2683 break;
2684 case MAR0 ... MAR0+7:
2685 s->mult[addr - MAR0] = val;
2686 break;
2687 case ChipCmd:
2688 rtl8139_ChipCmd_write(s, val);
2689 break;
2690 case Cfg9346:
2691 rtl8139_Cfg9346_write(s, val);
2692 break;
2693 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2694 rtl8139_TxConfig_writeb(s, val);
2695 break;
2696 case Config0:
2697 rtl8139_Config0_write(s, val);
2698 break;
2699 case Config1:
2700 rtl8139_Config1_write(s, val);
2701 break;
2702 case Config3:
2703 rtl8139_Config3_write(s, val);
2704 break;
2705 case Config4:
2706 rtl8139_Config4_write(s, val);
2707 break;
2708 case Config5:
2709 rtl8139_Config5_write(s, val);
2710 break;
2711 case MediaStatus:
2712 /* ignore */
7cdeb319
BP		 2713 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2714 val);
a41b2ff2
PB		 2715 break;
2716
2717 case HltClk:
7cdeb319 2718 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2719 if (val == 'R')
2720 {
2721 s->clock_enabled = 1;
2722 }
2723 else if (val == 'H')
2724 {
2725 s->clock_enabled = 0;
2726 }
2727 break;
2728
2729 case TxThresh:
7cdeb319 2730 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2731 s->TxThresh = val;
2732 break;
2733
2734 case TxPoll:
7cdeb319 2735 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2736 if (val & (1 << 7))
2737 {
7cdeb319
BP		 2738 DPRINTF("C+ TxPoll high priority transmission (not "
2739 "implemented)\n");
a41b2ff2
PB		 2740 //rtl8139_cplus_transmit(s);
2741 }
2742 if (val & (1 << 6))
2743 {
7cdeb319 2744 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2745 rtl8139_cplus_transmit(s);
2746 }
2747
2748 break;
2749
2750 default:
7cdeb319
BP		 2751 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2752 val);
a41b2ff2
PB		 2753 break;
2754 }
2755}
2756
2757static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2758{
2759 RTL8139State *s = opaque;
2760
a41b2ff2
PB		 2761 switch (addr)
2762 {
2763 case IntrMask:
2764 rtl8139_IntrMask_write(s, val);
2765 break;
2766
2767 case IntrStatus:
2768 rtl8139_IntrStatus_write(s, val);
2769 break;
2770
2771 case MultiIntr:
2772 rtl8139_MultiIntr_write(s, val);
2773 break;
2774
2775 case RxBufPtr:
2776 rtl8139_RxBufPtr_write(s, val);
2777 break;
2778
2779 case BasicModeCtrl:
2780 rtl8139_BasicModeCtrl_write(s, val);
2781 break;
2782 case BasicModeStatus:
2783 rtl8139_BasicModeStatus_write(s, val);
2784 break;
2785 case NWayAdvert:
7cdeb319 2786 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2787 s->NWayAdvert = val;
2788 break;
2789 case NWayLPAR:
7cdeb319 2790 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2791 break;
2792 case NWayExpansion:
7cdeb319 2793 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2794 s->NWayExpansion = val;
2795 break;
2796
2797 case CpCmd:
2798 rtl8139_CpCmd_write(s, val);
2799 break;
2800
6cadb320
FB		 2801 case IntrMitigate:
2802 rtl8139_IntrMitigate_write(s, val);
2803 break;
2804
a41b2ff2 2805 default:
7cdeb319
BP		 2806 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2807 addr, val);
a41b2ff2 2808
a41b2ff2
PB		 2809 rtl8139_io_writeb(opaque, addr, val & 0xff);
2810 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2811 break;
2812 }
2813}
2814
237c255c 2815static void rtl8139_set_next_tctr_time(RTL8139State *s)
05447803 2816{
37b9ab92 2817 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32;
05447803 2818
7cdeb319 2819 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803 2820
237c255c
PB		 2821 /* This function is called at least once per period, so it is a good
2822 * place to update the timer base.
2823 *
2824 * After one iteration of this loop the value in the Timer register does
2825 * not change, but the device model is counting up by 2^32 ticks (approx.
2826 * 130 seconds).
05447803 2827 */
237c255c
PB		 2828 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2829 s->TCTR_base += ns_per_period;
05447803 2830 }
05447803 2831
237c255c
PB		 2832 if (!s->TimerInt) {
2833 timer_del(s->timer);
2834 } else {
37b9ab92 2835 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD;
237c255c
PB		 2836 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2837 delta += ns_per_period;
2838 }
2839 timer_mod(s->timer, s->TCTR_base + delta);
05447803
FZ		 2840 }
2841}
2842
a41b2ff2
PB		 2843static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2844{
2845 RTL8139State *s = opaque;
2846
a41b2ff2
PB		 2847 switch (addr)
2848 {
2849 case RxMissed:
7cdeb319 2850 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2851 s->RxMissed = 0;
2852 break;
2853
2854 case TxConfig:
2855 rtl8139_TxConfig_write(s, val);
2856 break;
2857
2858 case RxConfig:
2859 rtl8139_RxConfig_write(s, val);
2860 break;
2861
2862 case TxStatus0 ... TxStatus0+4*4-1:
2863 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2864 break;
2865
2866 case TxAddr0 ... TxAddr0+4*4-1:
2867 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2868 break;
2869
2870 case RxBuf:
2871 rtl8139_RxBuf_write(s, val);
2872 break;
2873
2874 case RxRingAddrLO:
7cdeb319 2875 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2876 s->RxRingAddrLO = val;
2877 break;
2878
2879 case RxRingAddrHI:
7cdeb319 2880 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2881 s->RxRingAddrHI = val;
2882 break;
2883
6cadb320 2884 case Timer:
7cdeb319 2885 DPRINTF("TCTR Timer reset on write\n");
bc72ad67 2886 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
237c255c 2887 rtl8139_set_next_tctr_time(s);
6cadb320
FB		 2888 break;
2889
2890 case FlashReg:
7cdeb319 2891 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2892 if (s->TimerInt != val) {
2893 s->TimerInt = val;
237c255c 2894 rtl8139_set_next_tctr_time(s);
05447803 2895 }
6cadb320
FB		 2896 break;
2897
a41b2ff2 2898 default:
7cdeb319
BP		 2899 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2900 addr, val);
a41b2ff2
PB		 2901 rtl8139_io_writeb(opaque, addr, val & 0xff);
2902 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2903 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2904 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2905 break;
2906 }
2907}
2908
2909static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2910{
2911 RTL8139State *s = opaque;
2912 int ret;
2913
a41b2ff2
PB		 2914 switch (addr)
2915 {
2916 case MAC0 ... MAC0+5:
2917 ret = s->phys[addr - MAC0];
2918 break;
2919 case MAC0+6 ... MAC0+7:
2920 ret = 0;
2921 break;
2922 case MAR0 ... MAR0+7:
2923 ret = s->mult[addr - MAR0];
2924 break;
afe0a595 2925 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 2926 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2927 addr, 1);
afe0a595 2928 break;
a41b2ff2
PB		 2929 case ChipCmd:
2930 ret = rtl8139_ChipCmd_read(s);
2931 break;
2932 case Cfg9346:
2933 ret = rtl8139_Cfg9346_read(s);
2934 break;
2935 case Config0:
2936 ret = rtl8139_Config0_read(s);
2937 break;
2938 case Config1:
2939 ret = rtl8139_Config1_read(s);
2940 break;
2941 case Config3:
2942 ret = rtl8139_Config3_read(s);
2943 break;
2944 case Config4:
2945 ret = rtl8139_Config4_read(s);
2946 break;
2947 case Config5:
2948 ret = rtl8139_Config5_read(s);
2949 break;
2950
2951 case MediaStatus:
9e12c5af
JW		 2952 /* The LinkDown bit of MediaStatus is inverse with link status */
2953 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
7cdeb319 2954 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 2955 break;
2956
2957 case HltClk:
2958 ret = s->clock_enabled;
7cdeb319 2959 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 2960 break;
2961
2962 case PCIRevisionID:
6cadb320 2963 ret = RTL8139_PCI_REVID;
7cdeb319 2964 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 2965 break;
2966
2967 case TxThresh:
2968 ret = s->TxThresh;
7cdeb319 2969 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 2970 break;
2971
2972 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2973 ret = s->TxConfig >> 24;
7cdeb319 2974 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 2975 break;
2976
2977 default:
7cdeb319 2978 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 2979 ret = 0;
2980 break;
2981 }
2982
2983 return ret;
2984}
2985
2986static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2987{
2988 RTL8139State *s = opaque;
2989 uint32_t ret;
2990
a41b2ff2
PB		 2991 switch (addr)
2992 {
afe0a595 2993 case TxAddr0 ... TxAddr0+4*4-1:
3e48dd4a 2994 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
afe0a595 2995 break;
a41b2ff2
PB		 2996 case IntrMask:
2997 ret = rtl8139_IntrMask_read(s);
2998 break;
2999
3000 case IntrStatus:
3001 ret = rtl8139_IntrStatus_read(s);
3002 break;
3003
3004 case MultiIntr:
3005 ret = rtl8139_MultiIntr_read(s);
3006 break;
3007
3008 case RxBufPtr:
3009 ret = rtl8139_RxBufPtr_read(s);
3010 break;
3011
6cadb320
FB		 3012 case RxBufAddr:
3013 ret = rtl8139_RxBufAddr_read(s);
3014 break;
3015
a41b2ff2
PB		 3016 case BasicModeCtrl:
3017 ret = rtl8139_BasicModeCtrl_read(s);
3018 break;
3019 case BasicModeStatus:
3020 ret = rtl8139_BasicModeStatus_read(s);
3021 break;
3022 case NWayAdvert:
3023 ret = s->NWayAdvert;
7cdeb319 3024 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3025 break;
3026 case NWayLPAR:
3027 ret = s->NWayLPAR;
7cdeb319 3028 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3029 break;
3030 case NWayExpansion:
3031 ret = s->NWayExpansion;
7cdeb319 3032 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3033 break;
3034
3035 case CpCmd:
3036 ret = rtl8139_CpCmd_read(s);
3037 break;
3038
6cadb320
FB		 3039 case IntrMitigate:
3040 ret = rtl8139_IntrMitigate_read(s);
3041 break;
3042
a41b2ff2
PB		 3043 case TxSummary:
3044 ret = rtl8139_TSAD_read(s);
3045 break;
3046
3047 case CSCR:
3048 ret = rtl8139_CSCR_read(s);
3049 break;
3050
3051 default:
7cdeb319 3052 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3053
a41b2ff2
PB		 3054 ret = rtl8139_io_readb(opaque, addr);
3055 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3056
7cdeb319 3057 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3058 break;
3059 }
3060
3061 return ret;
3062}
3063
3064static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3065{
3066 RTL8139State *s = opaque;
3067 uint32_t ret;
3068
a41b2ff2
PB		 3069 switch (addr)
3070 {
3071 case RxMissed:
3072 ret = s->RxMissed;
3073
7cdeb319 3074 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3075 break;
3076
3077 case TxConfig:
3078 ret = rtl8139_TxConfig_read(s);
3079 break;
3080
3081 case RxConfig:
3082 ret = rtl8139_RxConfig_read(s);
3083 break;
3084
3085 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 3086 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3087 addr, 4);
a41b2ff2
PB		 3088 break;
3089
3090 case TxAddr0 ... TxAddr0+4*4-1:
3091 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3092 break;
3093
3094 case RxBuf:
3095 ret = rtl8139_RxBuf_read(s);
3096 break;
3097
3098 case RxRingAddrLO:
3099 ret = s->RxRingAddrLO;
7cdeb319 3100 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3101 break;
3102
3103 case RxRingAddrHI:
3104 ret = s->RxRingAddrHI;
7cdeb319 3105 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3106 break;
3107
3108 case Timer:
37b9ab92
LV		 3109 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) /
3110 PCI_PERIOD;
7cdeb319 3111 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3112 break;
3113
3114 case FlashReg:
3115 ret = s->TimerInt;
7cdeb319 3116 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3117 break;
3118
3119 default:
7cdeb319 3120 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3121
a41b2ff2
PB		 3122 ret = rtl8139_io_readb(opaque, addr);
3123 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3124 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3125 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3126
7cdeb319 3127 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3128 break;
3129 }
3130
3131 return ret;
3132}
3133
3134/* */
3135
060110c3 3136static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3137{
6597ebbb 3138 RTL8139State* s = opaque;
237c255c 3139 rtl8139_set_next_tctr_time(s);
060110c3 3140 if (version_id < 4) {
2c3891ab
AL		 3141 s->cplus_enabled = s->CpCmd != 0;
3142 }
3143
9e12c5af
JW		 3144 /* nc.link_down can't be migrated, so infer link_down according
3145 * to link status bit in BasicModeStatus */
b356f76d 3146 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
9e12c5af 3147
a41b2ff2
PB		 3148 return 0;
3149}
3150
c574ba5a
AW		 3151static bool rtl8139_hotplug_ready_needed(void *opaque)
3152{
3153 return qdev_machine_modified();
3154}
3155
3156static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3157 .name = "rtl8139/hotplug_ready",
3158 .version_id = 1,
3159 .minimum_version_id = 1,
5cd8cada 3160 .needed = rtl8139_hotplug_ready_needed,
d49805ae 3161 .fields = (VMStateField[]) {
c574ba5a
AW		 3162 VMSTATE_END_OF_LIST()
3163 }
3164};
3165
44b1ff31 3166static int rtl8139_pre_save(void *opaque)
05447803
FZ		 3167{
3168 RTL8139State* s = opaque;
bc72ad67 3169 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
05447803 3170
237c255c 3171 /* for migration to older versions */
37b9ab92 3172 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD;
bd80f3fc 3173 s->rtl8139_mmio_io_addr_dummy = 0;
44b1ff31
DDAG		 3174
3175 return 0;
05447803
FZ		 3176}
3177
060110c3
JQ		 3178static const VMStateDescription vmstate_rtl8139 = {
3179 .name = "rtl8139",
46fe8bef 3180 .version_id = 5,
060110c3 3181 .minimum_version_id = 3,
060110c3 3182 .post_load = rtl8139_post_load,
05447803 3183 .pre_save = rtl8139_pre_save,
d49805ae 3184 .fields = (VMStateField[]) {
88a411a8 3185 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
060110c3
JQ		 3186 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3187 VMSTATE_BUFFER(mult, RTL8139State),
3188 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3189 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3190
3191 VMSTATE_UINT32(RxBuf, RTL8139State),
3192 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3193 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3194 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3195
3196 VMSTATE_UINT16(IntrStatus, RTL8139State),
3197 VMSTATE_UINT16(IntrMask, RTL8139State),
3198
3199 VMSTATE_UINT32(TxConfig, RTL8139State),
3200 VMSTATE_UINT32(RxConfig, RTL8139State),
3201 VMSTATE_UINT32(RxMissed, RTL8139State),
3202 VMSTATE_UINT16(CSCR, RTL8139State),
3203
3204 VMSTATE_UINT8(Cfg9346, RTL8139State),
3205 VMSTATE_UINT8(Config0, RTL8139State),
3206 VMSTATE_UINT8(Config1, RTL8139State),
3207 VMSTATE_UINT8(Config3, RTL8139State),
3208 VMSTATE_UINT8(Config4, RTL8139State),
3209 VMSTATE_UINT8(Config5, RTL8139State),
3210
3211 VMSTATE_UINT8(clock_enabled, RTL8139State),
3212 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3213
3214 VMSTATE_UINT16(MultiIntr, RTL8139State),
3215
3216 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3217 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3218 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3219 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3220 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3221
3222 VMSTATE_UINT16(CpCmd, RTL8139State),
3223 VMSTATE_UINT8(TxThresh, RTL8139State),
3224
3225 VMSTATE_UNUSED(4),
3226 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3227 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3228
3229 VMSTATE_UINT32(currTxDesc, RTL8139State),
3230 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3231 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3232 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3233 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3234
3235 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3236 VMSTATE_INT32(eeprom.mode, RTL8139State),
3237 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3238 VMSTATE_UINT8(eeprom.address, RTL8139State),
3239 VMSTATE_UINT16(eeprom.input, RTL8139State),
3240 VMSTATE_UINT16(eeprom.output, RTL8139State),
3241
3242 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3243 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3244 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3245 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3246
3247 VMSTATE_UINT32(TCTR, RTL8139State),
3248 VMSTATE_UINT32(TimerInt, RTL8139State),
3249 VMSTATE_INT64(TCTR_base, RTL8139State),
3250
46fe8bef
DV		 3251 VMSTATE_UINT64(tally_counters.TxOk, RTL8139State),
3252 VMSTATE_UINT64(tally_counters.RxOk, RTL8139State),
3253 VMSTATE_UINT64(tally_counters.TxERR, RTL8139State),
3254 VMSTATE_UINT32(tally_counters.RxERR, RTL8139State),
3255 VMSTATE_UINT16(tally_counters.MissPkt, RTL8139State),
3256 VMSTATE_UINT16(tally_counters.FAE, RTL8139State),
3257 VMSTATE_UINT32(tally_counters.Tx1Col, RTL8139State),
3258 VMSTATE_UINT32(tally_counters.TxMCol, RTL8139State),
3259 VMSTATE_UINT64(tally_counters.RxOkPhy, RTL8139State),
3260 VMSTATE_UINT64(tally_counters.RxOkBrd, RTL8139State),
3261 VMSTATE_UINT32_V(tally_counters.RxOkMul, RTL8139State, 5),
3262 VMSTATE_UINT16(tally_counters.TxAbt, RTL8139State),
3263 VMSTATE_UINT16(tally_counters.TxUndrn, RTL8139State),
060110c3
JQ		 3264
3265 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3266 VMSTATE_END_OF_LIST()
c574ba5a 3267 },
5cd8cada
JQ		 3268 .subsections = (const VMStateDescription*[]) {
3269 &vmstate_rtl8139_hotplug_ready,
3270 NULL
060110c3
JQ		 3271 }
3272};
3273
a41b2ff2
PB		 3274/***********************************************************/
3275/* PCI RTL8139 definitions */
3276
1bebb0ad
AG		 3277static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3278 uint64_t val, unsigned size)
3279{
3280 switch (size) {
3281 case 1:
3282 rtl8139_io_writeb(opaque, addr, val);
3283 break;
3284 case 2:
3285 rtl8139_io_writew(opaque, addr, val);
3286 break;
3287 case 4:
3288 rtl8139_io_writel(opaque, addr, val);
3289 break;
3290 }
3291}
3292
3293static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3294 unsigned size)
3295{
3296 switch (size) {
3297 case 1:
3298 return rtl8139_io_readb(opaque, addr);
3299 case 2:
3300 return rtl8139_io_readw(opaque, addr);
3301 case 4:
3302 return rtl8139_io_readl(opaque, addr);
3303 }
3304
3305 return -1;
3306}
a41b2ff2 3307
bd80f3fc 3308static const MemoryRegionOps rtl8139_io_ops = {
1bebb0ad
AG		 3309 .read = rtl8139_ioport_read,
3310 .write = rtl8139_ioport_write,
3311 .impl = {
3312 .min_access_size = 1,
3313 .max_access_size = 4,
3314 },
bd80f3fc 3315 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3316};
3317
6cadb320
FB		 3318static void rtl8139_timer(void *opaque)
3319{
3320 RTL8139State *s = opaque;
3321
6cadb320
FB		 3322 if (!s->clock_enabled)
3323 {
7cdeb319 3324 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3325 return;
3326 }
3327
05447803
FZ		 3328 s->IntrStatus |= PCSTimeout;
3329 rtl8139_update_irq(s);
237c255c 3330 rtl8139_set_next_tctr_time(s);
6cadb320 3331}
6cadb320 3332
f90c2bcd 3333static void pci_rtl8139_uninit(PCIDevice *dev)
254111ec 3334{
39257515 3335 RTL8139State *s = RTL8139(dev);
254111ec 3336
012aef07
MA		 3337 g_free(s->cplus_txbuffer);
3338 s->cplus_txbuffer = NULL;
bc72ad67
AB		 3339 timer_del(s->timer);
3340 timer_free(s->timer);
948ecf21 3341 qemu_del_nic(s->nic);
b946a153
AL		 3342}
3343
9e12c5af
JW		 3344static void rtl8139_set_link_status(NetClientState *nc)
3345{
cc1f0f45 3346 RTL8139State *s = qemu_get_nic_opaque(nc);
9e12c5af
JW		 3347
3348 if (nc->link_down) {
3349 s->BasicModeStatus &= ~0x04;
3350 } else {
3351 s->BasicModeStatus |= 0x04;
3352 }
3353
3354 s->IntrStatus |= RxUnderrun;
3355 rtl8139_update_irq(s);
3356}
3357
1673ad51 3358static NetClientInfo net_rtl8139_info = {
f394b2e2 3359 .type = NET_CLIENT_DRIVER_NIC,
1673ad51
MM		 3360 .size = sizeof(NICState),
3361 .can_receive = rtl8139_can_receive,
3362 .receive = rtl8139_receive,
9e12c5af 3363 .link_status_changed = rtl8139_set_link_status,
1673ad51
MM		 3364};
3365
9af21dbe 3366static void pci_rtl8139_realize(PCIDevice *dev, Error **errp)
a41b2ff2 3367{
39257515
PC		 3368 RTL8139State *s = RTL8139(dev);
3369 DeviceState *d = DEVICE(dev);
a41b2ff2 3370 uint8_t *pci_conf;
3b46e624 3371
88a411a8 3372 pci_conf = dev->config;
817e0b6f 3373 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3374 /* TODO: start of capability list, but no capability
3375 * list bit in status register, and offset 0xdc seems unused. */
3376 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3377
eedfac6f
PB		 3378 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s,
3379 "rtl8139", 0x100);
726ec828
MP		 3380 memory_region_init_alias(&s->bar_mem, OBJECT(s), "rtl8139-mem", &s->bar_io,
3381 0, 0x100);
3382
88a411a8
AF		 3383 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3384 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3385
254111ec 3386 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3387
7165448a
WD		 3388 /* prepare eeprom */
3389 s->eeprom.contents[0] = 0x8129;
3390#if 1
3391 /* PCI vendor and device ID should be mirrored here */
3392 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3393 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3394#endif
3395 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3396 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3397 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3398
1673ad51 3399 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
39257515 3400 object_get_typename(OBJECT(dev)), d->id, s);
b356f76d 3401 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
6cadb320
FB		 3402
3403 s->cplus_txbuffer = NULL;
3404 s->cplus_txbuffer_len = 0;
3405 s->cplus_txbuffer_offset = 0;
3b46e624 3406
bc72ad67 3407 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s);
a41b2ff2 3408}
9d07d757 3409
afd7c850
GA		 3410static void rtl8139_instance_init(Object *obj)
3411{
3412 RTL8139State *s = RTL8139(obj);
3413
3414 device_add_bootindex_property(obj, &s->conf.bootindex,
3415 "bootindex", "/ethernet-phy@0",
3416 DEVICE(obj), NULL);
3417}
3418
40021f08
AL		 3419static Property rtl8139_properties[] = {
3420 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3421 DEFINE_PROP_END_OF_LIST(),
3422};
3423
3424static void rtl8139_class_init(ObjectClass *klass, void *data)
3425{
39bffca2 3426 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3427 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3428
9af21dbe 3429 k->realize = pci_rtl8139_realize;
40021f08 3430 k->exit = pci_rtl8139_uninit;
c45e5b5b 3431 k->romfile = "efi-rtl8139.rom";
40021f08
AL		 3432 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3433 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3434 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3435 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 3436 dc->reset = rtl8139_reset;
3437 dc->vmsd = &vmstate_rtl8139;
4f67d30b 3438 device_class_set_props(dc, rtl8139_properties);
125ee0ed 3439 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
40021f08
AL		 3440}
3441
8c43a6f0 3442static const TypeInfo rtl8139_info = {
39257515 3443 .name = TYPE_RTL8139,
39bffca2
AL		 3444 .parent = TYPE_PCI_DEVICE,
3445 .instance_size = sizeof(RTL8139State),
3446 .class_init = rtl8139_class_init,
afd7c850 3447 .instance_init = rtl8139_instance_init,
fd3b02c8
EH		 3448 .interfaces = (InterfaceInfo[]) {
3449 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3450 { },
3451 },
0aab0d3a
GH		 3452};
3453
83f7d43a 3454static void rtl8139_register_types(void)
9d07d757 3455{
39bffca2 3456 type_register_static(&rtl8139_info);
9d07d757
PB		 3457}
3458
83f7d43a 3459type_init(rtl8139_register_types)
Empty description
This page took 1.714239 seconds and 4 git commands to generate.