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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
a41b2ff2
PB		 48 */
49
87ecb68b
PB		 50#include "hw.h"
51#include "pci.h"
52#include "qemu-timer.h"
53#include "net.h"
254111ec 54#include "loader.h"
1ca4d09a 55#include "sysemu.h"
a41b2ff2 56
a41b2ff2
PB		 57/* debug RTL8139 card */
58//#define DEBUG_RTL8139 1
59
6cadb320
FB		 60#define PCI_FREQUENCY 33000000L
61
a41b2ff2
PB		 62/* debug RTL8139 card C+ mode only */
63//#define DEBUG_RTL8139CP 1
64
ccf1d14a
TS		 65/* Calculate CRCs properly on Rx packets */
66#define RTL8139_CALCULATE_RXCRC 1
a41b2ff2 67
a41b2ff2
PB		 68#if defined(RTL8139_CALCULATE_RXCRC)
69/* For crc32 */
70#include <zlib.h>
71#endif
72
73#define SET_MASKED(input, mask, curr) \
74 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
75
76/* arg % size for size which is a power of 2 */
77#define MOD2(input, size) \
78 ( ( input ) & ( size - 1 ) )
79
6cadb320
FB		 80#if defined (DEBUG_RTL8139)
81# define DEBUG_PRINT(x) do { printf x ; } while (0)
82#else
83# define DEBUG_PRINT(x)
84#endif
85
a41b2ff2
PB		 86/* Symbolic offsets to registers. */
87enum RTL8139_registers {
88 MAC0 = 0, /* Ethernet hardware address. */
89 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 90 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
91 /* Dump Tally Conter control register(64bit). C+ mode only */
92 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 93 RxBuf = 0x30,
94 ChipCmd = 0x37,
95 RxBufPtr = 0x38,
96 RxBufAddr = 0x3A,
97 IntrMask = 0x3C,
98 IntrStatus = 0x3E,
99 TxConfig = 0x40,
100 RxConfig = 0x44,
101 Timer = 0x48, /* A general-purpose counter. */
102 RxMissed = 0x4C, /* 24 bits valid, write clears. */
103 Cfg9346 = 0x50,
104 Config0 = 0x51,
105 Config1 = 0x52,
106 FlashReg = 0x54,
107 MediaStatus = 0x58,
108 Config3 = 0x59,
109 Config4 = 0x5A, /* absent on RTL-8139A */
110 HltClk = 0x5B,
111 MultiIntr = 0x5C,
112 PCIRevisionID = 0x5E,
113 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
114 BasicModeCtrl = 0x62,
115 BasicModeStatus = 0x64,
116 NWayAdvert = 0x66,
117 NWayLPAR = 0x68,
118 NWayExpansion = 0x6A,
119 /* Undocumented registers, but required for proper operation. */
120 FIFOTMS = 0x70, /* FIFO Control and test. */
121 CSCR = 0x74, /* Chip Status and Configuration Register. */
122 PARA78 = 0x78,
123 PARA7c = 0x7c, /* Magic transceiver parameter register. */
124 Config5 = 0xD8, /* absent on RTL-8139A */
125 /* C+ mode */
126 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
127 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
128 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
129 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
130 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
131 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
132 TxThresh = 0xEC, /* Early Tx threshold */
133};
134
135enum ClearBitMasks {
136 MultiIntrClear = 0xF000,
137 ChipCmdClear = 0xE2,
138 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
139};
140
141enum ChipCmdBits {
142 CmdReset = 0x10,
143 CmdRxEnb = 0x08,
144 CmdTxEnb = 0x04,
145 RxBufEmpty = 0x01,
146};
147
148/* C+ mode */
149enum CplusCmdBits {
6cadb320
FB		 150 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
151 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
152 CPlusRxEnb = 0x0002,
153 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 154};
155
156/* Interrupt register bits, using my own meaningful names. */
157enum IntrStatusBits {
158 PCIErr = 0x8000,
159 PCSTimeout = 0x4000,
160 RxFIFOOver = 0x40,
161 RxUnderrun = 0x20,
162 RxOverflow = 0x10,
163 TxErr = 0x08,
164 TxOK = 0x04,
165 RxErr = 0x02,
166 RxOK = 0x01,
167
168 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
169};
170
171enum TxStatusBits {
172 TxHostOwns = 0x2000,
173 TxUnderrun = 0x4000,
174 TxStatOK = 0x8000,
175 TxOutOfWindow = 0x20000000,
176 TxAborted = 0x40000000,
177 TxCarrierLost = 0x80000000,
178};
179enum RxStatusBits {
180 RxMulticast = 0x8000,
181 RxPhysical = 0x4000,
182 RxBroadcast = 0x2000,
183 RxBadSymbol = 0x0020,
184 RxRunt = 0x0010,
185 RxTooLong = 0x0008,
186 RxCRCErr = 0x0004,
187 RxBadAlign = 0x0002,
188 RxStatusOK = 0x0001,
189};
190
191/* Bits in RxConfig. */
192enum rx_mode_bits {
193 AcceptErr = 0x20,
194 AcceptRunt = 0x10,
195 AcceptBroadcast = 0x08,
196 AcceptMulticast = 0x04,
197 AcceptMyPhys = 0x02,
198 AcceptAllPhys = 0x01,
199};
200
201/* Bits in TxConfig. */
202enum tx_config_bits {
203
204 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
205 TxIFGShift = 24,
206 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
207 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
208 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
209 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
210
211 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
212 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
213 TxClearAbt = (1 << 0), /* Clear abort (WO) */
214 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
215 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
216
217 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
218};
219
220
221/* Transmit Status of All Descriptors (TSAD) Register */
222enum TSAD_bits {
223 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
224 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
225 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
226 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
227 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
228 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
229 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
230 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
231 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
232 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
233 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
234 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
235 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
236 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
237 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
238 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
239};
240
241
242/* Bits in Config1 */
243enum Config1Bits {
244 Cfg1_PM_Enable = 0x01,
245 Cfg1_VPD_Enable = 0x02,
246 Cfg1_PIO = 0x04,
247 Cfg1_MMIO = 0x08,
248 LWAKE = 0x10, /* not on 8139, 8139A */
249 Cfg1_Driver_Load = 0x20,
250 Cfg1_LED0 = 0x40,
251 Cfg1_LED1 = 0x80,
252 SLEEP = (1 << 1), /* only on 8139, 8139A */
253 PWRDN = (1 << 0), /* only on 8139, 8139A */
254};
255
256/* Bits in Config3 */
257enum Config3Bits {
258 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
259 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
260 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
261 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
262 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
263 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
264 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
265 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
266};
267
268/* Bits in Config4 */
269enum Config4Bits {
270 LWPTN = (1 << 2), /* not on 8139, 8139A */
271};
272
273/* Bits in Config5 */
274enum Config5Bits {
275 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
276 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
277 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
278 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
279 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
280 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
281 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
282};
283
284enum RxConfigBits {
285 /* rx fifo threshold */
286 RxCfgFIFOShift = 13,
287 RxCfgFIFONone = (7 << RxCfgFIFOShift),
288
289 /* Max DMA burst */
290 RxCfgDMAShift = 8,
291 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
292
293 /* rx ring buffer length */
294 RxCfgRcv8K = 0,
295 RxCfgRcv16K = (1 << 11),
296 RxCfgRcv32K = (1 << 12),
297 RxCfgRcv64K = (1 << 11) | (1 << 12),
298
299 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
300 RxNoWrap = (1 << 7),
301};
302
303/* Twister tuning parameters from RealTek.
304 Completely undocumented, but required to tune bad links on some boards. */
305/*
306enum CSCRBits {
307 CSCR_LinkOKBit = 0x0400,
308 CSCR_LinkChangeBit = 0x0800,
309 CSCR_LinkStatusBits = 0x0f000,
310 CSCR_LinkDownOffCmd = 0x003c0,
311 CSCR_LinkDownCmd = 0x0f3c0,
312*/
313enum CSCRBits {
5fafdf24 314 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 315 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
316 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
317 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 318 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 319 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
320 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
321 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
322 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
323};
324
325enum Cfg9346Bits {
326 Cfg9346_Lock = 0x00,
327 Cfg9346_Unlock = 0xC0,
328};
329
330typedef enum {
331 CH_8139 = 0,
332 CH_8139_K,
333 CH_8139A,
334 CH_8139A_G,
335 CH_8139B,
336 CH_8130,
337 CH_8139C,
338 CH_8100,
339 CH_8100B_8139D,
340 CH_8101,
c227f099 341} chip_t;
a41b2ff2
PB		 342
343enum chip_flags {
344 HasHltClk = (1 << 0),
345 HasLWake = (1 << 1),
346};
347
348#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
349 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
350#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
351
6cadb320
FB		 352#define RTL8139_PCI_REVID_8139 0x10
353#define RTL8139_PCI_REVID_8139CPLUS 0x20
354
355#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
356
a41b2ff2
PB		 357/* Size is 64 * 16bit words */
358#define EEPROM_9346_ADDR_BITS 6
359#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
360#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
361
362enum Chip9346Operation
363{
364 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
365 Chip9346_op_read = 0x80, /* 10 AAAAAA */
366 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
367 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
368 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
369 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
370 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
371};
372
373enum Chip9346Mode
374{
375 Chip9346_none = 0,
376 Chip9346_enter_command_mode,
377 Chip9346_read_command,
378 Chip9346_data_read, /* from output register */
379 Chip9346_data_write, /* to input register, then to contents at specified address */
380 Chip9346_data_write_all, /* to input register, then filling contents */
381};
382
383typedef struct EEprom9346
384{
385 uint16_t contents[EEPROM_9346_SIZE];
386 int mode;
387 uint32_t tick;
388 uint8_t address;
389 uint16_t input;
390 uint16_t output;
391
392 uint8_t eecs;
393 uint8_t eesk;
394 uint8_t eedi;
395 uint8_t eedo;
396} EEprom9346;
397
6cadb320
FB		 398typedef struct RTL8139TallyCounters
399{
400 /* Tally counters */
401 uint64_t TxOk;
402 uint64_t RxOk;
403 uint64_t TxERR;
404 uint32_t RxERR;
405 uint16_t MissPkt;
406 uint16_t FAE;
407 uint32_t Tx1Col;
408 uint32_t TxMCol;
409 uint64_t RxOkPhy;
410 uint64_t RxOkBrd;
411 uint32_t RxOkMul;
412 uint16_t TxAbt;
413 uint16_t TxUndrn;
414} RTL8139TallyCounters;
415
416/* Clears all tally counters */
417static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
418
419/* Writes tally counters to specified physical memory address */
c227f099 420static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
6cadb320 421
a41b2ff2 422typedef struct RTL8139State {
efd6dd45 423 PCIDevice dev;
a41b2ff2
PB		 424 uint8_t phys[8]; /* mac address */
425 uint8_t mult[8]; /* multicast mask array */
426
6cadb320 427 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 428 uint32_t TxAddr[4]; /* TxAddr0 */
429 uint32_t RxBuf; /* Receive buffer */
430 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
431 uint32_t RxBufPtr;
432 uint32_t RxBufAddr;
433
434 uint16_t IntrStatus;
435 uint16_t IntrMask;
436
437 uint32_t TxConfig;
438 uint32_t RxConfig;
439 uint32_t RxMissed;
440
441 uint16_t CSCR;
442
443 uint8_t Cfg9346;
444 uint8_t Config0;
445 uint8_t Config1;
446 uint8_t Config3;
447 uint8_t Config4;
448 uint8_t Config5;
449
450 uint8_t clock_enabled;
451 uint8_t bChipCmdState;
452
453 uint16_t MultiIntr;
454
455 uint16_t BasicModeCtrl;
456 uint16_t BasicModeStatus;
457 uint16_t NWayAdvert;
458 uint16_t NWayLPAR;
459 uint16_t NWayExpansion;
460
461 uint16_t CpCmd;
462 uint8_t TxThresh;
463
1673ad51 464 NICState *nic;
254111ec 465 NICConf conf;
a41b2ff2
PB		 466 int rtl8139_mmio_io_addr;
467
468 /* C ring mode */
469 uint32_t currTxDesc;
470
471 /* C+ mode */
2c3891ab
AL		 472 uint32_t cplus_enabled;
473
a41b2ff2
PB		 474 uint32_t currCPlusRxDesc;
475 uint32_t currCPlusTxDesc;
476
477 uint32_t RxRingAddrLO;
478 uint32_t RxRingAddrHI;
479
480 EEprom9346 eeprom;
6cadb320
FB		 481
482 uint32_t TCTR;
483 uint32_t TimerInt;
484 int64_t TCTR_base;
485
486 /* Tally counters */
487 RTL8139TallyCounters tally_counters;
488
489 /* Non-persistent data */
490 uint8_t *cplus_txbuffer;
491 int cplus_txbuffer_len;
492 int cplus_txbuffer_offset;
493
494 /* PCI interrupt timer */
495 QEMUTimer *timer;
05447803 496 int64_t TimerExpire;
6cadb320 497
a41b2ff2
PB		 498} RTL8139State;
499
05447803
FZ		 500static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
501
9596ebb7 502static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 503{
6cadb320 504 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
a41b2ff2
PB		 505
506 switch (command & Chip9346_op_mask)
507 {
508 case Chip9346_op_read:
509 {
510 eeprom->address = command & EEPROM_9346_ADDR_MASK;
511 eeprom->output = eeprom->contents[eeprom->address];
512 eeprom->eedo = 0;
513 eeprom->tick = 0;
514 eeprom->mode = Chip9346_data_read;
6cadb320
FB		 515 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
516 eeprom->address, eeprom->output));
a41b2ff2
PB		 517 }
518 break;
519
520 case Chip9346_op_write:
521 {
522 eeprom->address = command & EEPROM_9346_ADDR_MASK;
523 eeprom->input = 0;
524 eeprom->tick = 0;
525 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
6cadb320
FB		 526 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
527 eeprom->address));
a41b2ff2
PB		 528 }
529 break;
530 default:
531 eeprom->mode = Chip9346_none;
532 switch (command & Chip9346_op_ext_mask)
533 {
534 case Chip9346_op_write_enable:
6cadb320 535 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
a41b2ff2
PB		 536 break;
537 case Chip9346_op_write_all:
6cadb320 538 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
a41b2ff2
PB		 539 break;
540 case Chip9346_op_write_disable:
6cadb320 541 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
a41b2ff2
PB		 542 break;
543 }
544 break;
545 }
546}
547
9596ebb7 548static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 549{
550 int bit = eeprom->eedi?1:0;
551
552 ++ eeprom->tick;
553
6cadb320 554 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 555
556 switch (eeprom->mode)
557 {
558 case Chip9346_enter_command_mode:
559 if (bit)
560 {
561 eeprom->mode = Chip9346_read_command;
562 eeprom->tick = 0;
563 eeprom->input = 0;
6cadb320 564 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
a41b2ff2
PB		 565 }
566 break;
567
568 case Chip9346_read_command:
569 eeprom->input = (eeprom->input << 1) | (bit & 1);
570 if (eeprom->tick == 8)
571 {
572 prom9346_decode_command(eeprom, eeprom->input & 0xff);
573 }
574 break;
575
576 case Chip9346_data_read:
577 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
578 eeprom->output <<= 1;
579 if (eeprom->tick == 16)
580 {
6cadb320
FB		 581#if 1
582 // the FreeBSD drivers (rl and re) don't explicitly toggle
583 // CS between reads (or does setting Cfg9346 to 0 count too?),
584 // so we need to enter wait-for-command state here
585 eeprom->mode = Chip9346_enter_command_mode;
586 eeprom->input = 0;
587 eeprom->tick = 0;
588
589 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
590#else
591 // original behaviour
a41b2ff2
PB		 592 ++eeprom->address;
593 eeprom->address &= EEPROM_9346_ADDR_MASK;
594 eeprom->output = eeprom->contents[eeprom->address];
595 eeprom->tick = 0;
596
6cadb320
FB		 597 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
598 eeprom->address, eeprom->output));
a41b2ff2
PB		 599#endif
600 }
601 break;
602
603 case Chip9346_data_write:
604 eeprom->input = (eeprom->input << 1) | (bit & 1);
605 if (eeprom->tick == 16)
606 {
6cadb320
FB		 607 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
608 eeprom->address, eeprom->input));
609
a41b2ff2
PB		 610 eeprom->contents[eeprom->address] = eeprom->input;
611 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
612 eeprom->tick = 0;
613 eeprom->input = 0;
614 }
615 break;
616
617 case Chip9346_data_write_all:
618 eeprom->input = (eeprom->input << 1) | (bit & 1);
619 if (eeprom->tick == 16)
620 {
621 int i;
622 for (i = 0; i < EEPROM_9346_SIZE; i++)
623 {
624 eeprom->contents[i] = eeprom->input;
625 }
6cadb320
FB		 626 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
627 eeprom->input));
628
a41b2ff2
PB		 629 eeprom->mode = Chip9346_enter_command_mode;
630 eeprom->tick = 0;
631 eeprom->input = 0;
632 }
633 break;
634
635 default:
636 break;
637 }
638}
639
9596ebb7 640static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 641{
642 EEprom9346 *eeprom = &s->eeprom;
643 if (!eeprom->eecs)
644 return 0;
645
646 return eeprom->eedo;
647}
648
9596ebb7
PB		 649/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
650static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 651{
652 EEprom9346 *eeprom = &s->eeprom;
653 uint8_t old_eecs = eeprom->eecs;
654 uint8_t old_eesk = eeprom->eesk;
655
656 eeprom->eecs = eecs;
657 eeprom->eesk = eesk;
658 eeprom->eedi = eedi;
659
6cadb320
FB		 660 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
661 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 662
663 if (!old_eecs && eecs)
664 {
665 /* Synchronize start */
666 eeprom->tick = 0;
667 eeprom->input = 0;
668 eeprom->output = 0;
669 eeprom->mode = Chip9346_enter_command_mode;
670
6cadb320 671 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
a41b2ff2
PB		 672 }
673
674 if (!eecs)
675 {
6cadb320 676 DEBUG_PRINT(("=== eeprom: end access\n"));
a41b2ff2
PB		 677 return;
678 }
679
680 if (!old_eesk && eesk)
681 {
682 /* SK front rules */
683 prom9346_shift_clock(eeprom);
684 }
685}
686
687static void rtl8139_update_irq(RTL8139State *s)
688{
689 int isr;
690 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 691
80a34d67
PB		 692 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
693 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
6cadb320 694
efd6dd45 695 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 696}
697
698#define POLYNOMIAL 0x04c11db6
699
700/* From FreeBSD */
701/* XXX: optimize */
702static int compute_mcast_idx(const uint8_t *ep)
703{
704 uint32_t crc;
705 int carry, i, j;
706 uint8_t b;
707
708 crc = 0xffffffff;
709 for (i = 0; i < 6; i++) {
710 b = *ep++;
711 for (j = 0; j < 8; j++) {
712 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
713 crc <<= 1;
714 b >>= 1;
715 if (carry)
716 crc = ((crc ^ POLYNOMIAL) | carry);
717 }
718 }
719 return (crc >> 26);
720}
721
722static int rtl8139_RxWrap(RTL8139State *s)
723{
724 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
725 return (s->RxConfig & (1 << 7));
726}
727
728static int rtl8139_receiver_enabled(RTL8139State *s)
729{
730 return s->bChipCmdState & CmdRxEnb;
731}
732
733static int rtl8139_transmitter_enabled(RTL8139State *s)
734{
735 return s->bChipCmdState & CmdTxEnb;
736}
737
738static int rtl8139_cp_receiver_enabled(RTL8139State *s)
739{
740 return s->CpCmd & CPlusRxEnb;
741}
742
743static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
744{
745 return s->CpCmd & CPlusTxEnb;
746}
747
748static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
749{
750 if (s->RxBufAddr + size > s->RxBufferSize)
751 {
752 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
753
754 /* write packet data */
ccf1d14a 755 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 756 {
6cadb320 757 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
a41b2ff2
PB		 758
759 if (size > wrapped)
760 {
761 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
762 buf, size-wrapped );
763 }
764
765 /* reset buffer pointer */
766 s->RxBufAddr = 0;
767
768 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
769 buf + (size-wrapped), wrapped );
770
771 s->RxBufAddr = wrapped;
772
773 return;
774 }
775 }
776
777 /* non-wrapping path or overwrapping enabled */
778 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
779
780 s->RxBufAddr += size;
781}
782
783#define MIN_BUF_SIZE 60
c227f099 784static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 785{
786#if TARGET_PHYS_ADDR_BITS > 32
c227f099 787 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 788#else
789 return low;
790#endif
791}
792
1673ad51 793static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 794{
1673ad51 795 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 796 int avail;
797
aa1f17c1 798 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 799 if (!s->clock_enabled)
800 return 1;
801 if (!rtl8139_receiver_enabled(s))
802 return 1;
803
804 if (rtl8139_cp_receiver_enabled(s)) {
805 /* ??? Flow control not implemented in c+ mode.
806 This is a hack to work around slirp deficiencies anyway. */
807 return 1;
808 } else {
809 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
810 s->RxBufferSize);
811 return (avail == 0 || avail >= 1514);
812 }
813}
814
1673ad51 815static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 816{
1673ad51 817 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
4f1c942b 818 int size = size_;
a41b2ff2
PB		 819
820 uint32_t packet_header = 0;
821
822 uint8_t buf1[60];
5fafdf24 823 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 824 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
825
6cadb320 826 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
a41b2ff2
PB		 827
828 /* test if board clock is stopped */
829 if (!s->clock_enabled)
830 {
6cadb320 831 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
4f1c942b 832 return -1;
a41b2ff2
PB		 833 }
834
835 /* first check if receiver is enabled */
836
837 if (!rtl8139_receiver_enabled(s))
838 {
6cadb320 839 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
4f1c942b 840 return -1;
a41b2ff2
PB		 841 }
842
843 /* XXX: check this */
844 if (s->RxConfig & AcceptAllPhys) {
845 /* promiscuous: receive all */
6cadb320 846 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
a41b2ff2
PB		 847
848 } else {
849 if (!memcmp(buf, broadcast_macaddr, 6)) {
850 /* broadcast address */
851 if (!(s->RxConfig & AcceptBroadcast))
852 {
6cadb320
FB		 853 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
854
855 /* update tally counter */
856 ++s->tally_counters.RxERR;
857
4f1c942b 858 return size;
a41b2ff2
PB		 859 }
860
861 packet_header |= RxBroadcast;
862
6cadb320
FB		 863 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
864
865 /* update tally counter */
866 ++s->tally_counters.RxOkBrd;
867
a41b2ff2
PB		 868 } else if (buf[0] & 0x01) {
869 /* multicast */
870 if (!(s->RxConfig & AcceptMulticast))
871 {
6cadb320
FB		 872 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
873
874 /* update tally counter */
875 ++s->tally_counters.RxERR;
876
4f1c942b 877 return size;
a41b2ff2
PB		 878 }
879
880 int mcast_idx = compute_mcast_idx(buf);
881
882 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
883 {
6cadb320
FB		 884 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
885
886 /* update tally counter */
887 ++s->tally_counters.RxERR;
888
4f1c942b 889 return size;
a41b2ff2
PB		 890 }
891
892 packet_header |= RxMulticast;
893
6cadb320
FB		 894 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
895
896 /* update tally counter */
897 ++s->tally_counters.RxOkMul;
898
a41b2ff2 899 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 900 s->phys[1] == buf[1] &&
901 s->phys[2] == buf[2] &&
902 s->phys[3] == buf[3] &&
903 s->phys[4] == buf[4] &&
a41b2ff2
PB		 904 s->phys[5] == buf[5]) {
905 /* match */
906 if (!(s->RxConfig & AcceptMyPhys))
907 {
6cadb320
FB		 908 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
909
910 /* update tally counter */
911 ++s->tally_counters.RxERR;
912
4f1c942b 913 return size;
a41b2ff2
PB		 914 }
915
916 packet_header |= RxPhysical;
917
6cadb320
FB		 918 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
919
920 /* update tally counter */
921 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 922
923 } else {
924
6cadb320
FB		 925 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
926
927 /* update tally counter */
928 ++s->tally_counters.RxERR;
929
4f1c942b 930 return size;
a41b2ff2
PB		 931 }
932 }
933
934 /* if too small buffer, then expand it */
935 if (size < MIN_BUF_SIZE) {
936 memcpy(buf1, buf, size);
937 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
938 buf = buf1;
939 size = MIN_BUF_SIZE;
940 }
941
942 if (rtl8139_cp_receiver_enabled(s))
943 {
6cadb320 944 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
a41b2ff2
PB		 945
946 /* begin C+ receiver mode */
947
948/* w0 ownership flag */
949#define CP_RX_OWN (1<<31)
950/* w0 end of ring flag */
951#define CP_RX_EOR (1<<30)
952/* w0 bits 0...12 : buffer size */
953#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
954/* w1 tag available flag */
955#define CP_RX_TAVA (1<<16)
956/* w1 bits 0...15 : VLAN tag */
957#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
958/* w2 low 32bit of Rx buffer ptr */
959/* w3 high 32bit of Rx buffer ptr */
960
961 int descriptor = s->currCPlusRxDesc;
c227f099 962 target_phys_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 963
964 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
965 cplus_rx_ring_desc += 16 * descriptor;
966
6cadb320
FB		 967 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
968 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
a41b2ff2
PB		 969
970 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
971
972 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
973 rxdw0 = le32_to_cpu(val);
974 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
975 rxdw1 = le32_to_cpu(val);
976 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
977 rxbufLO = le32_to_cpu(val);
978 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
979 rxbufHI = le32_to_cpu(val);
980
6cadb320 981 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 982 descriptor,
6cadb320 983 rxdw0, rxdw1, rxbufLO, rxbufHI));
a41b2ff2
PB		 984
985 if (!(rxdw0 & CP_RX_OWN))
986 {
6cadb320
FB		 987 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
988
a41b2ff2
PB		 989 s->IntrStatus |= RxOverflow;
990 ++s->RxMissed;
6cadb320
FB		 991
992 /* update tally counter */
993 ++s->tally_counters.RxERR;
994 ++s->tally_counters.MissPkt;
995
a41b2ff2 996 rtl8139_update_irq(s);
4f1c942b 997 return size_;
a41b2ff2
PB		 998 }
999
1000 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1001
6cadb320
FB		 1002 /* TODO: scatter the packet over available receive ring descriptors space */
1003
a41b2ff2
PB		 1004 if (size+4 > rx_space)
1005 {
6cadb320
FB		 1006 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1007 descriptor, rx_space, size));
1008
a41b2ff2
PB		 1009 s->IntrStatus |= RxOverflow;
1010 ++s->RxMissed;
6cadb320
FB		 1011
1012 /* update tally counter */
1013 ++s->tally_counters.RxERR;
1014 ++s->tally_counters.MissPkt;
1015
a41b2ff2 1016 rtl8139_update_irq(s);
4f1c942b 1017 return size_;
a41b2ff2
PB		 1018 }
1019
c227f099 1020 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1021
1022 /* receive/copy to target memory */
1023 cpu_physical_memory_write( rx_addr, buf, size );
1024
6cadb320
FB		 1025 if (s->CpCmd & CPlusRxChkSum)
1026 {
1027 /* do some packet checksumming */
1028 }
1029
a41b2ff2
PB		 1030 /* write checksum */
1031#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1032 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1033#else
1034 val = 0;
1035#endif
1036 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1037
1038/* first segment of received packet flag */
1039#define CP_RX_STATUS_FS (1<<29)
1040/* last segment of received packet flag */
1041#define CP_RX_STATUS_LS (1<<28)
1042/* multicast packet flag */
1043#define CP_RX_STATUS_MAR (1<<26)
1044/* physical-matching packet flag */
1045#define CP_RX_STATUS_PAM (1<<25)
1046/* broadcast packet flag */
1047#define CP_RX_STATUS_BAR (1<<24)
1048/* runt packet flag */
1049#define CP_RX_STATUS_RUNT (1<<19)
1050/* crc error flag */
1051#define CP_RX_STATUS_CRC (1<<18)
1052/* IP checksum error flag */
1053#define CP_RX_STATUS_IPF (1<<15)
1054/* UDP checksum error flag */
1055#define CP_RX_STATUS_UDPF (1<<14)
1056/* TCP checksum error flag */
1057#define CP_RX_STATUS_TCPF (1<<13)
1058
1059 /* transfer ownership to target */
1060 rxdw0 &= ~CP_RX_OWN;
1061
1062 /* set first segment bit */
1063 rxdw0 |= CP_RX_STATUS_FS;
1064
1065 /* set last segment bit */
1066 rxdw0 |= CP_RX_STATUS_LS;
1067
1068 /* set received packet type flags */
1069 if (packet_header & RxBroadcast)
1070 rxdw0 |= CP_RX_STATUS_BAR;
1071 if (packet_header & RxMulticast)
1072 rxdw0 |= CP_RX_STATUS_MAR;
1073 if (packet_header & RxPhysical)
1074 rxdw0 |= CP_RX_STATUS_PAM;
1075
1076 /* set received size */
1077 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1078 rxdw0 |= (size+4);
1079
1080 /* reset VLAN tag flag */
1081 rxdw1 &= ~CP_RX_TAVA;
1082
1083 /* update ring data */
1084 val = cpu_to_le32(rxdw0);
1085 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1086 val = cpu_to_le32(rxdw1);
1087 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1088
6cadb320
FB		 1089 /* update tally counter */
1090 ++s->tally_counters.RxOk;
1091
a41b2ff2
PB		 1092 /* seek to next Rx descriptor */
1093 if (rxdw0 & CP_RX_EOR)
1094 {
1095 s->currCPlusRxDesc = 0;
1096 }
1097 else
1098 {
1099 ++s->currCPlusRxDesc;
1100 }
1101
6cadb320 1102 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
a41b2ff2
PB		 1103
1104 }
1105 else
1106 {
6cadb320
FB		 1107 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1108
a41b2ff2
PB		 1109 /* begin ring receiver mode */
1110 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1111
1112 /* if receiver buffer is empty then avail == 0 */
1113
1114 if (avail != 0 && size + 8 >= avail)
1115 {
6cadb320
FB		 1116 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1117 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1118
a41b2ff2
PB		 1119 s->IntrStatus |= RxOverflow;
1120 ++s->RxMissed;
1121 rtl8139_update_irq(s);
4f1c942b 1122 return size_;
a41b2ff2
PB		 1123 }
1124
1125 packet_header |= RxStatusOK;
1126
1127 packet_header |= (((size+4) << 16) & 0xffff0000);
1128
1129 /* write header */
1130 uint32_t val = cpu_to_le32(packet_header);
1131
1132 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1133
1134 rtl8139_write_buffer(s, buf, size);
1135
1136 /* write checksum */
1137#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1138 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1139#else
1140 val = 0;
1141#endif
1142
1143 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1144
1145 /* correct buffer write pointer */
1146 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1147
1148 /* now we can signal we have received something */
1149
6cadb320
FB		 1150 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1151 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 1152 }
1153
1154 s->IntrStatus |= RxOK;
6cadb320
FB		 1155
1156 if (do_interrupt)
1157 {
1158 rtl8139_update_irq(s);
1159 }
4f1c942b
MM		 1160
1161 return size_;
6cadb320
FB		 1162}
1163
1673ad51 1164static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1165{
1673ad51 1166 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1167}
1168
1169static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1170{
1171 s->RxBufferSize = bufferSize;
1172 s->RxBufPtr = 0;
1173 s->RxBufAddr = 0;
1174}
1175
7f23f812 1176static void rtl8139_reset(DeviceState *d)
a41b2ff2 1177{
7f23f812 1178 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1179 int i;
1180
1181 /* restore MAC address */
254111ec 1182 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1183
1184 /* reset interrupt mask */
1185 s->IntrStatus = 0;
1186 s->IntrMask = 0;
1187
1188 rtl8139_update_irq(s);
1189
1190 /* prepare eeprom */
1191 s->eeprom.contents[0] = 0x8129;
6cadb320
FB		 1192#if 1
1193 // PCI vendor and device ID should be mirrored here
deb54399
AL		 1194 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
1195 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
6cadb320 1196#endif
290a0933 1197
254111ec
GH		 1198 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
1199 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
1200 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
a41b2ff2
PB		 1201
1202 /* mark all status registers as owned by host */
1203 for (i = 0; i < 4; ++i)
1204 {
1205 s->TxStatus[i] = TxHostOwns;
1206 }
1207
1208 s->currTxDesc = 0;
1209 s->currCPlusRxDesc = 0;
1210 s->currCPlusTxDesc = 0;
1211
1212 s->RxRingAddrLO = 0;
1213 s->RxRingAddrHI = 0;
1214
1215 s->RxBuf = 0;
1216
1217 rtl8139_reset_rxring(s, 8192);
1218
1219 /* ACK the reset */
1220 s->TxConfig = 0;
1221
1222#if 0
1223// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1224 s->clock_enabled = 0;
1225#else
6cadb320 1226 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1227 s->clock_enabled = 1;
1228#endif
1229
1230 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1231
1232 /* set initial state data */
1233 s->Config0 = 0x0; /* No boot ROM */
1234 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1235 s->Config3 = 0x1; /* fast back-to-back compatible */
1236 s->Config5 = 0x0;
1237
5fafdf24 1238 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1239
1240 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1241 s->cplus_enabled = 0;
1242
a41b2ff2
PB		 1243
1244// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1245// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1246 s->BasicModeCtrl = 0x1000; // autonegotiation
1247
1248 s->BasicModeStatus = 0x7809;
1249 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1250 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1251 s->BasicModeStatus |= 0x0004; /* link is up */
1252
1253 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1254 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1255 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1256
1257 /* also reset timer and disable timer interrupt */
1258 s->TCTR = 0;
1259 s->TimerInt = 0;
1260 s->TCTR_base = 0;
1261
1262 /* reset tally counters */
1263 RTL8139TallyCounters_clear(&s->tally_counters);
1264}
1265
b1d8e52e 1266static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1267{
1268 counters->TxOk = 0;
1269 counters->RxOk = 0;
1270 counters->TxERR = 0;
1271 counters->RxERR = 0;
1272 counters->MissPkt = 0;
1273 counters->FAE = 0;
1274 counters->Tx1Col = 0;
1275 counters->TxMCol = 0;
1276 counters->RxOkPhy = 0;
1277 counters->RxOkBrd = 0;
1278 counters->RxOkMul = 0;
1279 counters->TxAbt = 0;
1280 counters->TxUndrn = 0;
1281}
1282
c227f099 1283static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
6cadb320
FB		 1284{
1285 uint16_t val16;
1286 uint32_t val32;
1287 uint64_t val64;
1288
1289 val64 = cpu_to_le64(tally_counters->TxOk);
1290 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1291
1292 val64 = cpu_to_le64(tally_counters->RxOk);
1293 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1294
1295 val64 = cpu_to_le64(tally_counters->TxERR);
1296 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1297
1298 val32 = cpu_to_le32(tally_counters->RxERR);
1299 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1300
1301 val16 = cpu_to_le16(tally_counters->MissPkt);
1302 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1303
1304 val16 = cpu_to_le16(tally_counters->FAE);
1305 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1306
1307 val32 = cpu_to_le32(tally_counters->Tx1Col);
1308 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1309
1310 val32 = cpu_to_le32(tally_counters->TxMCol);
1311 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1312
1313 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1314 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1315
1316 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1317 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1318
1319 val32 = cpu_to_le32(tally_counters->RxOkMul);
1320 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1321
1322 val16 = cpu_to_le16(tally_counters->TxAbt);
1323 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1324
1325 val16 = cpu_to_le16(tally_counters->TxUndrn);
1326 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1327}
1328
1329/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1330
1331static const VMStateDescription vmstate_tally_counters = {
1332 .name = "tally_counters",
1333 .version_id = 1,
1334 .minimum_version_id = 1,
1335 .minimum_version_id_old = 1,
1336 .fields = (VMStateField []) {
1337 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1338 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1339 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1340 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1341 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1342 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1343 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1344 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1345 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1346 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1347 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1348 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1349 VMSTATE_END_OF_LIST()
1350 }
1351};
a41b2ff2
PB		 1352
1353static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1354{
1355 val &= 0xff;
1356
6cadb320 1357 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
a41b2ff2
PB		 1358
1359 if (val & CmdReset)
1360 {
6cadb320 1361 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
7f23f812 1362 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1363 }
1364 if (val & CmdRxEnb)
1365 {
6cadb320 1366 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
718da2b9
FB		 1367
1368 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1369 }
1370 if (val & CmdTxEnb)
1371 {
6cadb320 1372 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
718da2b9
FB		 1373
1374 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1375 }
1376
1377 /* mask unwriteable bits */
1378 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1379
1380 /* Deassert reset pin before next read */
1381 val &= ~CmdReset;
1382
1383 s->bChipCmdState = val;
1384}
1385
1386static int rtl8139_RxBufferEmpty(RTL8139State *s)
1387{
1388 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1389
1390 if (unread != 0)
1391 {
6cadb320 1392 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
a41b2ff2
PB		 1393 return 0;
1394 }
1395
6cadb320 1396 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
a41b2ff2
PB		 1397
1398 return 1;
1399}
1400
1401static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1402{
1403 uint32_t ret = s->bChipCmdState;
1404
1405 if (rtl8139_RxBufferEmpty(s))
1406 ret |= RxBufEmpty;
1407
6cadb320 1408 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
a41b2ff2
PB		 1409
1410 return ret;
1411}
1412
1413static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1414{
1415 val &= 0xffff;
1416
6cadb320 1417 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
a41b2ff2 1418
2c3891ab
AL		 1419 s->cplus_enabled = 1;
1420
a41b2ff2
PB		 1421 /* mask unwriteable bits */
1422 val = SET_MASKED(val, 0xff84, s->CpCmd);
1423
1424 s->CpCmd = val;
1425}
1426
1427static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1428{
1429 uint32_t ret = s->CpCmd;
1430
6cadb320
FB		 1431 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1432
1433 return ret;
1434}
1435
1436static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1437{
1438 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1439}
1440
1441static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1442{
1443 uint32_t ret = 0;
1444
1445 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1446
1447 return ret;
1448}
1449
9596ebb7 1450static int rtl8139_config_writeable(RTL8139State *s)
a41b2ff2
PB		 1451{
1452 if (s->Cfg9346 & Cfg9346_Unlock)
1453 {
1454 return 1;
1455 }
1456
6cadb320 1457 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
a41b2ff2
PB		 1458
1459 return 0;
1460}
1461
1462static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1463{
1464 val &= 0xffff;
1465
6cadb320 1466 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1467
1468 /* mask unwriteable bits */
e3d7e843 1469 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1470
1471 if (1 || !rtl8139_config_writeable(s))
1472 {
1473 /* Speed setting and autonegotiation enable bits are read-only */
1474 mask |= 0x3000;
1475 /* Duplex mode setting is read-only */
1476 mask |= 0x0100;
1477 }
1478
1479 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1480
1481 s->BasicModeCtrl = val;
1482}
1483
1484static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1485{
1486 uint32_t ret = s->BasicModeCtrl;
1487
6cadb320 1488 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1489
1490 return ret;
1491}
1492
1493static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1494{
1495 val &= 0xffff;
1496
6cadb320 1497 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1498
1499 /* mask unwriteable bits */
1500 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1501
1502 s->BasicModeStatus = val;
1503}
1504
1505static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1506{
1507 uint32_t ret = s->BasicModeStatus;
1508
6cadb320 1509 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1510
1511 return ret;
1512}
1513
1514static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1515{
1516 val &= 0xff;
1517
6cadb320 1518 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
a41b2ff2
PB		 1519
1520 /* mask unwriteable bits */
1521 val = SET_MASKED(val, 0x31, s->Cfg9346);
1522
1523 uint32_t opmode = val & 0xc0;
1524 uint32_t eeprom_val = val & 0xf;
1525
1526 if (opmode == 0x80) {
1527 /* eeprom access */
1528 int eecs = (eeprom_val & 0x08)?1:0;
1529 int eesk = (eeprom_val & 0x04)?1:0;
1530 int eedi = (eeprom_val & 0x02)?1:0;
1531 prom9346_set_wire(s, eecs, eesk, eedi);
1532 } else if (opmode == 0x40) {
1533 /* Reset. */
1534 val = 0;
7f23f812 1535 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1536 }
1537
1538 s->Cfg9346 = val;
1539}
1540
1541static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1542{
1543 uint32_t ret = s->Cfg9346;
1544
1545 uint32_t opmode = ret & 0xc0;
1546
1547 if (opmode == 0x80)
1548 {
1549 /* eeprom access */
1550 int eedo = prom9346_get_wire(s);
1551 if (eedo)
1552 {
1553 ret |= 0x01;
1554 }
1555 else
1556 {
1557 ret &= ~0x01;
1558 }
1559 }
1560
6cadb320 1561 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
a41b2ff2
PB		 1562
1563 return ret;
1564}
1565
1566static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1567{
1568 val &= 0xff;
1569
6cadb320 1570 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
a41b2ff2
PB		 1571
1572 if (!rtl8139_config_writeable(s))
1573 return;
1574
1575 /* mask unwriteable bits */
1576 val = SET_MASKED(val, 0xf8, s->Config0);
1577
1578 s->Config0 = val;
1579}
1580
1581static uint32_t rtl8139_Config0_read(RTL8139State *s)
1582{
1583 uint32_t ret = s->Config0;
1584
6cadb320 1585 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
a41b2ff2
PB		 1586
1587 return ret;
1588}
1589
1590static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1591{
1592 val &= 0xff;
1593
6cadb320 1594 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
a41b2ff2
PB		 1595
1596 if (!rtl8139_config_writeable(s))
1597 return;
1598
1599 /* mask unwriteable bits */
1600 val = SET_MASKED(val, 0xC, s->Config1);
1601
1602 s->Config1 = val;
1603}
1604
1605static uint32_t rtl8139_Config1_read(RTL8139State *s)
1606{
1607 uint32_t ret = s->Config1;
1608
6cadb320 1609 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
a41b2ff2
PB		 1610
1611 return ret;
1612}
1613
1614static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1615{
1616 val &= 0xff;
1617
6cadb320 1618 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
a41b2ff2
PB		 1619
1620 if (!rtl8139_config_writeable(s))
1621 return;
1622
1623 /* mask unwriteable bits */
1624 val = SET_MASKED(val, 0x8F, s->Config3);
1625
1626 s->Config3 = val;
1627}
1628
1629static uint32_t rtl8139_Config3_read(RTL8139State *s)
1630{
1631 uint32_t ret = s->Config3;
1632
6cadb320 1633 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
a41b2ff2
PB		 1634
1635 return ret;
1636}
1637
1638static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1639{
1640 val &= 0xff;
1641
6cadb320 1642 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
a41b2ff2
PB		 1643
1644 if (!rtl8139_config_writeable(s))
1645 return;
1646
1647 /* mask unwriteable bits */
1648 val = SET_MASKED(val, 0x0a, s->Config4);
1649
1650 s->Config4 = val;
1651}
1652
1653static uint32_t rtl8139_Config4_read(RTL8139State *s)
1654{
1655 uint32_t ret = s->Config4;
1656
6cadb320 1657 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
a41b2ff2
PB		 1658
1659 return ret;
1660}
1661
1662static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1663{
1664 val &= 0xff;
1665
6cadb320 1666 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
a41b2ff2
PB		 1667
1668 /* mask unwriteable bits */
1669 val = SET_MASKED(val, 0x80, s->Config5);
1670
1671 s->Config5 = val;
1672}
1673
1674static uint32_t rtl8139_Config5_read(RTL8139State *s)
1675{
1676 uint32_t ret = s->Config5;
1677
6cadb320 1678 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
a41b2ff2
PB		 1679
1680 return ret;
1681}
1682
1683static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1684{
1685 if (!rtl8139_transmitter_enabled(s))
1686 {
6cadb320 1687 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1688 return;
1689 }
1690
6cadb320 1691 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1692
1693 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1694
1695 s->TxConfig = val;
1696}
1697
1698static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1699{
6cadb320
FB		 1700 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1701
1702 uint32_t tc = s->TxConfig;
1703 tc &= 0xFFFFFF00;
1704 tc |= (val & 0x000000FF);
1705 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1706}
1707
1708static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1709{
1710 uint32_t ret = s->TxConfig;
1711
6cadb320 1712 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
a41b2ff2
PB		 1713
1714 return ret;
1715}
1716
1717static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1718{
6cadb320 1719 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1720
1721 /* mask unwriteable bits */
1722 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1723
1724 s->RxConfig = val;
1725
1726 /* reset buffer size and read/write pointers */
1727 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1728
6cadb320 1729 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
a41b2ff2
PB		 1730}
1731
1732static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1733{
1734 uint32_t ret = s->RxConfig;
1735
6cadb320 1736 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
a41b2ff2
PB		 1737
1738 return ret;
1739}
1740
718da2b9
FB		 1741static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1742{
1743 if (!size)
1744 {
1745 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1746 return;
1747 }
1748
1749 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1750 {
1751 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1673ad51 1752 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
718da2b9
FB		 1753 }
1754 else
1755 {
1673ad51 1756 qemu_send_packet(&s->nic->nc, buf, size);
718da2b9
FB		 1757 }
1758}
1759
a41b2ff2
PB		 1760static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1761{
1762 if (!rtl8139_transmitter_enabled(s))
1763 {
6cadb320
FB		 1764 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1765 descriptor));
a41b2ff2
PB		 1766 return 0;
1767 }
1768
1769 if (s->TxStatus[descriptor] & TxHostOwns)
1770 {
6cadb320
FB		 1771 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1772 descriptor, s->TxStatus[descriptor]));
a41b2ff2
PB		 1773 return 0;
1774 }
1775
6cadb320 1776 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
a41b2ff2
PB		 1777
1778 int txsize = s->TxStatus[descriptor] & 0x1fff;
1779 uint8_t txbuffer[0x2000];
1780
6cadb320
FB		 1781 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1782 txsize, s->TxAddr[descriptor]));
a41b2ff2 1783
6cadb320 1784 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1785
1786 /* Mark descriptor as transferred */
1787 s->TxStatus[descriptor] |= TxHostOwns;
1788 s->TxStatus[descriptor] |= TxStatOK;
1789
718da2b9 1790 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
6cadb320
FB		 1791
1792 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
a41b2ff2
PB		 1793
1794 /* update interrupt */
1795 s->IntrStatus |= TxOK;
1796 rtl8139_update_irq(s);
1797
1798 return 1;
1799}
1800
718da2b9
FB		 1801/* structures and macros for task offloading */
1802typedef struct ip_header
1803{
1804 uint8_t ip_ver_len; /* version and header length */
1805 uint8_t ip_tos; /* type of service */
1806 uint16_t ip_len; /* total length */
1807 uint16_t ip_id; /* identification */
1808 uint16_t ip_off; /* fragment offset field */
1809 uint8_t ip_ttl; /* time to live */
1810 uint8_t ip_p; /* protocol */
1811 uint16_t ip_sum; /* checksum */
1812 uint32_t ip_src,ip_dst; /* source and dest address */
1813} ip_header;
1814
1815#define IP_HEADER_VERSION_4 4
1816#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1817#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1818
1819typedef struct tcp_header
1820{
1821 uint16_t th_sport; /* source port */
1822 uint16_t th_dport; /* destination port */
1823 uint32_t th_seq; /* sequence number */
1824 uint32_t th_ack; /* acknowledgement number */
1825 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1826 uint16_t th_win; /* window */
1827 uint16_t th_sum; /* checksum */
1828 uint16_t th_urp; /* urgent pointer */
1829} tcp_header;
1830
1831typedef struct udp_header
1832{
1833 uint16_t uh_sport; /* source port */
1834 uint16_t uh_dport; /* destination port */
1835 uint16_t uh_ulen; /* udp length */
1836 uint16_t uh_sum; /* udp checksum */
1837} udp_header;
1838
1839typedef struct ip_pseudo_header
1840{
1841 uint32_t ip_src;
1842 uint32_t ip_dst;
1843 uint8_t zeros;
1844 uint8_t ip_proto;
1845 uint16_t ip_payload;
1846} ip_pseudo_header;
1847
1848#define IP_PROTO_TCP 6
1849#define IP_PROTO_UDP 17
1850
1851#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1852#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1853#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1854
1855#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1856
1857#define TCP_FLAG_FIN 0x01
1858#define TCP_FLAG_PUSH 0x08
1859
1860/* produces ones' complement sum of data */
1861static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1862{
1863 uint32_t result = 0;
1864
1865 for (; len > 1; data+=2, len-=2)
1866 {
1867 result += *(uint16_t*)data;
1868 }
1869
1870 /* add the remainder byte */
1871 if (len)
1872 {
1873 uint8_t odd[2] = {*data, 0};
1874 result += *(uint16_t*)odd;
1875 }
1876
1877 while (result>>16)
1878 result = (result & 0xffff) + (result >> 16);
1879
1880 return result;
1881}
1882
1883static uint16_t ip_checksum(void *data, size_t len)
1884{
1885 return ~ones_complement_sum((uint8_t*)data, len);
1886}
1887
a41b2ff2
PB		 1888static int rtl8139_cplus_transmit_one(RTL8139State *s)
1889{
1890 if (!rtl8139_transmitter_enabled(s))
1891 {
6cadb320 1892 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
a41b2ff2
PB		 1893 return 0;
1894 }
1895
1896 if (!rtl8139_cp_transmitter_enabled(s))
1897 {
6cadb320 1898 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
a41b2ff2
PB		 1899 return 0 ;
1900 }
1901
1902 int descriptor = s->currCPlusTxDesc;
1903
c227f099 1904 target_phys_addr_t cplus_tx_ring_desc =
a41b2ff2
PB		 1905 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1906
1907 /* Normal priority ring */
1908 cplus_tx_ring_desc += 16 * descriptor;
1909
6cadb320
FB		 1910 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1911 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
a41b2ff2
PB		 1912
1913 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1914
1915 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1916 txdw0 = le32_to_cpu(val);
4ef1a3d3 1917 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
a41b2ff2
PB		 1918 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1919 txdw1 = le32_to_cpu(val);
1920 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1921 txbufLO = le32_to_cpu(val);
1922 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1923 txbufHI = le32_to_cpu(val);
1924
6cadb320 1925 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 1926 descriptor,
6cadb320 1927 txdw0, txdw1, txbufLO, txbufHI));
a41b2ff2 1928
4ef1a3d3
IK		 1929 /* TODO: the following discard cast should clean clang analyzer output */
1930 (void)txdw1;
1931
a41b2ff2
PB		 1932/* w0 ownership flag */
1933#define CP_TX_OWN (1<<31)
1934/* w0 end of ring flag */
1935#define CP_TX_EOR (1<<30)
1936/* first segment of received packet flag */
1937#define CP_TX_FS (1<<29)
1938/* last segment of received packet flag */
1939#define CP_TX_LS (1<<28)
1940/* large send packet flag */
1941#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1942/* large send MSS mask, bits 16...25 */
1943#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1944
a41b2ff2
PB		 1945/* IP checksum offload flag */
1946#define CP_TX_IPCS (1<<18)
1947/* UDP checksum offload flag */
1948#define CP_TX_UDPCS (1<<17)
1949/* TCP checksum offload flag */
1950#define CP_TX_TCPCS (1<<16)
1951
1952/* w0 bits 0...15 : buffer size */
1953#define CP_TX_BUFFER_SIZE (1<<16)
1954#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1955/* w1 tag available flag */
1956#define CP_RX_TAGC (1<<17)
1957/* w1 bits 0...15 : VLAN tag */
1958#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1959/* w2 low 32bit of Rx buffer ptr */
1960/* w3 high 32bit of Rx buffer ptr */
1961
1962/* set after transmission */
1963/* FIFO underrun flag */
1964#define CP_TX_STATUS_UNF (1<<25)
1965/* transmit error summary flag, valid if set any of three below */
1966#define CP_TX_STATUS_TES (1<<23)
1967/* out-of-window collision flag */
1968#define CP_TX_STATUS_OWC (1<<22)
1969/* link failure flag */
1970#define CP_TX_STATUS_LNKF (1<<21)
1971/* excessive collisions flag */
1972#define CP_TX_STATUS_EXC (1<<20)
1973
1974 if (!(txdw0 & CP_TX_OWN))
1975 {
6cadb320 1976 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
a41b2ff2
PB		 1977 return 0 ;
1978 }
1979
6cadb320
FB		 1980 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1981
1982 if (txdw0 & CP_TX_FS)
1983 {
1984 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1985
1986 /* reset internal buffer offset */
1987 s->cplus_txbuffer_offset = 0;
1988 }
a41b2ff2
PB		 1989
1990 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
c227f099 1991 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 1992
6cadb320
FB		 1993 /* make sure we have enough space to assemble the packet */
1994 if (!s->cplus_txbuffer)
1995 {
1996 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2bc6f59b 1997 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
6cadb320 1998 s->cplus_txbuffer_offset = 0;
718da2b9
FB		 1999
2000 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
6cadb320
FB		 2001 }
2002
2003 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2004 {
2005 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2137b4cc 2006 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2007
6cadb320
FB		 2008 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2009 }
2010
2011 if (!s->cplus_txbuffer)
2012 {
2013 /* out of memory */
a41b2ff2 2014
6cadb320
FB		 2015 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2016
2017 /* update tally counter */
2018 ++s->tally_counters.TxERR;
2019 ++s->tally_counters.TxAbt;
2020
2021 return 0;
2022 }
2023
2024 /* append more data to the packet */
2025
2026 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2027 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2028
2029 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2030 s->cplus_txbuffer_offset += txsize;
2031
2032 /* seek to next Rx descriptor */
2033 if (txdw0 & CP_TX_EOR)
2034 {
2035 s->currCPlusTxDesc = 0;
2036 }
2037 else
2038 {
2039 ++s->currCPlusTxDesc;
2040 if (s->currCPlusTxDesc >= 64)
2041 s->currCPlusTxDesc = 0;
2042 }
a41b2ff2
PB		 2043
2044 /* transfer ownership to target */
2045 txdw0 &= ~CP_RX_OWN;
2046
2047 /* reset error indicator bits */
2048 txdw0 &= ~CP_TX_STATUS_UNF;
2049 txdw0 &= ~CP_TX_STATUS_TES;
2050 txdw0 &= ~CP_TX_STATUS_OWC;
2051 txdw0 &= ~CP_TX_STATUS_LNKF;
2052 txdw0 &= ~CP_TX_STATUS_EXC;
2053
2054 /* update ring data */
2055 val = cpu_to_le32(txdw0);
2056 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
4ef1a3d3 2057 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
a41b2ff2
PB		 2058// val = cpu_to_le32(txdw1);
2059// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2060
6cadb320
FB		 2061 /* Now decide if descriptor being processed is holding the last segment of packet */
2062 if (txdw0 & CP_TX_LS)
a41b2ff2 2063 {
6cadb320
FB		 2064 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2065
2066 /* can transfer fully assembled packet */
2067
2068 uint8_t *saved_buffer = s->cplus_txbuffer;
2069 int saved_size = s->cplus_txbuffer_offset;
2070 int saved_buffer_len = s->cplus_txbuffer_len;
2071
2072 /* reset the card space to protect from recursive call */
2073 s->cplus_txbuffer = NULL;
2074 s->cplus_txbuffer_offset = 0;
2075 s->cplus_txbuffer_len = 0;
2076
718da2b9 2077 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320
FB		 2078 {
2079 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2080
2081 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2082 #define ETH_HLEN 14
718da2b9 2083 #define ETH_MTU 1500
6cadb320
FB		 2084
2085 /* ip packet header */
660f11be 2086 ip_header *ip = NULL;
6cadb320 2087 int hlen = 0;
718da2b9
FB		 2088 uint8_t ip_protocol = 0;
2089 uint16_t ip_data_len = 0;
6cadb320 2090
660f11be 2091 uint8_t *eth_payload_data = NULL;
718da2b9 2092 size_t eth_payload_len = 0;
6cadb320 2093
718da2b9 2094 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2095 if (proto == ETH_P_IP)
2096 {
2097 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2098
2099 /* not aligned */
718da2b9
FB		 2100 eth_payload_data = saved_buffer + ETH_HLEN;
2101 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2102
718da2b9 2103 ip = (ip_header*)eth_payload_data;
6cadb320 2104
718da2b9
FB		 2105 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2106 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
6cadb320
FB		 2107 ip = NULL;
2108 } else {
718da2b9
FB		 2109 hlen = IP_HEADER_LENGTH(ip);
2110 ip_protocol = ip->ip_p;
2111 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2112 }
2113 }
2114
2115 if (ip)
2116 {
2117 if (txdw0 & CP_TX_IPCS)
2118 {
2119 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2120
718da2b9 2121 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2122 /* bad packet header len */
2123 /* or packet too short */
2124 }
2125 else
2126 {
2127 ip->ip_sum = 0;
718da2b9 2128 ip->ip_sum = ip_checksum(ip, hlen);
6cadb320
FB		 2129 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2130 }
2131 }
2132
718da2b9 2133 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2134 {
718da2b9
FB		 2135#if defined (DEBUG_RTL8139)
2136 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2137#endif
2138 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2139 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
6cadb320 2140
718da2b9
FB		 2141 int tcp_send_offset = 0;
2142 int send_count = 0;
6cadb320
FB		 2143
2144 /* maximum IP header length is 60 bytes */
2145 uint8_t saved_ip_header[60];
6cadb320 2146
718da2b9
FB		 2147 /* save IP header template; data area is used in tcp checksum calculation */
2148 memcpy(saved_ip_header, eth_payload_data, hlen);
2149
2150 /* a placeholder for checksum calculation routine in tcp case */
2151 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2152 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2153
2154 /* pointer to TCP header */
2155 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2156
2157 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2158
2159 /* ETH_MTU = ip header len + tcp header len + payload */
2160 int tcp_data_len = ip_data_len - tcp_hlen;
2161 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2162
2163 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2164 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2165
2166 /* note the cycle below overwrites IP header data,
2167 but restores it from saved_ip_header before sending packet */
2168
2169 int is_last_frame = 0;
2170
2171 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2172 {
2173 uint16_t chunk_size = tcp_chunk_size;
2174
2175 /* check if this is the last frame */
2176 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2177 {
2178 is_last_frame = 1;
2179 chunk_size = tcp_data_len - tcp_send_offset;
2180 }
2181
2182 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2183
2184 /* add 4 TCP pseudoheader fields */
2185 /* copy IP source and destination fields */
2186 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2187
2188 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2189
2190 if (tcp_send_offset)
2191 {
2192 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2193 }
2194
2195 /* keep PUSH and FIN flags only for the last frame */
2196 if (!is_last_frame)
2197 {
2198 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2199 }
6cadb320 2200
718da2b9
FB		 2201 /* recalculate TCP checksum */
2202 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2203 p_tcpip_hdr->zeros = 0;
2204 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2205 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2206
2207 p_tcp_hdr->th_sum = 0;
2208
2209 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2210 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2211
2212 p_tcp_hdr->th_sum = tcp_checksum;
2213
2214 /* restore IP header */
2215 memcpy(eth_payload_data, saved_ip_header, hlen);
2216
2217 /* set IP data length and recalculate IP checksum */
2218 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2219
2220 /* increment IP id for subsequent frames */
2221 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2222
2223 ip->ip_sum = 0;
2224 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2225 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2226
2227 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2228 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2229 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2230
2231 /* add transferred count to TCP sequence number */
2232 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2233 ++send_count;
2234 }
2235
2236 /* Stop sending this frame */
2237 saved_size = 0;
2238 }
2239 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2240 {
2241 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2242
2243 /* maximum IP header length is 60 bytes */
2244 uint8_t saved_ip_header[60];
2245 memcpy(saved_ip_header, eth_payload_data, hlen);
2246
2247 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2248 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2249
2250 /* add 4 TCP pseudoheader fields */
2251 /* copy IP source and destination fields */
718da2b9 2252 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2253
718da2b9 2254 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320
FB		 2255 {
2256 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2257
718da2b9
FB		 2258 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2259 p_tcpip_hdr->zeros = 0;
2260 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2261 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2262
718da2b9 2263 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2264
2265 p_tcp_hdr->th_sum = 0;
2266
718da2b9 2267 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2268 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2269
2270 p_tcp_hdr->th_sum = tcp_checksum;
2271 }
718da2b9 2272 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320
FB		 2273 {
2274 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2275
718da2b9
FB		 2276 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2277 p_udpip_hdr->zeros = 0;
2278 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2279 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2280
718da2b9 2281 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2282
6cadb320
FB		 2283 p_udp_hdr->uh_sum = 0;
2284
718da2b9 2285 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2286 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2287
6cadb320
FB		 2288 p_udp_hdr->uh_sum = udp_checksum;
2289 }
2290
2291 /* restore IP header */
718da2b9 2292 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2293 }
2294 }
2295 }
2296
2297 /* update tally counter */
2298 ++s->tally_counters.TxOk;
2299
2300 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2301
718da2b9 2302 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
6cadb320
FB		 2303
2304 /* restore card space if there was no recursion and reset offset */
2305 if (!s->cplus_txbuffer)
2306 {
2307 s->cplus_txbuffer = saved_buffer;
2308 s->cplus_txbuffer_len = saved_buffer_len;
2309 s->cplus_txbuffer_offset = 0;
2310 }
2311 else
2312 {
2bc6f59b 2313 qemu_free(saved_buffer);
6cadb320 2314 }
a41b2ff2
PB		 2315 }
2316 else
2317 {
6cadb320 2318 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
a41b2ff2
PB		 2319 }
2320
a41b2ff2
PB		 2321 return 1;
2322}
2323
2324static void rtl8139_cplus_transmit(RTL8139State *s)
2325{
2326 int txcount = 0;
2327
2328 while (rtl8139_cplus_transmit_one(s))
2329 {
2330 ++txcount;
2331 }
2332
2333 /* Mark transfer completed */
2334 if (!txcount)
2335 {
6cadb320
FB		 2336 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2337 s->currCPlusTxDesc));
a41b2ff2
PB		 2338 }
2339 else
2340 {
2341 /* update interrupt status */
2342 s->IntrStatus |= TxOK;
2343 rtl8139_update_irq(s);
2344 }
2345}
2346
2347static void rtl8139_transmit(RTL8139State *s)
2348{
2349 int descriptor = s->currTxDesc, txcount = 0;
2350
2351 /*while*/
2352 if (rtl8139_transmit_one(s, descriptor))
2353 {
2354 ++s->currTxDesc;
2355 s->currTxDesc %= 4;
2356 ++txcount;
2357 }
2358
2359 /* Mark transfer completed */
2360 if (!txcount)
2361 {
6cadb320 2362 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
a41b2ff2
PB		 2363 }
2364}
2365
2366static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2367{
2368
2369 int descriptor = txRegOffset/4;
6cadb320
FB		 2370
2371 /* handle C+ transmit mode register configuration */
2372
2c3891ab 2373 if (s->cplus_enabled)
6cadb320
FB		 2374 {
2375 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2376
2377 /* handle Dump Tally Counters command */
2378 s->TxStatus[descriptor] = val;
2379
2380 if (descriptor == 0 && (val & 0x8))
2381 {
c227f099 2382 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2383
2384 /* dump tally counters to specified memory location */
2385 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2386
2387 /* mark dump completed */
2388 s->TxStatus[0] &= ~0x8;
2389 }
2390
2391 return;
2392 }
2393
2394 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
a41b2ff2
PB		 2395
2396 /* mask only reserved bits */
2397 val &= ~0xff00c000; /* these bits are reset on write */
2398 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2399
2400 s->TxStatus[descriptor] = val;
2401
2402 /* attempt to start transmission */
2403 rtl8139_transmit(s);
2404}
2405
2406static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2407{
2408 uint32_t ret = s->TxStatus[txRegOffset/4];
2409
6cadb320 2410 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
a41b2ff2
PB		 2411
2412 return ret;
2413}
2414
2415static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2416{
2417 uint16_t ret = 0;
2418
2419 /* Simulate TSAD, it is read only anyway */
2420
2421 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2422 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2423 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2424 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2425
2426 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2427 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2428 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2429 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2430
a41b2ff2
PB		 2431 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2432 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2433 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2434 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2435
a41b2ff2
PB		 2436 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2437 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2438 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2439 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2440
a41b2ff2 2441
6cadb320 2442 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
a41b2ff2
PB		 2443
2444 return ret;
2445}
2446
2447static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2448{
2449 uint16_t ret = s->CSCR;
2450
6cadb320 2451 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
a41b2ff2
PB		 2452
2453 return ret;
2454}
2455
2456static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2457{
6cadb320 2458 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
a41b2ff2 2459
290a0933 2460 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2461}
2462
2463static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2464{
290a0933 2465 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2466
6cadb320 2467 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
a41b2ff2
PB		 2468
2469 return ret;
2470}
2471
2472static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2473{
6cadb320 2474 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
a41b2ff2
PB		 2475
2476 /* this value is off by 16 */
2477 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2478
6cadb320
FB		 2479 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2480 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 2481}
2482
2483static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2484{
2485 /* this value is off by 16 */
2486 uint32_t ret = s->RxBufPtr - 0x10;
2487
6cadb320
FB		 2488 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2489
2490 return ret;
2491}
2492
2493static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2494{
2495 /* this value is NOT off by 16 */
2496 uint32_t ret = s->RxBufAddr;
2497
2498 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
a41b2ff2
PB		 2499
2500 return ret;
2501}
2502
2503static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2504{
6cadb320 2505 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
a41b2ff2
PB		 2506
2507 s->RxBuf = val;
2508
2509 /* may need to reset rxring here */
2510}
2511
2512static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2513{
2514 uint32_t ret = s->RxBuf;
2515
6cadb320 2516 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
a41b2ff2
PB		 2517
2518 return ret;
2519}
2520
2521static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2522{
6cadb320 2523 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2524
2525 /* mask unwriteable bits */
2526 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2527
2528 s->IntrMask = val;
2529
05447803 2530 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
a41b2ff2 2531 rtl8139_update_irq(s);
05447803 2532
a41b2ff2
PB		 2533}
2534
2535static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2536{
2537 uint32_t ret = s->IntrMask;
2538
6cadb320 2539 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2540
2541 return ret;
2542}
2543
2544static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2545{
6cadb320 2546 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2547
2548#if 0
2549
2550 /* writing to ISR has no effect */
2551
2552 return;
2553
2554#else
2555 uint16_t newStatus = s->IntrStatus & ~val;
2556
2557 /* mask unwriteable bits */
2558 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2559
2560 /* writing 1 to interrupt status register bit clears it */
2561 s->IntrStatus = 0;
2562 rtl8139_update_irq(s);
2563
2564 s->IntrStatus = newStatus;
05447803
FZ		 2565 /*
2566 * Computing if we miss an interrupt here is not that correct but
2567 * considered that we should have had already an interrupt
2568 * and probably emulated is slower is better to assume this resetting was
2569 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2570 */
2571 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
a41b2ff2 2572 rtl8139_update_irq(s);
05447803 2573
a41b2ff2
PB		 2574#endif
2575}
2576
2577static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2578{
05447803
FZ		 2579 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2580
a41b2ff2
PB		 2581 uint32_t ret = s->IntrStatus;
2582
6cadb320 2583 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2584
2585#if 0
2586
2587 /* reading ISR clears all interrupts */
2588 s->IntrStatus = 0;
2589
2590 rtl8139_update_irq(s);
2591
2592#endif
2593
2594 return ret;
2595}
2596
2597static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2598{
6cadb320 2599 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2600
2601 /* mask unwriteable bits */
2602 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2603
2604 s->MultiIntr = val;
2605}
2606
2607static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2608{
2609 uint32_t ret = s->MultiIntr;
2610
6cadb320 2611 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2612
2613 return ret;
2614}
2615
2616static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2617{
2618 RTL8139State *s = opaque;
2619
2620 addr &= 0xff;
2621
2622 switch (addr)
2623 {
2624 case MAC0 ... MAC0+5:
2625 s->phys[addr - MAC0] = val;
2626 break;
2627 case MAC0+6 ... MAC0+7:
2628 /* reserved */
2629 break;
2630 case MAR0 ... MAR0+7:
2631 s->mult[addr - MAR0] = val;
2632 break;
2633 case ChipCmd:
2634 rtl8139_ChipCmd_write(s, val);
2635 break;
2636 case Cfg9346:
2637 rtl8139_Cfg9346_write(s, val);
2638 break;
2639 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2640 rtl8139_TxConfig_writeb(s, val);
2641 break;
2642 case Config0:
2643 rtl8139_Config0_write(s, val);
2644 break;
2645 case Config1:
2646 rtl8139_Config1_write(s, val);
2647 break;
2648 case Config3:
2649 rtl8139_Config3_write(s, val);
2650 break;
2651 case Config4:
2652 rtl8139_Config4_write(s, val);
2653 break;
2654 case Config5:
2655 rtl8139_Config5_write(s, val);
2656 break;
2657 case MediaStatus:
2658 /* ignore */
6cadb320 2659 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
a41b2ff2
PB		 2660 break;
2661
2662 case HltClk:
6cadb320 2663 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
a41b2ff2
PB		 2664 if (val == 'R')
2665 {
2666 s->clock_enabled = 1;
2667 }
2668 else if (val == 'H')
2669 {
2670 s->clock_enabled = 0;
2671 }
2672 break;
2673
2674 case TxThresh:
6cadb320 2675 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2676 s->TxThresh = val;
2677 break;
2678
2679 case TxPoll:
6cadb320 2680 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2681 if (val & (1 << 7))
2682 {
6cadb320 2683 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
a41b2ff2
PB		 2684 //rtl8139_cplus_transmit(s);
2685 }
2686 if (val & (1 << 6))
2687 {
6cadb320 2688 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
a41b2ff2
PB		 2689 rtl8139_cplus_transmit(s);
2690 }
2691
2692 break;
2693
2694 default:
6cadb320 2695 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
a41b2ff2
PB		 2696 break;
2697 }
2698}
2699
2700static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2701{
2702 RTL8139State *s = opaque;
2703
2704 addr &= 0xfe;
2705
2706 switch (addr)
2707 {
2708 case IntrMask:
2709 rtl8139_IntrMask_write(s, val);
2710 break;
2711
2712 case IntrStatus:
2713 rtl8139_IntrStatus_write(s, val);
2714 break;
2715
2716 case MultiIntr:
2717 rtl8139_MultiIntr_write(s, val);
2718 break;
2719
2720 case RxBufPtr:
2721 rtl8139_RxBufPtr_write(s, val);
2722 break;
2723
2724 case BasicModeCtrl:
2725 rtl8139_BasicModeCtrl_write(s, val);
2726 break;
2727 case BasicModeStatus:
2728 rtl8139_BasicModeStatus_write(s, val);
2729 break;
2730 case NWayAdvert:
6cadb320 2731 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2732 s->NWayAdvert = val;
2733 break;
2734 case NWayLPAR:
6cadb320 2735 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2736 break;
2737 case NWayExpansion:
6cadb320 2738 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2739 s->NWayExpansion = val;
2740 break;
2741
2742 case CpCmd:
2743 rtl8139_CpCmd_write(s, val);
2744 break;
2745
6cadb320
FB		 2746 case IntrMitigate:
2747 rtl8139_IntrMitigate_write(s, val);
2748 break;
2749
a41b2ff2 2750 default:
6cadb320 2751 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
a41b2ff2 2752
a41b2ff2
PB		 2753 rtl8139_io_writeb(opaque, addr, val & 0xff);
2754 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2755 break;
2756 }
2757}
2758
05447803
FZ		 2759static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2760{
2761 int64_t pci_time, next_time;
2762 uint32_t low_pci;
2763
2764 DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
2765
2766 if (s->TimerExpire && current_time >= s->TimerExpire) {
2767 s->IntrStatus |= PCSTimeout;
2768 rtl8139_update_irq(s);
2769 }
2770
2771 /* Set QEMU timer only if needed that is
2772 * - TimerInt <> 0 (we have a timer)
2773 * - mask = 1 (we want an interrupt timer)
2774 * - irq = 0 (irq is not already active)
2775 * If any of above change we need to compute timer again
2776 * Also we must check if timer is passed without QEMU timer
2777 */
2778 s->TimerExpire = 0;
2779 if (!s->TimerInt) {
2780 return;
2781 }
2782
2783 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2784 get_ticks_per_sec());
2785 low_pci = pci_time & 0xffffffff;
2786 pci_time = pci_time - low_pci + s->TimerInt;
2787 if (low_pci >= s->TimerInt) {
2788 pci_time += 0x100000000LL;
2789 }
2790 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2791 PCI_FREQUENCY);
2792 s->TimerExpire = next_time;
2793
2794 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2795 qemu_mod_timer(s->timer, next_time);
2796 }
2797}
2798
a41b2ff2
PB		 2799static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2800{
2801 RTL8139State *s = opaque;
2802
2803 addr &= 0xfc;
2804
2805 switch (addr)
2806 {
2807 case RxMissed:
6cadb320 2808 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
a41b2ff2
PB		 2809 s->RxMissed = 0;
2810 break;
2811
2812 case TxConfig:
2813 rtl8139_TxConfig_write(s, val);
2814 break;
2815
2816 case RxConfig:
2817 rtl8139_RxConfig_write(s, val);
2818 break;
2819
2820 case TxStatus0 ... TxStatus0+4*4-1:
2821 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2822 break;
2823
2824 case TxAddr0 ... TxAddr0+4*4-1:
2825 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2826 break;
2827
2828 case RxBuf:
2829 rtl8139_RxBuf_write(s, val);
2830 break;
2831
2832 case RxRingAddrLO:
6cadb320 2833 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
a41b2ff2
PB		 2834 s->RxRingAddrLO = val;
2835 break;
2836
2837 case RxRingAddrHI:
6cadb320 2838 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
a41b2ff2
PB		 2839 s->RxRingAddrHI = val;
2840 break;
2841
6cadb320
FB		 2842 case Timer:
2843 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
6cadb320 2844 s->TCTR_base = qemu_get_clock(vm_clock);
05447803 2845 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2846 break;
2847
2848 case FlashReg:
2849 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
05447803
FZ		 2850 if (s->TimerInt != val) {
2851 s->TimerInt = val;
2852 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
2853 }
6cadb320
FB		 2854 break;
2855
a41b2ff2 2856 default:
6cadb320 2857 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
a41b2ff2
PB		 2858 rtl8139_io_writeb(opaque, addr, val & 0xff);
2859 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2860 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2861 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2862 break;
2863 }
2864}
2865
2866static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2867{
2868 RTL8139State *s = opaque;
2869 int ret;
2870
2871 addr &= 0xff;
2872
2873 switch (addr)
2874 {
2875 case MAC0 ... MAC0+5:
2876 ret = s->phys[addr - MAC0];
2877 break;
2878 case MAC0+6 ... MAC0+7:
2879 ret = 0;
2880 break;
2881 case MAR0 ... MAR0+7:
2882 ret = s->mult[addr - MAR0];
2883 break;
2884 case ChipCmd:
2885 ret = rtl8139_ChipCmd_read(s);
2886 break;
2887 case Cfg9346:
2888 ret = rtl8139_Cfg9346_read(s);
2889 break;
2890 case Config0:
2891 ret = rtl8139_Config0_read(s);
2892 break;
2893 case Config1:
2894 ret = rtl8139_Config1_read(s);
2895 break;
2896 case Config3:
2897 ret = rtl8139_Config3_read(s);
2898 break;
2899 case Config4:
2900 ret = rtl8139_Config4_read(s);
2901 break;
2902 case Config5:
2903 ret = rtl8139_Config5_read(s);
2904 break;
2905
2906 case MediaStatus:
2907 ret = 0xd0;
6cadb320 2908 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
a41b2ff2
PB		 2909 break;
2910
2911 case HltClk:
2912 ret = s->clock_enabled;
6cadb320 2913 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
a41b2ff2
PB		 2914 break;
2915
2916 case PCIRevisionID:
6cadb320
FB		 2917 ret = RTL8139_PCI_REVID;
2918 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
a41b2ff2
PB		 2919 break;
2920
2921 case TxThresh:
2922 ret = s->TxThresh;
6cadb320 2923 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2924 break;
2925
2926 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2927 ret = s->TxConfig >> 24;
6cadb320 2928 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2929 break;
2930
2931 default:
6cadb320 2932 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
a41b2ff2
PB		 2933 ret = 0;
2934 break;
2935 }
2936
2937 return ret;
2938}
2939
2940static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2941{
2942 RTL8139State *s = opaque;
2943 uint32_t ret;
2944
2945 addr &= 0xfe; /* mask lower bit */
2946
2947 switch (addr)
2948 {
2949 case IntrMask:
2950 ret = rtl8139_IntrMask_read(s);
2951 break;
2952
2953 case IntrStatus:
2954 ret = rtl8139_IntrStatus_read(s);
2955 break;
2956
2957 case MultiIntr:
2958 ret = rtl8139_MultiIntr_read(s);
2959 break;
2960
2961 case RxBufPtr:
2962 ret = rtl8139_RxBufPtr_read(s);
2963 break;
2964
6cadb320
FB		 2965 case RxBufAddr:
2966 ret = rtl8139_RxBufAddr_read(s);
2967 break;
2968
a41b2ff2
PB		 2969 case BasicModeCtrl:
2970 ret = rtl8139_BasicModeCtrl_read(s);
2971 break;
2972 case BasicModeStatus:
2973 ret = rtl8139_BasicModeStatus_read(s);
2974 break;
2975 case NWayAdvert:
2976 ret = s->NWayAdvert;
6cadb320 2977 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2978 break;
2979 case NWayLPAR:
2980 ret = s->NWayLPAR;
6cadb320 2981 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2982 break;
2983 case NWayExpansion:
2984 ret = s->NWayExpansion;
6cadb320 2985 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2986 break;
2987
2988 case CpCmd:
2989 ret = rtl8139_CpCmd_read(s);
2990 break;
2991
6cadb320
FB		 2992 case IntrMitigate:
2993 ret = rtl8139_IntrMitigate_read(s);
2994 break;
2995
a41b2ff2
PB		 2996 case TxSummary:
2997 ret = rtl8139_TSAD_read(s);
2998 break;
2999
3000 case CSCR:
3001 ret = rtl8139_CSCR_read(s);
3002 break;
3003
3004 default:
6cadb320 3005 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
a41b2ff2 3006
a41b2ff2
PB		 3007 ret = rtl8139_io_readb(opaque, addr);
3008 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3009
6cadb320 3010 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
a41b2ff2
PB		 3011 break;
3012 }
3013
3014 return ret;
3015}
3016
3017static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3018{
3019 RTL8139State *s = opaque;
3020 uint32_t ret;
3021
3022 addr &= 0xfc; /* also mask low 2 bits */
3023
3024 switch (addr)
3025 {
3026 case RxMissed:
3027 ret = s->RxMissed;
3028
6cadb320 3029 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
a41b2ff2
PB		 3030 break;
3031
3032 case TxConfig:
3033 ret = rtl8139_TxConfig_read(s);
3034 break;
3035
3036 case RxConfig:
3037 ret = rtl8139_RxConfig_read(s);
3038 break;
3039
3040 case TxStatus0 ... TxStatus0+4*4-1:
3041 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3042 break;
3043
3044 case TxAddr0 ... TxAddr0+4*4-1:
3045 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3046 break;
3047
3048 case RxBuf:
3049 ret = rtl8139_RxBuf_read(s);
3050 break;
3051
3052 case RxRingAddrLO:
3053 ret = s->RxRingAddrLO;
6cadb320 3054 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
a41b2ff2
PB		 3055 break;
3056
3057 case RxRingAddrHI:
3058 ret = s->RxRingAddrHI;
6cadb320
FB		 3059 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3060 break;
3061
3062 case Timer:
05447803
FZ		 3063 ret = muldiv64(qemu_get_clock(vm_clock) - s->TCTR_base,
3064 PCI_FREQUENCY, get_ticks_per_sec());
6cadb320
FB		 3065 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3066 break;
3067
3068 case FlashReg:
3069 ret = s->TimerInt;
3070 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
a41b2ff2
PB		 3071 break;
3072
3073 default:
6cadb320 3074 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
a41b2ff2 3075
a41b2ff2
PB		 3076 ret = rtl8139_io_readb(opaque, addr);
3077 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3078 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3079 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3080
6cadb320 3081 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
a41b2ff2
PB		 3082 break;
3083 }
3084
3085 return ret;
3086}
3087
3088/* */
3089
3090static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3091{
3092 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3093}
3094
3095static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3096{
3097 rtl8139_io_writew(opaque, addr & 0xFF, val);
3098}
3099
3100static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3101{
3102 rtl8139_io_writel(opaque, addr & 0xFF, val);
3103}
3104
3105static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3106{
3107 return rtl8139_io_readb(opaque, addr & 0xFF);
3108}
3109
3110static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3111{
3112 return rtl8139_io_readw(opaque, addr & 0xFF);
3113}
3114
3115static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3116{
3117 return rtl8139_io_readl(opaque, addr & 0xFF);
3118}
3119
3120/* */
3121
c227f099 3122static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3123{
3124 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3125}
3126
c227f099 3127static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3128{
3129 rtl8139_io_writew(opaque, addr & 0xFF, val);
3130}
3131
c227f099 3132static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3133{
3134 rtl8139_io_writel(opaque, addr & 0xFF, val);
3135}
3136
c227f099 3137static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3138{
3139 return rtl8139_io_readb(opaque, addr & 0xFF);
3140}
3141
c227f099 3142static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3143{
5fedc612 3144 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3145 return val;
a41b2ff2
PB		 3146}
3147
c227f099 3148static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3149{
5fedc612 3150 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3151 return val;
a41b2ff2
PB		 3152}
3153
060110c3 3154static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3155{
6597ebbb 3156 RTL8139State* s = opaque;
05447803 3157 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
060110c3 3158 if (version_id < 4) {
2c3891ab
AL		 3159 s->cplus_enabled = s->CpCmd != 0;
3160 }
3161
a41b2ff2
PB		 3162 return 0;
3163}
3164
05447803
FZ		 3165static void rtl8139_pre_save(void *opaque)
3166{
3167 RTL8139State* s = opaque;
3168 int64_t current_time = qemu_get_clock(vm_clock);
3169
3170 /* set IntrStatus correctly */
3171 rtl8139_set_next_tctr_time(s, current_time);
3172 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3173 get_ticks_per_sec());
3174}
3175
060110c3
JQ		 3176static const VMStateDescription vmstate_rtl8139 = {
3177 .name = "rtl8139",
3178 .version_id = 4,
3179 .minimum_version_id = 3,
3180 .minimum_version_id_old = 3,
3181 .post_load = rtl8139_post_load,
05447803 3182 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3183 .fields = (VMStateField []) {
3184 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3185 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3186 VMSTATE_BUFFER(mult, RTL8139State),
3187 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3188 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3189
3190 VMSTATE_UINT32(RxBuf, RTL8139State),
3191 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3192 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3193 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3194
3195 VMSTATE_UINT16(IntrStatus, RTL8139State),
3196 VMSTATE_UINT16(IntrMask, RTL8139State),
3197
3198 VMSTATE_UINT32(TxConfig, RTL8139State),
3199 VMSTATE_UINT32(RxConfig, RTL8139State),
3200 VMSTATE_UINT32(RxMissed, RTL8139State),
3201 VMSTATE_UINT16(CSCR, RTL8139State),
3202
3203 VMSTATE_UINT8(Cfg9346, RTL8139State),
3204 VMSTATE_UINT8(Config0, RTL8139State),
3205 VMSTATE_UINT8(Config1, RTL8139State),
3206 VMSTATE_UINT8(Config3, RTL8139State),
3207 VMSTATE_UINT8(Config4, RTL8139State),
3208 VMSTATE_UINT8(Config5, RTL8139State),
3209
3210 VMSTATE_UINT8(clock_enabled, RTL8139State),
3211 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3212
3213 VMSTATE_UINT16(MultiIntr, RTL8139State),
3214
3215 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3216 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3217 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3218 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3219 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3220
3221 VMSTATE_UINT16(CpCmd, RTL8139State),
3222 VMSTATE_UINT8(TxThresh, RTL8139State),
3223
3224 VMSTATE_UNUSED(4),
3225 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3226 VMSTATE_INT32(rtl8139_mmio_io_addr, RTL8139State),
3227
3228 VMSTATE_UINT32(currTxDesc, RTL8139State),
3229 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3230 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3231 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3232 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3233
3234 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3235 VMSTATE_INT32(eeprom.mode, RTL8139State),
3236 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3237 VMSTATE_UINT8(eeprom.address, RTL8139State),
3238 VMSTATE_UINT16(eeprom.input, RTL8139State),
3239 VMSTATE_UINT16(eeprom.output, RTL8139State),
3240
3241 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3242 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3243 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3244 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3245
3246 VMSTATE_UINT32(TCTR, RTL8139State),
3247 VMSTATE_UINT32(TimerInt, RTL8139State),
3248 VMSTATE_INT64(TCTR_base, RTL8139State),
3249
3250 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3251 vmstate_tally_counters, RTL8139TallyCounters),
3252
3253 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3254 VMSTATE_END_OF_LIST()
3255 }
3256};
3257
a41b2ff2
PB		 3258/***********************************************************/
3259/* PCI RTL8139 definitions */
3260
5fafdf24 3261static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 3262 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3263{
efd6dd45 3264 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3265
3266 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3267}
3268
5fafdf24 3269static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
6e355d90 3270 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3271{
efd6dd45 3272 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3273
3274 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3275 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3276
3277 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3278 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3279
3280 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3281 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3282}
3283
d60efc6b 3284static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
a41b2ff2
PB		 3285 rtl8139_mmio_readb,
3286 rtl8139_mmio_readw,
3287 rtl8139_mmio_readl,
3288};
3289
d60efc6b 3290static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
a41b2ff2
PB		 3291 rtl8139_mmio_writeb,
3292 rtl8139_mmio_writew,
3293 rtl8139_mmio_writel,
3294};
3295
6cadb320
FB		 3296static void rtl8139_timer(void *opaque)
3297{
3298 RTL8139State *s = opaque;
3299
6cadb320
FB		 3300 if (!s->clock_enabled)
3301 {
3302 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3303 return;
3304 }
3305
05447803
FZ		 3306 s->IntrStatus |= PCSTimeout;
3307 rtl8139_update_irq(s);
3308 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
6cadb320 3309}
6cadb320 3310
1673ad51 3311static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3312{
1673ad51 3313 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3314
1673ad51 3315 s->nic = NULL;
254111ec
GH		 3316}
3317
3318static int pci_rtl8139_uninit(PCIDevice *dev)
3319{
3320 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3321
3322 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
b946a153
AL		 3323 if (s->cplus_txbuffer) {
3324 qemu_free(s->cplus_txbuffer);
3325 s->cplus_txbuffer = NULL;
3326 }
b946a153
AL		 3327 qemu_del_timer(s->timer);
3328 qemu_free_timer(s->timer);
1673ad51 3329 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3330 return 0;
3331}
3332
1673ad51
MM		 3333static NetClientInfo net_rtl8139_info = {
3334 .type = NET_CLIENT_TYPE_NIC,
3335 .size = sizeof(NICState),
3336 .can_receive = rtl8139_can_receive,
3337 .receive = rtl8139_receive,
3338 .cleanup = rtl8139_cleanup,
3339};
3340
81a322d4 3341static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3342{
efd6dd45 3343 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3344 uint8_t *pci_conf;
3b46e624 3345
efd6dd45 3346 pci_conf = s->dev.config;
deb54399
AL		 3347 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3348 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
0b5b3547 3349 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
173a543b 3350 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
0b5b3547
MT		 3351 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3352 /* TODO: start of capability list, but no capability
3353 * list bit in status register, and offset 0xdc seems unused. */
3354 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3355
a41b2ff2
PB		 3356 /* I/O handler for memory-mapped I/O */
3357 s->rtl8139_mmio_io_addr =
2507c12a 3358 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
5cf7a3ca 3359 DEVICE_LITTLE_ENDIAN);
a41b2ff2 3360
efd6dd45 3361 pci_register_bar(&s->dev, 0, 0x100,
0392a017 3362 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
a41b2ff2 3363
efd6dd45 3364 pci_register_bar(&s->dev, 1, 0x100,
0392a017 3365 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
a41b2ff2 3366
254111ec 3367 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3368
1673ad51
MM		 3369 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3370 dev->qdev.info->name, dev->qdev.id, s);
3371 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3372
3373 s->cplus_txbuffer = NULL;
3374 s->cplus_txbuffer_len = 0;
3375 s->cplus_txbuffer_offset = 0;
3b46e624 3376
05447803 3377 s->TimerExpire = 0;
6cadb320 3378 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
05447803 3379 rtl8139_set_next_tctr_time(s, qemu_get_clock(vm_clock));
1ca4d09a
GN		 3380
3381 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3382
81a322d4 3383 return 0;
a41b2ff2 3384}
9d07d757 3385
0aab0d3a 3386static PCIDeviceInfo rtl8139_info = {
f82de8f0
GH		 3387 .qdev.name = "rtl8139",
3388 .qdev.size = sizeof(RTL8139State),
3389 .qdev.reset = rtl8139_reset,
be73cfe2 3390 .qdev.vmsd = &vmstate_rtl8139,
f82de8f0 3391 .init = pci_rtl8139_init,
e3936fa5 3392 .exit = pci_rtl8139_uninit,
8c52c8f3 3393 .romfile = "pxe-rtl8139.bin",
254111ec
GH		 3394 .qdev.props = (Property[]) {
3395 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3396 DEFINE_PROP_END_OF_LIST(),
3397 }
0aab0d3a
GH		 3398};
3399
9d07d757
PB		 3400static void rtl8139_register_devices(void)
3401{
0aab0d3a 3402 pci_qdev_register(&rtl8139_info);
9d07d757
PB		 3403}
3404
3405device_init(rtl8139_register_devices)
Empty description
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